Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: cell blocks each including a folded structure in which an electrode structure and an insulating structure are alternately disposed, in which the electrode structure and the insulating structure extend in a vertical direction and are connected to each other to have at least two U-shaped structures forming a fluff shape in a plan view, the electrode structure comprises a vertical electrode and a switching material layer, and the unit blocks are arranged along a first horizontal direction and a second horizontal direction intersected with the first horizontal direction; and a gate stack structure including gate electrodes and interlayer insulating layers alternately stacked in a vertical direction along sidewalls of the electrode structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0100705 filed on August 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor memory device, and more particularly, to a three-dimensional vertical memory device. Background Art

[0004] Since electronic products need to be miniaturized and multifunctional and have high performance, high-capacity semiconductor memory devices are needed, and increased integration is required to provide high-capacity semiconductor memory devices. Since the integration of two-dimensional (2D) semiconductor memory devices is mainly determined by the area occupied by a unit memory cell, the integration of two-dimensional semiconductor memory devices is increasing, but it is still limited. Therefore, a three-dimensional (3D) vertical memory device has been proposed, in which the storage capacity is increased by stacking a plurality of memory cells in a vertical direction on a substrate. Summary of the invention

[0005] One or more embodiments provide a three-dimensional vertical memory device with improved integration.

[0006] According to one aspect of the embodiment, a semiconductor memory device includes: a plurality of cell blocks, each cell block including a folded structure in which a plurality of electrode structures and a plurality of insulating structures are alternately arranged, wherein the plurality of electrode structures and the plurality of insulating structures extend in a vertical direction and are connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, the plurality of electrode structures including vertical electrodes and switching material layers, and the plurality of cell blocks are arranged along a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked in the vertical direction along the sidewalls of the plurality of electrode structures. Each of the plurality of gate electrodes includes a pad portion and a plurality of plate electrodes spaced apart from each other in each of the plurality of layers. In each of the two cell blocks in the first horizontal direction among the plurality of cell blocks and at least two cell blocks in the second horizontal direction among the plurality of cell blocks, at least one plate electrode among the plurality of plate electrodes is connected to the switching material layer of the plurality of electrode structures.

[0007] According to another aspect of the embodiment, a semiconductor memory device includes: a substrate including a plurality of pad regions and a plurality of cell regions, wherein the plurality of pad regions and the plurality of cell regions are alternately arranged along a first horizontal direction; at least two cell blocks are sequentially arranged in each of the plurality of cell regions along a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked along a vertical direction. Each of the plurality of gate electrodes includes a plurality of plate electrodes spaced apart from each other in each of a plurality of layers, and each of the plurality of plate electrodes includes a pad portion arranged in one of the plurality of pad regions, at least two shaft portions extending from the pad portion to at least one cell region adjacent to the one pad region, and a plurality of sawtooth portions extending from each of the at least two shaft portions. Each of the at least two cell blocks arranged in each of the plurality of cell regions includes a folded structure on the substrate, in which a plurality of electrode structures extending in the vertical direction and a plurality of insulating structures extending in the vertical direction are alternately arranged and connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, wherein the plurality of electrode structures extend into the gate stack structure in the vertical direction and include a vertical electrode and a switching material layer. Each of the plurality of serrated portions extends into the fuzz shape and is connected to the switching material layer.

[0008] According to another aspect of the embodiment, a semiconductor memory device includes: a substrate including a plurality of pad regions and a plurality of cell regions, wherein the plurality of pad regions and the plurality of cell regions are alternately arranged along a first horizontal direction; a plurality of cell blocks in each of the plurality of cell regions, including at least two cell blocks sequentially arranged along the first horizontal direction and at least two cell blocks sequentially arranged along a second horizontal direction intersecting the first horizontal direction; and a gate stack structure including a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked along a vertical direction. Each of the plurality of gate electrodes includes a plurality of plate electrodes spaced apart from each other in each of a plurality of layers, each of the plurality of plate electrodes includes a pad portion arranged in one of the plurality of pad regions and extending in the second horizontal direction, at least two shaft portions extending from the pad portion in the first horizontal direction to at least one cell region adjacent to the one pad region in the plurality of cell regions, and a plurality of sawtooth portions extending from each of the at least two shaft portions in the second horizontal direction. Each of the plurality of cell blocks arranged in each of the plurality of cell areas includes a folded structure on the substrate, in which a plurality of electrode structures extending in the vertical direction and a plurality of insulating structures extending in the vertical direction are alternately arranged and connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, wherein the plurality of electrode structures extend into the plurality of gate electrodes in the vertical direction and include a vertical electrode and a switching material layer. The fuzz shape faces the second horizontal direction, and each of the plurality of serrated portions extends into the fuzz shape of the folded structure and is connected to the switching material layer. In the at least two cell blocks sequentially arranged along the first horizontal direction, at least one plate electrode of the plurality of plate electrodes is connected to the switching material layer of the plurality of electrode structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects and features will become more apparent from the following description of the embodiments given in conjunction with the accompanying drawings, in which:

[0010] Figure 1A , Figure 1B and Figure 1C are a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment;

[0011] Figure 2A , Figure 2B and Figure 2C are a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment;

[0012] Figure 3A , Figure 3B and Figure 3C are a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment;

[0013] Figure 4A , Figure 4B and Figure 4C are a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment;

[0014] Figure 5A and Figure 5B are a plan view and a block diagram of a semiconductor memory device according to an embodiment;

[0015] Fig. 6A and Figure 6B is a plan view of a semiconductor memory device according to an embodiment;

[0016] Fig. 7A and Figure 7B are a plan view and a block diagram of a semiconductor memory device according to an embodiment;

[0017] Fig. 8A and Figure 8B is a plan view of a semiconductor memory device according to an embodiment;

[0018] Fig. 9A and Fig. 9B are a plan view and a block diagram of a semiconductor memory device according to an embodiment; and

[0019] Fig.10 is a plan view of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0020] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The embodiments described herein are example embodiments, therefore, the present disclosure is not limited thereto, and can be implemented in various other forms. It is not excluded that each embodiment provided in the following description is associated with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on the other element or layer, directly connected to or coupled to the other element or layer, or there can be an intermediate element or layer. On the contrary, when an element is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer. The term "and / or" used herein includes any combination and all combinations of one or more of the associated listed items. Statements such as "at least one of..." modify the entire element list when after the element list, rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will also be understood that even if a step or operation of a manufacturing device or structure is described as being later than another step or operation, the step or operation may be performed earlier than the other step or operation, unless the other step or operation is described as being performed before the step or operation. The same reference numerals are used for the same components in the drawings, and their repeated descriptions are omitted. In the following detailed description and claims, it will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from each other.

[0021] Figures 1A to 1C are a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment.

[0022] refer to Figures 1A to 1C, according to the embodiment, the semiconductor memory device 100 may include a substrate 101, a plurality of electrode structures 110, a gate stack structure 120, and a plurality of insulating structures 150. In one cell block BLK included in the semiconductor memory device 100, the plurality of electrode structures 110 and the plurality of insulating structures 150 may be alternately arranged along a path having a U-shaped structure forming a villus shape in a plan view. That is, the plurality of electrode structures 110 and the plurality of insulating structures 150 may form a villus shape of a U-shaped pattern in a plan view. The plurality of electrode structures 110 and the plurality of insulating structures 150 included in one cell block BLK may be alternately arranged to have at least two U-shaped structures forming a villus shape in a plan view, and may be connected to each other to form a folded structure FS. The folded structure FS may be arranged so that at least two insulating structures 150 face a second horizontal direction (y direction) or an opposite direction of the second horizontal direction (y direction), wherein each of the at least two insulating structures 150 is a villus-shaped protrusion. Although Figure 1A The folding structure FS is shown to have two U-shaped structures forming a fuzz shape, but the folding structure FS is not limited thereto. For example, the folding structure FS may have a U-shaped structure forming more than two fuzz shapes. The plurality of insulating structures 150 may include a plurality of partition wall pillars 130 and a plurality of trimming patterns 140 .

[0023] The substrate 101 may have a plurality of cell regions and a plurality of pad regions alternately arranged in a first horizontal direction (x direction), and Figures 1A to 4C , a cell region is shown in the figure. The first horizontal direction (x direction) and the second horizontal direction (y direction) may be orthogonal to each other. The substrate 101 may include silicon (Si), such as single crystal Si, polycrystalline Si, or amorphous Si. Of course, the material of the substrate 101 is not limited to Si. For example, in some embodiments, the substrate 101 may include a Group IV semiconductor (e.g., germanium (Ge)), a Group IV-IV compound semiconductor (e.g., silicon germanium (SiGe) or silicon carbide (SiC)), or a Group III-V compound semiconductor (e.g., gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)).

[0024] The substrate 101 may be based on a silicon bulk substrate. In addition, the substrate 101 may be based on a silicon on insulator (SOI) substrate or a germanium on insulator (GeOI) substrate. The substrate 101 may be a substrate based on an epitaxial wafer, a polished wafer, an annealed wafer, etc., and is not limited to a bulk substrate, SOI or GeOI substrate. The substrate 101 may include a conductive region, for example, a well doped with impurities or various structures doped with impurities. In addition, depending on the type of impurity ions doped, the substrate 101 may constitute a P-type substrate or an N-type substrate.

[0025] In some embodiments, the peripheral circuit and the wiring layer connected to the peripheral circuit may be arranged on a partial area of ​​the substrate 101. The peripheral circuit may receive addresses, commands, and control signals from devices outside the semiconductor memory device 100, and may send data to devices outside the semiconductor memory device 100 and receive data from devices outside the semiconductor memory device 100. The peripheral circuit may include a row decoder, a page buffer, a data input / output circuit, and a control logic. In some embodiments, the peripheral circuit may also include an input / output interface, a column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplification circuit, and the like.

[0026] like Figure 1A As shown, a plurality of electrode structures 110 may be arranged in a two-dimensional array structure on an xy plane. In particular, a plurality of electrode structures 110 may be spaced apart from each other in a first horizontal direction (x direction) and a second horizontal direction (y direction). The electrode structures 110 form lines in the second horizontal direction (y direction), and the electrode structures 110 adjacent to each other in the second horizontal direction (y direction) may be separated from each other by partition walls 130. In addition, the electrode structures 110 constituting two lines adjacent to each other in the first horizontal direction (x direction) may be connected to the gate electrode 122 of the gate stack structure 120.

[0027] The electrode structures 110 constituting lines in the second horizontal direction (y direction) may be arranged in a zigzag shape along the second horizontal direction (y direction) on two lines adjacent to each other in the first horizontal direction (x direction). For example, the electrode structures 110 may be arranged at a first pitch P1 in the second horizontal direction (y direction), and the electrode structures 110 may be arranged between two adjacent lines in the first horizontal direction (x direction) with an offset of 1 / 2 of the first pitch P1 in the second horizontal direction (y direction). For example, the electrode structures 110 may be arranged at a second pitch P2 in the first horizontal direction (x direction), and the electrode structures 110 may be arranged between two adjacent lines in the second horizontal direction (y direction) with an offset of 1 / 2 of the second pitch P2 in the first horizontal direction (x direction). In some embodiments, the first pitch P1 and the second pitch P2 may have substantially the same value.

[0028] The electrode structure 110 may have a cylindrical shape extending in a direction perpendicular to the top surface of the substrate 101 (i.e., in a vertical direction (z direction)). However, the shape of the electrode structure 110 is not limited to a cylindrical shape. For example, in some embodiments, the electrode structure 110 may have a shape of an elliptical column or a polygonal column.

[0029] Each of the electrode structures 110 may include a vertical electrode 112, a first selection electrode layer 114, a switching material layer 116, and a second selection electrode layer 118, which may be sequentially arranged from the center thereof. In some embodiments, at least one of the first selection electrode layer 114 and the second selection electrode layer 118 may be omitted. In the semiconductor memory device 100, the vertical electrode 112 may form a vertical bit line. Each of the first selection electrode layer 114 and the second selection electrode layer 118 may be made of a conductive material (e.g., carbon or a conductive material containing carbon). The switching material layer 116 may include a material having an omnidirectional threshold switching (OTS) characteristic.

[0030] The vertical electrode 112 may have a cylindrical shape extending in a vertical direction (z direction) on the top surface of the substrate 101. However, the shape of the vertical electrode 112 is not limited to a cylindrical shape. For example, the vertical electrode 112 may have the shape of an elliptical column or a polygonal column. The vertical electrode 112 may include a conductive material. For example, the vertical electrode 112 may include doped polysilicon, a metal, a conductive metal nitride, or a combination thereof. In some embodiments, a conductive contact portion connected to the vertical electrode 112 may be arranged below and / or above the electrode structure 110.

[0031] The first selection electrode layer 114 may cover the bottom surface and the side surface of the vertical electrode 112. For example, the first selection electrode layer 114 may have a cylindrical tube shape with a closed bottom surface. However, in some embodiments, the first selection electrode layer 114 may have an open cylindrical tube shape.

[0032] The switching material layer 116 may cover the bottom surface and the side surface of the first selection electrode layer 114. Therefore, the switching material layer 116 may have a cylindrical tube shape with one side closed. However, in some embodiments, the switching material layer 116 may have an open cylindrical tube shape.

[0033] The switching material layer 116 may function as a self-selective memory element. Here, the self-selective memory element may refer to an element capable of functioning as both a selection element and a memory element. The semiconductor memory device 100 may be a three-dimensional vertical memory device including a selector only memory (SOM) device or a self-selective memory (SSM) device.

[0034] The switching material layer 116 may include a chalcogenide material, such as a chalcogenide alloy and / or a chalcogenide glass, that acts as a self-selective memory device. The switching material layer 116 may respond to an applied voltage, such as a programming pulse. For example, for an applied voltage less than a threshold voltage, the switching material layer 116 may remain in a non-conductive state, i.e., an "off" state. In addition, in response to an applied voltage greater than a threshold voltage, the switching material layer 116 may change to a conductive state, i.e., an "on" state. The threshold voltage of the switching material layer 116 may change based on the polarity of the applied voltage. The threshold voltage of the switching material layer 116 may change depending on whether the polarity of the programming pulse is positive or negative. For example, the semiconductor memory device 100 may require a bipolar voltage to drive the memory device.

[0035] The switching material layer 116 may include a chalcogenide material having a phase that does not change during operation. For example, the switching material layer 116 may be made of a single layer or a multilayer made of a material selected from the following: a two-component system material, such as GeSe, GeS, AsSe, AsTe, AsS, SiTe, SiSe, SiS, GeAs, SiAs, SnSe, SnTe; a three-component system material, such as GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, GaAsTe, InAsSe, InAsTe, SnAsSe, SnAsTe; a four-component system material, such as GeSiAsTe, GeSiAsSe, GeSiSeTe, GeSeTeSb, GeSiSeSb, GeSiTeSb, GeSeTeBi, GeSiSeBi, GeSiTeBi, GeAsSeSb, GeAsTeSb, GeAsTeBi, GeAs SeBi, GeAsSeIn, GeAsSeGa, GeAsSeAl, GeAsSeTl, GeAsSeSn, GeAsSeZn, GeAsTeIn, GeAsTeGa, GeAsTeAl, GeAsTeTl, GeAsTeSn, GeAsTeZn;Five-component system materials, such as GeSiAsSeTe, GeAsSeTeS, GeSiAsSeS, GeSiAsTeS, GeSiSeTeS, GeSiAsSeP, GeSiAsTeP, GeAsSeTeP, GeSiAsSeIn, GeSiAsSeGa, GeSiAsSeAl, GeSiAsSeTl, GeSiAsSeZn, GeSiAsSeSn, GeSiAsTeIn, GeSiAsTeGa, GeSiAsTeAl, GeSiAsTeTl, GeSiAsTeZn, GeSiAsTeSn, GeAsSeTeIn, GeAsSeTeGa, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeAsSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTeSAl, GeAsTeSTl, GeAsTeSZn, GeAsTeSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsSeGaAl, GeAsSeGaTl, GeAsSeGaZn, GeAsSeGaSn, GeAsSeAlTl, GeAsSeAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn, GeAsSeZnSn;and six-component system materials such as GeSiAsSeTeS, GeSiAsSeTeIn, GeSiAsSeTeGa, GeSiAsSeTeAl, GeSiAsSeTeTl, GeSiAsSeTeZn , GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeS iAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, GeAsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTe PIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl , GeSiAsSeInTl, GeSiAsSeInZn, GeSiAsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeG aSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeT eGaAl, GeAsSeTeGaTl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeS InTl, GeAsSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, GeAsSeSAlSn. In some embodiments, the switching material layers 116 may each include at least one material selected from the two-component system materials to the six-component system materials shown above and at least one additional element selected from B, C, N, and O. ;

[0036] The second selection electrode layer 118 may cover the bottom surface and the side surface of the switching material layer 116. Therefore, the second selection electrode layer 118 may have a cylindrical tube shape with a closed bottom surface. However, in some embodiments, the second selection electrode layer 118 may have an open cylindrical tube shape.

[0037] For reference, when the conductive contact is arranged below the electrode structure 110, and when the first selection electrode layer 114, the switching material layer 116, and the second selection electrode layer 118 have a cylindrical tube structure with a closed bottom surface, the conductive contact may penetrate the first selection electrode layer 114, the switching material layer 116, and the second selection electrode layer 118 to be connected to the vertical electrode 112. Alternatively, when the first selection electrode layer 114, the switching material layer 116, and the second selection electrode layer 118 have an open cylindrical tube structure without a bottom surface, the conductive contact may be directly connected to the vertical electrode 112.

[0038] The gate stack structure 120 may include a plurality of gate electrodes 122 and a plurality of interlayer insulating layers 124. Figure 1B As shown, a plurality of gate electrodes 122 and a plurality of interlayer insulating layers 124 may be alternately stacked on the substrate 101 along the sidewalls of the electrode structure 110. In the semiconductor memory device 100, the gate electrodes 122 may constitute word lines.

[0039] Each of the plurality of gate electrodes 122 may have a plate shape. The plurality of gate electrodes 122 may be spaced apart from each other in the vertical direction (z direction). In this regard, the gate electrodes 122 in each layer may have a structure that is integrally connected to each other in a plate shape. Therefore, the gate electrode 122 may be referred to as a plate electrode. In addition, in some embodiments, the gate electrode 122 may be referred to as a word line plate.

[0040] In the semiconductor memory device 100, the gate electrode 122 may have a split plate electrode shape. For example, in each layer, the gate electrode 122 may include one side ( Figure 1A The first plate electrode PE1 on the upper side of the Figure 1A In addition, the first plate electrode PE1 and the second plate electrode PE2 may have a staggered comb form. For example, the first plate electrode PE1 and the second plate electrode PE2 may be arranged on both sides in the first horizontal direction (x direction) based on any one line in which the electrode structure 110 is arranged along the second horizontal direction (y direction). Each of the first plate electrode PE1 and the second plate electrode PE2 may include: a sawtooth portion extending into the fuzz shape of the folding structure FS, connected to the electrode structure 110, and extending in the second horizontal direction (y direction); and an axis portion extending in the first horizontal direction (x direction).

[0041] In the semiconductor memory device 100, since the gate electrode 122 has a split plate electrode shape, the operation speed can be improved by minimizing the parasitic capacitance on the word line. In addition, since the gate electrode 122 has a split plate electrode shape, the programming current can be increased by minimizing the area of ​​contact with the cell and reducing cell leakage.

[0042] The gate electrode 122 may include a conductive material, such as doped silicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The interlayer insulating layer 124 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In the semiconductor memory device 100, the interlayer insulating layer 124 may include silicon oxide. However, the material of the interlayer insulating layer 124 is not limited to silicon oxide. For example, the interlayer insulating layer 124 may be made of an insulating material having a lower dielectric constant than silicon oxide. In some embodiments, the interlayer insulating layer 124 may be composed of a tetraethyl orthosilicate (TEOS) layer or an ultra-low K (ULK) layer having an ultra-low dielectric constant K of about 2.2 to about 2.4. The ULK layer may include a SiOC layer or a SiCOH layer.

[0043] Each of the plurality of partition wall pillars 130 may be arranged between the electrode structures 110 arranged along the second horizontal direction (y direction). The partition wall pillars 130 may extend in the vertical direction (z direction). The partition wall pillars 130 have a substantially cylindrical shape, but some outer portions may be invaded by the electrode structures 110 arranged on both sides along the second horizontal direction (y direction). Therefore, the partition wall pillars 130 may include concave portions Cc located at both sides in the second horizontal direction (y direction). The partition wall pillars 130 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In the semiconductor memory device 100, the partition wall pillars 130 may include silicon oxide. However, the material of the partition wall pillars 130 is not limited to silicon oxide. For reference, Figure 1C The interlayer insulating layer 124 and the partition wall columns 130 are omitted, and the empty space between the electrode structures 110 in the second horizontal direction (y direction) may correspond to the partition wall columns 130, and the empty space between the gate electrodes 122 in the vertical direction (z direction) may correspond to the interlayer insulating layer 124.

[0044] A plurality of trimming patterns 140 may be arranged on both edge portions of the cell block BLK along the second horizontal direction (y direction). The trimming pattern 140 may extend in the vertical direction (z direction). Each of the plurality of insulating structures 150 including the plurality of partition wall pillars 130 and the plurality of trimming patterns 140 may extend in the vertical direction (z direction). Here, the cell block BLK may be defined by a folding structure FS, which is composed of a plurality of electrode structures 110 and a plurality of insulating structures 150 alternately arranged and connected to each other to have at least two U-shaped structures formed with a fuzz shape in a plan view. In this regard, one cell block BLK may include one folding structure FS. For example, each of the folding structures FS spaced apart from each other in a plan view may constitute a separate cell block BLK.

[0045] In some embodiments, the cell block BLK may extend in the first horizontal direction (x direction), the stepped pad may be arranged at the edge portion of the cell block BLK in the first horizontal direction (x direction), and the vertical contact portion may be connected to the pad. The word line voltage may be applied to the gate electrode 122 of each layer through the vertical contact portion and the pad. For example, the pad connected to the first plate electrode PE1 and the pad connected to the second plate electrode PE2 may be arranged at two edge portions of the cell block BLK in the first horizontal direction (x direction), respectively. In some embodiments, the first plate electrode PE1 and the pad connected to the first plate electrode PE1 may have an overall plate electrode shape, and the second plate electrode PE2 and the pad connected to the second plate electrode PE2 may have an overall plate electrode shape. The plate electrode in which the first plate electrode PE1 and the pad connected to the first plate electrode PE1 form an integral body and the plate electrode in which the second plate electrode PE2 and the pad connected to the second plate electrode PE2 form an integral body may be spaced apart from each other.

[0046] The trimming patterns 140 may each have an L shape in a plan view. In this regard, the trimming patterns 140 may each include a portion extending in the first horizontal direction (x direction) and a portion extending in the second horizontal direction (y direction). In addition, the trimming patterns 140 may each have a width covering two adjacent partition wall pillars 130 in the first horizontal direction (x direction). That is, among the lines arranged with the electrode structure 110 in the second horizontal direction (y direction), two adjacent lines in the first horizontal direction (x direction) may contact the trimming pattern 140 arranged below or above in the second horizontal direction (y direction) through the electrode structure 110. The trimming pattern 140 located below in the second horizontal direction (y direction) and the trimming pattern 140 located above in the second horizontal direction (y direction) may be arranged at alternating positions in the second horizontal direction (y direction). In addition, two trimming patterns 140 facing each other in the second horizontal direction (y direction) and adjacent to each other in the first horizontal direction (x direction) may cover a line in which the electrode structures 110 are arranged together along the second horizontal direction (y direction), and may be arranged in a point-symmetrical structure based on any portion on the line (for example, the electrode structure 110 in the center portion of the line).

[0047] The trimming pattern 140 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In the semiconductor memory device 100, a plurality of trimming patterns 140 may be formed together with a plurality of partition wall pillars 130, and the plurality of partition wall pillars 130 and the plurality of trimming patterns 140 may be referred to as a plurality of insulating structures 150. For example, the trimming patterns 140 may each include silicon oxide. However, the material of the trimming pattern 140 is not limited to silicon oxide.

[0048] The partition wall column 130 may have a first diameter D1, and the electrode structure 110 including the second selection electrode layer 118 may have a second diameter D2. The vertical electrode 112 may have a third diameter D3. The third diameter D3 may have a value smaller than each of the first diameter D1 and the second diameter D2. In some embodiments, the first diameter D1 and the second diameter D2 may have substantially the same value. For example, when each of the first pitch P1 and the second pitch P2 is about 160 nm, each of the first diameter D1 and the second diameter D2 may be about 120 nm, the third diameter D3 may be about 60 nm, and the first width W1 of the gate electrode 122 in the first horizontal direction (x direction) between the electrode structure 110 and the partition wall column 130 may be about 40 nm.

[0049] In the semiconductor memory device 100, a plurality of electrode structures 110 each having a vertical electrode 112 and a switching material layer 116 may extend in a vertical direction, and a plurality of gate electrodes 122 may have a vertical structure stacked in a vertical direction (z direction) along the sidewalls of the plurality of electrode structures 110. Therefore, the semiconductor memory device 100 may realize a large-capacity memory device with increased integration. In addition, in the semiconductor memory device 100, the gate electrode 122 may have the shape of a split plate electrode. Therefore, the semiconductor memory device (100) of this embodiment may increase the operating speed by minimizing parasitic capacitance, and may increase the programming current by minimizing the area of ​​contact with the cell and reducing the cell leakage. In addition, in the semiconductor memory device 100 of this embodiment, the electrode structures 110 are arranged in a line shape along the second horizontal direction (y direction), and may be separated from each other by cylindrical partition wall pillars 130. As described above, since the cylindrical partition wall pillars 130 have a structure arranged between the electrode structures 110 , it is possible to effectively prevent a tilt defect that may occur when a line pattern having a high aspect ratio is formed in the gate stack structure 120 of tens to hundreds of layers.

[0050] FIG. 2A to FIG. 2C 1 is a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment. FIG. 2A to FIG. 2C References will be briefly described or omitted. Figures 1A to 1C A repeated description of the content described.

[0051] refer to FIG. 2A to FIG. 2C The configuration of the electrode structure 110a of the semiconductor memory device 100a may be similar to Figure 1A The configuration of the electrode structure 110 of the semiconductor memory device 100 is different. Specifically, the semiconductor memory device 100a may include a substrate 101, a plurality of electrode structures 110a, a gate stack structure 120a, and a plurality of insulating structures 150. The substrate 101, the gate stack structure 120a, and the insulating structure 150 are the same as those described above. Figure 1A The substrate 101, the gate stack structure 120 and the insulating structure 150 of the semiconductor memory device 100 are the same. However, in the case of the gate stack structure 120a, at the portion in contact with the electrode structure 110a, the width of the gate electrode 122a in the first horizontal direction (x direction) may be greater than Figure 1A The width of the gate electrode 122a is narrow. The width of the gate electrode 122a will be described in more detail below in the description of the electrode structure 110a.

[0052] like Figure 2A As shown, the electrode structure 110a can be arranged into a two-dimensional array structure in the xy plane. Specifically, the electrode structure 110a forms a line in the second horizontal direction (y direction), and can be separated from each other in the second horizontal direction (y direction) by the partition wall column 130. In addition, the electrode structure 110a on two lines adjacent to each other in the first horizontal direction (x direction) can be connected to the gate electrode 122a of the gate stack structure 120a. In addition, the electrode structure 110a constituting a line in the second horizontal direction (y direction) can be arranged in a zigzag shape along the second horizontal direction (y direction) on two lines adjacent to each other along the first horizontal direction (x direction), and can have an offset of 1 / 2 pitch in the second horizontal direction (y direction).

[0053] Each of the electrode structures 110a may include a vertical electrode 112, a first selection electrode layer 114, a switching material layer 116a, and a second selection electrode layer 118a. In some embodiments, at least one of the first selection electrode layer 114 and the second selection electrode layer 118a may be omitted.

[0054] On the substrate 101, for each layer in the vertical direction (z direction), the switching material layer 116a may include a plurality of switching elements spaced apart from each other. Each switching element may have two arcs facing each other and surrounding a portion of the first selection electrode layer 114. For example, the switching elements of the switching material layer 116a may be arranged in an arc shape only on the layer where the gate electrode 122a of the gate stack structure 120a is located. In particular, as shown in FIG. Figure 2A and Figure 2C As can be seen, each of the switching elements of the switching material layer 116a may have a ring shape surrounding the first selection electrode layer 114, without a portion contacting the two partition wall pillars 130 in the second horizontal direction (y direction). For example, the arc-shaped side surface may face the partition wall pillars 130. Therefore, the first selection electrode layer 114 may contact the partition wall pillars 130 in the second horizontal direction (y direction). The switching elements of the switching material layer 116a may be separated from the switching elements of other layers in the vertical direction (z direction).

[0055] Since the switching material layer 116a has switching elements separated from each other in the vertical direction (z direction), diffusion between cells is prevented in the vertical direction (z direction), thereby improving the reliability of the semiconductor memory device 100a. In addition, the operating characteristics and specific materials of the switching material layer 116a are similar to those of the semiconductor memory device 100a. Figure 1A The operating characteristics and specific materials described in the switching material layer 116 of the semiconductor memory device 100 are the same.

[0056] The second selection electrode layer 118a may include a plurality of electrode elements spaced apart from each other for each layer in the vertical direction (z direction) and corresponding to the switching elements of the switching material layer 116a. Each electrode element may have two arcs surrounding the switching element of the corresponding switching material layer 116a. In particular, as shown in FIG. Figure 2A and Figure 2C It can be seen that, since the electrode elements of the second selection electrode layer 118a and the switching elements of the switching material layer 116a have two arcs, the first selection electrode layer 114 can contact two partition wall pillars 130 in the second horizontal direction (y direction). Similar to the switching material layer 116a, the electrode elements of the second selection electrode layer 118a can also be separated from the electrode elements of other layers in the vertical direction (z direction).

[0057] When the opening hole for forming the electrode structure 110a has the same Figure 1A When the opening holes of the electrode structure 110 in the semiconductor memory device 100 are of the same size, and when the thicknesses of the first selection electrode layer 114, the switching material layers 116 and 116a, and the second selection electrode layers 118 and 118a of the electrode structures 110 and 110a are respectively the same, due to the characteristics of the process, the size of the vertical electrode 112 of the electrode structure 110a, such as the horizontal radius, may be larger than Figure 1A The horizontal radius of the vertical electrode 112 of the electrode structure 110 of the gate stack 120a can be almost similar to the horizontal radius of the vertical electrode 112 of the electrode structure 110a. For example, when the second selection electrode layers 118 and 118a are very thin, the horizontal radius of the vertical electrode 112 of the electrode structure 110a can be almost similar to the horizontal radius of the entire electrode structure 110a. In addition, since the switching material layer 116a and the second selection electrode layer 118a of the electrode structure 110a are arranged in two arcs at both sides in the first horizontal direction (x direction), the gate electrode 122a of the gate stack structure 120a can have a narrower width in the first horizontal direction (x direction) at the portion in contact with the electrode structure 110a (for example, the second selection electrode layer 118a).

[0058] The partition wall pillars 130 may each have a first diameter D1, and the electrode structures 110a, except for the second selection electrode layer 118a, may each have a second diameter D2′. The vertical electrode 112 may have a third diameter D3. The third diameter D3 may have a value smaller than each of the first diameter D1 and the second diameter D2′. In some embodiments, the first diameter D1 and the second diameter D2′ may have substantially the same value. The second width W2 of the gate electrode 122a between the electrode structure 110a and the partition wall pillars 130 in the first horizontal direction (x direction) may be less than Figure 1A The gate electrode 122 is shown to have a first width W1. For example, the second width W2 may be smaller than the first width W1 by as much as the thickness of the second selection electrode layer 118a.

[0059] and Figure 1A Similar to the semiconductor memory device 100 of the present embodiment, the semiconductor memory device 100a of the present embodiment can have increased integration, improved operation speed, increased programming current and reduced tilt defects. In addition, the semiconductor memory device 100a has a structure in which the switching elements of the switching material layer 116a are separated from each other in the vertical direction (z direction), thereby preventing diffusion between cells and improving the reliability of the memory device.

[0060] FIG. 3A to FIG. 3C 1 is a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment. FIG. 3A to FIG. 3C References will be briefly described or omitted. Figures 1A to 2C A repeated description of the content described.

[0061] refer to FIG. 3A to FIG. 3C The configuration of the electrode structure 110b of the semiconductor memory device 100b may be similar to Figure 1A The configuration of the electrode structure 110 of the semiconductor memory device 100 is different. Specifically, the semiconductor memory device 100b may include a substrate 101, a plurality of electrode structures 110b, a gate stack structure 120b and a plurality of insulating structures 150. The substrate 101, the gate stack structure 120b and the insulating structure 150 are the same as those described above. Figure 1A The substrate 101, the gate stack structure 120 and the insulating structure 150 of the semiconductor memory device 100 are the same.

[0062] like Figure 3AAs shown, the electrode structure 110b can be arranged into a two-dimensional array structure in the xy plane. Specifically, the electrode structure 110b forms a line in the second horizontal direction (y direction) and can be separated from each other in the second horizontal direction (y direction) by the partition wall column 130. In addition, the electrode structure 110b on two lines adjacent to each other in the first horizontal direction (x direction) can be connected to the gate electrode 122b of the gate stack structure 120b. In addition, the electrode structure 110b constituting a line in the second horizontal direction (y direction) can be arranged in a zigzag shape along the second horizontal direction (y direction) on two lines adjacent to each other along the first horizontal direction (x direction), and can have an offset of 1 / 2 pitch in the second horizontal direction (y direction).

[0063] Each of the electrode structures 110b may include a vertical electrode 112, a first selection electrode layer 114, a switching material layer 116, and a second selection electrode layer 118b. In some embodiments, at least one of the first selection electrode layer 114 and the second selection electrode layer 118b may be omitted.

[0064] The second selection electrode layer 118b may include a plurality of electrode elements spaced apart from each other for each layer in the vertical direction (z direction). Each electrode element may have two arcs facing each other and surrounding a portion of the switching material layer 116. For example, the electrode elements of the second selection electrode layer 118b may be arranged in an arc shape only on the layer where the gate electrode 122b of the gate stack structure 120b is located. In particular, as shown in FIG. Figure 3A and Figure 3C It can be seen that each of the electrode elements of the second selection electrode layer 118b may have a ring shape surrounding the switching material layer 116 without a portion contacting the two partition wall pillars 130 in the second horizontal direction (y direction). For example, the arc-shaped side surface of the electrode element of the second selection electrode layer 118b may face the partition wall pillars 130. Therefore, the switching material layer 116 may contact the partition wall pillars 130 in the second horizontal direction (y direction). The electrode elements of the second selection electrode layer 118b may be spaced apart from the electrode elements of other layers in the vertical direction (z direction) and separated from each other.

[0065] FIG. 4A to FIG. 4C 1 is a plan view, a cross-sectional view, and a perspective view of a semiconductor memory device according to an embodiment. FIG. 4A to FIG. 4C References will be briefly described or omitted. Figures 1A to 3C A repeated description of the content described.

[0066] refer to FIG. 4A to FIG. 4C In the semiconductor memory device 100c, the structure of the plurality of insulating structures 155 may be similar to Figure 1A The structure of the plurality of insulating structures 150 of the semiconductor memory device 100 is different from that of Figures 1A to 3C Unlike the multiple insulating structures 150 shown, the multiple insulating structures 155 may have a linear shape. The multiple insulating structures 155 may include multiple partitioning pillars 135 and multiple trimming patterns 145. Specifically, the semiconductor memory device 100c may include a substrate 101, multiple electrode structures 110, a gate stack structure 120c, and multiple insulating structures 155. The substrate 101, the multiple electrode structures 110, and the gate stack structure 120c are similar to those described above. Figure 1A The substrate 101, the plurality of electrode structures 110, and the gate stack structure 120 of the semiconductor memory device 100 are the same. However, in the case of the gate stack structure 120c, at the portion in contact with the partition wall pillar 135, the width of the gate electrode 122c in the first horizontal direction (x direction) may be greater than Figure 1A The gate electrode 122 in the first horizontal direction (x direction) is wide.

[0067] In a cell block BLK included in a semiconductor memory device 100c, a plurality of electrode structures 110 and a plurality of insulating structures 155 may be alternately arranged along a path having a U-shaped structure forming a fuzz shape in a plan view. That is, the plurality of electrode structures 110 and the plurality of insulating structures 155 may form a fuzz shape of a U-shaped pattern in a plan view. The plurality of electrode structures 110 and the plurality of insulating structures 155 included in a cell block BLK may be alternately arranged to have at least two U-shaped structures forming a fuzz shape in a plan view, and may be connected to each other to form a folded structure FSa. The folded structure FSa may be arranged so that at least two insulating structures 155 face a second horizontal direction (y direction) or an opposite direction of the second horizontal direction (y direction), wherein each of the at least two insulating structures 155 is a protrusion of each fuzz shape. Although Figure 4A The folded structure FSa is shown to have two U-shaped structures forming a fluff shape, but the folded structure FSa is not limited thereto. For example, the folded structure FSa may have more than two U-shaped structures forming a fluff shape.

[0068] although Figure 4A It is shown that the plurality of electrode structures 110 are not arranged at the end of each fuzz-shaped protrusion of the folding structure FSa, but the embodiment is not limited thereto, and Figure 4A The plurality of electrode structures 110 shown may be Figure 1A The arrangement shown is at the end of each villi-shaped protrusion of the folded structure FSa.

[0069] Each of the plurality of partition wall pillars 135 may be arranged between the electrode structures 110 arranged along the second horizontal direction (y direction). The partition wall pillar 135 has a substantially quadrilateral shape, but some outer portions may be invaded by the electrode structures 110 arranged on both sides along the second horizontal direction (y direction). Therefore, the partition wall pillar 135 may include a concave portion Cc located at both sides in the second horizontal direction (y direction). The partition wall pillar 135 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In the semiconductor memory device 100c, the partition wall pillar 135 may include silicon oxide. However, the material of the partition wall pillar 135 is not limited to silicon oxide. For reference, Figure 4C The interlayer insulating layer 124 and the partition wall columns 135 are omitted, and the empty space between the electrode structures 110 in the second horizontal direction (y direction) may correspond to the partition wall columns 135, and the empty space between the gate electrodes 122 in the vertical direction (z direction) may correspond to the interlayer insulating layer 124.

[0070] A plurality of trimming patterns 145 may be arranged on both edge portions of the cell block BLK along the second horizontal direction (y direction). Here, the cell block BLK may be defined by a folding structure FSa, which is composed of a plurality of electrode structures 110 and a plurality of insulating structures 155 that are alternately arranged and connected to each other to have at least two U-shaped structures formed with a fuzz shape in a plan view. In this regard, one cell block BLK may include one folding structure FSa. For example, each of the folding structures FSa spaced apart from each other in a plan view may constitute a separate cell block BLK. Some of the trimming patterns 145 may have a U-shape in a plan view. In some embodiments, when the plurality of electrode structures 110 are arranged in a manner similar to that of the cell block BLK, the trimming patterns 145 may have a U-shape in a plan view. Figure 1A When the plurality of electrode structures 110 are arranged in the same manner as shown, the trimming patterns 145 may all have the same Figure 1A The trim patterns 140 are shown similarly “L” shaped. In this regard, the trim patterns 145 may each include a portion extending along a first horizontal direction (x-direction) and a portion extending along a second horizontal direction (y-direction).

[0071] In addition, the trimming patterns 145 may each have a width covering two adjacent partition wall pillars 135 in the first horizontal direction (x direction). That is, among the lines in which the electrode structure 110 is arranged in the second horizontal direction (y direction), the two adjacent lines in the first horizontal direction (x direction) may contact the trimming pattern 145 arranged below or above along the second horizontal direction (y direction) through the electrode structure 110. The trimming pattern 145 located below in the second horizontal direction (y direction) and the trimming pattern 145 located above in the second horizontal direction (y direction) may be arranged at alternating positions along the second horizontal direction (y direction). In addition, two trimming patterns 145 facing each other in the second horizontal direction (y direction) and adjacent to each other in the first horizontal direction (x direction) may cover a line in which the electrode structure 110 is arranged together along the second horizontal direction (y direction), and may be arranged in a point-symmetrical structure based on any one portion on the line (e.g., the electrode structure 110 in the center portion of the line).

[0072] The trimming pattern 145 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In the semiconductor memory device 100c, a plurality of trimming patterns 145 may be formed together with a plurality of partition wall pillars 135, and the plurality of partition wall pillars 135 and the plurality of trimming patterns 145 may be referred to as a plurality of insulating structures 155. For example, the trimming pattern 145 may include silicon oxide. However, the material of the trimming pattern 145 is not limited to silicon oxide.

[0073] The diameter of the electrode structure 110 may be CD1, the interval between the electrode structure 110 and the partition wall pillar 135 in the first horizontal direction (x direction) may be CD2, and the horizontal width of the plurality of insulating structures 155 having a line shape may be CD3. For example, when the interval PD between the electrode structure 110 and the partition wall pillar 135 in the first horizontal direction (x direction) is about 160 nm, CD1 may be about 120 nm, CD2 may be about 60 nm, and CD3 may be about 80 nm.

[0074] although FIG. 4A to FIG. 4C It is shown that the semiconductor memory device 100c includes a plurality of electrode structures 110, but the embodiment is not limited thereto, and instead of the plurality of electrode structures 110, the semiconductor memory device 100c may include FIG. 2A to FIG. 2C The multiple electrode structures 110a or FIG. 3A to FIG. 3C A plurality of electrode structures 110b are shown.

[0075] Figure 5A and Figure 5B are a plan view and a block diagram of a semiconductor memory device according to an embodiment.

[0076] refer to Figure 5A and Figure 5B, the semiconductor memory device 1 has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The plurality of pad regions PR-U and PR-B and the plurality of cell regions CR may be arranged alternately along a first horizontal direction (x direction). The semiconductor memory device 1 includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 1 may include a block group arranged along a first horizontal direction (x direction). Each block group may include a first cell block BLK-1, a second cell block BLK-2, a third cell block BLK-3, and a fourth cell block BLK-4 sequentially arranged along a second horizontal direction (y direction). One cell block included in each block group may be arranged along a first horizontal direction (x direction), and a plurality of cell blocks may be arranged along a second horizontal direction (y direction). For example, a block group may include a first block group ("left") arranged on the left and a second block group ("right") arranged on the right.

[0077] The first cell block BLK-1, the second cell block BLK-2, the third cell block BLK-3, and the fourth cell block BLK-4 sequentially arranged along the second horizontal direction (y direction) in the first block group "left" arranged on the left side may be referred to as the first left cell block, the second left cell block, the third left cell block, and the fourth left cell block, and the first cell block BLK-1, the second cell block BLK-2, the third cell block BLK-3, and the fourth cell block BLK-4 sequentially arranged along the second horizontal direction (v direction) in the second block group "right" arranged on the right side may be referred to as the first right cell block, the second right cell block, the third right cell block, and the fourth right cell block. The first left cell block, the second left cell block, the third left cell block, and the fourth left cell block may be arranged along the first horizontal direction (x direction) together with the first right cell block, the second right cell block, the third right cell block, and the fourth right cell block, respectively.

[0078] Each of the plurality of unit blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folding structure FS / FSa. The folding structure FS / FSa may be Figures 1A to 3C The folded structure FS shown or FIG. 4A to FIG. 4C The folded structure FSa is shown.

[0079] The folding structure FS / FSa included in the first cell block BLK-1 and the folding structure FS / FSa included in the second cell block BLK-2 may be symmetrically arranged based on a straight line extending along the first horizontal direction (x direction) between the first cell block BLK-1 and the second cell block BLK-2. Similarly, the folding structure FS / FSa included in the third cell block BLK-3 and the folding structure FS / FSa included in the fourth cell block BLK-4 may be symmetrically arranged based on a straight line extending along the first horizontal direction (x direction) between the third cell block BLK-3 and the fourth cell block BLK-4. The folding structure FS / FSa included in the first cell block BLK-1, the second cell block BLK-2, the third cell block BLK-3 and the fourth cell block BLK-4 (i.e., the first left cell block, the second left cell block, the third left cell block and the fourth left cell block) included in the first block group "left" and the folding structure FS / FSa included in the first cell block BLK-1, the second cell block BLK-2, the third cell block BLK-3 and the fourth cell block BLK-4 (i.e., the first right cell block, the second right cell block, the third right cell block and the fourth right cell block) included in the second block group "right" can be arranged symmetrically based on a straight line extending along the second horizontal direction (y direction) between the first block group "left" and the second block group "right".

[0080] For each layer in the vertical direction, the semiconductor memory device 1 may include three plate electrodes corresponding to four cell blocks. For example, for each layer in the vertical direction, the three plate electrodes may correspond to the first left cell block, the second left cell block, the first right cell block, and the second right cell block. Alternatively, for example, for each layer in the vertical direction, the three plate electrodes may correspond to the third left cell block, the fourth left cell block, the third right cell block, and the fourth right cell block. The plate electrode may include a pad portion, an axis portion, and a sawtooth portion. The three plate electrodes corresponding to the four cell blocks may include an odd plate electrode PE-O and two even plate electrodes PE-EL and PE-ER. The two even plate electrodes PE-EL and PE-ER may include a first even plate electrode PE-EL arranged on the left and a second even plate electrode PE-ER arranged on the right. In the following, although described based on the first left cell block, the second left cell block, the first right cell block, and the second right cell block, the same manner may also be applied to the third left cell block, the fourth left cell block, the third right cell block, and the fourth right cell block.

[0081] The odd plate electrode PE-O may include an odd pad portion POP, an odd axis portion POS extending from the odd pad portion POP, and a plurality of odd sawtooth portions POT extending from the odd axis portion POS. Each of the first even plate electrode PE-EL and the second even plate electrode PE-ER may include an even pad portion PEP, an even axis portion PES extending from the even pad portion PEP, and a plurality of even sawtooth portions PET extending from the even axis portion PES. The odd pad portion POP and the even pad portion PEP may extend in the second horizontal direction (y direction), the odd axis portion POS and the even axis portion PES may extend in the first horizontal direction (x direction), and the odd sawtooth portion POT and the even sawtooth portion PET may extend in the second horizontal direction (y direction).

[0082] The even pad portion PEP, the even axis portion PES, and the even sawtooth portion PET of the first even plate electrode PE-EL may be referred to as the first even pad portion, the first even axis portion, and the first even sawtooth portion, and the even pad portion PEP, the even axis portion PES, and the even sawtooth portion PET of the second even plate electrode PE-ER may be referred to as the second even pad portion, the second even axis portion, and the second even sawtooth portion. The odd pad portion POP, the odd axis portion POS, and the odd sawtooth portion POT of the odd plate electrode PE-O may be integrally connected, and the even pad portion PEP, the even axis portion PES, and the even sawtooth portion PET of each of the first even plate electrode PE-EL and the second even plate electrode PE-ER may be integrally connected.

[0083] A plurality of cell regions CR and a plurality of pad regions PR-U and PR-B may be alternately arranged along a first horizontal direction (x direction). The plurality of pad regions PR-U and PR-B may include a first pad region PR-U and a second pad region PR-B. The second pad region PR-B may be located between an even number of adjacent cell regions CR in the first horizontal direction (x direction), and the first pad region PR-U may be located at both ends of the plurality of cell regions CR in the first horizontal direction (x direction).

[0084] The first even-numbered axis portion and the plurality of first even-numbered sawtooth portions of the first even-numbered plate electrode PE-EL may be the first left unit block and the second left unit block. Figure 1A , Figure 1C , Figure 2A , Figure 2C , Figure 3A and Figure 3C The first plate electrode PE1 of the first left unit block and the odd-numbered plate electrode PE-0 and the odd-numbered axis portion POS and the plurality of odd-numbered sawtooth portions POT may be the first left unit block and the second left unit block. Figure 1A , Figure 1C , Figure 2A , Figure 2C , Figure 3A and Figure 3C The second plate electrode PE2. The odd-numbered axis portion POS and the plurality of odd-numbered sawtooth portions POT of the odd-numbered plate electrode PE-O may be the first plate electrode PE1 of the first right unit block and the second right unit block, and the second even-numbered axis portion and the plurality of second even-numbered sawtooth portions of the second even-numbered plate electrode PE-ER may be the second plate electrode PE2 of the first right unit block and the second right unit block. That is, the odd-numbered axis portion POS and the plurality of odd-numbered sawtooth portions POT of the odd-numbered plate electrode PE-O may be the second plate electrode PE2 of the first left unit block and the second left unit block and the first plate electrode PE1 of the first right unit block and the second right unit block.

[0085] Each of the first even pad portion of the first even plate electrode PE-EL and the second even pad portion of the second even plate electrode PE-ER may be arranged in the first pad region PR-U, and the odd pad portion POP of the odd plate electrode PE-O may be arranged in the second pad region PR-B.

[0086] When the first even pad portion of the first even plate electrode PE-EL is connected to the first plate electrode PE1 of the first left unit block and the second left unit block, the first even pad portion is shared by the first left unit block and the second left unit block. When the odd pad portion POP of the odd plate electrode PE-O is connected to the second plate electrode PE2 of the first left unit block and the second left unit block and the first plate electrode PE1 of the first right unit block and the second right unit block, the odd pad portion POP is shared by the first left unit block, the second left unit block, the first right unit block and the second right unit block. The second even pad portion of the second even plate electrode PE-ER can be shared by the first right unit block and the second right unit block to correspond to the pad connected to the second plate electrode PE2 of the first right unit block and the second right unit block.

[0087] Each of the first even pad portion of the first even plate electrode PE-EL and the second even pad portion of the second even plate electrode PE-ER can be connected to one of the cell blocks arranged along the first horizontal direction (x direction), and can be connected to two of the cell blocks arranged along the second horizontal direction (y direction) to be connected to the two cell blocks, respectively. The odd pad portion POP of the odd plate electrode PE-O can be connected to two rows of cell blocks arranged along the first horizontal direction (x direction), and can be connected to two columns of cell blocks arranged along the second horizontal direction (y direction) to be connected to four cell blocks.

[0088] As the number of memory cell stacks in the vertical direction increases, the area of ​​the pads in the form of steps for connecting to the memory cells increases. However, in the semiconductor memory device 1 according to the embodiment, for each layer in the vertical direction, three pads can correspond to four cell blocks, so that the area occupied by the stepped pads in the semiconductor memory device 1 is reduced, thereby improving the integration of the semiconductor memory device 1.

[0089] Fig. 6A and Figure 6B is a plan view of a semiconductor memory device according to an embodiment. Fig. 6A and Figure 6B References will be briefly described or omitted. Figure 5A and Figure 5B A repeated description of the content described.

[0090] refer to Fig. 6A , the semiconductor memory device 1a has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The semiconductor memory device 1a includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 1a may include a block group arranged along a first horizontal direction (x direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folded structure FS / FSa.

[0091] The folding structure FS / FSa included in each of the first left unit block, the second left unit block, the third left unit block, and the fourth left unit block has the same structure and can be arranged along the second horizontal direction (y direction), and the folding structure FS / FSa included in each of the first right unit block, the second right unit block, the third right unit block, and the fourth right unit block has the same structure and can be arranged along the second horizontal direction (y direction). The folding structure FS / FSa included in each of the first left unit block, the second left unit block, the third left unit block, and the fourth left unit block and the folding structure FS / FSa included in each of the first right unit block, the second right unit block, the third right unit block, and the fourth right unit block can be symmetrically arranged with respect to a straight line extending between the first block group "left" and the second block group "right" along the second horizontal direction (y direction).

[0092] The semiconductor memory device 1a may include an odd plate electrode PE-Oa, a first even plate electrode PE-ELa, and a second even plate electrode PE-ERa. The odd plate electrode PE-Oa, the first even plate electrode PE-ELa, and the second even plate electrode PE-ERa are generally connected to Figure 5AThe odd plate electrode PE-O, the first even plate electrode PE-EL and the second even plate electrode PE-ER shown are the same. However, the arrangement of the even axis portion PES and the even sawtooth portion PET connected thereto, and / or the arrangement of the odd axis portion POS and the odd sawtooth portion POT connected thereto may vary according to the arrangement of the folding structure FS / FSa included in each of the plurality of unit blocks BLK-1, BLK-2, BLK-3 and BLK-4. For example, Figure 5A The two even-numbered axis portions PES included in the first even-numbered plate electrode PE-EL or the second even-numbered plate electrode PE-ER are shown to extend to the upper side of one of the corresponding two folding structures FS / FSa and the lower side of the other folding structure FS / FSa. Fig. 6A Each of the two even-numbered axis portions PES included in the first even-numbered plate electrode PE-ELa or the second even-numbered plate electrode PE-ERa shown extends to the upper side of each of the corresponding two folded structures FS / FSa. Similarly, Figure 5A The two odd-numbered axis portions POS included in the odd-numbered plate electrode PE-O shown extend to the upper side of one of the corresponding two folding structures FS / FSa and the lower side of the other folding structure FS / FSA. Fig. 6A Each of the four odd-numbered axis portions POS included in the illustrated odd-numbered plate electrode PE-Oa extends to the lower side of each of the corresponding two folded structures FS / FSa.

[0093] refer to Figure 6B , the semiconductor memory device 1b has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The semiconductor memory device 1b includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 1b may include a block group arranged along a first horizontal direction (x direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folding structure FS / FSa. The folding structures FS / FSa included in the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 (i.e., a first left cell block, a second left cell block, a third left cell block, a fourth left cell block, a first right cell block, a second right cell block, a third right cell block, and a fourth right cell block) may be arranged in the same structure.

[0094] The semiconductor memory device 1b may include an odd plate electrode PE-Ob, a first even plate electrode PE-ELb, and a second even plate electrode PE-ERb. The odd plate electrode PE-Ob, the first even plate electrode PE-ELb, and the second even plate electrode PE-ERb are generally connected to Figure 5AThe odd plate electrode PE-O, the first even plate electrode PE-EL and the second even plate electrode PE-ER shown are the same. However, the arrangement of the even axis portion PES and the even sawtooth portion PET connected thereto, and / or the arrangement of the odd axis portion POS and the odd sawtooth portion POT connected thereto may vary according to the arrangement of the folding structure FS / FSa included in each of the plurality of unit blocks BLK-1, BLK-2, BLK-3 and BLK-4. For example, Figure 6B Each of the two even-numbered axis portions PES included in the first even-numbered plate electrode PE-ELb shown extends to the upper side of each of the corresponding two folding structures FS / FSa, and each of the two even-numbered axis portions PES included in the second even-numbered plate electrode PE-ERb extends to the lower side of each of the corresponding two folding structures FS / FSa. Among the four odd-numbered axis portions POS included in the odd-numbered plate electrode PE-Ob, each of the two odd-numbered axis portions POS corresponding to the folding structure FS / FSa arranged in the first block group "left" extends to the lower side of each of the corresponding folding structures FS / FSa, and each of the two odd-numbered axis portions POS corresponding to the folding structure FS / FSa arranged in the second block group "right" extends to the upper side of each of the corresponding folding structures FS / FSa.

[0095] Fig. 7A and Figure 7B 1 is a plan view and a block diagram of a semiconductor memory device according to an embodiment. Fig. 7A and Figure 7B References will be briefly described or omitted. FIG. 5A to FIG. 6B A repeated description of the content described.

[0096] refer to Fig. 7A and Figure 7B , the semiconductor memory device 2 has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The semiconductor memory device 2 includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 2 may include a block group arranged along a first horizontal direction (x direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folded structure FS / FSa.

[0097] The semiconductor memory device 2 may include an odd plate electrode PE-Oc, a first even plate electrode PE-ELc, and a second even plate electrode PE-ERc. The odd plate electrode PE-Oc, the first even plate electrode PE-ELc, and the second even plate electrode PE-ERc are generally connected to Figure 5AThe odd plate electrode PE-O, the first even plate electrode PE-EL, and the second even plate electrode PE-ER shown are the same, but the number of unit blocks connected to the odd plate electrode PE-Oc, the first even plate electrode PE-ELc, and the second even plate electrode PE-ERc can vary. Each of the first even pad portion of the first even plate electrode PE-ELc and the second even pad portion of the second even plate electrode PE-ERc can be connected to a column of unit blocks arranged along the second horizontal direction (y direction), and can be connected to four rows of unit blocks arranged along the first horizontal direction (x direction) to be connected to four unit blocks, respectively. The odd pad portion POP of the odd plate electrode PE-Oc can be connected to two unit blocks arranged in a row extending along the first horizontal direction (x direction), and can be connected to four unit blocks arranged in a column extending along the second horizontal direction (y direction) to be connected to eight unit blocks.

[0098] In the semiconductor memory device 2 , for each layer in the vertical direction, three pads may correspond to eight cell blocks, so that the area occupied by the stepped pads in the semiconductor memory device 2 is reduced, thereby improving the integration of the semiconductor memory device 2 .

[0099] exist Figure 5A and Figure 5B In the semiconductor memory device 1 shown in the figure, it is shown that for each layer in the vertical direction, three pads correspond to four cell blocks, and Fig. 7A and Figure 7B In the semiconductor memory device 2 shown, it is shown that for each layer in the vertical direction, three pads correspond to eight cell blocks, but the embodiment is not limited thereto. For example, in the semiconductor memory device according to the embodiment, for each layer in the vertical direction, three pads may correspond to six cell blocks or ten or more cell blocks, i.e., an even number of cell blocks. That is, in the semiconductor memory device according to the embodiment, for each layer in the vertical direction, three pads may correspond to 2×k cell blocks (k is an integer of 2 or greater).

[0100] Fig. 8A and Figure 8B is a plan view of a semiconductor memory device according to an embodiment. Fig. 8A and Figure 8B References will be briefly described or omitted. FIG. 5A to FIG. 7B A repeated description of the content described.

[0101] refer to Fig. 8A, the semiconductor memory device 2a has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The semiconductor memory device 2a includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 2a may include a block group arranged along a first horizontal direction (x direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folded structure FS / FSa.

[0102] The folding structure FS / FSa included in each of the first left unit block, the second left unit block, the third left unit block, and the fourth left unit block has the same structure and can be arranged along the second horizontal direction (y direction), and the folding structure FS / FSa included in each of the first right unit block, the second right unit block, the third right unit block, and the fourth right unit block has the same structure and can be arranged along the second horizontal direction (y direction). The folding structure FS / FSa included in each of the first left unit block, the second left unit block, the third left unit block, and the fourth left unit block and the folding structure FS / FSa included in each of the first right unit block, the second right unit block, the third right unit block, and the fourth right unit block can be symmetrically arranged with respect to a straight line extending between the first block group "left" and the second block group "right" along the second horizontal direction (y direction).

[0103] The semiconductor memory device 2a may include an odd plate electrode PE-Od, a first even plate electrode PE-ELd, and a second even plate electrode PE-ERd. The odd plate electrode PE-Od, the first even plate electrode PE-ELd, and the second even plate electrode PE-ERd are generally connected to Fig. 7A The odd plate electrode PE-Oc, the first even plate electrode PE-ELc and the second even plate electrode PE-ERc shown are the same. However, the arrangement of the even axis portion PES and the even sawtooth portion PET connected thereto, and / or the arrangement of the odd axis portion POS and the odd sawtooth portion POT connected thereto may vary according to the arrangement of the folding structure FS / FSa included in each of the multiple unit blocks BLK-1, BLK-2, BLK-3 and BLK-4. For example, each of the two even axis portions PES included in the first even plate electrode PE-ELd extends to the upper side of each of the corresponding folding structures FS / FSa, and each of the even axis portions PES included in the second even plate electrode PE-ERd extends to the upper side of each of the corresponding folding structures FS / FSa. Each of the odd axis portions POS included in the odd plate electrode PE-Od extends to the lower side of each of the corresponding folding structures FS / FSa.

[0104] refer to Figure 8B, the semiconductor memory device 2b has a plurality of cell regions CR and a plurality of pad regions PR-U and PR-B. The semiconductor memory device 2b includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 2b may include a block group arranged along a first horizontal direction (x direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folding structure FS / FSa. The folding structure FS / FSa included in the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 (i.e., a first left cell block, a second left cell block, a third left cell block, a fourth left cell block, a first right cell block, a second right cell block, a third right cell block, and a fourth right cell block) may be arranged in the same structure.

[0105] The semiconductor memory device 2b may include an odd plate electrode PE-Oe, a first even plate electrode PE-ELe, and a second even plate electrode PE-ERe. The odd plate electrode PE-Oe, the first even plate electrode PE-ELe, and the second even plate electrode PE-ERe are generally similar to Fig. 7A The odd plate electrode PE-Oc, the first even plate electrode PE-ELc, and the second even plate electrode PE-ERc shown are the same. However, the arrangement of the even axis portion PES and the even sawtooth portion PET, and / or the arrangement of the odd axis portion POS and the odd sawtooth portion POT may vary according to the arrangement of the folding structure FS / FSa included in each of the plurality of unit blocks BLK-1, BLK-2, BLK-3, and BLK-4. For example, Figure 8B Each of the even-numbered axis portions PES included in the first even-numbered plate electrode PE-ELe shown extends to the upper side of each of the corresponding folding structures FS / FSa, and each of the even-numbered axis portions PES included in the second even-numbered plate electrode PE-ERe extends to the lower side of each of the corresponding folding structures FS / FSa. Among the eight odd-numbered axis portions POS included in the odd-numbered plate electrode PE-Oe, each of the odd-numbered axis portions POS corresponding to the folding structure FS / FSa arranged in the first block group "left" extends to the lower side of each of the corresponding folding structures FS / FSa, and each of the odd-numbered axis portions POS corresponding to the folding structure FS / FSa arranged in the second block group "right" extends to the upper side of each of the corresponding folding structures FS / FSa.

[0106] Fig. 9A and Fig. 9B 1 is a plan view and a block diagram of a semiconductor memory device according to an embodiment. Fig. 9A and Fig. 9B References will be briefly described or omitted. FIG. 5A to FIG. 8B A repeated description of the content described.

[0107] refer to Fig. 9A and Fig. 9B , the semiconductor memory device 3 has a plurality of cell regions CR and a plurality of pad regions PR-R. The semiconductor memory device 3 includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 3 may include a plurality of block groups arranged along a first horizontal direction (x direction): the nth group, the n+1th group, the n+2th group, and the n+3th group (n is an integer of 1 or greater). Each of the plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group) may include a first cell block BLK-1, a second cell block BLK-2, a third cell block BLK-3, and a fourth cell block BLK-4 sequentially arranged along a second horizontal direction (y direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folding structure FS / FSa.

[0108] A plurality of repeated plate electrodes PE-R may be arranged between two adjacent block groups in the first horizontal direction (x direction) among the plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group). Each of the plurality of repeated plate electrodes PE-R has the same shape and may be repeatedly arranged between two adjacent block groups in the first horizontal direction (x direction) among the plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group).

[0109] The folding structure FS / FSa included in each of the unit blocks arranged along the first horizontal direction (x direction) may be arranged in the same structure. For example, the folding structure FS / FSa included in each of the first unit blocks BLK-1 included in a plurality of block groups (nth group, n+1th group, n+2th group, and n+3th group) may be arranged in the same structure, the folding structure FS / FSa included in each of the second unit blocks BLK-2 may be arranged in the same structure, the folding structure FS / FSa included in each of the third unit blocks BLK-3 may be arranged in the same structure, and the folding structure FS / FSa included in each of the fourth unit blocks BLK-4 may be arranged in the same structure. The folding structure FS / FSa included in the first unit block BLK-1 and the folding structure FS / FSa included in the second unit block BLK-2 can be symmetrically arranged based on a straight line extending along the first horizontal direction (x direction) between the first unit block BLK-1 and the second unit block BLK-2, the folding structure FS / FSa included in the second unit block BLK-2 and the folding structure FS / FSa included in the third unit block BLK-3 can be symmetrically arranged based on a straight line extending along the first horizontal direction (x direction) between the second unit block BLK-2 and the third unit block BLK-3, and the folding structure FS / FSa included in the third unit block BLK-3 and the folding structure FS / FSa included in the fourth unit block BLK-4 can be symmetrically arranged based on a straight line extending along the first horizontal direction (x direction) between the third unit block BLK-3 and the fourth unit block BLK-4.

[0110] The repeated plate electrode PE-R may include a repeated pad portion PRP, a repeated shaft portion PRS extending from the repeated pad portion PRP, and a plurality of repeated sawtooth portions PRT extending from the repeated shaft portion PRS. The repeated pad portion PRP may be arranged in the pad region PR-R. The repeated pad portion PRP may extend in the second horizontal direction (y direction), the repeated shaft portion PRS may extend in the first horizontal direction (x direction), and the repeated sawtooth portion PRT may extend in the second horizontal direction (y direction). The repeated plate electrode PE-R is generally similar to Fig. 7A , Fig. 8A and Figure 8BThe odd plate electrodes PE-Oc, PE-Od and PE-Oe shown including the odd pad portion POP, the odd axis portion POS and the odd sawtooth portion POT are the same. However, in response to the arrangement of the folding structure FS / FSa included in each of the plurality of unit blocks BLK-1, BLK-2, BLK-3 and BLK-4, the arrangement of the repeated axis portion PRS and the repeated sawtooth portion PRT connected thereto may vary. For example, the repeated axis portion PRS extending to the left from the repeated pad portion PRP included in a repeated plate electrode PE-R along the first horizontal direction (x direction) extends to the upper side of the corresponding folding structure FS / FSa, and the repeated axis portion PRS extending to the right from the repeated pad portion PRP included in a repeated plate electrode PE-R along the first horizontal direction (x direction) extends to the lower side of the corresponding folding structure FS / FSa.

[0111] In some embodiments, with reference to 7A to 8B Even plate electrodes identical or similar to the described first even plate electrodes PE-ELc, PE-ELd and PE-ELe and the second even plate electrodes PE-ERc, PE-ERd and PE-ERe can be connected to block groups arranged at opposite ends along the first horizontal direction (x direction) among multiple block groups (nth group, n+1th group, n+2th group and n+3th group).

[0112] Fig.10 is a plan view of a semiconductor memory device according to an embodiment. Fig.10 References will be briefly described or omitted. FIG. 5A to FIG. 9B A repeated description of the content described.

[0113] refer to Fig.10 , the semiconductor memory device 3a has a plurality of cell regions CR and a plurality of pad regions PR-R. The semiconductor memory device 3a includes a plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 arranged in the cell region CR. The semiconductor memory device 3a may include a plurality of block groups arranged along a first horizontal direction (x direction): the nth group, the n+1th group, the n+2th group, and the n+3th group (n is an integer of 1 or greater). Each of the plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group) may include a first cell block BLK-1, a second cell block BLK-2, a third cell block BLK-3, and a fourth cell block BLK-4 sequentially arranged along a second horizontal direction (y direction). Each of the plurality of cell blocks BLK-1, BLK-2, BLK-3, and BLK-4 may include a folded structure FS / FSa.

[0114] A plurality of repeated plate electrodes PE-Ra may be arranged between two adjacent block groups in the first horizontal direction (x direction) among a plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group). Each of the plurality of repeated plate electrodes PE-Ra has the same shape and may be repeatedly arranged between two adjacent block groups in the first horizontal direction (x direction) among a plurality of block groups (the nth group, the n+1th group, the n+2th group, and the n+3th group). The repeated plate electrodes PE-Ra and Fig. 9A The repeated plate electrodes PE-R shown are substantially the same, but the arrangement of the repeated shaft portions PRS may vary. For example, the repeated shaft portions PRS included in the repeated plate electrode PE-Ra may be arranged along the second horizontal direction (y direction) and may extend alternately to the upper and lower sides of the corresponding folded structures FS / FSa.

[0115] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor memory device, comprising: a plurality of unit blocks, each unit block including a folded structure in which a plurality of electrode structures and a plurality of insulating structures are alternately arranged, wherein the plurality of electrode structures and the plurality of insulating structures extend in a vertical direction and are connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, the plurality of electrode structures including vertical electrodes and a switching material layer, and the plurality of unit blocks are arranged along a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; and A gate stack structure, comprising a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked in the vertical direction along the sidewalls of the plurality of electrode structures, wherein each of the plurality of gate electrodes includes a pad portion and a plurality of plate electrodes spaced apart from each other in each of the plurality of layers, and Wherein, in two unit blocks in the first horizontal direction among the multiple unit blocks and in each of at least two unit blocks in the second horizontal direction among the multiple unit blocks, at least one plate electrode among the multiple plate electrodes is connected to the switching material layer of the multiple electrode structures.

2. The semiconductor memory device according to claim 1, wherein: Each of the plurality of plate electrodes comprises: at least two shaft portions extending from the pad portion; and a plurality of sawtooth portions extending from each of the at least two shaft portions, and Wherein, each of the plurality of sawtooth portions extends into the fluff shape of the folded structure.

3. The semiconductor memory device according to claim 2, wherein: The pad portion extends in the second horizontal direction, the at least two shaft portions extend in the first horizontal direction, and the plurality of sawtooth portions extend in the second horizontal direction.

4. The semiconductor memory device according to claim 2, wherein: Two plate electrodes among the plurality of plate electrodes are connected to the switching material layer of the plurality of electrode structures.

5. The semiconductor memory device according to claim 4, wherein: In two unit blocks arranged along the first horizontal direction among the plurality of unit blocks and in two unit blocks arranged along the second horizontal direction among the plurality of unit blocks, each of the two plate electrodes is connected to the switching material layer of the plurality of electrode structures.

6. The semiconductor memory device according to claim 4, wherein: The two plate electrodes connected to the switching material layer have a comb shape that is staggered with each other.

7. The semiconductor memory device according to claim 1, wherein: The pile shape of the folded structure faces the second horizontal direction.

8. The semiconductor memory device according to claim 1, wherein: The at least one plate electrode is connected to the switching material layer and at least two unit blocks among the plurality of unit blocks disposed along the second horizontal direction.

9. The semiconductor memory device according to claim 1, wherein: The plurality of unit blocks include a first unit block and a second unit block adjacent to each other in the second horizontal direction, and The folding structure of the first unit block and the folding structure of the second unit block are arranged symmetrically with respect to a straight line extending in the first horizontal direction.

10. The semiconductor memory device according to claim 1, wherein The plurality of unit blocks include a first unit block and a second unit block adjacent to each other in the first horizontal direction, and The folding structure of the first unit block and the folding structure of the second unit block are arranged symmetrically with respect to a straight line extending in the second horizontal direction.

11. A semiconductor memory device comprising: A substrate, comprising a plurality of pad regions and a plurality of unit regions, wherein the plurality of pad regions and the plurality of unit regions are alternately arranged along a first horizontal direction; at least two unit blocks sequentially arranged in a second horizontal direction intersecting the first horizontal direction in each of the plurality of unit regions; and The gate stack structure comprises a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked in a vertical direction, wherein each of the plurality of gate electrodes comprises a plurality of plate electrodes spaced apart from each other in each of the plurality of layers, each of the plurality of plate electrodes comprises a pad portion disposed in one of the plurality of pad regions, at least two shaft portions extending from the pad portion to at least one unit region adjacent to the one pad region, and a plurality of sawtooth portions extending from each of the at least two shaft portions, wherein each of the at least two cell blocks arranged in each of the plurality of cell regions comprises a folded structure on the substrate, in which a plurality of electrode structures extending in the vertical direction and a plurality of insulating structures extending in the vertical direction are alternately arranged and connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, wherein the plurality of electrode structures extend into the gate stack structure in the vertical direction and comprise a vertical electrode and a switching material layer, and Wherein, each of the plurality of sawtooth portions extends into the fluff shape and is connected to the switching material layer.

12. The semiconductor memory device according to claim 11, wherein: The pad portion extends in the second horizontal direction, the at least two shaft portions extend from the pad portion in the first horizontal direction, and the plurality of sawtooth portions extend from the at least two shaft portions in the second horizontal direction.

13. The semiconductor memory device according to claim 11, wherein: In at least one plate electrode among the plurality of plate electrodes, the at least two shaft portions are provided in each of two unit regions adjacent to each other in the first horizontal direction among the plurality of unit regions.

14. The semiconductor memory device according to claim 13, wherein: The at least two shaft portions of the at least one plate electrode among the plurality of plate electrodes extend to opposite sides of the corresponding unit block in the second horizontal direction.

15. The semiconductor memory device according to claim 13, wherein: In at least another plate electrode among the plurality of plate electrodes, the at least two shaft portions extend across only one unit region among the plurality of unit regions.

16. The semiconductor memory device according to claim 11, wherein In at least two plate electrodes among the plurality of plate electrodes, the at least two shaft portions extend across two unit regions among the plurality of unit regions.

17. The semiconductor memory device according to claim 11, wherein: Two of the plurality of plate electrodes have a comb shape that is staggered with each other and are connected to the switching material layer of the plurality of electrode structures.

18. The semiconductor memory device according to claim 11, wherein In one plate electrode among the plurality of plate electrodes, one of the at least two axis portions corresponding to one of the at least two unit blocks provided in one of the plurality of unit regions and another of the at least two axis portions corresponding to another of the at least two unit blocks extend to opposite sides of the corresponding unit blocks in the second horizontal direction.

19. A semiconductor memory device comprising: A substrate, comprising a plurality of pad regions and a plurality of unit regions, wherein the plurality of pad regions and the plurality of unit regions are alternately arranged along a first horizontal direction; The plurality of unit blocks in each of the plurality of unit areas include at least two unit blocks sequentially arranged along the first horizontal direction and at least two unit blocks sequentially arranged along a second horizontal direction intersecting the first horizontal direction; and The gate stack structure comprises a plurality of gate electrodes and a plurality of interlayer insulating layers alternately stacked in a vertical direction, wherein each of the plurality of gate electrodes includes a plurality of plate electrodes spaced apart from each other in each of the plurality of layers, each of the plurality of plate electrodes includes a pad portion disposed in one of the plurality of pad regions and extending in the second horizontal direction, at least two shaft portions extending from the pad portion to at least one unit region adjacent to the one pad region among the plurality of unit regions in the first horizontal direction, and a plurality of sawtooth portions extending from each of the at least two shaft portions in the second horizontal direction, wherein each of the plurality of cell blocks arranged in each of the plurality of cell regions comprises a folded structure on the substrate, in which a plurality of electrode structures extending in the vertical direction and a plurality of insulating structures extending in the vertical direction are alternately arranged and connected to each other to have at least two U-shaped structures forming a fuzz shape in a plan view, wherein the plurality of electrode structures extend into the plurality of gate electrodes in the vertical direction and comprise a vertical electrode and a switching material layer, wherein the fuzz shape faces the second horizontal direction, and each of the plurality of serrations extends into the fuzz shape of the folded structure and is connected to the switching material layer, and Among them, in the at least two unit blocks sequentially arranged along the first horizontal direction, at least one plate electrode of the plurality of plate electrodes is connected to the switching material layer of the plurality of electrode structures.

20. The semiconductor memory device according to claim 19, wherein The plurality of sawtooth portions extending from one of the at least two shaft portions of each of two plate electrodes of the plurality of plate electrodes are connected to the switching material layer of the plurality of electrode structures and have comb shapes staggered with each other.

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