Trench-type igbt device with low miller capacitance
By employing cross-shaped trenches and T-type or inverted T-type polysilicon gate structures in IGBT devices, the gate design is optimized, solving the problems of on-state voltage drop and Miller capacitance, improving switching speed and reducing switching losses.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NARI LIANYAN SEMICON CO LTD
- Filing Date
- 2024-11-04
- Publication Date
- 2026-05-19
AI Technical Summary
Existing IGBT devices have shortcomings in terms of on-state voltage drop and Miller capacitance, resulting in slow switching speed and high switching losses.
It employs a cross-shaped trench structure and a T-type or inverted T-type polysilicon gate design, optimizes the gate structure to reduce Miller capacitance and improve the depletion efficiency of the carrier storage layer, and combines the design of the N-type storage layer to reduce the on-state voltage drop.
This achieves lower on-state voltage drop and Miller capacitance, improving switching speed and reducing switching losses.
Smart Images
Figure CN119451146B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor devices, and more particularly to a trench IGBT device with low Miller capacitance. Background Technology
[0002] An insulated-gate bipolar transistor (IGBT) is a novel power electronic device that combines the advantages of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) and bipolar transistors. It possesses the advantages of MOSFETs (high input resistance, easy driving, and simple control) and bipolar transistors (low on-state voltage and high on-state current). It has become one of the core components in modern power electronic circuits and is widely used in transportation, energy, industry, and home appliances.
[0003] Since the advent of IGBTs in the early 1980s, over three decades of development have led to continuous improvements in the structure and manufacturing processes of IGBT devices. Currently, it has evolved to the seventh generation, featuring charge storage type insulated gate bipolar transistors (CSTBTs). The seventh-generation CSTBT introduces a highly doped N-type charge storage layer beneath the surface P-type base region, creating a hole barrier below the P-type base region. This significantly increases the hole concentration near the emitter during forward conduction, resulting in a lower forward voltage drop. However, with the continuous increase in the doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device has decreased significantly. Furthermore, as cell widths decrease and trench densities increase, gate capacitance also increases. This increased gate capacitance leads to slower switching speeds, thereby increasing switching losses. Summary of the Invention
[0004] Purpose of the invention: The purpose of this invention is to provide a trench IGBT device with low Miller capacitance, which effectively reduces Miller capacitance and on-state voltage drop.
[0005] Technical solution: The trench IGBT device with low Miller capacitance of the present invention includes, from bottom to top, a collector metal, a P-type collector region, an N-type field cutoff layer, and an N-type drift region. Above the N-type drift region, an N-type storage layer, a P-type body region, and an emitter metal are arranged in sequence. An N+ contact region is provided in the P-type body region. A first oxide layer dielectric is provided at the bottom center of the emitter metal.
[0006] Preferably, the cross-shaped groove is symmetrical from left to right, and its top end is flush with the bottom end of the emitter metal.
[0007] Preferably, the bottom of the cross-shaped trench is provided with a second oxide layer dielectric and a first gate polysilicon that divides the second oxide layer dielectric into left and right parts, the top of the cross-shaped trench is provided with a third oxide layer dielectric and a second gate polysilicon that divides the third oxide layer dielectric into left and right parts, and the top of the second gate polysilicon is flush with the bottom of the emitter metal.
[0008] Preferably, the bottom end of the N-type memory layer is not lower than the bottom end of the first gate polysilicon.
[0009] Preferably, the N-type drift region is provided with a cross-shaped groove, which divides the N-type drift region, the N-type storage layer, the P-type body region and the N+ contact region into left and right parts.
[0010] Preferably, a line-shaped polysilicon gate is provided between the first gate polysilicon and the second gate polysilicon, and the line-shaped polysilicon gate is in contact with the first gate polysilicon to form a T-shaped polysilicon gate.
[0011] More preferably, the length of the linear polysilicon gate is greater than the width of the second gate polysilicon.
[0012] More preferably, the potential of the T-type polysilicon gate is equal to the potential of the emitter metal.
[0013] Preferably, a line-shaped polysilicon gate is provided between the first gate polysilicon and the second gate polysilicon, and the line-shaped polysilicon gate is in contact with the second gate polysilicon to form an inverted T-shaped polysilicon gate.
[0014] More preferably, the length of the linear polysilicon gate is greater than the width of the first gate polysilicon.
[0015] More preferably, the potential of the inverted T-shaped polysilicon gate is equal to the potential of the emitter metal.
[0016] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) In the reverse blocking state of the device, the wide part of the cross-shaped trench can effectively assist in the depletion of the N-type carrier storage layer. Therefore, under the same breakdown voltage, the structure has a higher concentration of N-type carrier storage layer, thereby having a lower on-state voltage drop; (2) The trench-type IGBT device with low Miller capacitance provided by the present invention has a wider T-type polysilicon gate width than the width of the first gate polysilicon (or a wider inverted T-type polysilicon gate width than the width of the second gate polysilicon). During the switching process of the device, the change of the gate signal is effectively shielded by the wider T-type or inverted T-type polysilicon, thereby having a lower Miller capacitance, faster switching speed, and lower switching loss; (3) In the reverse blocking state of the device, the wide part of the T-type or inverted T-type trench can effectively assist in the depletion of the N-type carrier storage layer. Therefore, under the same breakdown voltage, the IGBT device has a higher concentration of N-type carrier storage layer, thereby having a lower on-state voltage drop. Attached Figure Description
[0017] Figure 1This is a schematic diagram of the cell structure of the trench IGBT device with low Miller capacitance described in Example 1;
[0018] Figure 2 This is a schematic diagram of the cell structure of the trench IGBT device with low Miller capacitance described in Example 2;
[0019] Figure 3 This is a schematic diagram of the cell structure of the trench IGBT device with low Miller capacitance described in Example 3. Detailed Implementation
[0020] The technical solution of the present invention will be further described below with reference to the embodiments.
[0021] Example 1
[0022] like Figure 1 As shown, the low Miller capacitance trench IGBT device of the present invention includes, from bottom to top, a collector metal 1, a P-type collector region 2, an N-type field cutoff layer 3, and an N-type drift region 4. Above the N-type drift region 4, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence. An N+ contact region 7 is provided in the P-type body region 6, and a first oxide dielectric layer 8 is provided at the bottom center of the emitter metal 9. A cross-shaped trench is provided in the N-type drift region 4, which divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into left and right parts.
[0023] The cross-shaped groove is symmetrical from left to right, and its top is flush with the bottom of the emitter metal 9.
[0024] The bottom of the cross-shaped trench is provided with a second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into left and right parts. The top of the cross-shaped trench is provided with a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into left and right parts. The top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.
[0025] The bottom of the N-type memory layer 5 is not lower than the bottom of the first gate polysilicon 11.
[0026] A T-shaped polysilicon gate 14 is provided between the first gate polysilicon 11 and the second gate polysilicon 13. The T-shaped polysilicon gate 14 is in contact with the first gate polysilicon 11 to form a T-shaped polysilicon gate.
[0027] The length of the linear polysilicon gate 14 is greater than the width of the second gate polysilicon 13.
[0028] The potential of the T-type polysilicon gate is equal to the potential of the emitter metal 9.
[0029] The working principle of the low Miller capacitance trench IGBT device described in this invention is as follows:
[0030] When collector metal 1 is positively biased, and the second gate polysilicon 13, T-type polysilicon gate, and emitter metal 9 are connected to a low voltage, the device is in a blocking state. In this state, the T-type polysilicon gate helps deplete the N-type memory layer 5, effectively reducing the impact of the N-type memory layer 5 on the device's breakdown voltage. When collector metal 1 is positively biased, the second gate polysilicon 13 is positively biased at a voltage higher than the device threshold voltage, and the T-type polysilicon gate and emitter metal 9 are connected to a low voltage, the device is in a conducting state. In this state, the N-type memory layer 5 forms a hole barrier, effectively increasing the carrier concentration on the emitter side, thus significantly reducing the device's on-resistance and consequently lowering the on-voltage drop.
[0031] Example 2
[0032] like Figure 2 As shown, the low Miller capacitance trench IGBT device of the present invention includes, from bottom to top, a collector metal 1, a P-type collector region 2, an N-type field cutoff layer 3, and an N-type drift region 4. Above the N-type drift region 4, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence. An N+ contact region 7 is provided in the P-type body region 6, and a first oxide dielectric layer 8 is provided at the bottom center of the emitter metal 9. A cross-shaped trench is provided in the N-type drift region 4, which divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into left and right parts.
[0033] The cross-shaped groove is symmetrical from left to right, and its top is flush with the bottom of the emitter metal 9.
[0034] The bottom of the cross-shaped trench is provided with a second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into left and right parts. The top of the cross-shaped trench is provided with a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into left and right parts. The top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.
[0035] The bottom of the N-type memory layer 5 is not lower than the bottom of the first gate polysilicon 11.
[0036] Example 3
[0037] like Figure 3As shown, the low Miller capacitance trench IGBT device of the present invention includes, from bottom to top, a collector metal 1, a P-type collector region 2, an N-type field cutoff layer 3, and an N-type drift region 4. Above the N-type drift region 4, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence. An N+ contact region 7 is provided in the P-type body region 6, and a first oxide dielectric layer 8 is provided at the bottom center of the emitter metal 9. A cross-shaped trench is provided in the N-type drift region 4, which divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6, and the N+ contact region 7 into left and right parts.
[0038] The cross-shaped groove is symmetrical from left to right, and its top is flush with the bottom of the emitter metal 9.
[0039] The bottom of the cross-shaped trench is provided with a second oxide layer dielectric 10 and a first gate polysilicon 11 that divides the second oxide layer dielectric 10 into left and right parts. The top of the cross-shaped trench is provided with a third oxide layer dielectric 12 and a second gate polysilicon 13 that divides the third oxide layer dielectric 12 into left and right parts. The top of the second gate polysilicon 13 is flush with the bottom of the emitter metal 9.
[0040] The bottom of the N-type memory layer 5 is not lower than the bottom of the first gate polysilicon 11.
[0041] A line-shaped polysilicon gate 14 is provided between the first gate polysilicon 11 and the second gate polysilicon 13. The line-shaped polysilicon gate 14 is in contact with the second gate polysilicon 12 to form an inverted T-shaped polysilicon gate.
[0042] The length of the linear polysilicon gate 14 is greater than the width of the first gate polysilicon 11.
[0043] The potential of the inverted T-type polysilicon gate is equal to the potential of the emitter metal 9.
[0044] Comparison of the advantages and effects of the three structures:
[0045] (1) In the structure of Example 1, the first gate polysilicon 11 has the strongest shielding effect on the second gate polysilicon 13 and the fastest switching speed; and because there is a wide lateral portion, it is beneficial to assist in depleting the carrier storage layer, so the withstand voltage is also high and the on-state voltage drop is low.
[0046] (2) The shielding effect of the first gate polysilicon 11 on the second gate polysilicon 13 is not as good as in Example 1, and the switching speed is relatively slower; however, there is no lateral wide part, which is not conducive to assisting in the depletion of the carrier storage layer, so the withstand voltage is lower than that in Example 1, and the on-state voltage drop is higher. However, its device structure is simpler and the manufacturing cost is lower.
[0047] (3) The shielding effect of the first gate polysilicon 11 on the second gate polysilicon 3 is not as good as in Examples 1 and 2, and the switching speed is relatively slower.
Claims
1. A trench IGBT device with low Miller capacitance, comprising, from bottom to top, a collector metal (1), a P-type collector region (2), an N-type field cutoff layer (3), and an N-type drift region (4), wherein an N-type storage layer (5), a P-type body region (6), and an emitter metal (9) are sequentially disposed above the N-type drift region (4), an N+ contact region (7) is disposed within the P-type body region (6), and a first oxide dielectric layer (8) is disposed at the bottom center of the emitter metal (9), characterized in that, The N-type drift region (4) is provided with a cross-shaped trench; the bottom of the cross-shaped trench is provided with a second oxide layer medium (10) and a first gate polysilicon (11) that divides the second oxide layer medium (10) into left and right parts; the top of the cross-shaped trench is provided with a third oxide layer medium (12) and a second gate polysilicon (13) that divides the third oxide layer medium (12) into left and right parts, and the top of the second gate polysilicon (13) is flush with the bottom of the emitter metal (9); the potential of the first gate polysilicon (11) is equal to the potential of the emitter metal (9); the bottom of the N-type storage layer (5) is located between the top and bottom of the width of the cross-shaped trench, and the top of the N-type storage layer (5) is higher than the top of the width of the cross-shaped trench.
2. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that, The cross-shaped groove is symmetrical from left to right, and its top end is flush with the bottom end of the emitter metal (9).
3. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that, The bottom of the N-type memory layer (5) is not lower than the bottom of the first gate polysilicon (11).
4. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that, The cross-shaped groove divides the N-type drift region (4), N-type storage layer (5), P-type body region (6) and N+ contact region (7) into left and right parts.
5. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that, A line-shaped polysilicon gate (14) is provided between the first gate polysilicon (11) and the second gate polysilicon (13). The line-shaped polysilicon gate (14) is in contact with the first gate polysilicon (11) to form a T-shaped polysilicon gate. The line-shaped polysilicon gate (14) is located in the wide part of the cross-shaped trench.
6. The trench IGBT device with low Miller capacitance according to claim 5, characterized in that, The length of the line-shaped polysilicon gate (14) is greater than the width of the second gate polysilicon (13).
7. The trench IGBT device with low Miller capacitance according to claim 5, characterized in that, The potential of the T-type polysilicon gate is equal to the potential of the emitter metal (9).
8. The trench IGBT device with low Miller capacitance according to claim 1, characterized in that, A line-shaped polysilicon gate (14) is provided between the first gate polysilicon (11) and the second gate polysilicon (13). The line-shaped polysilicon gate (14) is in contact with the second gate polysilicon (13) to form an inverted T-shaped polysilicon gate. The line-shaped polysilicon gate (14) is located in the wide part of the cross-shaped trench.
9. The trench IGBT device with low Miller capacitance according to claim 8, characterized in that, The length of the line-shaped polysilicon gate (14) is greater than the width of the first gate polysilicon (11).