Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure, which comprises an epitaxial layer with a groove; a dielectric spacer layer disposed in the trench; a conductive filling layer disposed on the dielectric spacer layer and including a dopant; the gate dielectric layer is arranged on the conductive filling layer; and the gate electrode layer is arranged in the groove and is separated from the conductive filling layer through the gate dielectric layer, and the dopant has a gradient doping concentration in the conductive filling layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and more particularly to a semiconductor structure with a gradient doping concentration of dopants in a conductive filling layer. Background Art

[0002] In recent years, the semiconductor industry has made significant progress in the development of power devices. Currently, a variety of power devices have been developed, such as high voltage metal-oxide-semiconductor (HVMOS) transistors, insulated gate bipolar transistors (IGBT), junction field effect transistors (JFET), and Schottky barrier diodes (SBD). These devices are usually used in power amplification, power control and other applications in power systems of instruments such as household appliances, communication equipment and automotive generators.

[0003] In the existing metal oxide semiconductor transistor design, the on-resistance of the transistor can be reduced by using a trench transistor structure. In addition, by forming a transistor including a split-gate, the parasitic capacitance of the semiconductor device can be reduced to reduce switching loss. However, in the structure of the split-gate transistor formed by the conventional process, the thickness of the oxide between the source polysilicon and the gate polysilicon, that is, the thickness of the inter-poly oxide (IPO) cannot be independently controlled.

[0004] Specifically, the oxide is grown simultaneously on the top surface of the epitaxial layer, the sidewalls of the trench, the sidewalls of the polysilicon, and the top surface of the polysilicon, and the thickness of the oxide on each part of these surfaces is related to each other and has a specific proportional relationship. The thickness of the oxide on these surfaces will affect the device size and electrical performance, and the oxide on the sidewalls and top surface of the source polysilicon will become inter-polysilicon oxide. If the startup resistor (R ON ) and critical voltage (V th) within a certain range and depositing a thinner oxide layer may make the inter-poly oxide too thin, resulting in the risk of short circuit or breakdown between the source polysilicon and the gate polysilicon. On the other hand, if a thicker inter-poly oxide is formed, the oxides in other parts will also become thicker, affecting the device size and electrical performance.

[0005] In summary, although existing trench transistors can generally meet their original intended uses, they still do not fully meet the needs in all aspects. For example, how to increase the thickness of the inter-polysilicon oxide without affecting the size and electrical performance of the semiconductor device is still a topic that the industry is committed to researching. Therefore, the research and development of trench transistors requires continuous updates and adjustments to solve the various problems faced by the manufacture of semiconductor devices. Summary of the invention

[0006] A semiconductor structure includes: an epitaxial layer having a groove; a dielectric spacer layer arranged in the groove; a conductive filling layer arranged on the dielectric spacer layer and including a dopant; a gate dielectric layer arranged on the conductive filling layer; and a gate electrode layer arranged in the groove and separated from the conductive filling layer by the gate dielectric layer, wherein the dopant has a gradient doping concentration in the conductive filling layer.

[0007] A method for forming a semiconductor structure comprises: forming a dielectric spacer layer in a groove of an epitaxial layer; forming a conductive filling layer in the groove; performing a doping process so that the conductive filling layer includes a dopant; forming a gate dielectric layer on the conductive filling layer; and forming a gate electrode layer in the groove, wherein the gate electrode layer is separated from the conductive filling layer by the gate dielectric layer, wherein the dopant has a gradient doping concentration in the conductive filling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustration. In fact, the size of the components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0009] Figure 1 According to some embodiments of the present application, a cross-sectional view of a semiconductor structure including a vertical split gate structure is shown.

[0010] Figure 2 According to some embodiments of the present application, a cross-sectional view of a semiconductor structure including a lateral split gate structure is shown.

[0011] Figures 3A to 3F According to some embodiments of the present application, cross-sectional views of various stages of a method for forming a vertical split gate structure are depicted.

[0012] Figures 4A to 4G According to some other embodiments of the present application, cross-sectional views of various stages of a method for forming a vertical split gate structure are depicted.

[0013] Figures 5A to 5F According to some embodiments of the present application, cross-sectional views of various stages of a method for forming a lateral split gate structure are depicted.

[0014]

Explanation of symbols

[0015] 10, 20: Semiconductor structure

[0016] 100: Epitaxial layer

[0017] 100T: Groove

[0018] 110: Dielectric spacer

[0019] 112: The rest

[0020] 120: Conductive filling layer

[0021] 130: Gate dielectric layer

[0022] 140: Gate electrode layer

[0023] 140': Conductive material

[0024] 142: Extension

[0025] 150: Doping structure

[0026] 152: Doping Well

[0027] 154: The first heavily doped region

[0028] 156: Second heavily doped region

[0029] 160: Covering layer

[0030] 170: Upper electrode layer

[0031] 180: Lower electrode layer

[0032] 1000, 2000: Doping process

[0033] T1: First thickness

[0034] T2: Second thickness DETAILED DESCRIPTION

[0035] The following disclosure provides many different embodiments or examples to show different components of the embodiments of the present invention. The following will disclose specific examples of the components of this specification and their arrangement to simplify the description of this application. Of course, these specific examples are not intended to limit the present application. For example, if the following invention content of this specification describes forming a first component on or above a second component, it means that it includes an embodiment in which the first and second components formed are in direct contact, and also includes an embodiment in which an additional component can be formed between the above-mentioned first and second components, and the first and second components are not in direct contact. In addition, the various examples in the description of this application may use repeated reference symbols and / or words. The purpose of these repeated symbols or words is to simplify and clarify, and is not used to limit the relationship between the various embodiments and / or the configurations.

[0036] Furthermore, in order to conveniently describe the relationship between one element or component and another element or component in the drawings, spatially relative terms such as "under", "below", "lower", "above", "upper" and the like may be used. In addition to the orientations shown in the drawings, spatially relative terms also cover different orientations of the device in use or operation. When the device is turned to a different orientation (for example, rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the orientation after the rotation.

[0037] Here, the terms "about", "approximately", and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, in the absence of specific description of "about", "approximately", and "generally", the meanings of "about", "approximately", and "generally" can still be implied.

[0038] Some embodiments of the present invention are described below. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Some of the stages described may be replaced or deleted in different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described may be replaced or deleted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0039] As used herein, the term "substantially" means that the value of a given quantity may vary based on a particular technology node associated with the target semiconductor device. In some embodiments, based on a particular technology node, the term "substantially" may mean that the value of a given quantity is within a range of, for example, ±5% of a target (or desired) value.

[0040] The present application provides a semiconductor structure for forming a separated gate structure and a method for forming the same. The semiconductor structure formed by such a method will have a gradual doping concentration distribution in the conductive filling layer of the separated gate structure, so that the resistance value of the conductive filling layer changes in the vertical direction. In addition, through the formation method of the present application, the thickness of the gate dielectric layer between the conductive layers of the separated gate structure can be freely controlled without affecting the thickness of the gate dielectric layer located on the top surface of the epitaxial layer and the sidewall of the trench. In this way, the size and electrical performance of the semiconductor device can be maintained, and the risk of short circuit or collapse in the separated gate structure can be reduced.

[0041] Figure 1 1 is a cross-sectional view of a semiconductor structure 10 including a vertical separated gate structure according to some embodiments of the present application. The semiconductor structure 10 may include an epitaxial layer 100 having a trench 100T and a dielectric spacer layer 110 disposed in the trench 100T. The semiconductor structure 10 may also include a conductive filling layer 120 disposed on the dielectric spacer layer 110 and including a dopant, and the dopant may have a gradient doping concentration in the conductive filling layer 120. It should be understood that the so-called gradient doping concentration means that the dopant has a gradient concentration distribution in the conductive filling layer 120. The semiconductor structure 10 may also include a gate dielectric layer 130 disposed on the conductive filling layer 120. In addition, the semiconductor structure 10 may also include a gate electrode layer 140 disposed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate dielectric layer 130.

[0042] The epitaxial layer 100 may be disposed on a substrate (not shown). In some embodiments, the substrate is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, the substrate is formed of silicon, germanium, other suitable semiconductor materials, or a combination thereof. For example, in a specific embodiment, the substrate comprises silicon. In some embodiments, the substrate may comprise a compound semiconductor, such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, other suitable semiconductor materials, or a combination thereof. In some embodiments, the substrate may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, other suitable materials, or a combination thereof. In some embodiments, the substrate may be composed of a multilayer material, such as a multilayer material comprising silicon / silicon germanium, silicon / silicon carbide.

[0043] In some embodiments of the present application, for example, the substrate is a wafer doped with a first conductivity type dopant, and the first conductivity type is n-type. In some other embodiments, the first conductivity type may also be p-type. In the case where the first conductivity type is n-type, the above-mentioned dopant with the first conductivity type may be, for example, nitrogen, phosphorus, arsenic, antimony, bismuth. In the case where the first conductivity type is p-type, the above-mentioned dopant with the first conductivity type may be, for example, boron, aluminum, gallium, indium, thallium. In some embodiments, the doping concentration of the substrate may be about 1e19 atoms / cm 3 to about 1e21 atoms / cm 3 between.

[0044] The epitaxial layer 100 may include the same or similar material as the substrate, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or combinations thereof. In some embodiments, the substrate and the epitaxial layer 100 have the same conductivity type (e.g., n-type), and the substrate and the epitaxial layer 100 may include the same dopant. In some embodiments, the doping concentration of the above dopant in the epitaxial layer 100 is less than the doping concentration in the substrate. In some embodiments, the doping concentration of the epitaxial layer 100 may be about 1e13 atoms / cm 3 to about 1e18 atoms / cm 3 In some embodiments of the present application, for example, the epitaxial layer 100 includes silicon carbide. By forming the epitaxial layer 100 with silicon carbide, the epitaxial layer 100 can be doped with a dopant that is suitable for the energy band range of silicon carbide and has a low activation energy. In addition, the epitaxial layer 100 formed of silicon carbide can provide a higher breakdown voltage, a lower leakage current, and a lower on-resistance.

[0045] like Figure 1 As shown, the dielectric spacer layer 110 and the conductive filling layer 120 may be disposed in the trench 100T of the epitaxial layer 100. The dielectric spacer layer 110 may extend between the conductive filling layer 120 and the epitaxial layer 100. The material of the dielectric spacer layer 110 may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon oxide hafnium, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the dielectric spacer layer 110 includes an oxide having an element in common with the epitaxial layer 100. For example, in a specific embodiment, the epitaxial layer 100 includes silicon or silicon carbide, and the dielectric spacer layer 110 includes silicon oxide.

[0046] In some embodiments, the doping concentration of the above-mentioned dopant is higher in the upper part of the conductive filling layer 120 than in the lower part of the conductive filling layer 120. The present application does not limit the types of the above-mentioned dopants, and generally, those skilled in the art can decide which dopant to use according to design requirements. The conductivity type of the above-mentioned dopant can be n-type or p-type. In the case where the conductivity type of the above-mentioned dopant is n-type, the above-mentioned dopant can be, for example, nitrogen, phosphorus, arsenic, antimony, and bismuth. In the case where the conductivity type of the above-mentioned dopant is p-type, the above-mentioned dopant can be, for example, boron, aluminum, gallium, indium, and thallium. The material of the conductive filling layer 120 may include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination of the foregoing.

[0047] like Figure 1 As shown, the gate dielectric layer 130 and the gate electrode layer 140 may also be disposed in the trench 100T of the epitaxial layer 100. In some embodiments, as Figure 1 As shown, the gate electrode layer 140 includes an extension portion 142 extending between the sidewall of the conductive filling layer 120 and the sidewall of the trench 100T. Figure 1 As shown, the bottom surface of the gate electrode layer 140 (e.g., the bottom surface of the extension portion 142) may be lower than the top surface of the conductive filling layer 120. However, in some other embodiments, the extension portion 142 does not extend between the sidewall of the conductive filling layer 120 and the sidewall of the trench 100T. In still other embodiments, the gate electrode layer 140 does not have the extension portion 142 extending downward and has a flat bottom surface.

[0048] In some embodiments, Figure 1 As shown, the gate dielectric layer 130 surrounds the gate electrode layer 140, so that the gate electrode layer 140 is separated from both the dielectric spacer layer 110 and the epitaxial layer 100. The gate dielectric layer 130 may extend between the gate electrode layer 140 and the conductive filling layer 120, may extend between the gate electrode layer 140 and the dielectric spacer layer 110, and may further extend between the gate electrode layer 140 and the epitaxial layer 100.

[0049] Specifically, if Figure 1 As shown, the gate dielectric layer 130 may include a lateral portion extending laterally between the top surface of the conductive filling layer 120 and the bottom surface of the gate electrode layer 140. In some embodiments, the thickness of the lateral portion is greater than the thickness of the portion of the gate dielectric layer 130 covering the sidewall of the trench 100T (e.g., Figure 1In some embodiments, the width of the gate electrode layer 140 is greater than the width of the conductive filling layer 120. The gate dielectric layer 130 may have a first thickness T1 between the conductive filling layer 120 and the sidewall of the gate electrode layer 140 (e.g., the sidewall of the extension 142) and a second thickness T2 between the gate electrode layer 140 and the sidewall of the trench 100T, and the first thickness T1 may be greater than the second thickness T2.

[0050] The gate dielectric layer 130 may include the same or similar material as the dielectric spacer layer 110. For example, the material of the gate dielectric layer 130 may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon oxide hafnium, silicon oxynitride hafnium, tantalum oxide hafnium, titanium oxide hafnium, zirconium oxide hafnium, other suitable high-k dielectric materials, or combinations thereof. The gate electrode layer 140 may include the same or similar material as the conductive fill layer 120. For example, the material of the gate electrode layer 140 may include polysilicon, metal, metal nitride, other suitable conductive materials, or combinations thereof.

[0051] It should be understood that the portion of the semiconductor structure 10 including the epitaxial layer 100, the dielectric spacer layer 110, the conductive filling layer 120, the gate dielectric layer 130, and the gate electrode layer 140 can be referred to as a split gate structure. In particular, since the conductive filling layer 120 and the gate electrode layer 140 of the semiconductor structure 10 overlap in the vertical direction of the semiconductor structure 10, the split gate structure of the semiconductor structure 10 can be referred to as a vertical split gate structure. Figures 3A to 3F as well as Figures 4A to 4G The method of forming a vertical separated gate structure is described below.

[0052] Figures 3A to 3F According to some embodiments of the present application, cross-sectional views of various stages of a method for forming a vertical split gate structure are depicted.

[0053] First, the epitaxial layer 100 may be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown). The epitaxial layer 100 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

[0054] The process for forming the trench 100T may include, for example, a patterning process. A patterned shielding layer (not shown) (e.g., positive / negative photoresist, hard mask, etc.) is formed above the epitaxial layer 100 before patterning. A shielding layer (not shown) may be formed on the epitaxial layer 100 (e.g., by a spin coating process), the shielding layer may be exposed to a pattern (e.g., by a photolithography process, such as photolithography, extreme ultraviolet lithography, etc.), and the shielding layer may be developed to form a patterned shielding layer. Afterwards, after the patterned shielding layer is in place, an etching process is performed on the epitaxial layer 100 according to the patterned shielding layer.

[0055] The etching process can remove the unshielded portion of the epitaxial layer 100, thereby forming the trench structure 100T. In some embodiments, the etching process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. Then, the patterned shielding layer can be stripped.

[0056] Reference Figure 3A , a dielectric spacer 110 may be formed in the trench 100T of the epitaxial layer 100, and a conductive filling layer 120 may be formed in the trench 100T. Specifically, a dielectric spacer 110 may be deposited over the epitaxial layer 100 and in the trench 100T, and a conductive filling layer 120 may be formed on the dielectric spacer 110.

[0057] In some embodiments, the dielectric spacer layer 110 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), sol-gel method, spin coating, other suitable methods, or a combination thereof. The conductive filling layer 120 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof.

[0058] Next, refer to Figure 3B , the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing the removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0059] After partially removing the dielectric spacer layer 110, a doping process 1000 is performed so that the conductive filling layer 120 includes a dopant. The types of dopants are as discussed previously, and a detailed description thereof is omitted here for the sake of simplicity. The doping process 1000 is an ion implantation process. After performing the doping process 1000, the dopant has a gradient doping concentration in the conductive filling layer 120. For example, in some embodiments, the dopant has a gradient concentration profile in the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 1000 includes introducing the dopant into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120. For example, in the case where the doping process 1000 is an ion implantation process, ions in a dopant source can be doped into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120.

[0060] After the doping process 1000 is performed, refer to Figure 3C , the dielectric spacer layer 110 is partially removed to expose a portion of the sidewall of the trench 100T. In some embodiments, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 is also removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above removal process, the exposed area of ​​the sidewall of the conductive filling layer 120 can be further increased, such as Figure 3C The removal process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0061] Next, refer to Figure 3D , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive filling layer 120 may be thicker than other portions of the gate dielectric layer 130. The formation method of the gate dielectric layer 130 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

[0062] Next, refer to Figure 3E ,3F , a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140' on the gate dielectric layer 130 and performing an etching process on the conductive material 140' to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The above-mentioned etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0063] Since the dopant can have a higher concentration in the upper part of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and / or side of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other parts is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the part between the conductive filling layer 120 and the gate electrode layer 140 can be maintained above a certain thickness. In other words, the vertical separated gate structure formed by the method of the above embodiment can reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

[0064] Figures 4A to 4G According to some other embodiments of the present application, cross-sectional views of various stages of a method for forming a vertical split gate structure are depicted.

[0065] and Figures 3A to 3F The embodiment of the formation method shown is similar. First, the epitaxial layer 100 having the trench 100T can be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown) and performing a patterning process. Figure 4A , a dielectric spacer layer 110 may be formed in the trench 100T of the epitaxial layer 100, and a conductive filling layer 120 may be formed in the trench 100T. Specifically, the dielectric spacer layer 110 may be deposited above the epitaxial layer 100 and in the trench 100T, and the conductive filling layer 120 may be formed on the dielectric spacer layer 110. The formation method of the epitaxial layer 100, the dielectric spacer layer 110, and the conductive filling layer 120 may be the same as Figures 3A to 3F The embodiments shown are the same or similar, and their detailed description is omitted here for simplicity.

[0066] Next, refer to Figure 4B, the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing the removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0067] After partially removing the dielectric spacer layer 110, a doping process 2000 is performed to make the conductive filling layer 120 include dopants. The doping process 2000 includes thermal diffusion using a precursor for the conductive filling layer 120. In a specific embodiment, the doping process 2000 may include thermal diffusion using a phosphorus-containing precursor. The phosphorus-containing precursor may include, for example, POCl3. After performing the doping process 2000, the dopant has a gradient doping concentration in the conductive filling layer 120. For example, in some embodiments, the dopant has a gradient concentration distribution in the upper part of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 2000 includes introducing the dopant into the conductive filling layer 120 from the top surface and / or sidewall of the conductive filling layer 120. For example, in the thermal diffusion of the doping process 2000, ions in the precursor may be doped into the conductive filling layer 120 from the top surface and / or sidewall of the conductive filling layer 120.

[0068] Since oxide including dopant elements is generated on the top of the conductive filling layer 120, an etching process is required to remove the oxide to prevent the electrical performance of the separated gate structure from being affected. Figure 4C . After performing the thermal diffusion process as the doping process 2000, a removal process may be performed on the top surface of the conductive filling layer 120 to remove the oxide. The above-mentioned etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. For example, in an embodiment in which the etching process uses a phosphorus-containing precursor for thermal diffusion, a thinner phospho-silicate glass (PSG) layer may be formed near the top surface of the conductive filling layer 120. The phospho-silicate glass layer may be removed by, for example, a wet etching process using HF as an etchant or other suitable etching processes. In some embodiments, as Figure 4CAs shown, the etching process also removes a portion of the dielectric spacer layer 110. For example, in some embodiments, the portion of the dielectric spacer layer located above the top surface of the epitaxial layer 100 is removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, the portion located on the sidewall of the trench 100T may also be thinned due to the etching process, leaving only a remaining portion 112, such as Figure 4C shown.

[0069] Next, refer to Figure 4D , partially removing the dielectric spacer layer 110 to expose a portion of the sidewall of the trench 100T. Figure 4C The remaining portion 112 of the dielectric spacer layer 110 is completely removed. In the case where there is still a remaining dielectric spacer layer 110 above the top surface of the epitaxial layer 100, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 can also be removed together, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above removal process, the exposed area of ​​the sidewall of the conductive filling layer 120 can be further increased, such as Figure 4D The removal process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0070] Next, refer to Figure 4E , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive filling layer 120 may be thicker than other portions of the gate dielectric layer 130. The formation method of the gate dielectric layer 130 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

[0071] Next, refer to Figure 4F , 4G, a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140' on the gate dielectric layer 130 and performing an etching process on the conductive material 140' to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The above-mentioned etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0072] Since the dopant can have a higher concentration in the upper part of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and / or side of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other parts is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the part between the conductive filling layer 120 and the gate electrode layer 140 can be maintained above a certain thickness. In other words, the vertical separated gate structure formed by the method of the above embodiment can also reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

[0073] Refer again Figure 1 In some embodiments, the epitaxial layer 100 includes a doped structure 150 that laterally surrounds the split gate structure. The doped structure 150 may include a doped well 152, a first heavily doped region 154, and a second heavily doped region 156. In some embodiments, a portion of the doped well 152 adjacent to the split gate structure can be used as a channel region when the semiconductor structure 10 is in operation. For example, when a forward bias is applied to the gate electrode layer 140, an inversion layer can be formed near the sidewall of the doped well 152 adjacent to the split gate structure to generate current. The second heavily doped region 156 can be used to electrically connect the doped well 152 to an upper electrode layer (e.g., an upper electrode layer 170 formed subsequently). The first heavily doped region 154 can be electrically connected to a source.

[0074] The first heavily doped region 154 may have the same first conductivity type (e.g., n-type) as the epitaxial layer 100, and the doped well 152 and the second heavily doped region 156 may have a second conductivity type (e.g., p-type). The doping concentration of the doped well 152 may be about 1e15 atoms / cm 3 to about 1e18 atoms / cm 3The doping concentration of the first heavily doped region 154 may be about 1e18 atoms / cm 3 to about 1e21 atoms / cm 3 The doping concentration of the second heavily doped region 156 may be about 1e18 atoms / cm 3 to about 1e21 atoms / cm 3 between.

[0075] The doped structure 150 may include the same or similar material as the portion of the doped structure 150 below the epitaxial layer 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium, silicon germanium carbide, other suitable materials, or combinations thereof. The doped structure 150 may be formed by performing a doping process on the epitaxial material used to form the epitaxial layer 100. In some embodiments, the top surface of the doped structure 150 is substantially coplanar with the top surface of the gate electrode layer 140.

[0076] In some embodiments, a capping layer 160 is formed on the split gate structure. Specifically, the capping layer 160 may be formed on the gate electrode layer 140. The material and formation method of the capping layer 160 may be the same as or similar to that of the dielectric spacer layer 110 or the gate dielectric layer 130, and a detailed description thereof is omitted for simplicity.

[0077] Then, if Figure 1 As shown, an upper electrode layer 170 may be formed on the doping structure 150 and the capping layer 160 , and a lower electrode layer 180 may be formed under the epitaxial layer 100 .

[0078] The upper electrode layer 108 and the lower electrode layer 180 may include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), benzene (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metals or metal nitrides, or combinations thereof.

[0079] The formation method of the upper electrode layer 170 and the lower electrode layer 180 may include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, sputtering, electrochemical plating, electroless plating, some other deposition processes, or a combination thereof.

[0080] Figure 21 is a cross-sectional view of a semiconductor structure 20 including a lateral split gate structure according to some embodiments of the present application. The semiconductor structure 20 may include an epitaxial layer 100 having a trench 100T and a dielectric spacer 110 disposed in the trench 100T. The semiconductor structure 20 may also include a conductive filling layer 120 disposed on the dielectric spacer 110 and including a dopant, and the dopant may have a gradient doping concentration in the conductive filling layer 120. The semiconductor structure 20 may also include a gate dielectric layer 130 disposed on the conductive filling layer 120. In addition, the semiconductor structure 20 may also include a gate electrode layer 140 disposed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate dielectric layer 130.

[0081] It should be understood that the portion of the semiconductor structure 20 including the epitaxial layer 100, the dielectric spacer layer 110, the conductive filling layer 120, the gate dielectric layer 130, and the gate electrode layer 140 can be referred to as a split gate structure. In particular, since the conductive filling layer 120 and the gate electrode layer 140 of the semiconductor structure 20 are arranged in the lateral direction of the semiconductor structure 20, the split gate structure of the semiconductor structure 20 can be referred to as a lateral split gate structure.

[0082] like Figure 2 As shown, the dielectric spacer layer 110 and the conductive filling layer 120 may be disposed in the trench 100T of the epitaxial layer 100. The dielectric spacer layer 110 may extend between the conductive filling layer 120 and the epitaxial layer 100. The material of the dielectric spacer layer 110 may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon oxide hafnium, silicon oxynitride hafnium, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, other suitable high-k dielectric materials, or combinations thereof. In some embodiments, the dielectric spacer layer 110 includes an oxide having an element in common with the epitaxial layer 100. For example, in a specific embodiment, the epitaxial layer 100 includes silicon or silicon carbide, and the dielectric spacer layer 110 includes silicon oxide.

[0083] In some embodiments, the doping concentration of the above-mentioned dopant is higher in the upper part of the conductive filling layer 120 than in the lower part of the conductive filling layer 120. The present application does not limit the types of the above-mentioned dopants, and generally, those skilled in the art can decide which dopant to use according to design requirements. The conductivity type of the above-mentioned dopant can be n-type or p-type. In the case where the conductivity type of the above-mentioned dopant is n-type, the above-mentioned dopant can be, for example, nitrogen, phosphorus, arsenic, antimony, and bismuth. In the case where the conductivity type of the above-mentioned dopant is p-type, the above-mentioned dopant can be, for example, boron, aluminum, gallium, indium, and thallium. The material of the conductive filling layer 120 may include polysilicon, metal, metal nitride, other suitable conductive materials, or a combination of the foregoing.

[0084] like Figure 2 As shown, the gate dielectric layer 130 and the gate electrode layer 140 may also be disposed in the trench 100T of the epitaxial layer 100. In some embodiments, as Figure 1 As shown, the gate dielectric layer 130 surrounds the gate electrode layer 140, so that the gate electrode layer 140 is separated from both the dielectric spacer layer 110 and the epitaxial layer 100. The gate dielectric layer 130 may extend between the gate electrode layer 140 and the conductive filling layer 120, may extend between the gate electrode layer 140 and the dielectric spacer layer 110, and may further extend between the gate electrode layer 140 and the epitaxial layer 100. In addition, the gate electrode layer 140 may be laterally divided into a plurality of portions by the conductive filling layer 120. For example, in Figure 2 In the two illustrated split gate structures, the conductive filling layer 120 in each split gate structure can separate the gate electrode layer 140 into two parts in the lateral direction. Figure 2 The top surface of the gate electrode layer 140 may be lower than the top surface of the conductive filling layer 120. In other embodiments, the gate dielectric layer 140 may include a lateral portion extending laterally from the top surface of the conductive filling layer 120 (as described later). Fig. 5F ), and the top surface of the gate electrode layer 140 is lower than the top surface of the above-mentioned lateral portion. The gate dielectric layer 130 may have a first thickness T1 between the conductive filling layer 120 and the sidewall of the gate electrode layer 140 and a second thickness T2 between the gate electrode layer 140 and the sidewall of the trench 100T, and the first thickness T1 may be greater than the second thickness T2.

[0085] The gate dielectric layer 130 may include the same or similar material as the dielectric spacer layer 110. For example, the material of the gate dielectric layer 130 may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxide hafnium alloy, silicon oxide hafnium, silicon oxynitride hafnium, tantalum oxide hafnium, titanium oxide hafnium, zirconium oxide hafnium, other suitable high-k dielectric materials, or combinations thereof. The gate electrode layer 140 may include the same or similar material as the conductive fill layer 120. For example, the material of the gate electrode layer 140 may include polysilicon, metal, metal nitride, other suitable conductive materials, or combinations thereof.

[0086] It should be understood that since the semiconductor structure 10 and the semiconductor structure 20 include other identical or similar components and film layers (such as the doping structure 150, the cap layer 160, the upper electrode layer 170, and the lower electrode layer 180, etc.), these components and film layers can be formed by the same or similar materials and formation methods, and detailed descriptions are omitted for simplicity. Figures 5A to 5F The method of forming a lateral separated gate structure is described.

[0087] Figures 5A to 5F According to some embodiments of the present application, cross-sectional views of various stages of a method for forming a lateral split gate structure are depicted.

[0088] and Figures 3A to 3F 4A to 4G, first, the epitaxial layer 100 having the trench 100T can be provided by depositing a material for the epitaxial layer 100 on a substrate (not shown) and performing a patterning process. Figure 5A , a dielectric spacer 110 may be formed in the trench 100T of the epitaxial layer 100, and a conductive filling layer 120 may be formed in the trench 100T. Specifically, the dielectric spacer 110 may be deposited above the epitaxial layer 100 and in the trench 100T, and the conductive filling layer 120 may be formed on the dielectric spacer 110. The method for forming the epitaxial layer 100, the dielectric spacer 110, and the conductive filling layer 120 may be the same or similar to that of the embodiment of the vertical split gate structure, and a detailed description thereof is omitted for simplicity. In addition, in some embodiments, in the process of forming the conductive filling layer 120, the conductive material is etched so that the top surface of the conductive filling layer 120 is substantially equal to the height of the epitaxial layer 100.

[0089] Next, refer to Figure 5B , the dielectric spacer layer 110 may be partially removed so that the dielectric spacer layer 110 has a thinner thickness at the upper portion of the sidewall of the trench 100T. In some embodiments, by performing the removal process, the portion of the dielectric spacer layer 110 above the top surface of the epitaxial layer 100 also becomes thinner. The etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0090] After partially removing the dielectric spacer layer 110, a doping process 1000 as an ion implantation process or a doping process 2000 as a thermal diffusion process is performed to make the conductive filling layer 120 include dopants. The types of dopants are as discussed above, and a detailed description thereof is omitted for simplicity.

[0091] In the case where the doping process 1000 is performed as an ion implantation process, after the doping process 1000 is performed, the dopant has a gradient doping concentration in the conductive filling layer 120. For example, in some embodiments, the dopant has a gradient concentration profile in the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 1000 includes introducing the dopant into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120. For example, in the case where the doping process 1000 is performed as an ion implantation process, ions in the dopant source may be doped into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120.

[0092] In the case of performing the doping process 2000 as a thermal diffusion process, after performing the doping process 2000, the dopant has a gradient doping concentration in the conductive filling layer 120. In a specific embodiment, the doping process 2000 may include performing thermal diffusion using a phosphorus-containing precursor. The phosphorus-containing precursor may include, for example, POCl3. For example, in some embodiments, the dopant has a gradient concentration profile in the upper portion of the conductive filling layer 120, and the concentration of the dopant decreases as the distance from the top surface of the conductive filling layer 120 increases. In some embodiments, the doping process 2000 includes introducing the dopant into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120. For example, in the thermal diffusion of the doping process 2000, ions in the precursor may be doped into the conductive filling layer 120 from the top surface and / or the sidewall of the conductive filling layer 120.

[0093] Since oxides including dopant elements are generated on the top of the conductive filling layer 120, an etching process is required to remove the oxides to avoid affecting the electrical performance of the separated gate structure. After the thermal diffusion process as the doping process 2000 is performed, a removal process can be performed on the top surface of the conductive filling layer 120 to remove the oxides. The above-mentioned etching process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination of the foregoing. For example, in an embodiment in which a phosphorus-containing precursor is used for thermal diffusion, a thinner phospho-silicate glass (PSG) layer is formed near the top surface of the conductive filling layer 120. The phospho-silicate glass layer can be removed by, for example, a wet etching process using HF as an etchant or other suitable etching processes. In some embodiments, the etching process also removes a portion of the dielectric spacer layer 110. For example, in some embodiments, a portion of the dielectric spacer layer located above the top surface of the epitaxial layer 100 is removed so that the top surface of the epitaxial layer 100 is exposed. In addition, the portion located on the sidewall of the trench 100T may also be thinned due to the etching process.

[0094] After the doping process 1000 is performed, refer to Figure 5C , the dielectric spacer layer 110 is partially removed to expose a portion of the sidewall of the trench 100T. In some embodiments, the portion of the dielectric spacer layer 110 located above the top surface of the epitaxial layer 100 is also removed, so that the top surface of the epitaxial layer 100 is exposed. In addition, by performing the above-mentioned removal process, the exposed area of ​​the sidewall of the conductive filling layer 120 can also be further increased. The above-mentioned removal process can be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof.

[0095] Next, refer to Figure 5D , a gate dielectric layer 130 may be formed on the conductive filling layer 120. In some embodiments, the gate dielectric layer 130 is conformally deposited on the conductive filling layer 120, the dielectric spacer 110, and the epitaxial layer 100. The gate dielectric layer 130 may have different thicknesses on different surfaces, depending on the material properties under the gate dielectric layer 130. In some embodiments, for example, a portion of the gate dielectric layer 130 on the conductive filling layer 120 is thicker than a portion on the dielectric spacer 110, and a portion on the dielectric spacer 110 is thicker than a portion on the epitaxial layer 100. In addition, a lateral portion of the gate dielectric layer 130 on the top surface of the conductive filling layer 120 may be thicker than other portions of the gate dielectric layer 130. The formation method of the gate dielectric layer 130 may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable methods, or a combination thereof.

[0096] Next, refer to Figure 5E , 5F , a gate electrode layer 140 may be formed in the trench 100T, and the gate electrode layer 140 may be separated from the conductive filling layer 120 by the gate electrode layer 130. Specifically, the formation of the gate electrode layer 140 may include depositing a conductive material 140' on the gate dielectric layer 130 and performing an etching process on the conductive material 140' to form the gate electrode layer 140. The deposition method of the conductive material 140' may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electron beam evaporation, electroplating, other suitable methods, or a combination thereof. The above-mentioned etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (RIE) process, other suitable etching processes, or a combination thereof. As Fig. 5FAs shown, the conductive material 140 ′ after the etching process becomes a gate electrode layer 140 having a plurality of portions laterally separated by the conductive filling layer 120 . An etching process may also be performed subsequently to remove a portion of the gate dielectric layer 130 above the top surface of the epitaxial layer 100 .

[0097] Since the dopant can have a higher concentration in the upper part of the conductive filling layer 120, it is helpful to deposit the gate dielectric layer 130 on the top surface and / or side of the conductive filling layer 120. Therefore, even if the gate dielectric layer 130 of other parts is formed to be thinner to maintain the size and basic electrical performance of the semiconductor device, the gate dielectric layer 130 of the part between the conductive filling layer 120 and the gate electrode layer 140 can be maintained above a certain thickness. In other words, the lateral separated gate structure formed by the method of the above embodiment can reduce the risk of short circuit or collapse between the conductive filling layer 120 and the gate electrode layer 140 while maintaining the size and basic electrical performance of the semiconductor device.

[0098] In passing Figures 5A to 5F After forming the lateral separated gate structure by the formation method shown, other components and film layers (such as the doping structure 150, the cap layer 160, the upper electrode layer 170, and the lower electrode layer 180, etc.) of the semiconductor structure 20 can be formed. These components and film layers can be formed by the materials and formation methods discussed above, and detailed descriptions are omitted here for simplicity.

[0099] In summary, the present application provides a semiconductor structure for forming a separated gate structure and a method for forming the same. The semiconductor structure formed by such a method will have a gradual doping concentration distribution in the conductive filling layer of the separated gate structure, so that the resistance value of the conductive filling layer changes in the vertical direction. In addition, through the formation method of the present application, the thickness of the gate dielectric layer of the portion between the conductive layers of the separated gate structure can be freely controlled without affecting the thickness of the gate dielectric layer located on the top surface of the epitaxial layer and the sidewall of the trench. In this way, the size and electrical performance of the semiconductor device can be maintained, and the risk of short circuit or collapse in the separated gate structure can be reduced.

[0100] The features of several embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present invention belongs can more easily understand the concepts of the embodiments of the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present invention belongs should also understand that such equivalent processes and structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: an epitaxial layer having a trench; a dielectric spacer layer disposed in the trench; a conductive filling layer, disposed on the dielectric spacer layer and comprising a dopant; a gate dielectric layer disposed on the conductive filling layer; and a gate electrode layer disposed in the trench and separated from the conductive filling layer by the gate dielectric layer; The characteristic of the invention is that the dopant has a gradient doping concentration in the conductive filling layer.

2. The semiconductor structure according to claim 1, wherein: The doping concentration is higher in the upper portion of the conductive filling layer than in the lower portion of the conductive filling layer.

3. The semiconductor structure according to claim 1, wherein: The gate electrode layer includes an extension portion extending between a sidewall of the conductive filling layer and a sidewall of the trench.

4. The semiconductor structure according to claim 1, wherein: The gate dielectric layer surrounds the gate electrode layer so that the gate electrode layer is separated from both the dielectric spacer layer and the epitaxial layer.

5. The semiconductor structure according to claim 1, wherein: A bottom surface of the gate electrode layer is lower than a top surface of the conductive filling layer.

6. The semiconductor structure according to claim 1, wherein: The gate dielectric layer has a first thickness between the conductive filling layer and the sidewall of the gate electrode layer and a second thickness between the gate electrode layer and the sidewall of the trench, and the first thickness is greater than the second thickness.

7. The semiconductor structure according to claim 1, wherein: The gate dielectric layer includes a lateral portion extending laterally between a top surface of the conductive fill layer and a bottom surface of the gate electrode layer.

8. The semiconductor structure according to claim 7, wherein: The thickness of the lateral portion is greater than the thickness of a portion of the gate dielectric layer covering a sidewall of the trench.

9. The semiconductor structure according to claim 7, wherein: The width of the gate electrode layer is greater than the width of the conductive filling layer.

10. The semiconductor structure according to claim 1, wherein: The gate electrode layer is laterally divided into a plurality of parts by the conductive filling layer.

11. The semiconductor structure according to claim 10, characterized in that The gate dielectric layer includes a lateral portion extending laterally from a top surface of the conductive filling layer, and a top surface of the gate electrode layer is lower than a top surface of the lateral portion.

12. The semiconductor structure according to claim 10, wherein: A top surface of the gate electrode layer is lower than a top surface of the conductive filling layer.

13. A method for forming a semiconductor structure, characterized in that: include: forming a dielectric spacer layer in a trench of an epitaxial layer; forming a conductive filling layer in the trench; Performing a doping process so that the conductive filling layer includes a dopant; forming a gate dielectric layer on the conductive filling layer; as well as forming a gate electrode layer in the trench, wherein the gate electrode layer is separated from the conductive filling layer by the gate dielectric layer; The dopant has a gradient doping concentration in the conductive filling layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: Also includes: depositing the dielectric spacer layer over the epitaxial layer and in the trench; forming the conductive filling layer on the dielectric spacer layer; as well as The dielectric spacer layer is partially removed to expose a portion of the sidewall of the trench.

15. The method for forming a semiconductor structure according to claim 13, wherein: The doping process includes introducing the dopant into the conductive filling layer from the top surface and / or the sidewall of the conductive filling layer.

16. The method for forming a semiconductor structure according to claim 13, wherein: The doping process is an ion implantation process.

17. The method for forming a semiconductor structure according to claim 13, wherein: The doping process includes thermal diffusion using a phosphorus-containing precursor.

18. The method for forming a semiconductor structure according to claim 13, wherein: The method also includes conformally depositing the gate dielectric layer on the conductive filling layer, the dielectric spacer, and the epitaxial layer.

19. The method for forming a semiconductor structure according to claim 13, wherein: The formation of the gate electrode layer includes: depositing a conductive material on the gate electrode layer; and An etching process is performed on the conductive material to form the gate electrode layer.

20. The method for forming a semiconductor structure according to claim 19, wherein: The conductive material, after the etching process, becomes the gate electrode layer having a plurality of portions laterally separated by the conductive filling layer.

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