Method of manufacturing a semiconductor device

Abstract

The application relates to a semiconductor device manufacturing method. In the manufacturing method, a first CMP process is used to form a zeroth interlayer dielectric layer around a dummy gate structure, a stack of the dummy gate structure and a contact etching stop layer is etched to expose a top surface of the dummy gate and form a height difference between the top surface of the dummy gate and a top surface of the zeroth interlayer dielectric layer, then a second CMP process is performed to reduce the height difference and make the dummy gate reach a target thickness, when the second CMP process is performed, the zeroth interlayer dielectric layer is ground more than the dummy gate, when the grinding is finished, the risk of generating a dish-shaped defect falls on the dummy gate, the dish-shaped defect on the dummy gate is removed with the removal of the dummy gate, the risk of forming a clear dish-shaped defect on the surface of the zeroth interlayer dielectric layer is reduced, the risk of leaving metal gate material on the top surface of the zeroth interlayer dielectric layer is reduced, and the process reliability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device. BACKGROUND

[0002] Conventional MOS transistors (Metal-Oxide-Semiconductor Field Effect Transistor) usually use doped polysilicon as gate material. However, boron penetration effect caused by dopant boron can result in reduced device performance, and polysilicon gate is more likely to be depleted, which increases the equivalent gate dielectric layer thickness and reduces the gate capacitance, and further results in weakened device driving ability. Currently, MOS transistor manufacturing process using metal gate to replace polysilicon gate has been developed, and the process usually uses gate last. In the process, a dummy gate is made on a substrate using polysilicon, and a gate sidewall and a source / drain region are formed. Then, a dielectric material covering the dummy gate and the substrate is formed. Then, CMP (Chemical Mechanical Polishing) processing is performed to expose the top surface of the dummy gate, and the remaining dielectric material is located around the dummy gate to form a first interlayer dielectric layer (ILD0). Then, the dummy gate is removed. Then, metal gate material is deposited in the gate trench and on the first interlayer dielectric layer. Again, CMP processing is performed to expose the top surface of the first interlayer dielectric layer, and the remaining metal gate material in the gate trench is the metal gate.

[0003] However, in the above process, after the first CMP processing, the top surface of the first interlayer dielectric layer often forms a dishing defect. Severe dishing defect can result in residual metal gate material on the top surface of the first interlayer dielectric layer after the second CMP processing. As the process node decreases, the influence of the residual metal gate material on the dishing defect on the reliability of subsequent processes also increases, which reduces the yield of semiconductor devices. SUMMARY

[0004] In order to improve the existing gate last process, avoid the formation of dishing defect on the top surface of the first interlayer dielectric layer which is easy to cause residual metal gate material, and improve the process reliability, the present application provides a method for manufacturing a semiconductor device.

[0005] The method for manufacturing a semiconductor device provided by the present application comprises:

[0006] forming at least one dummy gate structure on a substrate, the dummy gate structure comprising a dummy gate and a sidewall covering both sides of the dummy gate;

[0007] forming a contact etching stop layer conformally on the dummy gate structure and the surface of the substrate;

[0008] covering a dielectric material on the contact etch stop layer, a top surface of the dielectric material being higher than a top surface of the dummy gate structure;

[0009] performing a first CMP process to use the contact etch stop layer on top of the dummy gate structure as a polishing stop layer, and to leave the dielectric material remaining around the dummy gate structure to form a zeroth interlayer dielectric layer;

[0010] etching the stack of the dummy gate structure and the contact etch stop layer to expose a top surface of the dummy gate structure, and to form a height difference between the top surface of the dummy gate structure and a top surface of the zeroth interlayer dielectric layer;

[0011] performing a second CMP process to reduce the height difference and to reach a target thickness of the dummy gate structure;

[0012] removing the dummy gate structure to form a gate recess in an area of the dummy gate structure; and

[0013] forming a metal gate in the gate recess.

[0014] Optionally, forming the metal gate in the gate recess includes:

[0015] forming a work function metal layer conformally on an inner surface of the gate recess and on the top surface of the zeroth interlayer dielectric layer;

[0016] forming a metal electrode layer filling the gate recess and covering the top surface of the zeroth interlayer dielectric layer; and

[0017] performing a third CMP process to expose the top surface of the zeroth interlayer dielectric layer, and to leave the work function metal layer and the metal electrode layer remaining in the gate recess to form the metal gate.

[0018] Optionally, the dielectric material covering the contact etch stop layer includes a first dielectric layer stacked on a surface of the contact etch stop layer and a second dielectric layer stacked on a surface of the first dielectric layer, wherein a hardness of the second dielectric layer is greater than a hardness of the first dielectric layer.

[0019] Optionally, the first dielectric layer is a first silicon oxide layer formed by a HARP process, and the second dielectric layer is a second silicon oxide layer formed by a HDP process.

[0020] Optionally, before etching the stack of the dummy gate structure and the contact etch stop layer, a top surface of the dummy gate structure is lower than a top surface of the zeroth interlayer dielectric layer around the dummy gate structure.

[0021] Optionally, after forming the zeroth ILD layer around the dummy gate structure, the manufacturing method comprises:

[0022] measuring a first height of a top surface of the zeroth ILD layer relative to a top surface of the substrate, and measuring a second height of a top surface of the stack relative to the top surface of the substrate; and

[0023] deriving a thickness of the stack to be etched according to the first height, the second height, and the height difference to be formed, to set parameters for etching the stack according to the thickness of the stack to be etched.

[0024] Optionally, the thickness of the stack to be etched away is equal to (H2-(H1-H3)), where H1 represents the first height, H2 represents the second height, and H3 represents the height difference.

[0025] Optionally, the contact etch stop layer and the dummy gate both have etch selectivity with the zeroth ILD layer, and etching the stack of the dummy gate structure and the contact etch stop layer is performed using maskless etching.

[0026] Optionally, the dummy gate is used as a polishing stop layer when performing the second CMP process.

[0027] Optionally, a height difference between the top surface of the stack and the top surface of the zeroth ILD layer is greater than or equal to and less than or equal to

[0028] The semiconductor device manufacturing method provided by the application includes the following steps: after a first CMP process is performed to form a zeroth interlayer dielectric layer around the dummy gate structure, the stack of the dummy gate structure and the contact etching stop layer is etched to expose the top surface of the dummy gate structure, a height difference is formed between the top surface of the dummy gate structure and the top surface of the zeroth interlayer dielectric layer, then a second CMP process is performed to reduce the height difference and make the dummy gate structure reach a target thickness, and when the second CMP process is performed, the zeroth interlayer dielectric layer is ground more than the dummy gate structure, so that when the grinding is completed, the risk of forming a dish-shaped defect falls on the dummy gate structure, the risk of forming a dish-shaped defect on the surface of the zeroth interlayer dielectric layer is reduced, and the flatness of the dummy gate structure and the zeroth interlayer dielectric layer is improved; and since the dummy gate structure is removed, the dish-shaped defect on the dummy gate structure is removed together, the risk of forming a dish-shaped defect is transferred from the zeroth interlayer dielectric layer in the prior art to the dummy gate structure in the application, and with the effect of the second CMP process on the relatively low dummy gate structure being removed, the risk of residual metal gate material on the top surface of the zeroth interlayer dielectric layer is reduced, and the process reliability is improved.

[0029] In addition, when the zeroth interlayer dielectric layer is formed around the dummy gate structure, a dielectric material is covered on the contact etching stop layer, and the dielectric material is ground by using a first CMP process to cover the contact etching stop layer on the top of the dummy gate structure as a grinding stop layer, and after the first CMP process is completed, the contact etching stop layer on the top of the dummy gate structure is exposed. A dielectric material with high hardness can be used as the top layer of the dielectric material to be ground by using the first CMP process, so that the problem of forming a dish-shaped defect on the top surface of the zeroth interlayer dielectric layer is improved.

[0030] Unlike the prior art which only uses one CMP process to expose the dummy gate structure, the semiconductor device manufacturing method provided by the application uses two CMP processes to expose the dummy gate structure, wherein the zeroth interlayer dielectric layer around the dummy gate structure is formed by using a first CMP process, then the stack of the dummy gate structure and the contact etching stop layer is etched to form a height difference between the top surface of the dummy gate structure and the top surface of the zeroth interlayer dielectric layer, and then a second CMP process is performed, and since the etching of the stack bears part of the consumption of the stack, the grinding time can be shortened to avoid scratches caused by long-time grinding. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figures 1A-1Fis a cross-sectional view of a semiconductor device manufacturing method in a manufacturing process.

[0032] Figure 2 is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present application.

[0033] Figures 3A-3H is a cross-sectional view of a semiconductor device manufacturing method according to an embodiment of the present application in a manufacturing process. DETAILED DESCRIPTION

[0034] The semiconductor device manufacturing method according to the present application will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent from the following description. It should be understood that the drawings of the specification are very simplified and use non-precise proportions, only to facilitate, clarify the purpose of assisting the description of the embodiments of the present application. It should be noted that the order of the steps in the methods presented herein is not necessarily the only order in which the steps can be performed. Some of the steps described can be omitted and / or other steps not described herein can be added to the method. It should be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a structure is inverted or otherwise positioned in a different orientation than that shown in the figures, the exemplary term "on" can include both "on" and "under" in addition to other orientations.

[0035] Figures 1A-1F is a cross-sectional view of a semiconductor device manufacturing method in a manufacturing process. In order to more clearly illustrate the embodiments of the present application, the following first refers to Figures 1A-1F A semiconductor device manufacturing method is introduced, which forms a dummy gate on a substrate first, and then replaces the dummy gate with a metal gate. Specifically, the following processes are included:

[0036] As shown in Figure 1A , a dummy gate structure using a polysilicon gate is formed on a substrate 100, which includes a dummy gate DG, and a contact etch stop layer 110 (CESL) is formed along the dummy gate structure and the surface of the substrate 100;

[0037] As shown in Figure 1B , a dielectric material is covered on the dummy gate structure and the surrounding substrate 100;

[0038] As shown in Figure 1C , a CMP process is performed to expose the top surface of the dummy gate DG and reach a target thickness, and the remaining dielectric material serves as a zeroth interlayer dielectric layer ILD0;

[0039] As shown in Figure 1DAs shown, the dummy gate DG in the dummy gate structure is removed, and a gate trench GT is formed at the original location where the dummy gate DG was set.

[0040] like Figure 1E As shown, a metal material is deposited in the gate recess GT and on the zeroth interlayer dielectric layer ILD0;

[0041] like Figure 1F As shown, the CMP process is performed again to expose the top surface of the zeroth interlayer dielectric layer ILD0, and the remaining metal material located in the gate recess GT serves as the metal gate MG.

[0042] In the above process, such as Figure 1C and Figure 1D As shown, after the previous CMP process, a noticeable dish-shaped defect 10 will form on the top surface of the zero-layer interlayer dielectric layer ILD0. After the deposition of the metal material, the metal material on the bottom surface of the dish-shaped defect 10 is relatively thick; as... Figure 1F As shown, after the next CMP process, while ensuring the thickness and surface quality of the metal gate MG formed in the gate recess GT, the metal material on the bottom surface of the dish-shaped defect 10 is difficult to remove completely, forming metal residue 11, which affects the reliability of subsequent processes. For example, it can easily cause short circuits in the metal interconnects formed on the zero-layer inter-dielectric layer ILD0 and increase signal interference, which will reduce the yield of semiconductor devices.

[0043] Compared to Figures 1A-1F The process shown utilizes the semiconductor device fabrication method of this embodiment of the invention. Before performing the aforementioned previous CMP process, a height difference is created between the top surface of the dielectric material and the top surface of the dummy gate. During the previous CMP process to remove excess dielectric material and achieve the target thickness for the dummy gate, although the grinding speeds of the dielectric material and the dummy gate differ, the process of reducing the height difference due to the higher dielectric material is less likely to form dish-shaped defects on the surface of the formed inter-layer dielectric layer (ILD0). Furthermore, since the dummy gate will be removed later, the impact of this CMP process on the lower-height dummy gate is eliminated. Overall, the semiconductor device fabrication method of this embodiment of the invention can reduce the risk of forming dish-shaped defects on the top surface of the inter-layer dielectric layer (ILD0) that easily retain metal gate material, thereby improving process reliability.

[0044] The following combination Figure 2 and Figures 3A-3H The manufacturing method of the semiconductor device according to embodiments of the present invention will be described in detail.

[0045] Reference Figure 2 and Figure 3AFirst, step S1 is performed to form at least one dummy gate structure on the substrate 100, the dummy gate structure including a dummy gate DG and a sidewall 102 covering both sides of the dummy gate DG.

[0046] The substrate 100 can be a silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator substrate, a germanium-silicon-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride substrate or a gallium arsenide substrate), or other substrates known to those skilled in the art for supporting semiconductor devices.

[0047] The at least one dummy gate structure formed on the substrate 100 is used to form at least one MOS transistor, which can include an NMOS transistor and / or a PMOS transistor. Each dummy gate structure can include a gate dielectric layer 101 formed on the surface of the substrate 100, a dummy gate DG stacked on the gate dielectric layer 101, and a sidewall 102 covering the side surfaces of the gate dielectric layer 101 and the dummy gate DG. The gate dielectric layer 101 can be a single layer or multiple layers. For example, in one embodiment, the gate dielectric layer 101 includes a silicon oxide layer and a high dielectric constant layer stacked on the silicon oxide layer. In addition, the dummy gate structure can further include an etching stop layer (e.g., titanium nitride) between the gate dielectric layer 101 and the dummy gate DG, which protects the gate dielectric layer 101 when the dummy gate DG is removed later. The thickness of the dummy gate DG is, for example, about 1000-2000 angstroms.

[0048] The sidewall 102 covering both sides of the dummy gate DG can be a single-layer structure or a multi-layer structure, and can include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0049] Because of the height difference between the dummy gate structure and the surface of the substrate 100, a gap is formed around the dummy gate structure, which is filled with a dielectric material later.

[0050] It should be noted that the present embodiment focuses on how to avoid the problem of forming a disc-shaped defect that is prone to retaining metal material on the top surface of the zeroth ILD layer. Those skilled in the art can understand that the detailed whole process of manufacturing a semiconductor device does not need to be described in the specification, and the drawings only schematically represent a few dummy gate structures as examples. Before step S2, the following process steps (not shown) can also be completed, but are not limited to: a step of forming an isolation trench (e.g., a shallow trench isolation, STI) and an ion implantation region in the substrate 100, a step of forming an LDD region in the substrate 100 under the end portion of the dummy gate DG and the sidewall 102, and a step of forming a source region and a drain region in the substrate 100 on both sides of the dummy gate structure, etc.

[0051] Referring to Figure 2 and Figure 3A , a step S2 is performed to conformally form a contact etch stop layer 110 (CESL) on the dummy gate structure and the surface of the substrate 100. The contact etch stop layer 110 can serve as a stop layer for a subsequent CMP process and as a protective layer for the substrate 100. The contact etch stop layer 110 can include at least one of silicon oxide, silicon nitride and silicon oxynitride. As an example, in the present embodiment, the contact etch stop layer 110 is formed of silicon nitride.

[0052] Next, referring to Figure 2 , a step S3 is performed to form a zeroth interlayer dielectric layer around the dummy gate structure.

[0053] To form the zeroth interlayer dielectric layer around the dummy gate structure, a dielectric material can be first deposited on the contact etch stop layer 110 such that the surface of the dielectric material is higher than the top surface of the dummy gate structure, and then a CMP process (referred to as a first CMP process) is performed to polish the contact etch stop layer 110 on the top of the dummy gate structure as a polishing stop layer, and the remaining dielectric material is left around the dummy gate structure to form the zeroth interlayer dielectric layer (ILD0).

[0054] In view of the problems of the process shown in Figures 1A-1F , it is desirable to improve the flatness of the top surface of the zeroth interlayer dielectric layer ILD0 obtained after the CMP process is performed, and to avoid the formation of serious dishing defects. To this end, in the present embodiment, in the step S3, referring to Figure 3B , a first dielectric layer 121 is first deposited to fill the gap around the dummy gate structure. To ensure the filling quality, the first dielectric layer 121 can have a relatively low hardness, and then a second dielectric layer 122 having a relatively high hardness is deposited to serve as the top layer of the dielectric material to be polished in the subsequent CMP process, so as to reduce the polishing speed of the CMP process on the stack of the first dielectric layer 121 and the second dielectric layer 122, and to avoid the formation of serious dishing defects on the surface of the dielectric material obtained after polishing. As an example, the first dielectric layer 121 is a silicon oxide layer formed by a HARP (high aspect ratio process) process, and the second dielectric layer 122 is another silicon oxide layer formed by a HDP (high density plasma chemical vapor deposition) process.

[0055] Referring to Figure 3CIn this embodiment, after the first dielectric layer 121 and the second dielectric layer 122 are sequentially formed on the contact etching stop layer 110 by step S3, a CMP process (i.e., a first CMP process) is performed to expose the contact etching stop layer 110 covering the top of the dummy gate structure, and the remaining first dielectric layer 121 and the second dielectric layer 122 are located around the dummy gate structure as the zeroth interlayer dielectric layer ILD0. As an example, the abrasive used in the first CMP process is a silicon oxide abrasive, and the selectivity ratio of the abrasive to silicon oxide (exemplarily as the material of the first dielectric layer 121 and the second dielectric layer 122) and silicon nitride (exemplarily as the material of the contact etching stop layer 110) is greater than 5:1.

[0056] In step S3, by setting the second dielectric layer 122 with high hardness and appropriately setting the parameters of the first CMP process, the top surface of the zeroth interlayer dielectric layer ILD0 around the dummy gate structure can be made higher than the top surface of the dummy gate DG in the dummy gate structure while exposing the contact etching stop layer 110 on the top of the dummy gate structure, so as to avoid serious dishing defects and make the lowest point of the dishing on the surface of the zeroth interlayer dielectric layer ILD0 higher than the dummy gate DG, which can shorten the polishing time and reduce the risk of forming serious dishing and scratch defects on the surface of the contact etching stop layer 110 and the zeroth interlayer dielectric layer ILD0 due to long-time polishing.

[0057] After the zeroth interlayer dielectric layer ILD0 is filled around the dummy gate structure, a thickness test can be performed to detect the effect of the above-mentioned first CMP process and provide reference data for subsequent steps S4 and S5. For example, the first height H1 of the top surface of the zeroth interlayer dielectric layer ILD0 relative to the top surface of the substrate 100 can be measured by the built-in function of the CMP machine, and the second height H2 of the top surface of the stack (or wrapped structure) composed of the dummy gate structure and the contact etching stop layer 110 relative to the top surface of the substrate 100 can be measured.

[0058] Referring to Figure 2 and Figure 3D , step S4 can be performed to etch the stack composed of the dummy gate structure and the contact etching stop layer 110 to expose the top surface of the dummy gate DG and form a height difference H3 between the top surface of the dummy gate DG and the top surface of the zeroth interlayer dielectric layer ILD0. That is, by step S4, a step with a height of H3 is formed between the dummy gate DG and the zeroth interlayer dielectric layer ILD0 around the dummy gate DG.

[0059] The contact etching stop layer 110 and the zeroth interlayer dielectric layer ILD0 have better etching selectivity, for example, so that the etching of the stack of the dummy gate structure and the contact etching stop layer 110 can be performed by maskless etching. In this embodiment, the contact etching stop layer 110 and the zeroth interlayer dielectric layer ILD0 are formed of silicon nitride and silicon oxide respectively, and both have better etching selectivity. Therefore, the step S4 can be completed by maskless etching, which can simplify the process. The etching of the stack of the dummy gate structure and the contact etching stop layer 110 can be performed by dry etching or wet etching.

[0060] During the etching of the stack, according to the etching thickness requirement, the contact etching stop layer 110 above the top surface of the dummy gate DG can be etched and removed without etching the dummy gate DG, or the contact etching stop layer 110 above the top surface of the dummy gate DG and part of the thickness of the dummy gate DG can be etched and removed.

[0061] The height difference H3 can be set according to specific requirements, and should be avoided to be too large or too small. Because, if the height difference H3 is too large, the thickness of the remaining dummy gate DG after the etching of the step S4 is small, which can affect the thickness of the metal gate replacing the dummy gate DG in the subsequent process. However, if the height difference H3 is too small, the thickness of the remaining dummy gate DG after the etching of the step S4 is large, and the grinding amount is large when the dummy gate DG is further ground to the target thickness by the CMP process in the subsequent step S5, which can easily cause scratch defects. In this embodiment, the height difference H3 is about Preferably, the height difference H3 is greater than or equal to and less than or equal to

[0062] In addition, the height difference H3 can be set in advance before etching the stack layer composed of the dummy gate structure and the contact etching stop layer 110. In the embodiment, the height difference H3 is the thickness that needs to be removed at least in the second CMP process in step S5. Further, in order to shorten the polishing time of the second CMP process, the dummy gate DG formed in step S4 can be used as a polishing stop layer of the second CMP process or the height difference H3 can be used as a target removal amount of the second CMP process, so that the consumption of the dummy gate DG in step S5 is small, and after step S4, the thickness of the remaining dummy gate DG is equal to or slightly greater than the target thickness of the dummy gate DG in step S5. In this way, the height difference H3 to be formed in step S4 can be set according to the difference between the first height H1 corresponding to the zeroth interlayer dielectric layer ILD0 and the target height of the dummy gate DG, for example, the height difference H3 is equal to or slightly less than the difference between the first height H1 corresponding to the zeroth interlayer dielectric layer ILD0 and the target height of the dummy gate DG.

[0063] In the embodiment, the thickness to be etched (or etching degree) in step S4 can be calculated by using the first height H1 and the second height H2 measured after step S3 and the value of the height difference H3, which can improve the accuracy of the actual obtained height difference H3 and reduce errors. Specifically, the thickness of the stack layer to be etched can be obtained by calculating (H2-(H1-H3)). After obtaining the thickness of the stack layer to be etched, the etching parameters can be set based on the thickness to be removed.

[0064] Referring to Figure 2 and Figure 3E , step S5 is performed to perform a CMP process (referred to as a second CMP process) to reduce the height difference H3 and make the dummy gate DG reach the target thickness. As an example, the polishing liquid used in the second CMP process is a silicon oxide polishing liquid, which has a selectivity greater than 20:1 for silicon oxide (exemplarily used as the material of the first dielectric layer 121 and the second dielectric layer 122) and polysilicon (exemplarily used as the material of the dummy gate DG).

[0065] In the embodiment, a height difference H3 is formed between the top surface of the dummy gate DG and the top surface of the zeroth interlayer dielectric layer ILD0 before the second CMP process is performed; during the second CMP process, the top of the dummy gate DG after the etching in step S4 can be set as the polishing endpoint of the second CMP process, or the height difference H3 can be set as the target removal amount of the second CMP process; although there is a difference in polishing speed between the zeroth interlayer dielectric layer ILD0 and the dummy gate DG, because the top surface of the zeroth interlayer dielectric layer ILD0 is higher, the amount of the zeroth interlayer dielectric layer ILD0 to be polished is larger during the polishing process, and the risk of forming a clear dishing defect on the surface of the zeroth interlayer dielectric layer ILD0 is reduced, so that the flatness of the dummy gate DG and the zeroth interlayer dielectric layer ILD0 is improved after the second CMP process, compared with the process shown in Figures 1A-1F In addition, because the dummy gate DG is located lower, the risk of forming a dishing defect is transferred from the zeroth interlayer dielectric layer ILD0 to the dummy gate DG after the second CMP process, and because the dummy gate DG will be removed later, the influence of the second CMP process on the dummy gate DG located lower (such as the possible surface defects, such as dishing) is removed, and the metal gate will not be affected. The manufacturing method of the embodiment reduces the risk of forming a dishing defect that is easy to leave metal material on the top surface of the zeroth interlayer dielectric layer ILD0, thereby reducing the risk of leaving metal material on the top surface of the zeroth interlayer dielectric layer ILD0, and improving the process reliability.

[0066] Referring to Figure 2 and Figure 3F , step S6 is performed to remove the dummy gate DG, and a gate recess GT is formed in the area of the dummy gate DG.

[0067] The dummy gate DG can be removed by dry etching or wet etching. In the embodiment, the dummy gate DG is made of polysilicon, and if the dummy gate DG is removed by wet etching, an etching solution containing nitric acid can be used, and if the dummy gate DG is removed by dry etching, chlorine or hydrogen bromide can be used as the process gas. After the dummy gate DG is removed, the area where the dummy gate DG was originally located forms a gate recess GT, the sidewall of the gate recess GT is formed by the sidewall of the sidewall 102 originally located on the side of the dummy gate GT, and the bottom wall of the gate recess GT exposes the gate dielectric layer 101 originally located below the dummy gate DG.

[0068] Referring to Figure 2Afterwards, step S7 can be performed to form a metal gate in the gate trench GT. The metal gate can include a work function metal layer and a metal electrode layer, which can satisfy the work function requirement of the corresponding transistor. Depending on the type of the transistor to be formed by the metal gate, the material of the metal gate filled in each gate trench GT can be selected accordingly, and the structure of the metal gate can refer to the technology disclosed in the art.

[0069] As an example, step S7 can include:

[0070] First, a work function metal layer is conformally formed on the inner surface of the gate trench GT and the top surface of the zeroth interlayer dielectric layer ILD0. In some embodiments, different work function metal layers are formed in two different gate trenches GT, and then a work function metal layer is conformally deposited in each gate trench GT and the surface of the zeroth interlayer dielectric layer ILD0. After that, part of the work function metal layer in the gate trench GT is removed by a lithography and etching process, and then another work function metal layer is deposited. In addition, the work function metal layer formed in the same gate trench GT can be one or more layers.

[0071] Afterwards, referring to Figure 3G , a metal electrode layer 130 is formed, which fills the gate trench GT and covers the top surface of the zeroth interlayer dielectric layer ILD0.

[0072] Then, referring to Figure 3H , a CMP process (denoted as the third CMP process) is performed to expose the top surface of the zeroth interlayer dielectric layer ILD0, and the remaining work function metal layer and metal electrode layer 130 are located in the gate trench GT and form a metal gate MG. Each metal gate MG and the source and drain regions formed on both sides thereof in the substrate 100 constitute a MOS transistor.

[0073] The manufacturing method of the semiconductor device described in the above embodiments has a high flatness of the dummy gate DG and the zeroth interlayer dielectric layer ILD0 after the second CMP process, so that when the third CMP process is performed, the work function metal layer and the metal electrode layer 130 on the top surface of the zeroth interlayer dielectric layer ILD0 can be easily removed, while ensuring that the metal gate MG formed in the gate trench GT is not excessively polished. The performance of the manufactured semiconductor device can be optimized.

[0074] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application by using the disclosed methods and technical contents. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: At least one dummy gate structure is formed on a substrate, the dummy gate structure including a dummy gate and sidewalls covering both sides of the dummy gate; A contact etch stop layer is formed conformally on the dummy gate structure and the substrate surface; A dielectric material is covered on the contact etch stop layer, and the top surface of the dielectric material is higher than the top surface of the dummy gate structure. A first CMP process is performed, with the contact etch stop layer covering the top of the dummy gate structure serving as the grinding stop layer, and the remaining dielectric material located around the dummy gate structure to form the zeroth interlayer dielectric layer; The stack of the dummy gate structure and the contact etch stop layer is etched to expose the top surface of the dummy gate, forming a height difference between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer, wherein the top surface of the dummy gate is lower than the top surface of the zeroth interlayer dielectric layer. A second CMP process is performed to reduce the height difference and make the dummy gate reach the target thickness. Remove the dummy gate and form a gate recess in the region of the dummy gate; and A metal gate is formed within the gate recess.

2. The manufacturing method as described in claim 1, characterized in that, Forming the metal gate within the gate recess includes: A conformal topographic functional metal layer is formed on the inner surface of the gate recess and the top surface of the zeroth interlayer dielectric layer; A metal electrode layer is formed, the metal electrode layer filling the gate recess and covering the top surface of the zeroth interlayer dielectric layer; and A third CMP process is performed to expose the top surface of the zeroth interlayer dielectric layer. The remaining work function metal layer and the metal electrode layer are located within the gate recess and form the metal gate.

3. The manufacturing method as described in claim 1, characterized in that, The dielectric material covering the contact etch stop layer includes a first dielectric layer stacked on the surface of the contact etch stop layer and a second dielectric layer stacked on the surface of the first dielectric layer, wherein the hardness of the second dielectric layer is greater than the hardness of the first dielectric layer.

4. The manufacturing method as described in claim 3, characterized in that, The first dielectric layer is a silicon oxide layer formed using the HARP process, and the second dielectric layer is another silicon oxide layer formed using the HDP process.

5. The manufacturing method as described in claim 1, characterized in that, Before etching the stack formed by the dummy gate structure and the contact etch stop layer, the top surface of the dummy gate is lower than the top surface of the surrounding zeroth interlayer dielectric layer.

6. The manufacturing method as described in claim 1, characterized in that, After forming the zeroth interlayer dielectric layer around the dummy gate structure, the fabrication method includes: Measure a first height of the top surface of the zeroth interlayer dielectric layer relative to the top surface of the substrate, and measure a second height of the top surface of the stacked layers relative to the top surface of the substrate; and The thickness of the stack to be etched away is determined based on the first height, the second height, and the height difference to be formed, so that the parameters for etching the stack are set according to the thickness of the stack to be etched away.

7. The manufacturing method as described in claim 6, characterized in that, The thickness of the stack to be etched away is equal to (H2-(H1-H3)), where H1 represents the first height, H2 represents the second height, and H3 represents the height difference.

8. The manufacturing method as described in claim 1, characterized in that, Both the contact etch stop layer and the dummy gate have etch selectivity with the zeroth layer dielectric layer, and the stack formed by the dummy gate structure and the contact etch stop layer is etched using maskless etching.

9. The manufacturing method as described in claim 1, characterized in that, During the second CMP process, the dummy gate is used as the grinding stop layer.

10. The manufacturing method according to any one of claims 1 to 9, characterized in that, The height difference formed between the top surface of the dummy gate and the top surface of the zeroth interlayer dielectric layer is greater than or equal to 100 Å and less than or equal to 150 Å.

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