Light emitting diodes and articles with improved etch bias

Abstract

The invention provides a light emitting diode capable of improving etching deviation and a product, and belongs to the technical field of photoelectron manufacturing. The light emitting diode comprises an epitaxial layer, the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are stacked in sequence, and the second semiconductor layer is provided with a first through hole exposing the first semiconductor layer; the surface of the second semiconductor layer is provided with a cutting channel exposed out of the first semiconductor layer, the cutting channel is located on the peripheral edge of the second semiconductor layer, and the distance between the side wall of the cutting channel and the side wall of the first semiconductor layer is 3.5-6 microns. According to the embodiment of the invention, the problem of etching deviation caused by photomask deviation when the cutting channel is etched can be improved, and the light-emitting diode is prevented from easily leaking electricity and being short-circuited.

Description

Technical Field

[0001] The present disclosure relates to the technical field of optoelectronic manufacturing, and in particular to a light emitting diode and a product with improved etching deviation. Background Art

[0002] Light Emitting Diode (LED) is a common product. LED is usually manufactured by manufacturing various film layers on a substrate, performing graphic processing, and then cutting to form individual LED core particles.

[0003] In the related art, the product usually includes: a sapphire substrate and an epitaxial layer. The epitaxial layer is stacked on the sapphire substrate. A cutting path is provided on the epitaxial layer. In the subsequent process, a mask of corresponding size will be designed according to the distribution position of the cutting path, and the epitaxial layer will be etched along the cutting path, which can divide the epitaxial layer into multiple independent light-emitting structures.

[0004] For vertically structured light-emitting diodes, laser lift-off is usually used to remove the sapphire substrate after preparation. Since the lattice parameter of the sapphire substrate is smaller than that of the epitaxial layer, the epitaxial layer grown on the sapphire substrate will be subjected to compressive stress. After the sapphire substrate is removed, the compressive stress acting on the epitaxial layer disappears, causing the peripheral edge of the epitaxial layer to have a certain degree of lateral expansion in the direction parallel to the sapphire substrate. If the original size mask is still used to etch the epitaxial layer, the area outside the cutting path of the epitaxial layer will be etched, resulting in etching deviation, which can easily lead to leakage and short circuit. Summary of the invention

[0005] The embodiments of the present disclosure provide a light-emitting diode and product with improved etching deviation, which can improve the problem of mask deviation when etching cutting paths, thereby preventing the light-emitting diode from easily leaking electricity and short-circuiting. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode, which includes an epitaxial layer, wherein the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, the second semiconductor layer having a first through hole exposing the first semiconductor layer; the surface of the second semiconductor layer has a cutting path exposing the first semiconductor layer, the cutting path is located at the peripheral edge of the second semiconductor layer, and the distance from the side wall of the cutting path to the side wall of the first semiconductor layer is 3.5μm to 6μm.

[0007] Optionally, the light-emitting diode also includes a transparent conductive layer, which is located on a surface of the second semiconductor layer away from the first semiconductor layer, and has a second through hole exposing the first through hole; the shortest distance between the side wall of the transparent conductive layer and the side wall of the cutting path is greater than the shortest distance between the side wall of the second through hole and the side wall of the first through hole.

[0008] Optionally, the light-emitting diode also includes a reflective layer, which is located on the surface of the transparent conductive layer away from the epitaxial layer, and has a third through hole exposing the first through hole and the second through hole; the shortest distance between the side wall of the reflective layer and the side wall of the epitaxial layer is greater than the shortest distance between the side wall of the third through hole and the first through hole.

[0009] Optionally, the light-emitting diode further includes an electrode layer and a passivation layer; the electrode layer is located on a surface of the transparent conductive layer away from the epitaxial layer, and wraps the reflective layer; the passivation layer is located on a surface of the epitaxial layer and on a surface of the transparent conductive layer away from the epitaxial layer, and wraps the electrode layer.

[0010] Optionally, the passivation layer is also located in the first through hole, and the passivation layer has a groove exposing the first semiconductor layer; the light-emitting diode also includes a bonding metal layer and a conductive substrate, the bonding metal layer is located on the surface of the passivation layer away from the epitaxial layer and in the first through hole, and the bonding metal layer is electrically connected to the first semiconductor layer through the groove, and the conductive substrate is located on the surface of the bonding metal layer away from the epitaxial layer.

[0011] An embodiment of the present disclosure provides a product, which includes an epitaxial layer, wherein the epitaxial layer includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence, wherein the surface of the second semiconductor layer has a cutting path exposing the first semiconductor layer, and the cutting path divides the epitaxial layer into a plurality of light-emitting structures; the surface of the epitaxial layer has a central area and an annular area, the annular area surrounds the central area, and a plurality of the light-emitting structures are arranged in the central area and the annular area; the width of at least one cutting path in the annular area is greater than the width of at least one cutting path in the central area.

[0012] Optionally, the annular area includes multiple sub-annular areas, which are arranged around the central area in sequence; for any two adjacent sub-annular areas among the multiple sub-annular areas, the width of at least one cutting path in the sub-annular areas close to the central area is smaller than the width of at least one cutting path in the sub-annular areas away from the central area.

[0013] Optionally, the annular area includes a first sub-annular area and a second sub-annular area sequentially surrounding the central area; the width of at least one cutting line in the central area is 15μm to 55μm, the width of at least one cutting line in the first sub-annular area is 20μm to 60μm, and the width of at least one cutting line in the second sub-annular area is 25μm to 65μm.

[0014] Optionally, the product also includes a transparent conductive layer, which is located on the surface of the second semiconductor layer; the residual length of the light-emitting structure located in the annular area is greater than the residual length of the light-emitting structure located in the central area, and the residual length is the shortest distance from the side wall of the transparent conductive layer to the cutting path.

[0015] Optionally, a residual length of the light emitting structure in the first sub-annular region is smaller than a residual length of the light emitting structure in the second sub-annular region.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diodes provided in the embodiment of the present disclosure are distributed in the edge area of ​​the substrate of the product before segmentation. In this way, the distance between the side wall of the cutting path of the light-emitting diode located in the annular area and the side wall of the first semiconductor layer is larger. When the sapphire substrate is removed, the compressive stress acting on the epitaxial layer disappears, so that the pattern made on the epitaxial layer is laterally expanded in the direction of the peripheral edge of the epitaxial layer. In addition, the size of the lateral expansion is inconsistent for different products, so in order to ensure that the light-emitting structure located in the edge area will not be different in the lateral expansion during the subsequent photolithography process, resulting in the subsequent photolithography pattern being offset to exceed the safety window. By allowing the distance between the cutting path of the light-emitting diode located in the edge area and the side wall of the first semiconductor layer to be larger. In this way, even if the original size mask is still used to etch the epitaxial layer, it is not easy to cause the photolithography to deviate from the safety window due to the lateral expansion of the epitaxial layer, resulting in etching to the second semiconductor layer and other film layers on the second semiconductor layer, causing leakage and short circuit problems in the light-emitting diode. Improve the reliability of the light-emitting diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 It is a structural schematic diagram of a product provided by the related technology;

[0020] Figure 2 It is a top view of a light emitting diode provided by the related technology;

[0021] Figure 3 yes Figure 2 An AA cross-sectional view is provided;

[0022] Figure 4 It is a schematic diagram of growing a GaN layer on a sapphire substrate provided by the related technology;

[0023] Figure 5 It is a schematic diagram of etching of a light emitting diode provided by the related technology;

[0024] Figure 6 is a structural schematic diagram of a product provided by an embodiment of the present disclosure;

[0025] Figure 7 is a schematic diagram of two adjacent light-emitting structures located in a ring area provided by an embodiment of the present disclosure;

[0026] Figure 8 is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure;

[0027] Fig. 9 yes Figure 8 A BB cross-section diagram is provided;

[0028] Fig.10 is a schematic diagram of a light-emitting structure located in a central area provided by an embodiment of the present disclosure;

[0029] Fig.11 yes Fig.10 A CC cross-section diagram is provided;

[0030] Fig.12 is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure;

[0031] Fig.13 yes Fig.12 A DD cross-section diagram is provided;

[0032] Fig.14 is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure;

[0033] Fig.15 yes Fig.14 A cross-sectional view of an EE provided;

[0034] Fig.16 is a schematic diagram of a light-emitting structure located in a central area provided by an embodiment of the present disclosure;

[0035] Fig.17 yes Fig.16 A FF cross-sectional view is provided;

[0036] Fig.18 is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure;

[0037] Fig.19 yes Fig.18 A GG cross-section diagram is provided;

[0038] Fig. 20 is a schematic diagram of a light-emitting structure provided by an embodiment of the present disclosure;

[0039] Fig.21 is an experimental test parameter diagram of a product provided by an embodiment of the present disclosure;

[0040] Fig. 22 It is an experimental test parameter diagram of a product provided by the relevant technology.

[0041] The descriptions of the marks in the figure are as follows:

[0042] 10. Substrate;

[0043] 20, epitaxial layer; 201, cutting road; 202, first through hole; 203, light emitting structure;

[0044] 210, central area; 220, annular area; 221, first sub-annular area; 222, second sub-annular area;

[0045] 21. first semiconductor layer; 22. multi-quantum well layer; 23. second semiconductor layer;

[0046] 30. Transparent conductive layer; 301. Second through hole; 31. Reflective layer; 311. Third through hole; 32. Electrode layer; 33. Passivation layer; 34. Conductive substrate; 35. Bonding metal layer. DETAILED DESCRIPTION

[0047] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0048] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0049] Figure 1 It is a structural schematic diagram of a product provided by the related technology. Figure 1 As shown, the product in the related art includes: a sapphire substrate 10 and an epitaxial layer 20, and the epitaxial layer 20 is located on the surface of the sapphire substrate 10. A cutting path 201 is provided on the epitaxial layer 20, and the cutting path 201 divides the epitaxial layer 20 into a plurality of light-emitting structures 203.

[0050] In the subsequent process, a mask of a corresponding size is designed according to the distribution position of the cutting road 201 , and the epitaxial layer 20 is etched along the cutting road 201 through the mask to divide the epitaxial layer 20 into a plurality of independent light-emitting structures 203 .

[0051] Figure 2 This is a top view of a light emitting diode provided by the related technology. Figure 2 It indicates Figure 1 Any one of the multiple light emitting structures 203. Figure 3 yes Figure 2 An AA cross-section diagram is provided. Figure 2 , 3 As shown, the epitaxial layer 20 includes a first semiconductor layer 21, a multi-quantum well layer 22 and a second semiconductor layer 23 stacked sequentially on a sapphire substrate 10, and the second semiconductor layer 23 has a plurality of first through holes 202 exposing the first semiconductor layer 21, and the plurality of first through holes 202 are arranged at intervals.

[0052] like Figure 3 As shown, a distance Q1 between the sidewall of the cutting street 201 and the sidewall of the first semiconductor layer 21 is less than or equal to a diameter Q2 of the first through hole 202 .

[0053] Due to the vertical structure of the light emitting diode, after the preparation is completed, the sapphire substrate 10 is usually removed by laser lift-off.

[0054] Figure 4 FIG. 1 is a schematic diagram of a GaN layer grown on a sapphire substrate provided by the related art. Figure 4 As shown, the lattice parameter of the sapphire substrate is smaller than that of the epitaxial layer, which causes the epitaxial layer grown on the sapphire substrate to be subjected to compressive stress.

[0055] Figure 5 FIG. 1 is a schematic diagram of etching a light emitting diode provided by the related technology. Figure 5 As shown, after the sapphire substrate is removed, the compressive stress acting on the epitaxial layer 20 disappears, causing the epitaxial layer 20 to have a certain degree of lateral expansion in a direction parallel to the sapphire substrate.

[0056] like Figure 5 As shown, if the original-size mask is still used to etch the epitaxial layer 20, the area outside the cutting path 201 of the epitaxial layer 20 (see the X in the figure) will be etched. Figure 5 After the first semiconductor layer 21, the multi-quantum well layer 22 and the second semiconductor layer 23 of the epitaxial layer 20 are etched, the transparent conductive layer 30 located on the surface of the second semiconductor layer 23 is also etched and exposed, which may easily cause leakage and short circuit problems.

[0057] In particular, the peripheral edge of the epitaxial layer 20 is more likely to expand laterally to a greater extent after the sapphire substrate 10 is removed.

[0058] To this end, an embodiment of the present disclosure provides a product. Figure 6 Schematic diagram of a product provided by an embodiment of the present disclosure. Figure 6 As shown, the article includes an epitaxial layer 20 .

[0059] The epitaxial layer includes a first semiconductor layer 21 , a multi-quantum well layer 22 and a second semiconductor layer 23 stacked in sequence, and a surface of the second semiconductor layer 23 has a cutting path 201 exposing the first semiconductor layer 21 .

[0060] like Figure 6 As shown, the cutting road 201 divides the epitaxial layer 20 into a plurality of light emitting structures 203. The surface of the epitaxial layer 20 has a central region 210 and an annular region 220, which surrounds the central region 210 and has a plurality of light emitting structures 203 arranged therein.

[0061] Figure 7 Schematic diagram of two adjacent light-emitting structures located in a ring area provided by an embodiment of the present disclosure. Figure 7 As shown, the cutting lane 201 refers to a lane between two adjacent light emitting structures 203. The width S of the cutting lane 201 is the distance between the two light emitting structures 203.

[0062] The width S of at least one cutting line in the annular area 220 is greater than the width of at least one cutting line in the central area 210 .

[0063] Figure 8 It is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure. Fig. 9 yes Figure 8 A BB cross-section diagram is provided. Fig.10 It is a schematic diagram of a light-emitting structure located in the central area provided by the present disclosure. Fig.11 yes Fig.10 A CC cross-section diagram is provided.

[0064] Figure 7 and Fig. 9 The difference is Figure 7 The cross-sectional view of two adjacent light-emitting structures is shown in FIG. Figure 7 The cutting can be obtained by cutting at the dotted line indicated in the middle cutting path 201. Fig. 9 A single light emitting structure is shown.

[0065] like Fig. 9 , 11 As shown, the aisle width M1 of the light emitting structure 203 located in the annular area 220 is greater than the aisle width M2 of the light emitting structure 203 located in the central area 210 .

[0066] See also Figure 7 , the aisle width (M1, M2, M3) is half of the width S of the cutting street 201.

[0067] The product provided by the embodiment of the present disclosure includes an epitaxial layer 20, and the epitaxial layer 20 is divided into a plurality of light-emitting structures 203 by a cutting path 201. Among them, the walkway width of the light-emitting structure 203 distributed in the annular region 220 of the epitaxial layer 20 is greater than the walkway width of the light-emitting structure 203 distributed in the central region 210 of the epitaxial layer 20. The walkway width refers to the distance between the side wall of the cutting path 201 and the side wall of the first semiconductor layer 21. That is, the distance between the side wall of the cutting path 201 of the light-emitting structure 203 located in the annular region 220 on the epitaxial layer 20 and the side wall of the first semiconductor layer 21 is made larger. When the sapphire substrate 10 is removed, the compressive stress acting on the epitaxial layer 20 disappears, so that the pattern on the epitaxial layer and the pattern already made on the epitaxial layer will expand laterally in the direction of the peripheral edge of the epitaxial layer 20. In addition, different products have different lateral expansion sizes. Therefore, in order to ensure that the light-emitting structure located at the edge will not deviate beyond the safety window due to different lateral expansion during the subsequent photolithography process, different aisle widths will be set at the edge and in the middle. In this way, even if the original size mask is still used to etch the epitaxial layer, it is not easy for the lithography to deviate from the safety window due to the lateral expansion of the epitaxial layer, resulting in etching to the light-emitting area of ​​the epitaxial layer and the transparent conductive layer, causing leakage and short circuit problems in the light-emitting diode. Improve the reliability of the light-emitting diode.

[0068] Optionally, the product may further include a substrate 10, and the epitaxial layer 20 is located on the substrate 10. Exemplarily, the substrate may be a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate is a transparent substrate. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the LED has good luminous effect and stability.

[0069] Alternatively, if Figure 6 As shown, the central area 210 is circular, the annular area 220 is annular, and the central area 210 and the annular area 220 are concentrically distributed.

[0070] In the disclosed embodiment, the substrate is a four-inch wafer, and the radius of the substrate is 50000 μm. The epitaxial layer 20 located on the substrate is also circular. The radius of the epitaxial layer 20 is 1 μm to 100 μm smaller than the radius of the substrate. For example, the radius of the epitaxial layer 20 may be 49950 μm.

[0071] Alternatively, if Figure 6 As shown, the epitaxial layer 20 is circular, and the ratio of the radius of the central region 210 to the radius of the epitaxial layer 20 is 0.1 to 0.4.

[0072] After removing the substrate, the epitaxial layer 20 located in the edge area of ​​the substrate is more easily deformed and laterally expanded because the epitaxial layer 20 located in the edge area of ​​the substrate is less restricted than the epitaxial layer 20 located in the central area 210 of the substrate. That is, the lateral expansion of the epitaxial layer in the central area 210 of the epitaxial layer 20 is smaller, so the central area 210 can be set relatively large. Since the distance between the side wall of the cutting path 201 and the side wall of the first semiconductor layer 21 in the light-emitting structure 203 in the central area 210 is closer, the area of ​​the light-emitting structure 203 in the central area 210 is larger, thereby increasing the light-emitting area of ​​a single light-emitting structure to increase the brightness of the light-emitting structure 203.

[0073] Exemplarily, the ratio of the radius of the central region 210 to the radius of the epitaxial layer 20 is 0.3.

[0074] Optionally, a ratio of the width of the annular region 220 to the radius of the epitaxial layer 20 is 0.6 to 0.9.

[0075] After removing the substrate, the epitaxial layer 20 located in the edge region of the substrate is less restricted than the epitaxial layer 20 located in the edge region of the substrate. Therefore, the epitaxial layer 20 has a larger lateral expansion in the annular region 220 of the epitaxial layer 20. In order to avoid etching the epitaxial layer 20 to the area outside the cutting path 201 during the subsequent etching, the annular region 220 can be controlled to account for a larger proportion in the epitaxial layer 20, so as to prevent leakage and short circuit problems in the light-emitting diode.

[0076] Exemplarily, the ratio of the radius of the annular region 220 to the radius of the epitaxial layer 20 is 0.7.

[0077] Alternatively, if Figure 6 As shown, the annular region 220 includes a plurality of sub-annular regions 220 , and the plurality of sub-annular regions 220 are sequentially surrounded by the central region 210 .

[0078] In the embodiment of the present disclosure, for any two adjacent sub-annular areas among the multiple sub-annular areas, the width of at least one cutting road in the sub-annular area close to the central area 210 is smaller than the width of at least one cutting road in the sub-annular area away from the central area 210.

[0079] Moreover, for any two adjacent sub-annular areas 220 among the multiple sub-annular areas 220, the aisle width of the light-emitting structure 203 in the sub-annular area 220 close to the central area 210 is smaller than the aisle width of the light-emitting structure 203 in the sub-annular area 220 far from the central area 210.

[0080] After removing the substrate, the epitaxial layer 20 located in the edge region of the substrate is less restricted than the epitaxial layer 20 located in the central region 210 of the substrate, and the restriction on the epitaxial layer 20 gradually decreases from the center to the peripheral edge of the substrate.

[0081] For each sub-annular region 220 in the annular region 220, the epitaxial layer of the light emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is easier to expand laterally, so the epitaxial layer of the light emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is more deformed. Therefore, the aisle width of the light emitting structure 203 in the sub-annular region 220 close to the central region 210 is controlled to be smaller than the aisle length of the light emitting structure 203 in the sub-annular region 220 away from the central region 210. In this way, the area of ​​the light emitting structure 203 in the sub-annular region 220 close to the central region 210 is larger to improve the luminous brightness of the sub-annular region 220; while the area of ​​the light emitting structure 203 in the sub-annular region 220 away from the central region 210 is relatively small to prevent leakage and short circuit problems.

[0082] For example, Figure 6 As shown, the annular region 220 includes a first sub-annular region 221 and a second sub-annular region 222 which are sequentially surrounded by the central region 210 .

[0083] The width of at least one cutting line in the central area 210 is 15 μm to 55 μm, the width of at least one cutting line in the first sub-annular area 221 is 20 μm to 60 μm, and the width of at least one cutting line in the second sub-annular area 222 is 25 μm to 65 μm.

[0084] Fig.12 It is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure. Fig.13 yes Fig.12 A DD cross-section diagram is provided. Fig.12 , Fig.13 The diagram shows the light emitting structure of the first sub-annular area. Figure 8 , Fig. 9 The diagram shows the light emitting structure of the second sub-annular area.

[0085] See also Fig. 9 , 13 , the aisle width M3 of the light emitting structure 203 in the first sub-annular area 221 is smaller than the aisle width M1 of the light emitting structure 203 in the second sub-annular area 222 .

[0086] The walkway width of the light emitting structure 203 in the central area 210 is significantly reduced compared with the walkway width of the light emitting structure 203 in the first sub-annular area 221 and the second sub-annular area 222. This not only makes the area of ​​the epitaxial layer covering the light emitting structure 203 large enough to improve the brightness of the light emitting structure 203 in the central area 210, but also makes the area of ​​the epitaxial layer of the light emitting structure 203 in the first sub-annular area 221 and the second sub-annular area 222 far from the central area 210 relatively small, so as to prevent the subsequent etching of the cutting path from etching the epitaxial layer and the film layer thereon, thereby causing leakage and short circuit problems.

[0087] Optionally, the ratio of the width of the first sub-annular region 221 to the radius of the epitaxial layer 20 is 0.1 to 0.4, and the ratio of the width of the second sub-annular region 222 to the radius of the epitaxial layer 20 is 0.1 to 0.4.

[0088] The width of the first sub-annular region 221 refers to the width of the first sub-annular region 221 in the radial direction of the epitaxial layer 20 , that is, the distance between the inner ring and the outer ring of the first sub-annular region 221 .

[0089] Exemplarily, the ratio of the width of the first sub-annular region 221 to the radius of the epitaxial layer 20 is 0.3.

[0090] Exemplarily, the ratio of the width of the second sub-annular region 222 to the radius of the epitaxial layer 20 is 0.3.

[0091] It should be noted that the widths of the first sub-annular region 221 and the second sub-annular region 222 may be the same or different, and this embodiment of the present disclosure does not limit this.

[0092] Fig.14 It is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure. Fig.15 yes Fig.14 A cross-sectional view of an EE is provided. Fig.16 It is a schematic diagram of a light-emitting structure located in the central area provided by the implementation of the present disclosure. Fig.17 yes Fig.16 A cross-sectional view of an FF is provided.

[0093] like Fig.15 , 17 As shown, the transparent conductive layer 30 is located on the surface of the second semiconductor layer 23 .

[0094] See also Fig.15 , 17 The residual length X1 of the light emitting structure 203 located in the annular area 220 is greater than the residual length X2 of the light emitting structure 203 located in the central area 210 .

[0095] The margin length is the shortest distance from the sidewall of the transparent conductive layer 30 to the cutting path 201 .

[0096] The product provided by the embodiment of the present disclosure includes an epitaxial layer 20 and a transparent conductive layer 30, and the epitaxial layer 20 is divided into a plurality of light-emitting structures 203 by a cutting path 201. Among them, the residual length of the light-emitting structure 203 distributed in the annular region 220 of the epitaxial layer 20 is greater than the residual length of the light-emitting structure 203 distributed in the central region 210 of the epitaxial layer 20. The residual length refers to the shortest distance from the side wall of the transparent conductive layer 30 to the cutting path 201. That is, the distance from the side wall of the transparent conductive layer 30 of the light-emitting structure 203 located in the annular region 220 on the epitaxial layer 20 to the cutting path 201 is larger. When the sapphire substrate 10 is removed, the compressive stress acting on the epitaxial layer 20 disappears, so that the pattern on the epitaxial layer and the pattern already made on the epitaxial layer will expand laterally in the direction of the peripheral edge of the epitaxial layer 20. In addition, different products have different lateral expansion sizes. Therefore, in order to ensure that the light-emitting structure located at the edge will not deviate beyond the safety window due to different lateral expansion during the subsequent photolithography process, different margin lengths will be set at the edge and in the middle. In this way, even if the original size mask is still used to etch the epitaxial layer, it is not easy for the lithography to deviate from the safety window due to the lateral expansion of the epitaxial layer, resulting in etching on the transparent conductive layer, causing leakage and short circuit problems in the light-emitting diode. Improve the reliability of the light-emitting diode.

[0097] Optionally, the transparent conductive layer may be an indium tin oxide (ITO) layer. The ITO layer has good transmittance and low resistivity. Using the ITO layer as the transparent conductive layer can allow more light to be transmitted from the transparent conductive layer, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves injection efficiency.

[0098] For example, the transparent conductive layer may be an indium zinc oxide (IZO) layer. The IZO layer has good transmittance and low resistivity. Using the IZO layer as the transparent conductive layer can allow more light to be transmitted from the transparent conductive layer, thereby ensuring the light output effect; at the same time, due to the low resistivity, it is also convenient for carrier conduction and improves injection efficiency.

[0099] Exemplarily, the thickness of each transparent conductive layer may be 600 angstroms to 2000 angstroms. For example, the thickness of the transparent conductive layer 30 is 1500 angstroms.

[0100] In the embodiment of the present disclosure, for any two adjacent sub-annular areas 220 among the multiple sub-annular areas 220, the residual length of the light-emitting structure 203 in the sub-annular area 220 close to the central area 210 is smaller than the residual length of the light-emitting structure 203 in the sub-annular area 220 far from the central area 210.

[0101] After removing the substrate, the epitaxial layer 20 located in the edge region of the substrate is less restricted than the epitaxial layer 20 located in the central region 210 of the substrate, and the restriction on the epitaxial layer 20 gradually decreases from the center to the peripheral edge of the substrate.

[0102] For each sub-annular region 220 in the annular region 220, the transparent conductive layer 30 of the light emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is easier to expand laterally, so the deformation degree of the transparent conductive layer 30 of the light emitting structure 203 in the sub-annular region 220 closer to the peripheral edge of the epitaxial layer 20 is greater. Therefore, the residual length of the light emitting structure 203 in the sub-annular region 220 close to the central region 210 is controlled to be smaller than the residual length of the light emitting structure 203 in the sub-annular region 220 away from the central region 210. In this way, the coverage rate of the transparent conductive layer 30 of the light emitting structure 203 in the sub-annular region 220 close to the central region 210 is greater, so as to improve the luminous brightness of the sub-annular region 220; while the coverage rate of the transparent conductive layer 30 of the light emitting structure 203 in the sub-annular region 220 away from the central region 210 is relatively small, so as to prevent leakage and short circuit problems.

[0103] Fig.18 It is a schematic diagram of a light-emitting structure located in a ring area provided by an embodiment of the present disclosure. Fig.19 yes Fig.18 A cross-sectional view of GG is provided. Fig.18 , Fig.19 The light emitting structure 203 of the first sub-annular region 221 is shown. Fig.14 , Fig.15 The light emitting structure 203 of the second sub-annular region 222 is shown.

[0104] See also Fig.15 , 19 , the remaining length X3 of the light emitting structure 203 in the first sub-annular region 221 is smaller than the remaining length X1 of the light emitting structure 203 in the second sub-annular region 222 .

[0105] Optionally, the residual length of the light emitting structure 203 in the first sub-annular region 221 is 9 μm to 12 μm.

[0106] Exemplarily, the remaining length of the light emitting structure 203 in the first sub-annular region 221 is 10 μm.

[0107] Optionally, the remaining length of the light emitting structure 203 in the second sub-annular region 222 is 15 μm to 20 μm.

[0108] Exemplarily, the residual length of the light emitting structure 203 in the second sub-annular region 222 is 17 μm.

[0109] Optionally, the residual length of the light emitting structure 203 in the central area 210 is 1 μm to 5 μm.

[0110] Exemplarily, the residual length of the light emitting structure 203 in the central region 210 is 3 μm.

[0111] The residual length of the light emitting structure 203 in the central area 210 is significantly reduced compared with the residual length of the light emitting structure 203 in the first sub-annular area 221 and the second sub-annular area 222. In this way, the area covered by the transparent conductive layer on the light emitting structure 203 is large enough to improve the brightness of the light emitting structure 203 in the central area 210; and the coverage rate of the transparent conductive layer 30 of the light emitting structure 203 in the first sub-annular area 221 and the second sub-annular area 222 far from the central area 210 is relatively small to prevent leakage and short circuit problems.

[0112] Fig. 20 Schematic diagram of a light emitting structure provided by an embodiment of the present disclosure. Fig. 20 As shown, the product further includes a reflective layer 31, an electrode layer 32 and a passivation layer 33. The reflective layer 31 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the electrode layer 32 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the electrode layer 32 covers the reflective layer 31.

[0113] The reflective layer 31 can be used to reflect the light emitted from the epitaxial layer 20 , so that more light can be emitted from the light-emitting surface of the epitaxial layer 20 , thereby improving the light-emitting intensity of the light-emitting diode.

[0114] At the same time, an electrode layer 32 is also covered on the reflective layer 31 to prevent the metal in the reflective layer 31 from migrating upwards, and the electrode layer 32 is used to connect to an external power source to energize the epitaxial layer 20 .

[0115] Optionally, the reflective layer 31 includes an Ag layer, a Ni layer, and a TiW layer stacked in sequence.

[0116] Since Ag has a good reflective effect, providing an Ag layer in the reflective layer can enhance the reflection of light by the reflective layer and improve the light emitting brightness of the light emitting surface of the light emitting diode.

[0117] The Ni layer has good corrosion resistance and wear resistance, and the TiW layer can be successfully deposited on other films as an adhesion layer without peeling or cracking. The alternating stacked Ni and TiW layers can act as a barrier layer to protect the silver mirror.

[0118] Exemplarily, the thickness of the Ag layer is 1400 angstroms to 1700 angstroms. For example, the thickness of the Ag layer is 1500 angstroms.

[0119] Exemplarily, the thickness of the Ni layer is 100 angstroms to 300 angstroms. For example, the thickness of the Ni layer is 200 angstroms.

[0120] Exemplarily, the thickness of the TiW layer is 700 angstroms to 1000 angstroms. For example, the thickness of the TiW layer is 800 angstroms.

[0121] Optionally, the electrode layer 32 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms respectively.

[0122] like Fig.13 As shown, the passivation layer 33 is located on the surface of the epitaxial layer 20 and the surface of the transparent conductive layer 30 away from the epitaxial layer 20 , and the passivation layer 33 covers the electrode layer 32 .

[0123] In the above implementation, a passivation layer 33 is provided on the epitaxial layer 20, so that the passivation layer 33 covers the electrode layer 32 and the transparent conductive layer 30 to play a protective role. It can also isolate the electrode layer 32 from other metal film layers formed subsequently to prevent the electrode layer 32 from being electrically connected to other metal film layers, thereby preventing leakage problems.

[0124] Optionally, the passivation layer 33 is a silicon oxide layer or a distributed Bragg reflector (DBR) layer.

[0125] As an example, in the embodiment of the present disclosure, the passivation layer 33 is a silicon oxide layer.

[0126] The silicon oxide layer has good insulation properties, which can prevent the epitaxial layer 20 from contacting other impurities in the external environment and causing leakage, thereby improving the reliability of the light-emitting diode.

[0127] As an example, in the embodiment of the present disclosure, the passivation layer 33 includes a plurality of silicon oxide layers and a plurality of titanium oxide layers that are alternately stacked.

[0128] Among them, multiple periodically alternately stacked SiO2 layers and TiO2 layers can form a DBR layer.

[0129] Exemplarily, the number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0130] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0131] Optionally, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0132] Exemplarily, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0133] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0134] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0135] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0136] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0137] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0138] like Fig. 20 As shown, the product also includes a bonding metal layer 35 and a conductive substrate 34. The bonding metal layer 35 is located on the surface of the passivation layer 33 away from the epitaxial layer 20 and in the first through hole 202, and the bonding metal layer 35 is electrically connected to the first semiconductor layer 21 through the groove. The conductive substrate 34 is located on the surface of the bonding metal layer 35 away from the epitaxial layer 20.

[0139] In the embodiment of the present disclosure, the first through hole 202 exposes the first semiconductor layer 21 so that the bonding metal layer 35 can be electrically connected to the first semiconductor layer 21 through the first through hole 202. At the same time, a conductive substrate 34 is arranged on the bonding metal layer 35 so that an external power source can inject current into the first semiconductor layer 21 through the conductive substrate 34 and the bonding metal layer 35 in sequence.

[0140] Exemplarily, optionally, the bonding metal layer 35 may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0141] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0142] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0143] By way of example, the conductive substrate 34 may be a silicon substrate.

[0144] Fig.21 It is an experimental test parameter diagram of a product provided in an embodiment of the present disclosure. Fig. 22 It is an experimental test parameter diagram of a product provided by the relevant technology. Fig.21 , 22 As shown, the area of ​​the purple region Q of the product in the related art is larger than the area of ​​the purple region Q of the product in the embodiment of the present disclosure. The purple region Q indicates that the leakage current is too large. Therefore, it can be judged that the product provided by the embodiment of the present disclosure can effectively improve the problem of leakage and short circuit of the light-emitting diode.

[0145] The present disclosure provides a light emitting diode. Figure 8 As shown, the light emitting diode includes an epitaxial layer 20 , which includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 stacked in sequence, and the second semiconductor layer 23 has a first through hole 202 exposing the first semiconductor layer 21 .

[0146] like Fig. 9 , 13 As shown, the surface of the second semiconductor layer 23 has a cutting line 201 exposing the first semiconductor layer 21 . The cutting line 201 is located at the peripheral edge of the second semiconductor layer 23 . The distances M1 and M3 from the sidewalls of the cutting line 201 to the sidewalls of the first semiconductor layer 21 are 3.5 μm to 6 μm.

[0147] Optionally, the ratio of the distances M1 and M3 from the sidewall of the cutting path 201 to the sidewall of the first semiconductor layer 21 to the shortest distance M0 from the sidewall of the first through hole 202 to the cutting path 201 is 0.3 to 0.9. This ensures that the cutting path can occupy a sufficiently large width, and it is not easy to cause the photolithography to deviate from the safety window due to the lateral expansion of the epitaxial layer, resulting in etching to the second semiconductor layer and other film layers on the second semiconductor layer, causing leakage and short circuit problems in the light-emitting diode.

[0148] Optionally, the diameter Q2 of the first through hole 202 is 20 μm to 52 μm.

[0149] Exemplarily, the distance from the sidewall of the scribe line 201 to the sidewall of the first semiconductor layer 21 is 10 μm to 40 μm.

[0150] Exemplarily, the distance from the sidewall of the scribe line 201 to the sidewall of the first semiconductor layer 21 is 30 μm to 50 μm.

[0151] Alternatively, if Fig.15 , 17 As shown in FIG. 19 , the light emitting diode further includes a transparent conductive layer 30 . The transparent conductive layer 30 is located on a surface of the second semiconductor layer 23 away from the first semiconductor layer 21 , and the transparent conductive layer 30 has a second through hole 301 exposing the first through hole 202 .

[0152] like Fig.15 , 17 As shown in FIGS. 19 and 19 , the shortest distances X1 and X3 from the sidewall of the transparent conductive layer 30 to the sidewall of the epitaxial layer 20 are greater than the shortest distance L1 from the sidewall of the second through hole 301 to the first through hole 202 .

[0153] Exemplarily, the shortest distance L1 from the sidewall of the second through hole 301 to the first through hole 202 may be 1 μm to 5 μm.

[0154] Exemplarily, the shortest distance from the sidewall of the transparent conductive layer 30 to the sidewall of the epitaxial layer 20 may be 15 μm to 20 μm, or 9 μm to 12 μm.

[0155] The light-emitting diodes in the above implementation are distributed in the edge area of ​​the substrate of the product before segmentation. In this way, the distance from the side wall of the transparent conductive layer 30 of the light-emitting structure 203 located in the annular area 220 on the epitaxial layer 20 of the product to the cutting path 201 is larger. After the sapphire substrate 10 is removed, the compressive stress acting on the epitaxial layer 20 disappears, so that the epitaxial layer and the pattern already made on the epitaxial layer are laterally expanded in the direction of the peripheral edge of the epitaxial layer 20. In addition, the size of the lateral expansion is inconsistent for different products, so in order to ensure that the light-emitting structure located at the edge position will not cause the subsequent photolithography pattern to deviate beyond the safety window due to different lateral expansion during the subsequent photolithography process, different margin lengths will be set at the edge and in the middle. In this way, even if the original size mask is still used to etch the epitaxial layer, it is not easy to cause the photolithography to deviate from the safety window due to the lateral expansion of the epitaxial layer, resulting in etching on the transparent conductive layer, causing leakage and short circuit problems in the light-emitting diode. Improve the reliability of the light-emitting diode.

[0156] Alternatively, if Fig. 20 As shown, the light-emitting diode also includes a reflective layer 31, which is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20, and the reflective layer 31 has a third through hole 311 exposing the first through hole 202 and the second through hole 301; the shortest distance between the side wall of the reflective layer 31 and the side wall of the epitaxial layer 20 is greater than the shortest distance between the side wall of the third through hole 311 and the first through hole 202.

[0157] By making the shortest distance between the side wall of the reflective layer 31 and the side wall of the epitaxial layer 20 larger than the shortest distance between the side wall of the third through hole 311 and the first through hole 202, it is possible to avoid the photolithography from deviating from the safety window, resulting in etching of the reflective layer and causing leakage and short circuit problems in the light-emitting diode.

[0158] For example, Fig. 20 As shown, the shortest distance from the sidewall of the reflective layer 31 to the sidewall of the epitaxial layer 20 is 15 μm to 20 μm, or 9 μm to 12 μm.

[0159] For example, Fig. 20 As shown, the shortest distance from the side wall of the reflective layer 31 to the first through hole 202 is 2 μm to 12 μm.

[0160] Alternatively, if Fig. 20 As shown, the light emitting diode further includes an electrode layer 32 and a passivation layer 33 ; the electrode layer 32 is located on the surface of the transparent conductive layer 30 away from the epitaxial layer 20 , and wraps the reflective layer 31 .

[0161] like Fig. 20 As shown, the passivation layer 33 is located on the surface of the epitaxial layer 20 and the surface of the transparent conductive layer 30 away from the epitaxial layer 20 , and wraps the electrode layer 32 .

[0162] Optionally, the electrode layer 32 includes a Cr layer, an Al layer, a Ti layer, an Al layer, a Ti layer, an Al layer, a Cr layer, a Pt layer and a Ti layer stacked in sequence, and the thickness of each metal layer is 30 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 1000 angstroms, 2000 angstroms, 500 angstroms, 2000 angstroms and 500 angstroms respectively.

[0163] Optionally, the passivation layer is a silicon oxide layer or a distributed Bragg reflector (Distributed Bragg Reflection, DBR for short) layer.

[0164] As an example, in the embodiment of the present disclosure, the passivation layer is a silicon oxide layer.

[0165] Alternatively, if Fig. 20 As shown, the passivation layer 33 is also located in the first through hole 202 , and the passivation layer 33 has a groove exposing the first semiconductor layer 21 .

[0166] The light-emitting diode also includes a bonding metal layer 35 and a conductive substrate 34. The bonding metal layer 35 is located on the surface of the passivation layer 33 away from the epitaxial layer 20 and in the first through hole 202, and the bonding metal layer 35 is electrically connected to the first semiconductor layer 21 through a groove. The conductive substrate 34 is located on the surface of the bonding metal layer 35 away from the epitaxial layer 20.

[0167] In the embodiment of the present disclosure, the bonding metal layer 35 can be electrically connected to the first semiconductor layer 21 through the first through hole 202 and the groove. At the same time, a conductive substrate 34 is arranged on the bonding metal layer 35 so that an external power source can inject current into the first semiconductor layer 21 through the conductive substrate 34 and the bonding metal layer 35 in sequence.

[0168] Exemplarily, optionally, the bonding metal layer may be a first Al layer, a first Ti layer, a second Al layer, a second Ti layer, and an Au layer stacked in sequence.

[0169] The thickness of the first Al layer is 8000 angstroms to 12000 angstroms, the thickness of the first Ti layer is 100 angstroms to 500 angstroms, the thickness of the second Al layer is 8000 angstroms to 12000 angstroms, the thickness of the second Ti layer is 500 angstroms to 1500 angstroms, and the thickness of the Au layer is 2000 angstroms to 5000 angstroms.

[0170] For example, the thickness of the first Al layer is 10000 angstroms, the thickness of the first Ti layer is 200 angstroms, the thickness of the second Al layer is 10000 angstroms, the thickness of the second Ti layer is 1000 angstroms, and the thickness of the Au layer is 3000 angstroms.

[0171] Exemplarily, the conductive substrate may be a silicon substrate.

[0172] The present disclosure provides a method for preparing a light emitting diode, the method comprising:

[0173] Step 1: growing an epitaxial layer 20 on a sapphire substrate 10 .

[0174] The epitaxial layer 20 grown on the sapphire substrate 10 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 stacked in sequence.

[0175] The sapphire substrate 10 may be pre-treated, placed in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber, and baked for 12 to 18 minutes. As an example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0176] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0177] For example, the first semiconductor layer 21 may be an n-type layer, and the second semiconductor layer 23 may be a p-type layer.

[0178] Optionally, the n-type layer is a silicon-doped n-type GaN layer. The thickness of the n-type GaN layer may be 0.5 μm to 3 μm.

[0179] The growth temperature of the n-type GaN layer may be 1000° C. to 1100° C., and the growth pressure of the n-type GaN layer may be 100 torr to 300 torr.

[0180] Optionally, the multi-quantum well layer 22 includes alternately grown InGaN quantum well layers and GaN quantum barrier layers. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0181] When growing the multi-quantum well layer 22, the pressure of the MOCVD reaction chamber is controlled at 200 torr. When growing the InGaN quantum well layer, the temperature of the reaction chamber is 760° C. to 780° C. When growing the GaN quantum barrier layer, the temperature of the reaction chamber is 860° C. to 890° C.

[0182] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0183] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0184] Optionally, the p-type layer is a magnesium-doped p-type GaN layer. The thickness of the p-type GaN layer may be 0.5 μm to 3 μm.

[0185] When growing the p-type GaN layer, the growth pressure of the p-type GaN layer may be 200 Torr to 600 Torr, and the growth temperature of the p-type GaN layer may be 800° C. to 1000° C.

[0186] Step 2: etching the epitaxial layer 20 to form a first through hole 202 exposing the first semiconductor layer 21 on the surface of the second semiconductor layer 23 , and a cutting path 201 dividing the epitaxial layer 20 into a plurality of light emitting structures 203 .

[0187] The cutting street 201 and the first through hole 202 are both etched to the first semiconductor layer 21. In this way, the cutting street 201 and the first through hole 202 can be prepared by a single etching process, which can improve the preparation efficiency.

[0188] In the disclosed embodiment, the surface of the epitaxial layer 20 has a central region 210 and an annular region 220 . The annular region 220 surrounds the central region 210 . A plurality of light emitting structures 203 are arranged in both the central region 210 and the annular region 220 .

[0189] When etching the cutting streets, the lane width of the light emitting structure 203 located in the annular area 220 is controlled to be greater than the lane width of the light emitting structure 203 located in the central area 210 .

[0190] The street width is the distance between the sidewall of the cutting street 201 and the sidewall of the first semiconductor layer 21 .

[0191] Step three: forming a transparent conductive layer 30 on the surface of the second semiconductor layer 23 .

[0192] The transparent conductive layer 30 is located outside the first through hole 202 and the cutting street 201 .

[0193] When preparing the transparent conductive layer 30 , the residual length of the light emitting structure 203 located in the annular region 220 is controlled to be greater than the residual length of the light emitting structure 203 located in the central region 210 .

[0194] The margin length is the shortest distance from the sidewall of the transparent conductive layer 30 to the cutting path 201 .

[0195] Exemplarily, the transparent conductive layer 30 is an indium tin oxide layer or an indium zinc oxide layer.

[0196] Exemplarily, the thickness of the transparent conductive layer 30 is 100 angstroms to 300 angstroms. For example, the thickness of the transparent conductive layer 30 is 200 angstroms.

[0197] Step 4: fabricating the reflective layer 31 , the electrode layer 32 and the passivation layer 33 .

[0198] A reflective layer 31 and an electrode layer 32 are formed on the surface of the transparent conductive layer 30 , and the electrode layer 32 covers the reflective layer 31 . A passivation layer 33 is located on the surface of the second semiconductor layer 23 and the surface of the transparent conductive layer 30 , and covers the electrode layer 32 .

[0199] The passivation layer 33 extends into the first through hole 202 , and the passivation layer 33 has a groove exposing the first semiconductor layer 21 .

[0200] Step 5: fabricate a bonding metal layer 35 and laser lift off the sapphire substrate 10 .

[0201] The specific steps may include:

[0202] First, a bonding metal layer 35 is bonded on the surface of the passivation layer 33 away from the epitaxial layer 20 and in the first through hole 202 , so that the bonding metal layer 35 is electrically connected to the first semiconductor layer 21 through the groove.

[0203] Then, a conductive substrate 34 is also formed on the surface of the bonding metal layer 35 .

[0204] By way of example, the conductive substrate 34 may be a silicon substrate.

[0205] Next, the sapphire substrate 10 is removed by laser lift-off to expose the first semiconductor layer 21 .

[0206] In the sixth step, the product is cut along the cutting line 201 to obtain a plurality of light emitting diodes.

[0207] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A light emitting diode, characterized in that: The light emitting diode comprises an epitaxial layer (20), wherein the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked in sequence, and the second semiconductor layer (23) has a first through hole (202) exposing the first semiconductor layer (21); The surface of the second semiconductor layer (23) has a cutting path (201) exposing the first semiconductor layer (21), the cutting path (201) is located at the peripheral edge of the second semiconductor layer (23), and the distance (M1, M3) from the side wall of the cutting path (201) to the side wall of the first semiconductor layer (21) is 3.5μm to 6μm.

2. The light emitting diode according to claim 1, characterized in that: The light emitting diode further comprises a transparent conductive layer (30), the transparent conductive layer (30) being located on a surface of the second semiconductor layer (23) away from the first semiconductor layer (21), and the transparent conductive layer (30) having a second through hole (301) exposing the first through hole (202); The shortest distance (X1, X3) between the side wall of the transparent conductive layer (30) and the side wall of the cutting path (201) is greater than the shortest distance (L1) between the side wall of the second through hole (301) and the side wall of the first through hole (202).

3. The light emitting diode according to claim 2, characterized in that: The light emitting diode further comprises a reflective layer (31), the reflective layer (31) being located on a surface of the transparent conductive layer (30) away from the epitaxial layer (20), and the reflective layer (31) having a third through hole (311) exposing the first through hole (202) and the second through hole (301); the shortest distance between the side wall of the reflective layer (31) and the side wall of the epitaxial layer (20) is greater than the shortest distance between the side wall of the third through hole (311) and the first through hole (202).

4. The light emitting diode according to claim 3, characterized in that: The light-emitting diode further comprises an electrode layer (32) and a passivation layer (33); the electrode layer (32) is located on a surface of the transparent conductive layer (30) away from the epitaxial layer (20), and wraps around the reflective layer (31); The passivation layer (33) is located on the surface of the epitaxial layer (20) and on the surface of the transparent conductive layer (30) away from the epitaxial layer (20), and wraps the electrode layer (32).

5. The light emitting diode according to claim 4, characterized in that: The passivation layer (33) is also located in the first through hole (202), and the passivation layer (33) has a groove exposing the first semiconductor layer (21); The light-emitting diode further comprises a bonding metal layer (35) and a conductive substrate (34); the bonding metal layer (35) is located on a surface of the passivation layer (33) away from the epitaxial layer (20) and in the first through hole (202); the bonding metal layer (35) is electrically connected to the first semiconductor layer (21) via the groove; and the conductive substrate (34) is located on a surface of the bonding metal layer (35) away from the epitaxial layer (20).

6. A product, characterized in that The product comprises an epitaxial layer (20), wherein the epitaxial layer (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked in sequence, wherein the surface of the second semiconductor layer (23) has a cutting path (201) exposing the first semiconductor layer (21), and the cutting path (201) divides the epitaxial layer (20) into a plurality of light-emitting structures (203); The surface of the epitaxial layer (20) has a central region (210) and an annular region (220), the annular region (220) surrounds the central region (210), and a plurality of the light-emitting structures (203) are arranged in the central region (210) and the annular region (220); The width of at least one cutting path in the annular area (220) is greater than the width of at least one cutting path in the central area (210).

7. The product according to claim 6, characterized in that The annular region (220) includes a plurality of sub-annular regions, and the plurality of sub-annular regions are sequentially surrounded by the central region (210); For any two adjacent sub-annular areas among the multiple sub-annular areas, the width of at least one cutting path in the sub-annular area close to the central area (210) is smaller than the width of at least one cutting path in the sub-annular area far from the central area (210).

8. The product according to claim 7, characterized in that The annular region (220) includes a first sub-annular region (221) and a second sub-annular region (222) which are sequentially surrounded outside the central region (210); The width of at least one cutting line in the central area (210) is 15 μm to 55 μm, the width of at least one cutting line in the first sub-annular area (221) is 20 μm to 60 μm, and the width of at least one cutting line in the second sub-annular area (222) is 25 μm to 65 μm.

9. The product according to claim 8, characterized in that The product further comprises a transparent conductive layer (30), wherein the transparent conductive layer (30) is located on the surface of the second semiconductor layer (23); The residual length of the light-emitting structure (203) located in the annular area (220) is greater than the residual length of the light-emitting structure (203) located in the central area (210), and the residual length is the shortest distance from the side wall of the transparent conductive layer (30) to the cutting path (201).

10. The product according to claim 9, characterized in that The remaining length (X3) of the light emitting structure (203) in the first sub-annular region (221) is smaller than the remaining length (X3) of the light emitting structure (203) in the second sub-annular region (222).

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