Display substrate, manufacturing method thereof and display device

Abstract

The invention discloses a display substrate, a manufacturing method thereof and a display device, the display substrate comprises a sub-pixel, the sub-pixel comprises a pixel circuit, the pixel circuit comprises a light-emitting device and a driving transistor, and the driving transistor is configured to control the size of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit further comprises a control transistor. A first electrode of the control transistor is electrically connected with a grid electrode of the driving transistor. The active layer of the driving transistor is made of a first semiconductor material, the active layer of the control transistor is made of a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly and electrically connected with the grid electrode of the driving transistor and the first electrode of the control transistor.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate and a manufacturing method thereof, and a display device. Background Art

[0002] LTPO display substrates integrate oxide transistors (Oxide TFT) and low-temperature polysilicon transistors (LTPSTFT), and have the advantage of low-frequency driving, which can reduce the power consumption of display products. They have been increasingly used in organic light-emitting diode (OLED) display substrates, such as flexible active organic light-emitting diode (AMOLED) display substrates for mobile display products. However, since LTPO display substrates integrate two transistors, LTPS TFT and Oxide TFT, the low-hydrogen process of Oxide TFT is easily affected by the high-hydrogen and high-temperature process of LTPS TFT, making the device stability of Oxide TFT worse; and since LTPO display substrates integrate two transistors, LTPS TFT and Oxide TFT, the signal line layout of the pixel area is very complicated, which will affect the aperture ratio and transmittance of the LTPO display substrate, making the design more difficult. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, and the sub-pixel includes a pixel circuit. The pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the size of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, and a first electrode of the control transistor is electrically connected to a gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0004] For example, at least one embodiment of the present disclosure provides a display substrate in which the active layer of the driving transistor and the active layer of the control transistor are arranged in different layers, and the gate of the driving transistor is located between the electrodes where the active layers of the driving transistor and the control transistor are located.

[0005] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the active layer of the driving transistor is located on the side of the active layer of the control transistor close to the base substrate.

[0006] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit includes a first reset transistor, and the first reset transistor is configured to write a first reset signal to the gate of the driving transistor under the control of a first reset control signal; the control transistor includes the first reset transistor, and the electrode where the active layer of the first reset transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the first reset transistor.

[0007] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first pole of the first reset transistor, the material of the first pole of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first pole of the first reset transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in a different layer, and the first pole of the first reset transistor contacts the gate of the driving transistor through a first via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first pole of the first reset transistor.

[0008] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the first reset transistor is located also includes the second electrode of the first reset transistor, and the material of the second electrode of the first reset transistor is the material after the second semiconductor material is conductorized; the pixel circuit also includes a first reset signal line arranged in a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor contacts the first reset signal line through a second via hole exposing the first reset signal line to directly electrically connect the first reset signal line.

[0009] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a compensation transistor, and the compensation transistor is configured to compensate for the signal applied to the gate of the driving transistor in response to the compensation scan signal and the data signal; the control transistor also includes the compensation transistor, and the electrode where the active layer of the compensation transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the compensation transistor.

[0010] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the electrode where the active layer of the compensation transistor is located also includes the first electrode of the compensation transistor, the materials of the active layer of the compensation transistor and the first electrode of the compensation transistor are both the materials after the second semiconductor material is conductorized, the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and constitute an integrated structure; the gate of the driving transistor and the electrode where the active layer of the compensation transistor is located are arranged in a different layer, and the first electrode of the compensation transistor contacts the gate of the driving transistor through a third via hole that exposes the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

[0011] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure, the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in different layers, and the first electrode of the first reset transistor is in direct contact with the gate of the driving transistor through a first via hole exposing the gate of the driving transistor. When the gate of the driving transistor and the first electrode of the first reset transistor are electrically connected, the electrode where the active layer of the compensation transistor is located is arranged on the same layer as the electrode where the active layer of the first reset transistor is located and forms an integrated structure, the first electrode of the first reset transistor and the first electrode of the compensation transistor are integrated, and the first via hole and the second via hole are the same via hole; the material of the active layer of the compensation transistor is the second semiconductor material, the material of the first electrode of the compensation transistor is the material after the second semiconductor material is conductively converted, the first electrode of the first reset transistor, the first electrode of the compensation transistor and the active layer of the compensation transistor are connected in sequence, arranged on the same layer and form an integrated structure.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a first light-emitting control transistor, and the first light-emitting control transistor is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor and the active layer of the control transistor are arranged in different layers; the electrode where the active layer of the compensation transistor is located also includes a connecting portion, and the material of the connecting portion is the material after the second semiconductor material is conductively converted, and the connecting portion is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; the connecting portion contacts the active layer of the first light-emitting control transistor through a fourth via hole that exposes the active layer of the first light-emitting control transistor to electrically connect the active layer of the first light-emitting control transistor, and the connecting portion serves as the first electrode of the first light-emitting control transistor and the second electrode of the compensation transistor.

[0013] For example, at least one embodiment of the present disclosure provides a display substrate in which the active layer of the first light-emitting control transistor and the active layer of the driving transistor are arranged on the same layer, and / or the gate of the driving transistor and the gate of the first light-emitting control transistor are arranged on the same layer.

[0014] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a first light-emitting control transistor, and the first light-emitting control transistor is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor is arranged in a different layer from the active layer of the control transistor; the electrode where the active layer of the control transistor is located is arranged in a different layer from the second pole of the first light-emitting control transistor, the electrode where the active layer of the control transistor is located is in contact with the active layer of the first light-emitting control transistor through a fourth via hole exposing the active layer of the first light-emitting control transistor, and the second pole of the first light-emitting control transistor is in contact with the active layer of the first light-emitting control transistor through a fifth via hole exposing the active layer of the first light-emitting control transistor.

[0015] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the second electrode of the first light-emitting control transistor is located on the side of the electrode where the active layer of the control transistor is located, away from the base substrate.

[0016] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located also includes the second electrode of the first reset transistor, the material of the second electrode of the first reset transistor is the material after the second semiconductor material is conductorized, the pixel circuit also includes a first reset signal line arranged in a different layer from the second electrode of the first reset transistor, and the first reset signal line is arranged in a different layer from the second electrode of the first reset transistor when the second electrode of the first reset transistor is electrically connected to the first reset signal line through a second via hole exposing the first reset signal line.

[0017] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the first reset signal line and the gate of the driving transistor are both located between the gate of the driving transistor and the electrode where the active layer of the control transistor is located; the first reset signal line and the gate of the driving transistor are arranged in different layers or in the same layer.

[0018] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the control transistor is a single-gate transistor, and the gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor; or, the control transistor is a dual-gate transistor, and the first gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor, and the second gate of the control transistor is located between the active layer of the control transistor and the active layer of the driving transistor, and the second gate of the control transistor is arranged on the same layer or on a different layer as the first reset signal line.

[0019] For example, at least one embodiment of the present disclosure provides a display substrate in which the second gate of the control transistor and the gate of the driving transistor are arranged in the horizontal direction; when the control transistor is a dual-gate transistor, the line width of the second gate of the control transistor in the horizontal direction is greater than the line width of the first gate of the control transistor in the horizontal direction.

[0020] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, the driving transistor is arranged on the main surface of the base substrate; the first reset signal line and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the base substrate.

[0021] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a first light-emitting control transistor, and the first light-emitting control transistor is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor and the active layer of the control transistor are arranged in different layers; the electrode where the active layer of the compensation transistor is located also includes the second electrode of the compensation transistor, and the material of the second electrode of the compensation transistor is the material after the second semiconductor material is conductive, and the second electrode of the compensation transistor is arranged in the same layer as the active layer of the compensation transistor and constitutes an integrated structure; the pixel circuit includes a first connection structure, and the first connection structure, the second electrode of the compensation transistor and the electrode where the active layer of the control transistor is located are all arranged in different layers from each other; the first connection structure is electrically connected to the second electrode of the compensation transistor through a sixth via hole, and is electrically connected to the active layer of the first light-emitting control transistor through a seventh via hole.

[0022] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the display substrate includes a base substrate, and the driving transistor is arranged on the main surface of the base substrate; the fifth via penetrates the second pole of the compensation transistor, and the first connection structure includes an inner hole portion located in the sixth via, and the side surface of the inner hole portion contacts the second pole of the compensation transistor, and the surface where the side surface of the inner hole portion is located intersects with the surface where the main surface of the base substrate is located; or, the fifth via exposes the upper surface of the second pole of the compensation transistor, and the upper surface of the second pole of the compensation transistor is away from the main surface of the base substrate, and the first connection structure includes an inner hole portion located in the sixth via, and the bottom surface of the inner hole portion contacts the upper surface of the second pole of the compensation transistor.

[0023] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the pixel circuit also includes a first light-emitting control transistor, and the first light-emitting control transistor is configured to enable the driving current to be applied to the light-emitting device under the control of a first light-emitting control signal; the material of the active layer of the first light-emitting control transistor is the first semiconductor material, and the active layer of the first light-emitting control transistor is arranged in a different layer from the active layer of the control transistor; the electrode where the active layer of the compensation transistor is located also includes the second pole of the compensation transistor, and the material of the second pole of the compensation transistor is the material after the second semiconductor material is conductorized, and the connecting portion is arranged in the same layer as the active layer of the compensation transistor and constitutes an integrated structure; the pixel circuit also includes a second connection structure and a third connection structure, and the second pole of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light-emitting control transistor are all arranged in different layers from each other; the second pole of the compensation transistor is electrically connected to the second connection structure through an eighth via hole, the third connection structure is electrically connected to the second connection structure through a ninth via hole, and the third connection structure is electrically connected to the active layer of the first light-emitting control transistor through a tenth via hole.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate in which the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

[0025] For example, at least one embodiment of the present disclosure provides a display substrate, wherein the transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO).

[0026] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0027] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, the manufacturing method including: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuits includes forming light-emitting devices and driving transistors, and the driving transistors are configured to control the magnitude of a driving current flowing through the light-emitting devices according to a data signal; the forming of the pixel circuits also includes: forming a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, and a material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; and an electrode where the active layer of the control transistor is located is directly electrically connected to the gate electrode of the driving transistor and the first electrode of the control transistor.

[0028] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: forming a first type of via, wherein the first type of via at least exposes an active layer composed of the first semiconductor material; forming a first conductive structure to electrically connect to the surface of the active layer composed of the first semiconductor material exposed by the first type of via through the first type of via; after forming the first type of via, performing a high temperature annealing process on the display substrate; and performing a contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via.

[0029] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, including: using the second semiconductor material to form a second semiconductor layer through a single patterning process; conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conductive portion and a non-conductive portion, and the conductive portion and the non-conductive portion constitute an integrated structure; the non-conductive portion constitutes the active layer of the control transistor, the conductive portion directly electrically connects the gate of the driving transistor and the first electrode of the control transistor, and the material of the conductive portion is the material after the second semiconductor material is conducted; and forming a second type of via, the conductive portion of the second conductive structure directly electrically connects the gate of the driving transistor and the first electrode of the control transistor through the second type of via.

[0030] For example, at least one embodiment of the present disclosure provides a method for manufacturing a display substrate, wherein the high temperature annealing process is performed on the display substrate after forming the second type of via holes and before forming the second conductive structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0032] Figure 1 A schematic plan view of a display substrate provided for at least one embodiment of the present disclosure;

[0033] Figure 2 A schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure;

[0034] Figure 3 A partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided by at least one embodiment of the present disclosure;

[0035] Figure 4 is a partial cross-sectional schematic diagram of a pixel circuit;

[0036] Figure 5 is a partial plan schematic diagram of a pixel circuit;

[0037] Figure 6 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0038] Figure 7 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 8 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0040] Fig. 9 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0041] Fig.10 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0042] Fig.11 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0043] Fig.12 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure;

[0044] Fig.13 is a schematic diagram of a display device provided by an embodiment of the present disclosure;

[0045] Figures 14A-14D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0046] Figures 15A-15D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0047] Figures 16A-16D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure;

[0048] Figures 17A-17D It is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0051] The terms in this disclosure are explained as follows:

[0052] (1) Meaning of integrated structure: The description that structure A and structure B form an integrated structure means that there is no joint between structure A and structure B, and the structure is a uniform and integrated structure, for example, formed by the same composition process. The letters A and B are used to refer to the corresponding structures described in the text.

[0053] (2) The meaning of “same-layer arrangement” is the relationship between multiple structures formed after a film formed of the same material is subjected to the same patterning process. “Same-layer arrangement” here does not always mean that the thickness of multiple structures is the same or the height of multiple structures in the cross-sectional view is the same.

[0054] (3) The meaning of a patterning process: a film layer is patterned by using a mask plate and a single exposure process.

[0055] The drawings in this disclosure are not drawn strictly according to the actual scale, and the number of sub-pixels in the display substrate is not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structures.

[0056] At least one embodiment of the present disclosure provides a display substrate, which includes a sub-pixel, and the sub-pixel includes a pixel circuit. The pixel circuit includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the size of a driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, and a first electrode of the control transistor is electrically connected to a gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor.

[0057] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0058] At least one embodiment of the present disclosure also includes a method for manufacturing a display substrate, the manufacturing method including: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuits includes forming light-emitting devices and driving transistors, and the driving transistors are configured to control the magnitude of a driving current flowing through the light-emitting devices according to a data signal; the forming of the pixel circuits also includes: forming a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, and a material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; and an electrode where the active layer of the control transistor is located is directly electrically connected to the gate electrode of the driving transistor and the first electrode of the control transistor.

[0059] Figure 1 FIG. 1 is a schematic plan view of a display substrate provided by at least one embodiment of the present disclosure. Figure 1 As shown, for example, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the plurality of pixels 100 include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting device and a pixel circuit that drives the light-emitting device to emit light. For example, the pixel circuit may include a 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 4T2C, 5T1C, 7T1C, or nTmC (n, m are positive integers) pixel circuit. For example, in different embodiments, the pixel circuit may further include a compensation subcircuit, the compensation subcircuit includes an internal compensation subcircuit or an external compensation subcircuit, and the compensation subcircuit may include a transistor, a capacitor, etc. For example, as needed, the pixel circuit may further include a reset circuit, a light-emitting control subcircuit, a detection circuit, etc.

[0060] For example, Figure 1As shown, a plurality of pixels 100 are located in the display area. For example, in the display substrate 10 provided in some embodiments, some of the plurality of pixels 100 are dummy pixels 101, which do not participate in the display work, and each dummy pixel 101 includes a plurality of dummy sub-pixels, but does not include a sub-pixel that plays a display driving role.

[0061] For example, the display substrate 10 is an organic light emitting diode (OLED) display substrate, and the light emitting device is an OLED. The display substrate 10 may also include a plurality of scan lines and a plurality of data lines for providing scan signals (e.g., gate lines, control signals, reference signals) to the plurality of sub-pixels. Figure 5 ) and data signals to drive the plurality of sub-pixels. As required, the display substrate 10 may further include power lines, detection lines, etc.

[0062] The pixel circuit of the display substrate 10 provided in the embodiment of the present disclosure includes a light-emitting device and a driving transistor, and the driving transistor is configured to control the size of the driving current flowing through the light-emitting device according to a data signal; the pixel circuit also includes a control transistor, and the first electrode of the control transistor is electrically connected to the gate of the driving transistor; the material of the active layer of the driving transistor is a first semiconductor material, and the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor, that is, the electrode where the active layer of the control transistor is located serves as a connecting line electrically connecting the gate of the driving transistor and the first electrode of the control transistor.

[0063] It should be noted that, what is meant here that “the electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor” is that the electrode where the active layer of the control transistor is located is in direct contact with both the gate of the driving transistor and the first electrode of the control transistor, thereby electrically connecting the gate of the driving transistor and the first electrode of the control transistor, rather than indirectly electrically connecting the first electrode of the active layer of the control transistor to the gate of the driving transistor via other conductive structures (for example, conductive structures located on other layers).

[0064] For example, Figure 2 A schematic diagram of a pixel circuit provided in at least one embodiment of the present disclosure, wherein Figure 2 Taking the 7T1C pixel circuit shown as an example, the structure of the sub-pixel of the display substrate is introduced.

[0065] refer to Figure 2, the pixel circuit includes a light emitting device EL and a driving transistor T3, and the driving transistor T3 is configured to control the magnitude of the driving current flowing through the light emitting device EL according to the data signal Vd. For example, the pixel circuit includes a first reset transistor T1, and the first reset transistor T1 is configured to write a first reset signal Vinit1 to the gate T3g of the driving transistor T3 under the control of a first reset control signal Rst1. For example, the first reset signal Vinit1 and the second reset signal Vinit2 are the same signal, coming from the same reset signal line connected to the same reset signal terminal, so that one reset signal line can be saved. Of course, the first reset signal Vinit1 and the second reset signal Vinit2 can also be two independent signals.

[0066] Figure 3 A partial cross-sectional schematic diagram of a pixel circuit of a display substrate provided by at least one embodiment of the present disclosure. Figure 2 and Figure 3 For example, the control transistor includes a first reset transistor T1, and the electrode ET where the active layer T1a of the first reset transistor T1 is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. The electrode ET where the active layer T1a of the first reset transistor T1 is located is an integrated structure, and includes the active layer T1a of the first reset transistor T1 and other parts, that is, the active layer T1a of the first reset transistor T1 and other parts constitute the electrode ET of the integrated structure. In this case, the material of the active layer T3a of the driving transistor T3 is the first semiconductor material, and the material of the active layer T1a of the first reset transistor T1 is the second semiconductor material. The electrode ET where the active layer T1a of the first reset transistor T1 is located further includes a conductive part, which forms an integrated structure with the active layer T1a of the first reset transistor T1. The conductive part includes the first electrode T1s of the first reset transistor T1. For example, the first electrode T1s of the first reset transistor T1 is adjacent to the active layer T1a of the first reset transistor T1 and forms an integrated structure. Moreover, the conductive part contacts the gate T3g of the driving transistor T3, so that the first electrode T1s of the first reset transistor T1 is electrically connected to the active layer T1a of the first reset transistor T1 and to the gate T3g of the driving transistor T3. For example, the material of the conductive part is the material after the second semiconductor material is conductively connected.

[0067] Figure 4 is a partial cross-sectional schematic diagram of a pixel circuit ( Figure 4 It does not represent the prior art. Figure 4 It is a design made by the inventor based on the structure of the pixel circuit of the display substrate provided in the embodiment of the present application, but the connection design of the control transistor and other transistors is different from that in the embodiment of the present application). Figure 4The circuit diagram of the pixel circuit shown can be Figure 2 The same as shown, however, in Figure 4 In the pixel circuit shown, the first reset transistor T1 includes a dual gate T10g1 and T10g2, an active layer T10a, a first electrode and a second electrode. The active layer T10a of the first reset transistor T1 is electrically connected to the gate T30g of the driving transistor T3 through a first connection structure S1, and the first connection structure S1 serves as the first electrode of the first reset transistor T1; the first connection structure S1 and the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor T3 are all located in different layers, for example, the first connection structure S1 is located on the side of the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor away from the substrate 010, and the first connection structure S1 is electrically connected to the active layer T10a of the first reset transistor T1 and the gate T30g of the driving transistor T3 through two types of vias. For example, the first connection structure S1 is often arranged in the same layer as the data line providing the data signal. Figure 4 In the embodiment, the first connection structure S1 also electrically connects the gate T30g of the driving transistor T3 and the active layer T20a of the compensation transistor T2 through the via hole, and is reused as the first electrode of the compensation transistor T2. The compensation transistor T2 includes dual gates T20g1 and T20g2. Figure 4 In the embodiment, the second electrode of the first reset transistor T1 is electrically connected to the active layer T10a of the first reset transistor T1 and the first reset signal line LVinitial0 through the second connection structure S2 via two types of vias. The second connection structure S2 is arranged in the same layer or in a different layer as the first connection structure S1, but the second connection structure S2 and the first connection structure S1 are both provided with an insulating layer between the active layer T10a of the first reset transistor T1, an insulating layer between the first reset signal line LVinitial0, and an insulating layer between the active layer T20a of the compensation transistor T2. The second connection structure S2 is an additional conductive structure provided outside the layers where the active layer T10a of the first reset transistor T1, the first reset signal line LVinitial0, and the active layer T20a of the compensation transistor T2 are located, so as to realize electrical connection between the above three or electrical connection between the above three and other structures through these conductive structures.

[0068] In the display substrate provided by the embodiment of the present disclosure, the electrode ET where the active layer T1a of the first reset transistor T1 having the conductive portion is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. Figure 4The structure of the pixel circuit shown in the figure, the display substrate provided by the embodiment of the present disclosure can at least achieve the following technical effects. On the one hand, in the display substrate provided by the embodiment of the present disclosure, the electrode ET where the active layer T1a of the first reset transistor T1 is located is reused as a connection electrode to realize the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, and there is no need to additionally set a special connection electrode in other layers (for example, the conductive layer SD1 on the side of the active layer T1a of the first reset transistor T1 away from the base substrate BS) to use the connection electrode to electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, thereby greatly simplifying the structure of the pixel circuit. On the other hand, by using the display substrate provided by the embodiment of the present disclosure, other signal lines, such as data lines for providing data signals Vd or connecting electrodes for electrical connection between other elements of the pixel circuit, can be set in other layers (for example, the conductive layer SD1), without setting connecting electrodes to connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, thereby reducing the number of conductive structures set in the other layers and the number of connecting vias, thereby simplifying the process of making vias, which is conducive to reducing the design difficulty and improving the yield of the display panel. At the same time, the density of the conductive structures set in the other layers (for example, the conductive layer SD1) is reduced, the parasitic capacitance generated by the overly dense conductive structures is reduced, and the display quality is improved.

[0069] For example, the first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material. For example, the transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO). In this case, the display substrate 10 is an LTPO display substrate that integrates oxide transistors (Oxide TFT) and low-temperature polysilicon transistors (LTPS TFT), which has the advantage of low-frequency driving and can reduce the power consumption of display products. Of course, the first semiconductor material and the second semiconductor material are not limited to the types listed above, and the embodiments of the present disclosure do not limit the specific types of the first semiconductor material and the second semiconductor material.

[0070] Combination Figure 2 and Figure 3 For example, the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the first electrode T1s of the first reset transistor T1, and is electrically connected to the gate T3g of the driving transistor T3 through the first via hole V1.

[0071] Combination Figure 2 and Figure 3, the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1, and the conductive part of the electrode ET where the active layer T1a of the first reset transistor T1 is located includes the first electrode T1s of the first reset transistor T1; for example, the material of the first electrode T1s of the first reset transistor T1 is the material after the second semiconductor material is conductively converted, the active layer T1a of the first reset transistor T1 and the first electrode T1s of the first reset transistor T1 are arranged in the same layer and constitute an integrated structure, that is, the material of the conductive part of the electrode ET where the active layer T1a of the first reset transistor T1 is the material after the second semiconductor material is conductively converted, the first electrode T1s of the first reset transistor T1 belongs to the conductive part of the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the active layer T1a of the first reset transistor T1 is the non-conductive part. For example, the gate T3g of the driving transistor T3 is arranged in a different layer from the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the first electrode T1s of the first reset transistor T1 is in contact with the gate T3g of the driving transistor T3 through the first via hole V1 that exposes the gate T3g of the driving transistor T3, so as to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. In this way, for example, the conductive part of the electrode ET where the active layer T1a of the first reset transistor T1 is located can be electrically connected to the gate T3g of the driving transistor T3 only through the first via hole V1, and the active layer T1a of the first reset transistor T1 and the active layer T1a of the first reset transistor T1 form an integrated structure, thereby realizing the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, without the need for the first via hole V1. Figure 3 A connection structure is additionally provided in other layers and is electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two via holes, respectively, so that the electrode EL where the material of the active layer T1a of the first reset transistor T1 is located is fully utilized, the structure of the sub-pixel is simplified, the connection wiring is reduced, and the light transmittance is increased; and the number of conductive structures provided in the other layers is further reduced, which is conducive to reducing the design difficulty, reducing the density of the conductive structures provided in the other layers, and reducing the parasitic capacitance generated by the overly dense conductive structures.

[0072] For example, refer to Figure 2 and Figure 3, the electrode ET where the active layer T1a of the first reset transistor T1 is located also includes the second electrode T1d of the first reset transistor T1, and the material of the second electrode T1d of the first reset transistor T1 is also the material after the second semiconductor material is conductorized, and the second electrode T1d of the first reset transistor T1 also belongs to the conductorized part of the electrode ET where the active layer T1a of the first reset transistor T1 is located; the pixel circuit also includes a first reset signal line LVini1 that is arranged in a different layer from the second electrode T1d of the first reset transistor T1, and the second electrode T1d of the first reset transistor T1 contacts the first reset signal line LVini1 through the second via V2 that exposes the first reset signal line LVini1 to directly electrically connect to the first reset signal line LVini1. In this way, the second electrode T1d of the first reset transistor T1 (the material after the second semiconductor material is conductorized) can be electrically connected to the first reset signal line LVini1 only through the second via V2. There is no need as Figure 4 In other layers, additional connections are set (e.g. Figure 4 The second connection structure S2 in the structure is electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1 through at least two vias, respectively, which makes full use of the electrode EL where the material of the active layer T1a of the first reset transistor T1 is located, simplifies the structure of the sub-pixel, reduces the connection wiring, and thus can also increase the transmittance; and further reduces the number of conductive structures arranged in the other layers, reduces the number of connecting vias, thereby simplifying the process of making vias, which is conducive to reducing the design difficulty and improving the yield of the display panel. At the same time, the density of the conductive structures arranged in the other layers is reduced, and the parasitic capacitance generated by the overly dense conductive structures is reduced.

[0073] For example, refer to Figure 3 The active layer T3a of the driving transistor T3 and the active layer T1a of the first reset transistor T1 are arranged in different layers, and the gate T3g of the driving transistor T3 is located between the active layer T3a of the driving transistor T3 and the electrode ET where the active layer T1a of the first reset transistor T1 is located, that is, the gate T3g of the driving transistor T3 is located on the side of the active layer T3a of the driving transistor T3 close to the electrode ET where the active layer T1a of the first reset transistor T1 is located, so that during the manufacturing process of the display substrate, the gate T3g of the driving transistor T3 is in contact with the conductive part of the electrode ET where the active layer T1a of the first reset transistor T1 is located, and the function of the driving transistor T3 is not affected.

[0074] For example, refer to Figure 3, the display substrate includes a base substrate BS, the driving transistor T3 is arranged on the main surface of the base substrate BS; the active layer T3a of the driving transistor T3 is located on the side of the active layer T1a of the first reset transistor T1 close to the base substrate BS. That is, the active layer of the oxide transistor (Oxide TFT) is on the top, and the low-temperature polysilicon transistor (LTPS TFT) is on the bottom, and the direction "down" here is closer to the base substrate BS than the direction "up", so that in the manufacturing process of the display substrate, the active layer of the low-temperature polysilicon transistor (LTPS TFT) will be formed first, and then the active layer of the oxide transistor (Oxide TFT) will be formed, so as to avoid the process of forming the active layer of the low-temperature polysilicon transistor (LTPS TFT) after forming the active layer of the oxide transistor (Oxide TFT) (such as IGZO) affects the performance of the oxide transistor (Oxide TFT).

[0075] For example, refer to Figure 2 and Figure 4, the pixel circuit also includes a compensation transistor T2, and the compensation transistor T2 is configured to compensate the signal applied to the gate T3g of the driving transistor T3 in response to the compensation scanning signal and the data signal Vd. For example, the above-mentioned control transistor also includes a compensation transistor T2, and the electrode ET where the active layer T2a of the compensation transistor T2 is located is also directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2. The electrode ET where the active layer T2a of the compensation transistor T2 is located is an integrated structure, and includes the active layer T2a of the compensation transistor T2 and other parts, and the active layer T2a of the compensation transistor T2 and other parts constitute the electrode ET of the integrated structure. In this case, the material of the active layer T3a of the driving transistor T3 is the first semiconductor material, and the material of the active layer T2a of the compensation transistor T2 is the second semiconductor material. For example, the electrode ET where the active layer T2a of the compensation transistor T2 is located also includes a conductive portion, and the conductive portion and the active layer T2a of the compensation transistor T2 form an integrated structure. The conductive portion is in contact with the first electrode T2s of the compensation transistor T2 and the gate T3g of the driving transistor T3 to achieve electrical connection with the two. For example, the material of the conductive portion is the material after the second semiconductor material is conductive. In this way, the electrode ET where the active layer T2a of the compensation transistor T2 having the conductive portion is located is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1. On the one hand, the electrode ET where the active layer T1a of the first reset transistor T1 is located can be reused as a connecting electrode to achieve electrical connection between the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2, and there is no need to additionally set a special connecting electrode in other layers (for example, a conductive layer on the side of the active layer T2a of the compensation transistor T2 away from the substrate BS) to connect to the driving transistor T3 through at least two vias. The gate T3g of the driving transistor T3 is electrically connected to the first electrode T2s of the compensation transistor T2, thereby simplifying the structure of the pixel circuit; on the other hand, other signal lines, such as a data line for providing a data signal Vd or a connecting electrode for electrical connection between other elements of the pixel circuit, can be arranged in other layers, without additionally arranging a connecting electrode to connect the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, thereby reducing the number of conductive structures arranged in the other layers, which is conducive to reducing the design difficulty, reducing the density of the conductive structures arranged in the other layers, reducing the parasitic capacitance generated by the overly dense conductive structures, and improving the display quality.

[0076] For example, refer to Figure 3The electrode ET where the active layer T2a of the compensation transistor T2 is located includes the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2. The materials of the active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are both materials after the second semiconductor material is conductively converted, and both belong to the conductive part of the electrode ET where the active layer T2a of the compensation transistor T2 is located. The active layer T2a of the compensation transistor T2 and the first electrode T2s of the compensation transistor T2 are arranged in the same layer and form an integrated structure. The gate T3g of the driving transistor T3 and the electrode where the active layer T2a of the compensation transistor T2 are arranged in different layers. The first electrode T2s of the compensation transistor T2 contacts the gate T3g of the driving transistor T3 through the third via hole V3 exposing the gate T3g of the driving transistor T3 to directly electrically connect the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2.

[0077] For example, in Figure 3 In the illustrated embodiment, the electrode ET where the active layer T2a of the compensation transistor T2 is located is arranged in the same layer as the electrode ET where the active layer T1a of the first reset transistor T1 is located and forms an integrated structure, that is, the electrode ET where the active layer T2a of the compensation transistor T2 is located is the same electrode as the electrode ET where the active layer T1a of the first reset transistor T1 is located, the first electrode T1s of the first reset transistor T1 and the first electrode T2s of the compensation transistor T2 are integrated, and the first via hole V1 and the third via hole V3 are the same via hole. The electrode ET where the active layer T2a of the compensation transistor T2 is located also includes the first electrode T2s of the compensation transistor T2, the material of the active layer T2a of the compensation transistor T2 is the second semiconductor material, the material of the first electrode T2s of the compensation transistor T2 is the material after the second semiconductor material is conductively converted, the first electrode T1s of the first reset transistor T1, the first electrode T2s of the compensation transistor T2 and the active layer T2a of the compensation transistor T2 are sequentially connected, arranged in the same layer and form an integrated structure.

[0078] For example, Figure 3 As shown, the first electrode T1s of the first reset transistor T1 is adjacent to the first electrode T2s of the compensation transistor T2 and are integrally formed to form a conductive connection portion CS, that is, the conductorized portion of the electrode ET where the active layer of the control transistor is located includes the conductive connection portion CS, and the conductive connection portion CS is electrically connected to the gate T3g of the driving transistor T3 through the third via V3.

[0079] exist Figure 3In the illustrated embodiment, the same electrode ET including the active layer of the control transistor and the conductive part is used to realize the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T1s of the first reset transistor T1, the electrical connection between the gate T3g of the driving transistor T3 and the first electrode T2s of the compensation transistor T2, and the electrical connection between the second electrode T1d of the first reset transistor T1 and the first reset signal line LVini1, so that the active layer including the control transistor is fully utilized, and the number and density of conductive structures for connecting various transistors, capacitors and other elements of sub-pixels arranged in other layers (for example, the conductive layer on the side of the active layer T1a of the first reset transistor T1 away from or close to the base substrate BS) are greatly reduced, thereby greatly reducing the design difficulty, reducing the parasitic capacitance caused by the excessive density of the conductive structure in the other layers, and improving the display quality of the display substrate.

[0080] Of course, in other embodiments, the gate T3g of the driving transistor T3 may be electrically connected to the first electrode T1s of the first reset transistor T1, but not to the first electrode T2s of the compensation transistor T2; or, the gate T3g of the driving transistor T3 may be electrically connected to the first electrode T2s of the compensation transistor T2, but not to the first electrode T1s of the first reset transistor T1. The above-mentioned methods can achieve the above-mentioned technical effects of the display substrate provided by the present application to varying degrees, and solve the corresponding technical problems.

[0081] refer to Figure 2 The pixel circuit further includes a first light emission control transistor T6, which is configured to apply a driving current to the light emitting device EL under the control of a first light emission control signal EM1. Figure 3 The material of the active layer T6a of the first light-emitting control transistor T6 is the above-mentioned first semiconductor material (silicon semiconductor material), and the active layer T6a of the first light-emitting control transistor T6 is arranged in a different layer from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the compensation transistor T2); the electrode where the active layer T2a of the compensation transistor T2 is located also includes a connecting portion C1, the material of the connecting portion C1 is the material after the second semiconductor material is conductorized, and the connecting portion C1 is arranged in the same layer as the active layer T2a of the compensation transistor T2 to form an integrated structure; the connecting portion C1 contacts the active layer T6a of the first light-emitting control transistor T6 through the fourth via hole V4 that exposes the active layer T6a of the first light-emitting control transistor T6 to be electrically connected to the active layer T6a of the first light-emitting control transistor T6, thereby, the connecting portion C1 serves as the first electrode T6s of the first light-emitting control transistor T6 and the second electrode T2d of the compensation transistor T2.

[0082] For example, refer to Figure 3The active layer T6a of the first light emission control transistor T6 and the active layer T3a of the driving transistor T3 are arranged on the same layer, and / or the gate T3g of the driving transistor T3 and the gate T6g of the first light emission control transistor T6 are arranged on the same layer, so that the same semiconductor layer (the material is the first semiconductor material) is subjected to the same patterning process to form the active layer T6a of the first light emission control transistor T6 and the active layer T3a of the driving transistor T3, and the same conductive layer is subjected to the same patterning process to form the gate T3g of the driving transistor T3 and the gate T6g of the first light emission control transistor T6.

[0083] For example, refer to Figure 3 The material of the active layer T6a of the first light-emitting control transistor T6 is the above-mentioned first semiconductor material, and the active layer T6a of the first light-emitting control transistor T6 is arranged in a different layer from the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the compensation transistor T2); the electrode ET where the active layer of the control transistor is located is arranged in a different layer from the second electrode T6d of the first light-emitting control transistor T6, the electrode where the active layer of the control transistor is located is in contact with the active layer T6a of the first light-emitting control transistor T6 through a fourth via hole V4 that exposes the active layer T6a of the first light-emitting control transistor T6, and the second electrode T6d of the first light-emitting control transistor T6 is in contact with the active layer T6a of the first light-emitting control transistor T6 through a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6. For example, the second electrode T6d of the first light-emitting control transistor T6 is located in the conductive layer SD1, thus reducing the routing of the conductive layer SD1, avoiding the situation where winding is generated in the conductive layer SD1 to avoid the structure in the same layer, reducing the design difficulty of the conductive layer SD1, and avoiding parasitic capacitance.

[0084] For example, refer to Figure 3 The second electrode T6d of the first light-emitting control transistor T6 is located on the side of the electrode ET where the active layer of the control transistor is located, which is away from the substrate BS, that is, the conductive layer SD1 is located on the side of the electrode ET where the active layer of the control transistor is located, which is away from the substrate BS, so as to avoid the second electrode T6d of the first light-emitting control transistor T6 being located between the electrode ET where the active layer of the control transistor is located and the gate T6g of the first light-emitting control transistor T6, thereby avoiding interference with the arrangement of the electrode ET where the active layer of the control transistor is located and the gate T6g of the first light-emitting control transistor T6, reducing the difficulty of layout, reducing the difficulty of manufacturing process, and reducing the difficulty of manufacturing process while optimizing the above-mentioned performance of the pixel circuit, which is very important for ensuring the yield of the product.

[0085] For example, the data line providing the above data signal Vd is also located in the conductive layer SD1, that is, it is arranged in the same layer as the second electrode T6d of the first light emission control transistor T6. In the embodiment of the present disclosure, at least there is no connection electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, the connection electrode for electrically connecting the active layer of the first reset transistor T1 and the gate of the driving transistor T3, and the connection electrode for electrically connecting the active layer of the first reset transistor and the first reset signal line in the conductive layer SD1, thereby greatly reducing the number of wires or conductive structures in the conductive layer SD1, reducing the density of wires or conductive structures arranged in the conductive layer SD1, reducing parasitic capacitance generated by over-dense conductive structures, and improving display quality.

[0086] For example, in Figure 3 In the embodiment shown, the first reset signal line LVini1 and the second electrode T6d of the first light-emitting control transistor T6 are arranged in different layers to avoid the first reset signal line LVini1 being located in the conductive layer SD1, which causes the first reset signal line LVini1 to need to avoid other conductive structures and have a winding design, that is, bypass other structures to avoid intersecting with other conductive structures. Figure 5 This is a schematic diagram of the planar structure of a current pixel circuit. Figure 5 , the circuit diagram of the pixel circuit may be, for example, Figure 2 The equivalent circuit shown is Figure 5 The dotted rectangle in the figure is a schematic diagram of the planar structure of a pixel circuit of a sub-pixel unit. Figure 5 , the first scan line LGa1 provides Figure 2 The first scanning signal Ga1 (data scanning signal) in the second scanning line LGa2 provides Figure 2 The second scanning signal (compensation scanning signal) Ga2 in the light emitting control scanning line LEM provides Figure 2 The first light emitting control signal EM1 and the second light emitting control signal EM2 in the first reset scanning line LRst1 provide Figure 2 The first reset scan signal Rst1 in the second reset scan line LRst2 provides Figure 2 The first reset signal line LV1 is connected to the second reset scan signal Rst2. Figure 2 The first connection electrode S1 (ie, the first connection electrode S1 of the first node N1) Figure 4 In order to avoid the first connection electrode S1, the first reset signal line LV1 adopts a winding design, that is, it meanders upward and then extends to the right, including a winding portion R. Figure 5The above solution shown in FIG. 1 increases the parasitic capacitance between the conductive layer SD1 and other conductive layers. On the other hand, the first reset signal line LV1 has to pass through the channel region ( 100 ) of the first reset transistor T1 due to wiring difficulties. Figure 5 In the embodiment of the present application, since the electrode ET where the active layer of the control transistor is located (the conductive portion of the electrode ET where the active layer of the control transistor is located) is directly electrically connected to the gate T3g of the driving transistor T3 and the first electrode of the control transistor, there is no need to additionally provide a conductive portion in the conductive layer SD1 specifically for electrically connecting the gate T3g of the driving transistor T3 and the electrode ET where the active layer of the control transistor is located, thereby reducing the number and density of conductive structures in the conductive layer SD1, and improving the technical problem that the winding caused by the excessive density of the conductive structure in the conductive layer SD1, thereby causing excessive parasitic capacitance and affecting the switching characteristics of the first reset transistor T1; further, since the first reset signal line LVini1 and the second electrode T6d of the first light-emitting control transistor T6 are arranged in different layers, the above-mentioned technical problem can be further improved.

[0087] For example, refer to Figure 3 , the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are both located between the active layer T3a of the driving transistor T3 and the electrode ET where the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) is located. Figure 3 For example, the first reset signal line LVini1 and the gate T3g of the driving transistor T3 are arranged in different layers to avoid the conductive structure density in the conductive layer where the two are located being too high, especially for a display substrate with a high PPI, the space of each sub-pixel is more limited, so that the structure of the pixel circuit can meet the requirements of a display substrate with a higher PPI. For example, the gate T3g of the driving transistor T3 is located in the first conductive layer Gate1, the first reset signal line LVini1 is located in the second conductive layer Gate2, and the second conductive layer Gate2 is located on the side of the first conductive layer Gate1 away from the base substrate BS, so that in the direction perpendicular to the main surface of the base substrate BS, the second conductive layer Gate2 is closer to the electrode ET where the active layer T1a of the first reset transistor T1 is located, so that the active layer T1a of the first reset transistor T1 is in contact with the first reset signal line LVini1 located in the second conductive layer Gate2 through the second via V2 to be electrically connected.

[0088] Alternatively, in other embodiments, the first reset signal line LVini1 and the gate T3g of the driving transistor T3 may also be disposed on the same layer.

[0089] For example, in Figure 3 In the illustrated embodiment, the control transistor is a dual-gate transistor, for example, the first reset transistor T1 and the compensation transistor T2 are both dual-gate transistors, the first reset transistor T1 includes a first gate T1g1 and a second gate T1g2, and the compensation transistor T2 includes a first gate T2g1 and a second gate T2g2. Of course, at least one of the first reset transistor T1 and the compensation transistor T2 is a dual-gate transistor, and the first gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the first gate T2g1 of the compensation transistor T2) is located on the side of the active layer of the control transistor away from the active layer T3a of the driving transistor T3, for example, located on the third conductive layer Gate3; the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is located between the active layer of the control transistor (the active layer T1a of the first reset transistor T1 and / or the active layer T2a of the compensation transistor T2) and the active layer T3a of the driving transistor T3, and the second gate of the control transistor (the first gate T1g1 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2) is arranged on the same layer as the first reset signal line LVini1, for example, both are located on the second conductive layer Gate2.

[0090] Alternatively, in other embodiments, the second gate of the control transistor and the first reset signal line LVini1 may be arranged at different layers.

[0091] For example, refer to Figure 3 , the second gate T1g2 of the first reset transistor T1 and / or the second gate T2g2 of the compensation transistor T2 are arranged in the horizontal direction with the gate T3g of the driving transistor T3, and are horizontally parallel to the main surface of the substrate BS, that is, the second gate of the control transistor and the gate T3g of the driving transistor T3 are arranged in the horizontal direction; in the case where the control transistor is a dual-gate transistor, the line width of the second gate of the control transistor in the horizontal direction is greater than the line width of the first gate of the control transistor in the horizontal direction. For example, the line width of the second gate T1g2 of the first reset transistor T1 in the horizontal direction is greater than the line width of the first gate T1g1 of the first reset transistor T1 in the horizontal direction, and the line width of the second gate T2g2 of the compensation transistor T2 in the horizontal direction is greater than the line width of the first gate T2g1 of the compensation transistor T2 in the horizontal direction.

[0092] For example, refer to Figure 3 The first reset signal line LVini1 and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the substrate BS to prevent parasitic capacitance caused by the overlap of the two in a direction perpendicular to the main surface of the substrate BS.

[0093] For example, refer to Figure 3The display substrate further includes a first flexible layer PI1, a second flexible layer PI2, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a bottom shielding electrode BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second buffer layer Buffer2, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2, which are arranged on a base substrate BS. Each insulating layer directly insulates each conductive layer, and each buffer layer can isolate impurities from a film layer subsequently formed on the corresponding buffer layer. The material of the first flexible layer PI1 and the second flexible layer PI2 is, for example, polyimide (PI) so that the display substrate is a flexible substrate. The substrate including polyimide (PI) contains movable fixed charges. When the gate voltage of the driving transistor T3 changes, the movable charges will move up and down with the change of the electric field formed by the gate voltage of the driving transistor T3, forming a built-in electric field that changes with the gate voltage of the driving transistor T3, thereby affecting the characteristics of the driving transistor T3 and the image quality of the display substrate. After applying a fixed voltage to the bottom shielding electrode BSM, the influence of the fixed charges in the polyimide (PI) on the characteristics of the driving transistor T3 can be shielded, thereby improving the display quality. For example, the bottom shielding electrode BSM is connected to the first voltage signal VDD.

[0094] Figure 6 It is a partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in an embodiment of the present disclosure. Figure 6 The technical solution is the same as above Figure 3 The technical solutions have the following differences.

[0095] refer to Figure 6 , the electrode ET where the active layer T2a of the compensation transistor T2 is located also includes the second electrode T2d of the compensation transistor T2, the material of the second electrode T2d of the compensation transistor T2 is the material after the second semiconductor material is conductively converted, and the second electrode T2d of the compensation transistor T2 is arranged in the same layer as the active layer T2a of the compensation transistor T2 and forms an integrated structure; the pixel circuit includes a first connection structure CS1, and the first connection structure CS1, the second electrode T2d of the compensation transistor T2 and the electrode ET where the active layer of the control transistor is located are all arranged in different layers; for example, the first connection structure CS1 is arranged in the same layer as the second electrode T6d of the first light-emitting control transistor T6, for example, both are located in the conductive layer SD1. The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via hole V6, and is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through the seventh via hole V7. Figure 6In the embodiment shown, the gate T3g of the driving transistor T3 and the first electrode of the control transistor are directly electrically connected by the electrode ET where the active layer of the control transistor is located, which can also greatly simplify the structure of the pixel circuit, and there is no need to additionally set a connecting electrode in other layers to connect the gate T3g of the driving transistor T3 and the first electrode of the control transistor, thereby reducing the number of conductive structures set in the other layers, and, Figure 6 In the embodiment shown, the first connection structure CS1 contacts the second electrode T2d of the compensation transistor T2 and the active layer T6a of the first light-emitting control transistor T6 through the sixth via hole V6 and the seventh via hole V7 respectively to electrically connect the two. The material of the first connection structure CS1 can be a common conductive material such as a metal conductive material such as aluminum, copper, chromium, etc. and their alloys. It can also avoid the problem of large contact resistance caused by the direct electrical connection between the conductive part of the electrode ET composed of the conductive IGZO and P-Si, thereby improving the display uniformity of the pixel array of the display substrate and enhancing the display effect.

[0096] refer to Figure 6 For example, the sixth via hole V6 penetrates the second electrode T2d of the compensation transistor T2 in a direction perpendicular to the main surface of the substrate BS, and the first connection structure CS1 includes an in-hole portion PIV located in the sixth via hole V6, a side surface of the in-hole portion PIV contacts the second electrode T2d of the compensation transistor T2 to be electrically connected to the second electrode T2d of the compensation transistor T2, and a surface where the side surface of the in-hole portion PIV is located intersects with a surface where the main surface of the substrate BS is located, that is, a surface of the in-hole portion PIV that contacts the hole wall of the hole that penetrates the second electrode T2d of the compensation transistor T2. Figure 6 The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 by side-stack connection.

[0097] Figure 6 The other features and corresponding technical effects of the embodiments shown are the same as those Figure 3 The same as in, please refer to the previous description.

[0098] Figure 7 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Figure 7 The technical solution is the same as above Figure 6 The technical solutions have the following differences.

[0099] refer to Figure 7The sixth via hole V6 exposes the upper surface of the second electrode T2d of the compensation transistor T2, and the upper surface of the second electrode T2d of the compensation transistor T2 is far away from the main surface of the substrate BS. The first connection structure CS1 includes an inner hole portion PIV located in the sixth via hole V6, and the bottom surface of the inner hole portion PIV (the surface facing the substrate BS) contacts the upper surface of the second electrode T2d of the compensation transistor T2 to be electrically connected to the second electrode T2d of the compensation transistor T2. Figure 7 The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 by using a bottom-stack method.

[0100] exist Figure 3 Based on the technical effects achieved by the embodiments, Figure 7 The display substrate shown can also avoid the problem of large contact resistance caused by direct electrical connection between the conductive part of the electrode ET composed of conductive IGZO and P-Si, thereby improving the display uniformity of the pixel array of the display substrate and enhancing the display effect.

[0101] Figure 7 The other features and corresponding technical effects of the embodiments shown are the same as those Figure 6 or Figure 3 The same as in, please refer to the previous description.

[0102] Figure 8 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Figure 8 The technical solution is the same as above Figure 6 The technical solutions have the following differences.

[0103] refer to Figure 8, the material of the active layer T6a of the first light-emitting control transistor T6 is the first semiconductor material, and the active layer T6a of the first light-emitting control transistor T6 is arranged in a different layer from the active layer of the control transistor; the electrode ET where the active layer T2a of the compensation transistor T2 is located also includes the second electrode T2d of the compensation transistor T2, and the material of the second electrode T2d of the compensation transistor T2 is the material after the second semiconductor material is conductorized, that is, the conductorized part of the electrode ET includes the second electrode T2d of the compensation transistor T2; the second electrode T2d of the compensation transistor T2 is arranged in the same layer as the active layer T2a of the compensation transistor T2 and constitutes an integrated structure; the pixel circuit includes a second connection structure CS2 and a third connection structure CS3, and the second electrode T2d of the compensation transistor T2, the second connection structure CS2, the third connection structure CS3 and the active layer T6a of the first light-emitting control transistor T6 are all arranged in different layers from each other. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 through the eighth via hole V8, the third connection structure CS3 is electrically connected to the second connection structure CS2 through the ninth via hole V9, and the third connection structure CS3 is electrically connected to the active layer T6a of the first light emission control transistor T6 through the tenth via hole V10, so that the third connection structure CS3 serves as the first electrode T6s of the first light emission control transistor T6. Figure 3 Based on the technical effects achieved by the embodiments, Figure 8 The display substrate shown can also avoid the problem of large contact resistance caused by direct electrical connection between the conductive part of the electrode ET composed of conductive IGZO and P-Si, thereby improving the display uniformity of the pixel array of the display substrate and enhancing the display effect.

[0104] For example, refer to Figure 8 The second connection structure CS2 is disposed on the same layer as the gate T6g of the first light emission control transistor T6, both of which are located in the first conductive layer Gate1; for example, the third connection structure CS3 is disposed on the same layer as the second electrode T6d of the first light emission control transistor T6, that is, located in the conductive layer SD1.

[0105] Figure 8 The other features and corresponding technical effects of the embodiments shown are the same as those Figure 6 or Figure 3 The same as in, please refer to the previous description.

[0106] For example, in some embodiments of the present disclosure, the control transistor may be a single-gate transistor, the gate of which is located on a side of the active layer of the control transistor away from the active layer of the driving transistor. The control transistor may still include at least one of the first reset transistor T1 and the compensation transistor T2.

[0107] For example, Fig. 9A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Fig. 9 The technical solution is the same as above Figure 3 The technical solutions have the following differences. Fig. 9 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, Fig. 9 The illustrated case is that both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors, the first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g. For example, the gate T1g of the first reset transistor T1 is located on the side of the active layer T1a of the first reset transistor T1 away from the substrate BS, and the gate T2g of the compensation transistor T2 is located on the side of the active layer T2a of the compensation transistor T2 away from the substrate BS; for example, the gate T1g of the first reset transistor T1 and the gate T2g of the compensation transistor T2 are both arranged in different layers from the first reset signal line Lvinil and the gate T3g of the driving transistor T3, so as to avoid excessive parasitic capacitance or increased manufacturing difficulty caused by excessive density of conductive structures in the same layer, especially in the case of more limited space for each sub-pixel in a high-resolution (high PPI) display substrate, where this problem has a greater impact on the display effect. For example, referring to Fig. 9 , the gate T1g and the gate T2g are located in the third conductive layer Gate3; the first reset signal line Lvinil is located in the second conductive layer Gate2; the gate T3g of the driving transistor T3 is located in the first conductive layer Gate1. This is a preferred method in consideration of manufacturing convenience and preventing the density of the conductive structure in the same layer from being too high, but the conductive layer where the gates T1g, T2g and T3g are located is not limited to this method.

[0108] For example, the manufacturing method of the pixel circuit provided in at least one embodiment of the present application includes: forming a first type of via hole, the first type of via hole at least exposing an active layer composed of a first semiconductor material (for example, P-Si), and forming a first conductive structure to electrically connect to the surface of the active layer exposed by the first type of via hole through the first type of via hole. After forming the first type of via hole, in order to improve the characteristics of the LTPS TFT device, it is necessary to perform a high temperature annealing process on the display substrate; for example, the manufacturing method of the pixel circuit includes: performing a contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole to reduce the contact resistance of the exposed surface, for example, the surface can be made to achieve ohmic contact with the conductive structure contacted with it through the first type of via hole; for example, the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole can be etched to remove the oxide layer of the exposed surface, thereby reducing the contact resistance of the exposed surface. For example, the first type of via hole includes a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6.

[0109] For example, the manufacturing method of the pixel circuit provided in the embodiment of the present application further includes: forming a second conductive structure, wherein the second conductive structure is the electrode where the active layer of the control transistor is located, the second conductive structure includes the active layer of the control transistor and the conductive part that forms an integrated structure with the active layer of the control transistor, the active layer of the control transistor is composed of a second semiconductor material (for example, IGZO), and the conductive part is the material after the second semiconductor material is conductive; and forming a second type of via, wherein the conductive part of the second conductive structure contacts the structure exposed by the second type of via through the second type of via to be electrically connected, for example, the conductive part of the second conductive structure directly electrically connects the gate of the driving transistor and the first electrode of the control transistor through the second type of via. For example, the above-mentioned process of reducing the contact resistance treatment can be performed after forming the second type of via and before forming the second conductive structure, so that the contact resistance reduction treatment will not affect the performance of the control transistor, and the stability of the characteristics of the control transistor is maintained. Therefore, the control transistor can achieve ideal performance by using a single gate, thereby simplifying the structure.

[0110] refer to Fig. 9 ,and Figure 3 Compared with the structure shown in FIG. 1 , for the first reset transistor T1, the first gate T1g1 with a smaller lateral length is retained, and the second gate T1g2 with a larger lateral length is removed; similarly, for the compensation transistor T2, the first gate T2g1 with a smaller lateral length is retained, and the second gate T2g2 with a larger lateral length is removed. In this way, the lateral length of the gate of the control transistor (the first reset transistor T1 and / or the compensation transistor T2) is reduced, for example, Fig. 9 In the embodiment of the control transistor using a single-gate structure, the length of the first gate T1g1 of the first reset transistor T1 and / or the first gate T2g1 of the compensation transistor T2 along the lateral direction is smaller than the length of the gate of other transistors in the pixel circuit along the lateral direction, for example, smaller than the length of the gate of the driving transistor T3 along the lateral direction, or smaller than the length of the gate of the first light-emitting control transistor T6 along the lateral direction, or smaller than the length of the gate of the data transistor T4 along the lateral direction, etc. Since the material of the gate is usually a light-proof conductive material such as a metal material, the above-mentioned length of the gate of the single-gate control transistor is reduced, which can improve the aperture ratio of the display substrate; in addition, for the corresponding control transistor, taking the first reset transistor T1 as an example, the length of the channel region of the first reset transistor T1 in the direction from the first pole T1s of the first reset transistor T1 to the second pole T1d of the first reset transistor T1 is L, that is, in Fig. 9The length in the horizontal direction is L, and the width of the channel region in the direction perpendicular to the horizontal direction is W. Therefore, when W remains unchanged, L decreases, which increases the width-to-length ratio W / L of the first reset transistor T1, that is, increases the width-to-length ratio of the first reset transistor T1, which is beneficial to reducing the heat generation of the first reset transistor T1 and improving the life of the first reset transistor T1. Similarly, the same is true for the compensation transistor T2 with a single gate having a shorter length.

[0111] Fig. 9 The other features and corresponding technical effects of the embodiments shown are the same as those Figure 3 The same as in, please refer to the previous description.

[0112] Fig.10 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Fig.10 The technical solution is the same as above Figure 6 The technical solutions have the following differences. Fig.10 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, Fig.10 The illustrated case is that both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0113] Fig.10 The other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g are similar to those of Fig. 9 For the same Fig. 9 The description will not be repeated here.

[0114] Fig.10 Other unmentioned features and corresponding technical effects of the embodiments shown are the same as those Figure 6 The same as in, please refer to the previous description.

[0115] Fig.11 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Fig.11 The technical solution is the same as above Figure 7 The technical solutions have the following differences. Fig.11 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, Fig.11 The illustrated case is that both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0116] Fig.11The other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g are similar to those of Fig. 9 For the same Fig. 9 The description will not be repeated here.

[0117] Fig.11 Other unmentioned features and corresponding technical effects of the embodiments shown are the same as those Figure 7 The same as in, please refer to the previous description.

[0118] Fig.12 A partial cross-sectional schematic diagram of a pixel circuit of another display substrate provided in at least one embodiment of the present disclosure. Fig.12 The technical solution is the same as above Figure 8 The technical solutions have the following differences. Fig.12 , for example, at least one of the first reset transistor T1 and the compensation transistor T2 is a single-gate transistor, Fig.12 The illustrated case is that both the first reset transistor T1 and the compensation transistor T2 are single-gate transistors. The first reset transistor T1 has a gate T1g, and the compensation transistor T2 has a gate T2g.

[0119] Fig.12 The other features and corresponding technical effects of the first reset transistor T1 having a gate T1g and the compensation transistor T2 having a gate T2g are similar to those of Fig. 9 For the same Fig. 9 The description will not be repeated here.

[0120] Fig.12 Other unmentioned features and corresponding technical effects of the embodiments shown are the same as those Figure 8 The same as in, please refer to the previous description.

[0121] Fig.13 is a schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.13 At least one embodiment of the present disclosure further provides a display device 100, and the display device 100 includes any one of the display substrates 10 provided in the embodiments of the present disclosure. The display device can be, for example, a display panel, or a display, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. Of course, the display device provided in the embodiments of the present disclosure is not limited to the types listed above.

[0122] Accordingly, the display panel and the display device provided by the embodiments of the present disclosure both have the technical effects of the pixel circuit and the display substrate provided by the embodiments of the present disclosure.

[0123] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, which includes: forming sub-pixels, including forming pixel circuits, wherein the forming of the pixel circuits includes forming light-emitting devices and driving transistors, and the driving transistors are configured to control the magnitude of a driving current flowing through the light-emitting devices according to a data signal; the forming of the pixel circuits also includes: forming a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, and a material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; and an electrode where the active layer of the control transistor is located is directly electrically connected to the gate electrode of the driving transistor and the first electrode of the control transistor.

[0124] For example, a method for manufacturing a display substrate includes: using the second semiconductor material to form a second semiconductor layer through a single patterning process; conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conductive portion and a non-conductive portion, and the conductive portion and the non-conductive portion constitute an integrated structure; the non-conductive portion constitutes the active layer of the control transistor, the conductive portion directly electrically connects the gate of the drive transistor and the first electrode of the control transistor, and the material of the conductive portion is the material after the second semiconductor material is conducted; and forming a second type of via, the conductive portion of the second conductive structure directly electrically connects the gate of the drive transistor and the first electrode of the control transistor through the second type of via.

[0125] The "direct electrical connection" here means that at least part of the conductive part is in direct contact with the gate of the driving transistor and the first electrode of the control transistor to be electrically connected thereto, rather than the conductive part needing to be indirectly connected to the gate of the driving transistor and the first electrode of the control transistor through other non-integrated conductive structures or even conductive structures arranged in different layers.

[0126] For example, the conductive portion of the electrode where the active layer of the control transistor is located includes a first electrode of the control transistor, and the first electrode of the control transistor and the active layer of the control transistor are arranged in the same layer to form an integrated structure.

[0127] In this way, in the manufacturing method of the display substrate provided in the embodiment of the present disclosure, the second semiconductor layer can be formed through a single patterning process, and the number of electrodes and vias used for switching is reduced, thereby simplifying the manufacturing process and design difficulty of the display substrate, greatly reducing the density of the conductive structure on the same layer, and reducing the wiring difficulty of the conductive structure or wire on the same layer, which plays an important role in improving the yield of the display substrate.

[0128] In a conventional method for manufacturing a display substrate, for example, Figure 4 In the manufacturing process of the display substrate shown, usually after forming the first type of via hole, taking the first type of via hole including the via hole V01 on the surface of the active layer T60a composed of the first semiconductor material exposing the first light-emitting control transistor T6 as an example, the surface of the active layer T60a exposed by the via hole V01 is etched to remove the oxide film on the surface thereof to reduce the contact resistance; then, a process of forming the via hole V02 on the surface of the active layer T10a / T20a composed of the second semiconductor material is performed, and then the first connection structure S1, the second connection structure S2 and the third connection structure S3 are formed, so as to electrically connect the first reset transistor T1, the compensation transistor T2 and the first light-emitting control transistor T6 through the via hole V01 and the via hole V02 by using the first connection structure S1, the second connection structure S2 and the third connection structure S3. In this manufacturing method, a certain period of time is required from the etching process of the surface of the active layer T60a exposed by the via V01 to the formation of the first connection structure S1, the second connection structure S2 and the third connection structure S3 (for example, usually formed by deposition or sputtering). During this period of time, on the one hand, an oxide layer will be formed again on the surface of the active layer T60a exposed by the via V01, thereby affecting the ohmic contact between the active layer T60a and the third connection structure S3; on the other hand, the presence of foreign matter such as impurity particles at some vias V01 will affect the electrical connection between the active layer T60a and the third connection structure S3, thereby affecting the yield of the display substrate.

[0129] For example, the manufacturing method of the pixel circuit provided in at least one embodiment of the present application includes: forming a first type of via hole, the first type of via hole at least exposing an active layer composed of a first semiconductor material (for example, P-Si), and forming a first conductive structure to electrically connect the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole. After forming the first type of via hole, in order to improve the characteristics of the LTPS TFT device, it is necessary to perform a high temperature annealing process on the display substrate; for example, the manufacturing method of the pixel circuit includes: performing a contact resistance reduction treatment on the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole to reduce the contact resistance of the exposed surface, for example, the surface can be made to achieve ohmic contact with the conductive structure contacted with it through the first type of via hole; for example, the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole can be etched to remove the oxide layer of the exposed surface, thereby reducing the contact resistance of the exposed surface. For example, the first type of via hole includes a fifth via hole V5 that exposes the active layer T6a of the first light-emitting control transistor T6.

[0130] For example, the manufacturing method of the pixel circuit provided in the embodiment of the present application also includes: forming a second type of via, and forming a second conductive structure in the second type of via; the electrode where the second conductive structure is located includes the active layer of the above-mentioned control transistor, and the active layer of the control transistor is composed of a second semiconductor material (for example, IGZO), and the electrode where the second conductive structure is located also includes a conductive part that forms an integrated structure with the active layer of the control transistor, and the conductive part is the material after the second semiconductor material is conductive. For example, the part of the second conductive structure located in the second type of via is electrically connected to the structure exposed by the second type of via through the second type of via. For example, the above-mentioned process of reducing the contact resistance treatment can be performed after forming the second type of via and before forming the second conductive structure, so that the contact resistance reduction treatment will not affect the performance of the control transistor. Therefore, the control transistor can achieve ideal performance by using a single gate, thereby simplifying the structure.

[0131] For example, Figures 14A-14D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure, for example Figures 14A-14D Shows Figure 3 The manufacturing method of the display substrate shown.

[0132] refer to Fig.14A , a substrate BS is provided, and a first flexible layer PI1, a first barrier layer Barrier1, a second flexible layer PI2, a second barrier layer Barrier2-1, a BSM, a third barrier layer Barrier2-2, a first buffer layer Buffer1, an active layer composed of a first semiconductor material including but not limited to an active layer T3a of a driving transistor T3 and an active layer T6a of a first light-emitting control transistor T6, a first gate insulating layer GI1, a first metal layer Gate1, a second gate insulating layer GI2, a second metal layer Gate2, a first interlayer insulating layer ILD1, and a second buffer layer Buffer2 are formed on the substrate BS; then, the above-mentioned second-type vias are formed by a patterning process, where the second-type vias include a first via V1, a second via V2 (in this embodiment, the second via V2 is also the third via V3) and a fourth via V4. For example, in a single pixel circuit, these three second-type vias are formed. Of course, the number of the second-type vias is not limited to this case.

[0133] Next, refer to Fig. 14B, the second semiconductor material is used to form a second semiconductor layer (not shown in the figure), for example, the second semiconductor layer is formed by a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a part of the connection electrode pattern is subjected to a conductor treatment to form a second conductive structure, a part of the second conductive structure is located in the first via hole V1, the second via hole V2 and the fourth via hole V4, the second conductive structure is the electrode ET where the active layer of the control transistor is located, the second conductive structure includes the active layer T1a of the first reset transistor T1, the active layer T2a of the compensation transistor T2, and the conductorized part that forms an integrated structure with the active layer T1a of the first reset transistor T1 and the active layer T2a of the compensation transistor T2, so that the active layer T1a of the first reset transistor T1 and the active layer T2a of the compensation transistor T2 are both composed of the second semiconductor material (for example, IGZO), and the conductorized part is the material after the second semiconductor material is conductorized. For example, the conductorized part includes For example, the portion of the second conductive structure located in the second type of via hole contacts the structure exposed by the second type of via hole through the second type of via hole to be electrically connected. Thus, a second conductive structure is formed. Figure 3 The electrode ET where the active layer T1a of the first reset transistor T1 is located and the specific connection relationship of the second conductive structure can be seen in Figure 3 Description.

[0134] Then, if Fig. 14C As shown, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are formed in sequence, and the first type of via holes are formed through a single patterning process. For example, the first type of via holes include a fifth via hole V5.

[0135] Then, after forming the first type of via hole (e.g., the fifth via hole V5), a high temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first light emission control transistor T6). Then, the surface of the active layer T6a composed of the first semiconductor material of the first light emission control transistor T6 exposed by the fifth via hole V5 is subjected to a contact resistance reduction process to reduce the contact resistance of the exposed surface, so that the surface is in ohmic contact with the second electrode T6d of the first light emission control transistor T6 that is subsequently formed and contacts therewith through the fifth via hole V5; for example, the surface of the active layer T6a exposed by the fifth via hole V5 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5, thereby reducing the contact resistance of the exposed surface.

[0136] Then, if Fig.14DAs shown, a conductive layer SD1 is formed, for example, by a deposition method and a one-time patterning process, and the conductive layer SD1 includes a second electrode T6d of the first light-emitting control transistor T6. The second electrode T6d of the first light-emitting control transistor T6 is electrically connected to the active layer T6a of the first light-emitting control transistor T6 through a fifth via hole V5.

[0137] It can be seen that in the manufacturing method of the display substrate provided by at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5, the conductive layer SD1 can be immediately manufactured without the need for a process of forming the second type of via hole in between. In this way, on the one hand, the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 can be effectively improved; on the other hand, the formation of foreign matter such as impurity particles in the fifth via hole V5 can be effectively prevented, thereby preventing the influence of foreign matter such as impurity particles on the electrical connection between the active layer composed of the first semiconductor material and the conductive layer SD1, thereby improving the yield of the display substrate.

[0138] For example, in another Figure 3 In the manufacturing method of the display substrate shown, a high-temperature annealing process can also be performed on the display substrate after forming the second type of via and before forming the second conductive structure (i.e., the electrode ET where the active layer of the above-mentioned control transistor is located) to prevent the high-temperature annealing process from affecting the performance of the second conductive structure composed of the second semiconductor material, thereby not affecting the performance of the control transistor.

[0139] Figures 15A-15D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure, for example Figures 15A-15D Shows Figure 6 The manufacturing method of the display substrate shown.

[0140] refer to Fig.15A ,and Fig.14A The difference between the steps shown in the figure is that the second type of via holes mentioned above are formed by a patterning process, and the second type of via holes include the first via hole V1 and the second via hole V2 (the second via hole V2 is also the third via hole V3 in this embodiment), and no via hole V1 is formed. Fig.14A The fourth via V4 in.

[0141] Next, refer to Fig. 15B The second semiconductor material is used to form a second semiconductor layer (not shown), for example, the second semiconductor layer is formed by a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a portion of the connection electrode pattern is subjected to a conductor treatment to form a second conductive structure. The second conductive structure is Figure 6 The electrode ET where the active layer T1a of the first reset transistor T1 is located and the specific structure and connection relationship of the second conductive structure are shown in FIG. Figure 6Then, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are formed in sequence, and the first type of vias are formed by a single patterning process. For example, the first type of vias include a fifth via V5 and a seventh via V7, and the fifth via V5 and the seventh via V7 expose the surface of the active layer T1a of the first reset transistor T1 formed of the first semiconductor material; here, the first type of vias also include a sixth via V6 that exposes the conductorized portion of the second conductive structure (that is, the integrated electrode ET), and the sixth via V6 exposes the end of the electrode ET that is laterally close to the first light emission control transistor T6, and the end of the electrode ET that is laterally close to the first light emission control transistor T6 is reused as the second electrode T2d of the compensation transistor T2.

[0142] Next, refer to Fig. 15C , a high temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first light emission control transistor T6). Then, the surface of the active layer T6a composed of the first semiconductor material of the first light emission control transistor T6 exposed by the fifth via hole V5 and the seventh via hole V7 is subjected to a contact resistance reduction treatment; for example, the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7 may be subjected to an etching treatment to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, thereby reducing the contact resistance of the exposed surface. After the etching treatment, Fig. 15B The end of the electrode ET exposed by the sixth via hole V6 in the lateral direction close to the first light-emitting control transistor T6 is pierced, that is, the second electrode T2d of the compensation transistor T2 is pierced, so that the sixth via hole V6 passes through the second electrode T2d of the compensation transistor T2 in a direction perpendicular to the main surface of the substrate BS.

[0143] Next, refer to Fig.15D , forming a conductive layer SD1, for example, by using a deposition method and a one-time patterning process to form the conductive layer SD1, the conductive layer SD1 includes a second electrode T6d of the first light emission control transistor T6 and a first connection structure CS1. The second electrode T6d of the first light emission control transistor T6 is electrically connected to the active layer T6a of the first light emission control transistor T6 through the fifth via hole V5; the first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via hole V6, and is electrically connected to the active layer T6a of the first light emission control transistor T6 through the seventh via hole V7.

[0144] Thus, the formation Figure 6 The display substrate is shown. Figure 6The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 by a side overlap method. In the manufacturing method of the display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, the conductive layer SD1 can be immediately manufactured without the need for a process of forming the second type of via hole in between. In this way, the technical effect of effectively improving the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of foreign matter such as impurity particles in the fifth via hole V5 can also be achieved.

[0145] Figures 16A-16D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure, for example Figures 16A-16D Shows Figure 7 The manufacturing method of the display substrate shown.

[0146] refer to Fig.16A ,and Fig.15A The steps shown are the same.

[0147] Next, refer to Fig. 16B The second semiconductor material is used to form a second semiconductor layer (not shown), for example, the second semiconductor layer is formed by a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a portion of the connection electrode pattern is subjected to a conductor treatment to form a second conductive structure. The second conductive structure is Figure 6 The electrode ET where the active layer T1a of the first reset transistor T1 is located and the specific structure and connection relationship of the second conductive structure are shown in FIG. Figure 6 Then, a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2 are sequentially formed, and the first type of via holes are formed by a single patterning process. Fig. 15B The steps shown are different in that the first type of vias here do not include the sixth via V6 exposing the conductorized portion of the second conductive structure (i.e., the integrated electrode ET), but include the fifth via V5 and the seventh via V7. The fifth via V5 and the seventh via V7 expose the surface of the active layer T1a of the first reset transistor T1 formed of the first semiconductor material.

[0148] Next, refer to Fig. 16C, a high temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (for example, the first light emission control transistor T6). Then, the surface of the active layer T6a composed of the first semiconductor material of the first light emission control transistor T6 exposed by the fifth via hole V5 and the seventh via hole V7 is subjected to a contact resistance reduction treatment; for example, the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7 can be etched to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, thereby reducing the contact resistance of the exposed surface. After the etching treatment, the sixth via hole V6 is formed by a patterning process, and the sixth via hole V6 exposes the upper surface of the end of the electrode ET in the lateral direction close to the first light emission control transistor T6, and the end of the electrode ET in the lateral direction close to the first light emission control transistor T6 is reused as the second electrode T2d of the compensation transistor T2.

[0149] Next, refer to Fig.16D , forming a conductive layer SD1, for example, by using a deposition method and a one-time patterning process to form the conductive layer SD1, the conductive layer SD1 includes a second electrode T6d of the first light emission control transistor T6 and a first connection structure CS1. The second electrode T6d of the first light emission control transistor T6 is electrically connected to the active layer T6a of the first light emission control transistor T6 through the fifth via hole V5; the first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 through the sixth via hole V6, and is electrically connected to the active layer T6a of the first light emission control transistor T6 through the seventh via hole V7.

[0150] Thus, the formation Figure 7 The display substrate is shown. Figure 7 The first connection structure CS1 is electrically connected to the second electrode T2d of the compensation transistor T2 by a bottom overlap method. In the manufacturing method of the display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, the conductive layer SD1 can be immediately manufactured without the need for a process of forming the second type of via hole in between. In this way, the technical effect of effectively improving the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of foreign matter such as impurity particles in the fifth via hole V5 and the seventh via hole V7 can also be achieved.

[0151] Figures 17A-17D is a schematic diagram of a method for manufacturing a display substrate provided by an embodiment of the present disclosure, for example Figures 17A-17D Shows Figure 8 The manufacturing method of the display substrate shown.

[0152] refer to Fig.17A ,and Fig.15AThe steps shown are different in that the first metal layer Gate1 also includes a second connection structure CS2. The second type of vias are formed by the same patterning process, where the second type of vias include a first via V1, a second via V2 (the second via V2 is also the third via V3 in this embodiment), and an eighth via V8 exposing the second connection structure CS2.

[0153] Next, refer to Fig. 17B The second semiconductor material is used to form a second semiconductor layer (not shown), for example, the second semiconductor layer is formed by a deposition method, and a patterning process is performed on the second semiconductor layer to form a connection electrode pattern, and then a portion of the connection electrode pattern is subjected to a conductor treatment to form a second conductive structure. The second conductive structure is Figure 8 The electrode ET where the active layer T1a of the first reset transistor T1 is located and the specific structure and connection relationship of the second conductive structure are shown in FIG. Figure 8 Description.

[0154] Then, refer to Fig. 17C , sequentially forming a third gate insulating layer GI3, a third conductive layer Gate3 and a second interlayer insulating layer ILD2, and forming the first type of via holes through a single patterning process. Fig. 15B The steps shown are different in that the first type of vias here do not include the sixth via V6 exposing the conductive portion of the second conductive structure (i.e., the integrated electrode ET), but include the fifth via V5 and the tenth via V10 respectively exposing the source region and the drain region of the active layer T6a of the first light-emitting control transistor T6, and the ninth via V9 exposing the second connection structure CS2.

[0155] Next, a high temperature annealing process is performed on the display substrate to improve the characteristics of the LTPS TFT device (e.g., the first light emission control transistor T6). Then, the surface of the active layer T6a of the first light emission control transistor T6 exposed by the fifth via hole V5 and the seventh via hole V7, which is made of the first semiconductor material, is subjected to a contact resistance reduction process; for example, the surface of the active layer T6a exposed by the fifth via hole V5 and the tenth via hole V10 may be subjected to an etching process to remove the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the seventh via hole V7, thereby reducing the contact resistance of the exposed surface.

[0156] Next, refer to Fig.17D, forming a conductive layer SD1, for example, by using a deposition method and a one-time patterning process to form the conductive layer SD1, the conductive layer SD1 includes a first connection structure CS1, a second connection structure CS2 and a third connection structure CS3. The second electrode T6d of the first light emission control transistor T6 is electrically connected to the active layer T6a of the first light emission control transistor T6 through the fifth via hole V5. The second electrode T2d of the compensation transistor T2 is electrically connected to the second connection structure CS2 through the eighth via hole V8, the third connection structure CS3 is electrically connected to the second connection structure CS2 through the ninth via hole V9, and the third connection structure CS3 is electrically connected to the active layer T6a of the first light emission control transistor T6 through the tenth via hole V10, so that the third connection structure CS3 acts as the first electrode T6s of the first light emission control transistor T6.

[0157] Thus, the formation Figure 8 The display substrate shown. In the manufacturing method of the display substrate provided in at least one embodiment of the present disclosure, after removing the oxide layer on the surface of the active layer T6a exposed by the fifth via hole V5 and the tenth via hole V10, the conductive layer SD1 can be immediately manufactured without the need for a process of forming the second type of via hole in between. In this way, the technical effect of effectively improving the ohmic contact between the active layer composed of the first semiconductor material and the conductive layer SD1 and effectively preventing the formation of foreign matter such as impurity particles in the fifth via hole V5 and the tenth via hole V10 can also be achieved.

[0158] for Figures 9 to 12 The manufacturing method of the display substrate shown in Figure 3 , Figure 6 , Figure 7 , Figure 8 Based on the manufacturing method of the display substrate shown in FIG. 1 , in the process of forming the second metal layer Gate2 by the patterning process, the patterning pattern is changed so as not to form the second gate T1g2 of the first reset transistor T1 and the second gate T2g2 of the compensation transistor T2. Figure 3 , Figure 6 , Figure 7 , Figure 8 The manufacturing method of the display substrate shown in FIG. can also achieve Figure 3 , Figure 6 , Figure 7 , Figure 8 The technical effect of the manufacturing method of the display substrate shown is shown, and removing the second gate simplifies the design of the mask plate and the process.

[0159] There are a few points to note:

[0160] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0161] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0162] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A display substrate, comprising sub-pixels, wherein: The sub-pixel includes a pixel circuit, the pixel circuit includes a light-emitting device and a driving transistor, the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; The pixel circuit further comprises a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; The material of the active layer of the driving transistor is a first semiconductor material, the material of the active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; The electrode where the active layer of the control transistor is located is directly electrically connected to the gate of the drive transistor and the first electrode of the control transistor.

2. The display substrate according to claim 1, wherein: The active layer of the driving transistor and the active layer of the control transistor are arranged in different layers, and the gate of the driving transistor is located between the electrodes where the active layers of the driving transistor and the control transistor are located.

3. The display substrate according to claim 2, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The active layer of the driving transistor is located on a side of the active layer of the control transistor close to the base substrate.

4. The display substrate according to claim 1, wherein: The pixel circuit comprises a first reset transistor, wherein the first reset transistor is configured to write a first reset signal to a gate of the driving transistor under the control of a first reset control signal; The control transistor includes the first reset transistor, and an electrode where an active layer of the first reset transistor is located is directly electrically connected to a gate of the drive transistor and a first electrode of the first reset transistor.

5. The display substrate according to claim 4, wherein: The electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is converted into a conductor, and the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure; The gate of the driving transistor is arranged in a different layer from the electrode where the active layer of the first reset transistor is located, and the first electrode of the first reset transistor contacts the gate of the driving transistor through a first via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor.

6. The display substrate according to claim 5, wherein: The electrode where the active layer of the first reset transistor is located also includes a second electrode of the first reset transistor, and a material of the second electrode of the first reset transistor is a material obtained by converting the second semiconductor material into a conductor; The pixel circuit also includes a first reset signal line disposed at a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor contacts the first reset signal line through a second via hole exposing the first reset signal line to be directly electrically connected to the first reset signal line.

7. The display substrate according to any one of claims 1 to 6, wherein: The pixel circuit further includes a compensation transistor configured to compensate a signal applied to a gate of the driving transistor in response to a compensation scan signal and the data signal; The control transistor also includes the compensation transistor, and the electrode where the active layer of the compensation transistor is located is directly electrically connected to the gate of the driving transistor and the first electrode of the compensation transistor.

8. The display substrate according to claim 7, wherein: The electrode where the active layer of the compensation transistor is located also includes the first electrode of the compensation transistor, the materials of the active layer of the compensation transistor and the first electrode of the compensation transistor are both the materials after the second semiconductor material is conductive, and the active layer of the compensation transistor and the first electrode of the compensation transistor are arranged in the same layer and form an integrated structure; The gate of the driving transistor is arranged in a different layer from the electrode where the active layer of the compensation transistor is located, and the first electrode of the compensation transistor contacts the gate of the driving transistor through a third via hole exposing the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the compensation transistor.

9. The display substrate according to claim 8, wherein: In the case where the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located includes the active layer of the first reset transistor and the first electrode of the first reset transistor, the material of the first electrode of the first reset transistor is the material after the second semiconductor material is conductive, the active layer of the first reset transistor and the first electrode of the first reset transistor are arranged in the same layer and form an integrated structure, the gate of the driving transistor and the electrode where the active layer of the first reset transistor is located are arranged in different layers, and the first electrode of the first reset transistor contacts the gate of the driving transistor through a first via hole that exposes the gate of the driving transistor to directly electrically connect the gate of the driving transistor and the first electrode of the first reset transistor, The electrode where the active layer of the compensation transistor is located is arranged in the same layer as the electrode where the active layer of the first reset transistor is located and forms an integrated structure, the first electrode of the first reset transistor and the first electrode of the compensation transistor are integrated, and the first via hole and the second via hole are the same via hole; The material of the active layer of the compensation transistor is the second semiconductor material, the material of the first electrode of the compensation transistor is the material after the second semiconductor material is conductive, the first electrode of the first reset transistor, the first electrode of the compensation transistor and the active layer of the compensation transistor are connected in sequence, arranged in the same layer and constitute an integrated structure.

10. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located further includes a connection portion, the material of the connection portion is the material after the second semiconductor material is converted into a conductor, and the connection portion is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; The connection portion contacts the active layer of the first emission control transistor through a fourth via hole exposing the active layer of the first emission control transistor to electrically connect the active layer of the first emission control transistor, and the connection portion serves as a first electrode of the first emission control transistor and a second electrode of the compensation transistor.

11. The display substrate according to claim 10, wherein: The active layer of the first light emitting control transistor and the active layer of the driving transistor are arranged in the same layer, and / or, The gate of the driving transistor is arranged in the same layer as the gate of the first light emitting control transistor.

12. The display substrate according to any one of claims 1 to 6, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the control transistor is located is arranged at a different layer from the second pole of the first light-emitting control transistor, the electrode where the active layer of the control transistor is located is in contact with the active layer of the first light-emitting control transistor through a fourth via hole exposing the active layer of the first light-emitting control transistor, and the second pole of the first light-emitting control transistor is in contact with the active layer of the first light-emitting control transistor through a fifth via hole exposing the active layer of the first light-emitting control transistor.

13. The display substrate according to claim 12, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The second electrode of the first light emitting control transistor is located on a side of the electrode where the active layer of the control transistor is located, away from the substrate.

14. The display substrate according to claim 12, wherein: In the case where the control transistor includes a first reset transistor, the electrode where the active layer of the first reset transistor is located also includes a second electrode of the first reset transistor, a material of the second electrode of the first reset transistor is a material obtained by converting the second semiconductor material into a conductor, the pixel circuit also includes a first reset signal line provided at a different layer from the second electrode of the first reset transistor, and the second electrode of the first reset transistor is electrically connected to the first reset signal line via a second via hole exposing the first reset signal line, The first reset signal line is arranged at a second polarization layer with respect to the first light emission control transistor.

15. The display substrate according to claim 14, wherein: The first reset signal line and the gate of the driving transistor are both located between the gate of the driving transistor and the electrode where the active layer of the control transistor is located; The first reset signal line and the gate of the driving transistor are arranged in a different layer or in the same layer.

16. The display substrate according to claim 15, wherein: The control transistor is a single-gate transistor, and the gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the drive transistor; or, The control transistor is a dual-gate transistor, the first gate of the control transistor is located on a side of the active layer of the control transistor away from the active layer of the driving transistor, the second gate of the control transistor is located between the active layer of the control transistor and the active layer of the driving transistor, and the second gate of the control transistor is set on the same layer or on a different layer as the first reset signal line.

17. The display substrate according to claim 15, wherein: The second gate of the control transistor and the gate of the driving transistor are arranged in a lateral direction; In the case where the control transistor is a dual-gate transistor, a line width of the second gate of the control transistor in the lateral direction is greater than a line width of the first gate of the control transistor in the lateral direction.

18. The display substrate according to claim 14, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The first reset signal line and the gate of the control transistor do not overlap in a direction perpendicular to the main surface of the base substrate.

19. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located also includes a second electrode of the compensation transistor, the material of the second electrode of the compensation transistor is the material after the second semiconductor material is converted into a conductor, and the second electrode of the compensation transistor is arranged in the same layer as the active layer of the compensation transistor to form an integrated structure; The pixel circuit comprises a first connection structure, wherein the first connection structure, the second electrode of the compensation transistor and the electrode where the active layer of the control transistor is located are all arranged in different layers from each other; The first connection structure is electrically connected to the second electrode of the compensation transistor through a sixth via hole, and is electrically connected to the active layer of the first light emission control transistor through a seventh via hole.

20. The display substrate according to claim 19, wherein: The display substrate comprises a base substrate, and the driving transistor is arranged on a main surface of the base substrate; The fifth via hole penetrates the second electrode of the compensation transistor, the first connection structure includes an inner hole portion located in the sixth via hole, a side surface of the inner hole portion contacts the second electrode of the compensation transistor, and a surface where the side surface of the inner hole portion is located intersects with a surface where the main surface of the substrate is located; or, The fifth via hole exposes the upper surface of the second electrode of the compensation transistor, and the upper surface of the second electrode of the compensation transistor is far away from the main surface of the substrate substrate. The first connection structure includes an inner hole portion located in the sixth via hole, and the bottom surface of the inner hole portion is in contact with the upper surface of the second electrode of the compensation transistor.

21. The display substrate according to claim 7, wherein: The pixel circuit further includes a first light emission control transistor, which is configured to enable the driving current to be applied to the light emitting device under the control of a first light emission control signal; The material of the active layer of the first light emission control transistor is the first semiconductor material, and the active layer of the first light emission control transistor and the active layer of the control transistor are arranged in different layers; The electrode where the active layer of the compensation transistor is located also includes a second electrode of the compensation transistor, the material of the second electrode of the compensation transistor is the material after the second semiconductor material is converted into a conductor, and the connecting portion is arranged at the same layer as the active layer of the compensation transistor to form an integrated structure; The pixel circuit further includes a second connection structure and a third connection structure, and the second electrode of the compensation transistor, the second connection structure, the third connection structure and the active layer of the first light emission control transistor are all arranged in different layers; The second electrode of the compensation transistor is electrically connected to the second connection structure through an eighth via hole, the third connection structure is electrically connected to the second connection structure through a ninth via hole, and the third connection structure is electrically connected to the active layer of the first light emission control transistor through a tenth via hole.

22. The display substrate according to any one of claims 1 to 6, wherein: The first semiconductor material is a silicon semiconductor material, and the second semiconductor material is a transparent metal oxide semiconductor material.

23. The display substrate according to claim 22, wherein: The transparent metal oxide semiconductor material includes indium gallium zinc oxide (IGZO).

24. A display device, comprising the display substrate according to any one of claims 1-23.

25. A method for manufacturing a display substrate, comprising: Forming a sub-pixel, including forming a pixel circuit, wherein the forming the pixel circuit includes forming a light-emitting device and a driving transistor, wherein the driving transistor is configured to control the magnitude of a driving current flowing through the light-emitting device according to a data signal; The forming of the pixel circuit also includes: forming a control transistor, wherein a first electrode of the control transistor is electrically connected to a gate electrode of the driving transistor; a material of an active layer of the driving transistor is a first semiconductor material, a material of an active layer of the control transistor is a second semiconductor material, and the first semiconductor material is different from the second semiconductor material; an electrode where the active layer of the control transistor is located is directly electrically connected to the gate electrode of the driving transistor and the first electrode of the control transistor.

26. The method for manufacturing a display substrate according to claim 25 comprises: forming a first type of via hole, wherein the first type of via hole at least exposes the active layer composed of the first semiconductor material; forming a first conductive structure to electrically connect to the surface of the active layer composed of the first semiconductor material exposed by the first type of via hole through the first type of via hole; After forming the first type via hole, performing a high temperature annealing process on the display substrate; and The surface of the active layer made of the first semiconductor material and exposed by the first type via hole is processed to reduce contact resistance.

27. The method for manufacturing a display substrate according to claim 26, comprising: Using the second semiconductor material to form a second semiconductor layer through a single patterning process; Conducting a portion of the second semiconductor layer to form a second conductive structure, wherein the second conductive structure serves as an electrode where the active layer of the control transistor is located, and includes a conductive portion and a non-conductive portion, wherein the conductive portion and the non-conductive portion form an integrated structure; the non-conductive portion constitutes the active layer of the control transistor, the conductive portion directly electrically connects the gate of the drive transistor and the first electrode of the control transistor, and the conductive portion is made of a material obtained by conducting the second semiconductor material; and A second type of via is formed, and the conductorized portion of the second conductive structure is directly electrically connected to the gate of the driving transistor and the first electrode of the control transistor through the second type of via.

28. The method for manufacturing a display substrate according to claim 27, wherein: After forming the second type via hole and before forming the second conductive structure, the high temperature annealing process is performed on the display substrate.

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