Capacitor device and manufacturing method thereof

Abstract

The invention provides a capacitor device. The capacitor device includes a capacitor structure, a wire, an interlayer dielectric (ILD), and a first via conductor. The capacitor structure comprises a lower electrode and an upper electrode. The wire and the lower electrode are located on the same horizontal plane, and the wire is electrically isolated from the lower electrode. The ILD is disposed over the capacitor structure and the conductive lines. The first via conductor is adjacent to the capacitor structure and is electrically coupled to the wire. The invention also provides a manufacturing method of the capacitor crystal grain.

Description

Technical Field

[0001] The present application relates to a capacitor device and a manufacturing method thereof. In particular, the disclosed capacitor device includes a sealing ring structure laterally surrounding the capacitor structure. Background Art

[0002] Decoupling capacitors, also known as bypass capacitors, can act as energy storage for the circuits they are integrated with. In some applications, decoupling capacitors are implemented as integrated passive devices (IPDs). IPD capacitors are widely used due to their high / dense capacitance values ​​and low equivalent series resistance (ESR) and equivalent series inductance (ESL). IPD technology is a system in package (SiP) solution in which high-quality passive components can be manufactured on a wafer and then connected to a main die by wire bonding or solder mounting. Before being connected to the main die, the IPD capacitors manufactured on the wafer can be singulated into multiple IPD capacitor dies. However, the IPD capacitors may be damaged during the singulation operation, such as die cracking, die edge cracking, or defects, which may reduce the reliability of the IPD capacitors. Therefore, there is a need for alternative methods to manufacture capacitor devices to improve their reliability. Summary of the invention

[0003] In an exemplary embodiment of the present application, a capacitor device is provided. The capacitor device includes a capacitor structure, a wire, an interlayer dielectric (ILD), and a first through-hole conductor. The capacitor structure includes a lower electrode and an upper electrode. The wire is located at the same horizontal plane as the lower electrode and is electrically isolated from the lower electrode. The ILD is disposed above the capacitor structure and the wire. The first through-hole conductor is adjacent to the capacitor structure and is electrically coupled to the upper surface of the wire.

[0004] In another exemplary embodiment of the present application, a capacitor device is provided. The capacitor device includes a capacitor structure, a first through-hole conductor, and a second through-hole conductor. The capacitor structure includes a lower electrode and an upper electrode. The first through-hole conductor is electrically connected to the lower electrode. The second through-hole conductor is adjacent to the first through-hole conductor and electrically isolated from the first through-hole conductor. The second through-hole conductor is configured as a sealing ring structure to surround the capacitor structure and the first through-hole conductor.

[0005] In another exemplary embodiment of the present application, a method for manufacturing an integrated capacitor device is provided. The method includes the following operations. A capacitor wafer is received. The capacitor wafer has a capacitor structure and a wire surrounding the capacitor structure. The capacitor structure includes a lower electrode and an upper electrode, and the wire is located at the same level as the lower electrode and is electrically isolated from the lower electrode. A first through-hole conductor is formed on the wire, and the first through-hole conductor laterally surrounds the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure can be best understood by reading the following embodiments and the accompanying drawings. It should be noted that the various features in the drawings are not drawn to scale, in accordance with standard operating practices in the art. In fact, the size of some features may be deliberately enlarged or reduced in order to be clearly described.

[0007] Figure 1A A cross-sectional view of a capacitor device according to some embodiments of the present application is shown.

[0008] Figure 1B A cross-sectional view of a capacitor device according to some embodiments of the present application is shown.

[0009] Figure 2 A top view of a capacitor device according to some embodiments of the present application is shown, in a state where no metal lines are formed.

[0010] Figure 3 A top view of a capacitor device according to some embodiments of the present application is shown, which shows metal lines formed on Figure 2 In the capacitor device shown.

[0011] Figure 4 A top view of a capacitor device according to some embodiments of the present application is shown, showing that the conductive terminals are formed on Figure 3 In the capacitor device shown.

[0012] Figure 5 A layout diagram of a capacitor device according to some embodiments of the present application is shown, in a state where no metal lines are formed.

[0013] Figure 6 A layout diagram of a capacitor device according to some embodiments of the present application is shown, which shows that metal lines are formed on Figure 5 In the capacitor device shown.

[0014] Figures 7 to 13 A cross-sectional view of a capacitor device formed according to some embodiments of the present application is shown. DETAILED DESCRIPTION

[0015] This application claims priority to U.S. application No. 18 / 363,623, filed on August 1, 2023, the entirety of which is incorporated herein by reference.

[0016] The following disclosure provides many different embodiments or examples for implementing the different features of the present application. The following describes specific examples of components and configurations to simplify the present application. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first component is formed above a second component or a first component is formed on a second component, and an embodiment in which the first component and the second component are directly in contact may be included, and an embodiment in which an additional component is formed between the first component and the second component may be included, so that the first component and the second component may not be in direct contact. In addition, the disclosed content of the present application may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another element or components, as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0018] As used herein, terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or sections, which should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer, or section from another. When the terms "first," "second," and "third" are used herein, no order or sequence is implied unless clearly indicated by the context.

[0019] Figure 1A Draw along Figure 2 A cross-sectional view of the capacitor device taken along line segment AA. Figure 1B Draw along Figure 2 A cross-sectional view of the capacitor device taken along line segment BB. Figure 1A and Figure 1B It can be a schematic diagram of part or all of the capacitor device 100. The capacitor device 100 can be an integrated capacitor device or an integrated capacitor. In order to more clearly demonstrate the innovative concept of the present application, Figure 1A to Figure 1BThe capacitor device 100 may have additional features, and some of the features described below may be replaced, modified, or deleted in other embodiments of the capacitor device 100. Figure 1A As shown, the capacitor device 100 includes a capacitor structure 110, an interlayer dielectric (ILD) 130 disposed above the capacitor structure 110, and a through-hole conductor 140 adjacent to the capacitor structure 110. The capacitor device 100 has a lower surface 102 and an upper surface 104. In some embodiments, the capacitor device 100 includes an oxide film (not shown in the figure) exposed on the lower surface 102. The capacitor structure 110 can be formed above the oxide film on a semiconductor substrate (not shown in the figure). In some embodiments, the oxide film is also called a silicon oxide film.

[0020] The capacitor structure 110 includes a first electrode including a lower metal plate 112, a second electrode including an upper metal plate 114, and an insulating film 126 located between the first electrode and the second electrode. In the example of the present application, the first electrode including the lower metal plate 112 is also referred to as a lower electrode, and the second electrode including the upper metal plate 114 is also referred to as an upper electrode. The lower electrode including the lower metal plate 112 is electrically connected to at least one first conductive terminal 182 exposed to the upper surface 104 of the capacitor device 100. The upper electrode including the upper metal plate 114 is electrically connected to at least one second conductive terminal 184 exposed to the upper surface 104 of the capacitor device 100. The capacitor device 100 may include a plurality of first conductive terminals 182 and a plurality of second conductive terminals 184.

[0021] The lower electrode, the upper electrode and the insulating film 126 form a capacitor structure 110. Since each of the lower electrode and the upper electrode includes at least one metal film (such as the lower metal plate 112 or the upper metal plate 114), the formed capacitor structure 110 is a MIM (metal-insulator-metal) capacitor. Figure 1A As shown, the capacitor structure 110 is a crown type stacked capacitor.

[0022] Each lower electrode and upper electrode includes a plurality of stacked conductor films. The lower electrode includes a lower metal plate 112 (also referred to as a metal film) and a metal film 122 as a conductor film. The lower metal plate 112 and the metal film 122 are electrically connected to each other and serve as an integrated lower electrode. The metal film 122 can serve as a barrier metal. The upper electrode includes a metal film 124, doped silicon 128 and an upper metal plate 114 (also referred to as a metal film) as a conductor film. The doped silicon 128 can fill the hollow space of the crown stack capacitor, which has good coverage and improves the mechanical strength of the crown stack capacitor. The metal film 124, the doped silicon 128 and the upper metal plate 114 are electrically connected to each other and serve as an integrated upper electrode. The capacitor structure 110 may further include one or more nitride films 127 between the insulating films 126. Alternatively, the capacitor structure 110 may further include one or more nitride films (not shown) formed on the upper surface of the lower metal plate 112.

[0023] The lower metal plate 112, the metal film 122, the metal film 124, and the upper metal plate 114 may be made of a conductive material, such as titanium (Ti) or Ti-TiN. Alternatively, the metal film 122 and the metal film 124 are made of Ti-TiN, and the lower metal plate 112 and the upper metal plate 114 are made of tungsten (W). The doped silicon 128 may be made of a boron-doped silicon germanium film. The insulating film 126 may be made of, for example, a high-k dielectric material. The insulating film 126 made of a high-k dielectric material includes, for example, one or more of high-k dielectric materials such as Ta2O5, Al2O3, HfO2, ZrO2, and TiO2.

[0024] The capacitor device 100 includes an interlayer dielectric (ILD) 130. The ILD 130 may include a single layer structure or a multi-layer structure. For example, the ILD 130 may be Figure 1AA three-layer structure is shown, but the present application is not limited thereto. In some embodiments, the three-layer ILD 130 may include dielectric films 132, 134, and 138. The dielectric films 132, 134, and 138 may include silicon oxide films. The ILD 130 covers the upper metal plate 114 of the upper electrode. Optionally, the protection layer 120 is disposed between the ILD 130 and the upper metal plate 114 to protect the upper surface of the capacitor structure 110. The ILD 130 further covers the lower metal plate 112 of the lower electrode. The ILD 130 is disposed above the wire 116. The wire 116 is substantially located at the same horizontal plane as the lower metal plate 112. The wire 116 may be formed of a material similar to that of the lower metal plate 112. In some embodiments, the wire 116 and the lower metal plate 112 are also referred to as different segments in the same metal layer (also referred to as a metallization layer). The wire 116 may be separated from the lower metal plate 112 by a spacing S1. The conductive line 116 is electrically isolated from the lower metal plate 112 of the lower electrode. In some embodiments, the thickness of the conductive line 116 is substantially the same as the thickness of the lower electrode of the capacitor structure 110. In some embodiments, the thickness of the conductive line 116 is substantially the same as the thickness of the lower metal plate 112 of the lower electrode of the capacitor structure 110.

[0025] One or more through-hole conductors 140 may be disposed in the ILD 130. The through-hole conductor 140 penetrates the dielectric film 132 of the ILD 130 and contacts the conductive line 116. The through-hole conductor 140 is electrically coupled to the upper surface of the conductive line 116. The through-hole conductor 140 may laterally surround the capacitor structure 110. The conductive line 116 combined with the through-hole conductor 140 is disposed in a peripheral area surrounding the capacitor structure 110 and is electrically isolated from the capacitor structure 110. The upper surface 141a of the through-hole conductor 140 is higher than the upper surface of the upper metal plate 114 of the capacitor structure 110, and the lower surface 141b of the through-hole conductor 140 is substantially located at the same level as the upper surface of the lower metal plate 112 of the capacitor structure 110. The through-hole conductor 140 may include a single-layer structure or a multi-layer structure. For example, the through-hole conductor 140 may be as follows. Figure 1A 140 . A double-layer structure is shown, but the present application is not limited thereto. In some embodiments, the double-layer via conductor 140 may include a conductive layer 140 a and a barrier metal layer 140 b. The conductive layer 140 a may be made of tungsten (W), and the barrier metal layer 140 b may be made of TiN. Alternatively, the barrier metal layer 140 b may be omitted so that the conductive layer 140 a directly contacts the ILD 130.

[0026] In some embodiments, the density of the conductive material of the via conductor 140 is greater than the density of the conductive material of the capacitor structure 110. For example, the density of the conductive layer 140a of the via conductor 140 is greater than the density of the lower metal plate 112 or the upper metal plate 114 of the capacitor structure 110. In some embodiments, the Mohs hardness of the conductive material of the via conductor 140 is greater than the Mohs hardness of the conductive material of the capacitor structure 110. For example, the Mohs hardness of the conductive layer 140a of the via conductor 140 is greater than the Mohs hardness of the conductive material of the capacitor structure 110. In some embodiments, the shear modulus of the conductive material of the via conductor 140 is greater than the shear modulus of the conductive material of the capacitor structure 110. For example, the shear modulus of the conductive layer 140a of the via conductor 140 is greater than the shear modulus of the conductive material of the capacitor structure 110. In some embodiments, the via conductor 140 is configured as a sealing ring structure to surround the capacitor structure 110.

[0027] like Figure 1A and Figure 1B As shown, one or more via conductors 142 and one or more via conductors 144 may be disposed in the ILD 130. The via conductor 142 is disposed adjacent to the capacitor structure 110 and electrically coupled to the bottom electrode of the capacitor structure 110. Figure 1B As shown, the via conductor 142 is disposed between the capacitor structure 110 and the via conductor 140. In some embodiments, the via conductor 140 is configured as a sealing ring structure to surround the capacitor structure 110 and the via conductor 142. The conductive wire 116 combined with the via conductor 140 surrounds the capacitor structure 110 and the via conductor 142. The via conductor 142 penetrates the dielectric film 132 of the ILD 130 and contacts the lower metal plate 112. The via conductor 142 is electrically connected to the lower metal plate 112. The via conductor 144 is disposed above the upper electrode of the capacitor structure 110 and is electrically coupled to the upper electrode of the capacitor structure 110. The conductive wire 116 combined with the via conductor 140 surrounds the via conductor 144. The via conductor 144 penetrates the dielectric film 132 of the ILD 130 and contacts the upper metal plate 114. The via conductor 144 is electrically connected to the upper metal plate 114.

[0028] Each of the via conductors 142 and 144 may include a single layer structure or a multi-layer structure. For example, each of the via conductors 142 and 144 may include a Figure 1A and Figure 1BA double-layer structure is shown, but the present application is not limited thereto. In some embodiments, the double-layer through-hole conductor 142 may include a conductive layer 142a and a barrier metal layer 142b, and the double-layer through-hole conductor 144 may include a conductive layer 144a and a barrier metal layer 144b. The double-layer through-hole conductor 142 and the double-layer through-hole conductor 144 may be formed of materials similar to the double-layer through-hole conductor 140, and the relevant details are omitted here and are not repeated. The upper surface 141a of the through-hole conductor 140 is located at the same level as the upper surface 143a of the through-hole conductor 142, and the lower surface 141b of the through-hole conductor 140 is located at the same level as the lower surface 143b of the through-hole conductor 142. Alternatively or additionally, the upper surface 141a of the through-hole conductor 140 is at least located at the same level as the upper surface 143a of the through-hole conductor 142 and the upper surface 145a of the through-hole conductor 144.

[0029] The metal layer may be disposed above the capacitor structure 110 and embedded in the ILD 130. The metal layer may include one or more metal lines 150, 152, 154. The metal lines 150, 152, 154 may be disposed above the through-hole conductors 140, 142, 144, respectively, and electrically connected thereto, respectively. The metal line 150 is substantially located at the same level as the metal line 152. The metal line 150 is substantially located at the same level as the metal line 154. Each of the metal lines 150, 152, 154 may include a single layer structure or a multi-layer structure. For example, each of the metal lines 150, 152, 154 may be as follows: Figure 1A and Figure 1B A three-layer structure is shown, but the present application is not limited thereto. In some embodiments, the three-layer metal line 150 may include a conductive layer 150a, a protective layer 150b, and a barrier layer 150c. The conductive layer 150a may be made of tungsten (W), and the barrier layer 150c may be made of TiN. Alternatively, the protective layer 150b and the barrier layer 150c may be omitted so that the conductive layer 150a directly contacts the conductive layer 140a. The three-layer metal line 152 may include a conductive layer 152a, a protective layer 152b, and a barrier layer 152c, and the three-layer metal line 154 may include a conductive layer 154a, a protective layer 154b, and a barrier layer 154c. The three-layer metal line 152 and the three-layer metal line 154 may be formed of materials similar to the three-layer metal line 150, and the relevant details are omitted here and are not repeated.

[0030] The via layer may be disposed above the capacitor structure 110 and embedded in the ILD 130. The via layer may include one or more via conductors 160, 162, 164. The via conductors 160, 162, 164 may be disposed above the metal lines 150, 152, 154, respectively, and electrically connected thereto, respectively. Each via conductor 160, 162, 164 may include a single layer structure or a multi-layer structure. For example, each via conductor 160, 162, 164 may be as follows: Figure 1A and Figure 1B A double-layer structure is shown, but the present application is not limited thereto. In some embodiments, the double-layer via conductors 160, 162, 164 may include conductive layers 160a, 162a, 164a and barrier layers 160b, 162b, 164b, respectively. The double-layer via conductors 160, 162, 164 may be formed of materials similar to the double-layer via conductors 142, 144, and the relevant details are omitted and not repeated.

[0031] Another metal layer may be disposed over the capacitor structure 110 and embedded in the ILD 130. The metal layer may include one or more metal lines 170, 172, 174. The metal lines 170, 172, 174 may be disposed over and electrically connected to the via conductors 160, 162, 164, respectively. The metal lines 170, 172, 174 may be electrically connected to the metal lines 150, 152, 154, respectively. The via conductor 160 is coupled between the metal line 150 and the metal line 170. The via conductor 162 is coupled between the metal line 152 and the metal line 172. The via conductor 164 is coupled between the metal line 154 and the metal line 174. In some embodiments, the metal line 170 is embedded in the ILD 130, and the metal lines 172, 174 are exposed outside the ILD 130. Each metal line 170, 172, 174 may include a single layer structure or a multi-layer structure. For example, each metal line 170, 172, 174 may be Figure 1A and Figure 1B A three-layer structure is shown, but the present application is not limited thereto. In some embodiments, the three-layer metal lines 170, 172, 174 may include conductive layers 170a, 172a, 174a, protective layers 170b, 172b, 174b, and barrier layers 170c, 172c, 174c, respectively. The three-layer metal lines 170, 172, 174 may be formed of materials similar to the three-layer metal lines 150, 152, 154, and the relevant details are omitted here and are not repeated.

[0032] One or more conductive terminals 182, 184 may be disposed above the metal lines 172, 174, respectively, and electrically connected thereto. Each conductive terminal 182, 184 may be attached to and disposed on the metal lines 172, 174, respectively. The conductive terminals 182, 184 are configured to be electrically coupled to a power signal or a ground signal, respectively. The conductive terminals 182, 184 may be C4 solder bumps, gold bumps, or micro bumps. The capacitor device 100 further includes a passivation layer 136 disposed above the ILD 130. The passivation layer 136 serves as a protective film to improve the mechanical strength of the conductive terminals 182, 184. The passivation layer 136 may be made of polyimide.

[0033] The capacitor structure 110 can be electrically coupled to the conductive terminals 182, 184 at the upper surface 104 of the capacitor device 100 through the metal lines 152, 154, 172, 174 and the through-hole conductors 142, 144, 162, 164. The conductive terminals 182, 184 (or the metal lines 172, 174 receiving the conductive terminals 182, 184, respectively) can be implemented as different terminals of the capacitor structure 110. For example, the conductive terminal 182 is implemented as a terminal for electrically coupling the capacitor structure 110 to a power signal, and the conductive terminal 184 is implemented as a terminal for electrically coupling the capacitor structure 110 to a ground signal. Accordingly, by electrically coupling to the conductive terminals 182, 184, the capacitor structure 110 in the capacitor device 100 can be electrically coupled to a power signal (e.g., a VDD pad) and a ground signal (e.g., a VSS pad) of an active wafer (not shown in the figure).

[0034] Since the through-hole conductor 140 is electrically coupled to the wire 116 which is electrically isolated from the lower metal plate 112, the through-hole conductor 140 is electrically isolated from the conductive terminals 182 and 184. The through-hole conductor 140, the metal wire 150, the through-hole conductor 160 and the metal wire 170 are electrically connected to each other and serve as an integrated sealing ring structure. The sealing ring structure laterally surrounds the functional area of ​​the capacitor structure 110 from top to bottom. The sealing ring structure is made of a conductive material having a higher density, a higher shear modulus and a higher Mohs hardness than the conductive material in the capacitor structure 110. Accordingly, the sealing ring structure can protect the functional area of ​​the capacitor structure 110 and prevent the capacitor structure 110 from being damaged during the monomerization operation.

[0035] Figure 2 A top view of capacitor device 100 is disclosed in a state where metal lines 150 , 152 , or 154 have not yet been formed. Figure 2 The capacitor device 100 includes a plurality of capacitor units formed on a rectangular semiconductor substrate (not shown in the figure), the rectangular semiconductor substrate having sides extending along a first direction and a second direction orthogonal to each other. In the present application, Figure 2The X direction shown or the like may also be referred to as the first direction, and the Y direction may be referred to as the second direction. For simplicity and clarity, Figure 2 Only the lower metal plate 112 , the upper metal plate 114 , the conductive line 116 , and the through-hole conductors 140 , 142 , 144 are disclosed.

[0036] like Figure 2 As shown, in a top view, the lower metal plate 112 includes a plurality of lower metal plates 112 forming a discrete pattern array, and the upper metal plate 114 includes a plurality of upper metal plates 114 forming a discrete pattern array. Each upper metal plate 114 is arranged to be offset from the lower metal plate 112. Each lower metal plate 112 and each upper metal plate 114 are partially opposite and capacitively coupled to each other, and each pair of capacitively coupled lower metal plates 112 and upper metal plates 114 forms a capacitor unit. Figure 2 As shown, in a top view, the through-hole conductor 142 includes a plurality of through-hole conductors 142 forming a discrete pattern array, and the through-hole conductor 144 includes a plurality of through-hole conductors 144 forming a discrete pattern array. Each through-hole conductor 142 is arranged to be offset from the through-hole conductor 144. The through-hole conductors 142 and 144 are electrically coupled to the lower metal plate 112 and the upper metal plate 114, respectively. The through-hole conductors 142 and 144 can be referred to as cell terminals of the capacitor cell.

[0037] like Figure 2 As shown, in the top view, the upper surface of the conductive line 116 forms a continuous pattern. The conductive line 116 surrounds the lower metal plate 112, the upper metal plate 114, and the through-hole conductors 142 and 144. The upper surface of the through-hole conductor 140 also forms a continuous pattern. The through-hole conductor 140 surrounds the discrete pattern array of the through-hole conductor 142. The through-hole conductor 140 surrounds the discrete pattern array of the through-hole conductor 144. The through-hole conductor 140 surrounds the lower metal plate 112, the upper metal plate 114, and the through-hole conductors 142 and 144. In other words, the through-hole conductor 140 surrounds the capacitor structure 110 in the top view.

[0038] Figure 3 A top view of capacitor device 100 is shown, showing metal lines 170, 172, 174 formed on Figure 2 In the capacitor device 100 shown in FIG. 1 , each metal line 172 and 174 is electrically connected to a portion of the plurality of cell terminals including the through-hole conductors 142 and 144. Figure 3In the example of , each metal wire 172, 174 has a comb shape. The metal wire 172 includes a plurality of first portions (portions extending in the X direction) electrically connected to the through-hole conductor 142, and a second portion (portions extending in the Y direction) connecting these first portions. The metal wire 174 includes a plurality of first portions (portions extending in the X direction) electrically connected to the through-hole conductor 144, and a second portion (portions extending in the Y direction) connecting these first portions. Each first portion of the metal wires 172, 174 is formed to fit each other. Each metal wire 172, 174 is arranged so that each row of a plurality of unit terminals is alternately electrically connected to the metal wires 172, 174. As Figure 3 As shown, in a top view, the upper surface of the metal line 170 forms a continuous pattern. The metal line 170 surrounds the metal lines 172 and 174 in a top view.

[0039] Figure 4 A top view of the capacitor device 100 is shown, which shows that the conductive terminals 182, 184 are formed on Figure 3 In the capacitor device 100 shown in FIG. 1 , the conductive terminal 182 includes a plurality of conductive terminals 182 forming a discrete pattern array and electrically coupled to the metal line 172. The conductive terminal 184 includes a plurality of conductive terminals 184 forming a discrete pattern array and electrically coupled to the metal line 174. The conductive terminals 182 and 184 can be connected to a voltage source having any voltage. For example, one of the conductive terminals 182 and 184 can be connected to a power source, while the other can be grounded.

[0040] Figure 5 A partial schematic diagram of the layout of the capacitor device 100 is disclosed, which is disclosed in a state where metal lines 150, 152, 154 have not yet been formed. For simplicity and clarity, Figure 5 Only through-hole conductors 140, 142, 144 are disclosed. Figure 5 As shown, the upper surface of the through-hole conductor 140 forms a continuous pattern, while the upper surface of the through-hole conductor 142 or the through-hole conductor 144 forms a plurality of discrete patterns. The upper surface of the through-hole conductor 140 may have a moat-like shape, while the upper surface of the through-hole conductor 142 or the through-hole conductor 144 may have a hole-like shape from a top view. In the top view, the through-hole conductor 140 surrounds the capacitor structure 110 (where the through-hole conductor 142 or the through-hole conductor 144 is located). The size of the upper surface of the through-hole conductor 140 is greater than the size of the upper surface of the through-hole conductor 142 or the through-hole conductor 144. For example, the length of the upper surface of the through-hole conductor 140 is greater than the diameter of the upper surface of the through-hole conductor 142 or the through-hole conductor 144. In some embodiments, the through-hole conductor 140 includes two adjacent conductive sealing rings to surround the capacitor structure 110 and the through-hole conductor 142.

[0041] Figure 6 A layout diagram of the capacitor device 100 is shown, which shows that metal lines 170, 172, 174 are formed on Figure 5 In the capacitor device 100 shown. Figure 6 As shown, in a top view, metal line 170 surrounds capacitor structure 110 (where metal lines 172 and 174 are located). In some embodiments, metal line 170 includes two adjacent trenches filled with conductive material. In other words, capacitor device 100 may have more than one integrated sealing ring structure. The number of sealing ring structures may vary according to different design requirements.

[0042] Figures 7 to 13 Disclosed are some embodiments of the invention. Figure 1A and Figure 1B The process of the capacitor device 100 is shown. Figure 7 As shown, in some embodiments, a capacitor wafer 200 (also referred to as an integrated passive device (IPD) wafer) is received. The capacitor wafer 200 includes one or more capacitor structures 110. Figure 7 It can be a schematic diagram of part or all of the capacitor wafer 200. In order to more clearly demonstrate the innovative concept of the present application, Figure 7 Additional features may be added to the capacitor wafer 200 , and some of the features described below may be replaced, modified, or deleted in other embodiments of the capacitor wafer 200 .

[0043] In some embodiments, the capacitor wafer 200 includes an oxide film (not shown in the figure) exposed on the lower surface 102. The capacitor wafer 200 may include a semiconductor substrate (not shown in the figure) located below the oxide film. A metal layer including a lower metal plate 112 and a wire 116 may be formed above the oxide film. A groove 118 may be formed between the lower metal plate 112 and the wire 116 to separate the lower metal plate 112 and the wire 116. The capacitor wafer 200 may include multiple die regions, and the present application only illustrates two die regions (for forming capacitor devices 100a, 100b) in the figure. A groove 318 may be formed between the wires 116 of different capacitor devices 100a, 100b to separate the capacitor device 100a from the capacitor device 100b. In some embodiments, the grooves 118, 318 are filled with a dielectric material similar to the oxide film. Each wire 116 may surround a corresponding capacitor structure 110 in the capacitor devices 100a, 100b.

[0044] like Figure 8As shown, in some embodiments, one or more trenches 340 may be formed, and one or more recesses 342, 344 may be formed. The trench 340 may be a continuous trench in the dielectric film 132 of the ILD 130 in which the capacitor structure 110 is embedded. The recesses 342, 344 may be formed by an etching operation. The recesses 342, 344 may be a plurality of discrete recesses in the dielectric film 132 of the ILD 130. In one example, the method of forming the trench 340 and the recesses 342, 344 includes a photolithography patterning process and an etching process to etch the trench 340 and the recesses 342, 344 in the dielectric film 132 of the ILD 130. The photolithography patterning process includes coating photoresist (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other appropriate processes, and / or combinations thereof. The etching process includes dry etching, wet etching and / or other etching methods (eg, reactive ion etching).

[0045] In some embodiments, forming the continuous trench 340 and forming the discrete grooves 342, 344 can be performed in a single operation. The etching process can be selectively adjusted to remove the dielectric material of the dielectric film 132 but not remove the conductive material of the upper metal plate 114, the conductive material of the lower metal plate 112, and the conductive material of the wire 116. In other words, in the etching process, the conductive material of the upper metal plate 114, the conductive material of the lower metal plate 112, and the conductive material of the conductive line 116 can serve as etching stop points. For example, etching stops at the lower metal plate 112 when forming the groove 342, etching stops at the upper metal plate 114 when forming the groove 344, and etching stops at the conductive line 116 when forming the trench 340. Accordingly, the trench 340 and the grooves 342, 344 can be formed simultaneously in the same etching operation. The depth of the trench 340 can be substantially the same as the depth of the groove 342. The depth of the groove 342 can be greater than the depth of the groove 344. In a top view, the length of the groove 340 is greater than the length (or diameter) of the recess 342 .

[0046] like Fig. 9As shown, in some embodiments, the groove 340 and the grooves 342, 344 are filled with a conductive material to form a through-hole conductor 140, a through-hole conductor 142 and a through-hole conductor 144. The groove 340 and the grooves 342, 344 may be filled with a conductive material through an electroplating operation. Alternatively, the groove 340 and the grooves 342, 344 may be filled with a conductive material through a deposition operation. The deposition operation includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other appropriate methods and / or combinations thereof. Each through-hole conductor 142 is formed on a corresponding lower metal plate 112 and is electrically connected thereto. Each through-hole conductor 144 is formed on a corresponding upper metal plate 114 and is electrically connected thereto. Each through-hole conductor 140 is formed on a corresponding wire 116, and each through-hole conductor 140 laterally surrounds a corresponding capacitor structure 110. Due to the presence of the trench 118 , each via conductor 140 is electrically isolated from the corresponding capacitor structure 110 .

[0047] After forming the through-hole conductor 140, the through-hole conductor 142 and the through-hole conductor 144, metal lines 150, 152, 154 may be formed on the through-hole conductor 140, the through-hole conductor 142 and the through-hole conductor 144, respectively, and electrically connected thereto, respectively. The metal lines 150, 152, 154 are formed by any suitable process. For example, the metal lines 150, 152, 154 may be formed by a process including deposition, photolithography patterning and etching processes. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), other appropriate methods and combinations thereof. The photolithography patterning process includes coating photoresist (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., hard baking), other appropriate processes and combinations thereof. The etching process includes dry etching, wet etching and other etching methods (e.g., reactive ion etching).

[0048] like Fig.10 As shown, in some embodiments, another dielectric film 134 is formed on the metal lines 150, 152, 154. The dielectric film 133 may be formed of a material similar to the dielectric film 132. Via conductors 160, 162, 164 may be formed on the metal lines 150, 152, 154, respectively, and electrically connected thereto. The via conductors 160, 162, 164 may be formed of a material and process similar to the material and process used to form the via conductors 140, 142, 144. Metal lines 170, 172, 174 may be formed on the via conductors 160, 162, 164, respectively, and electrically connected thereto. The metal lines 170, 172, 174 may be formed of a material and process similar to the material and process used to form the metal lines 150, 152, 154.

[0049] like Fig.11 As shown, in some embodiments, another dielectric film 138 is formed over the dielectric film 134. The dielectric film 138 may be formed of a material similar to that used to form the dielectric film 134. The dielectric film 138, the dielectric film 134, and the dielectric film 132 together define a continuous interlayer dielectric layer, such as the ILD 130. The passivation layer 136 is formed over the ILD 130. One or more openings 310 may be formed in the passivation layer 136 to define the location of the cutting line for use in a subsequent singulation operation. The opening 310 may be formed between two adjacent through-hole conductors 140 of different capacitor devices 100a, 100b. Additionally, one or more openings 312 may be formed in the passivation layer 136 to define the location of the conductive terminals 182, 184. The openings 310, 312 may be formed by any suitable process. For example, the openings 310 , 312 may be formed by a process including photolithography patterning and etching processes.

[0050] like Fig.12 As shown, in some embodiments, the conductive terminals 182, 184 can be respectively configured to contact the metal lines 172, 174 to be electrically connected to other semiconductor structures or devices, such as an interposer or a printed circuit board. In some embodiments, the conductive terminals 182, 184 are formed of a low melting point material, which can be formed through a low temperature operation.

[0051] like Fig.13 As shown, in some embodiments, the capacitor wafer 200 is singulated to obtain the capacitor devices 100a, 100b. The capacitor wafer 200 may be singulated by sawing or other suitable cutting methods. The singulation operation includes forming openings in two adjacent through-hole conductors 140 of different capacitor devices 100a, 100b.

[0052] The presence of the through-hole conductor 140 or the sealing ring structure (i.e., the through-hole conductor 140, the metal line 150, the through-hole conductor 160, and the metal line 170) can provide many advantages. In some comparative embodiments, if there is no through-hole conductor 140, the capacitor structure 110 may be damaged during the singulation operation, such as grain cracking, grain edge cracking, or defects, which may reduce the reliability of the capacitor structure 110. The through-hole conductor 140 surrounds the capacitor structure 110 laterally and completely covers the functional area of ​​the capacitor structure 110 from top to bottom. The through-hole conductor 140 is electrically isolated from the capacitor structure 110. The through-hole conductor 140 is made of a material having a higher density and hardness than the capacitor structure 110. Based on these features, the through-hole conductor 140 can protect the capacitor structure 110 and prevent the capacitor structure 110 from being potentially damaged during the singulation operation. As a result, the damage to the capacitor structure 110 can be reduced. In addition, the purpose of improving the performance of the capacitor device 100 can also be achieved.

[0053] In short, according to the above embodiments, the sealing ring structure laterally surrounds the functional area of ​​the IPD device from top to bottom. The sealing ring structure is electrically isolated from the IPD device. The sealing ring structure is made of a material having a higher density and hardness than the IPD device. Therefore, the sealing ring structure can protect the functional area of ​​the IPD device and prevent the functional area of ​​the IPD device from being damaged during the singulation operation. As a result, damage to the IPD device can be reduced.

[0054] The foregoing content summarizes the structures of several embodiments so that those skilled in the art can better understand the aspects disclosed in this application. Those skilled in the art should understand that they can easily use this application as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced in this application. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of this application, and they can make various changes, substitutions and modifications in this application without departing from the spirit and scope of this application.

[0055] Explanation of symbols

[0056] 100: Capacitor device

[0057] 100a: Capacitor device

[0058] 100b: Capacitor device

[0059] 102: Lower surface

[0060] 104: Upper surface

[0061] 110:Capacitor structure

[0062] 112: Lower metal plate

[0063] 114: Upper metal plate

[0064] 116: Wire

[0065] 118: Groove

[0066] 122:Metal film

[0067] 120: Protective layer

[0068] 124:Metal film

[0069] 126: Insulation film

[0070] 127: Nitride film

[0071] 128: Doped Silicon

[0072] 130: Interlayer Dielectric (ILD)

[0073] 132: Dielectric film

[0074] 134: Dielectric film

[0075] 136: passivation layer

[0076] 138: Dielectric film

[0077] 140:Through hole conductor

[0078] 140a: conductive layer

[0079] 140b: barrier metal layer

[0080] 141a: Upper surface

[0081] 141b: Lower surface

[0082] 142:Through hole conductor

[0083] 142a: Conductive layer

[0084] 142b: Barrier metal layer

[0085] 143a: Upper surface

[0086] 143b: Lower surface

[0087] 144:Through hole conductor

[0088] 144a: Conductive layer

[0089] 144b: Barrier metal layer

[0090] 145a: Upper surface

[0091] 150:Metal wire

[0092] 150a: conductive layer

[0093] 150b: Protective layer

[0094] 150c: Barrier layer

[0095] 152:Metal Wire

[0096] 152a: conductive layer

[0097] 152b: Protective layer

[0098] 152c: Barrier layer

[0099] 154:Metal Wire

[0100] 154a: conductive layer

[0101] 154b: Protective layer

[0102] 154c: Barrier layer

[0103] 160:Through hole conductor

[0104] 160a: conductive layer

[0105] 160b: Barrier layer

[0106] 162:Through hole conductor

[0107] 162a: Conductive layer

[0108] 162b: Barrier layer

[0109] 164:Through hole conductor

[0110] 164a: Conductive layer

[0111] 164b: Barrier layer

[0112] 170:Metal Wire

[0113] 170a: conductive layer

[0114] 170b: Protective layer

[0115] 170c: Barrier layer

[0116] 172:Metal Wire

[0117] 172a: Conductive layer

[0118] 172b: Protective layer

[0119] 172c: Barrier layer

[0120] 174:Metal Wire

[0121] 174a: Conductive layer

[0122] 174b: Protective layer

[0123] 174c: Barrier layer

[0124] 182: (first) conductive terminal

[0125] 184: (Second) Conductive Terminal

[0126] 200:Capacitor Wafer

[0127] 310: Opening

[0128] 312: Opening

[0129] 318: Groove

[0130] 340: Groove

[0131] 342: Groove

[0132] 344: Groove

[0133] AA: Line segment

[0134] BB: Line segment

[0135] S1: Spacing

Claims

1. A capacitor device, comprising: A capacitor structure comprising a lower electrode and an upper electrode; A wire, which is located at the same horizontal plane as the lower electrode and is electrically isolated from the lower electrode; an interlayer dielectric disposed above the capacitor structure and the conductive line; and The first through-hole conductor is adjacent to the capacitor structure and electrically coupled to the upper surface of the conductive line. 2 . The capacitor device of claim 1 , wherein the conductive line combined with the first through-hole conductor is disposed in a peripheral area surrounding the capacitor structure and is electrically isolated from the capacitor structure.

3. The capacitor device of claim 1, further comprising a second via conductor adjacent to the capacitor structure and electrically coupled to the lower electrode, wherein the conductive line combined with the first via conductor surrounds the capacitor structure and the second via conductor.

4. The capacitor device of claim 3, further comprising: a third through-hole conductor disposed above the upper electrode of the capacitor structure and electrically coupled to the capacitor structure, The conductive line combined with the first through-hole conductor further surrounds the third through-hole conductor. 5 . The capacitor device of claim 4 , wherein the third via conductor comprises a plurality of third via conductors forming a discrete pattern array as viewed from above, and the first via conductor surrounds the discrete pattern array. 6 . The capacitor device according to claim 4 , wherein an upper surface of the first through-hole conductor is located at the same level as at least one of an upper surface of the second through-hole conductor and an upper surface of the third through-hole conductor.

7. The capacitor device of claim 4, further comprising a first metal layer disposed above the capacitor structure and embedded in the interlayer dielectric, the first metal layer comprising: a first metal wire connected to the first through-hole conductor; a second metal wire connected to the second through-hole conductor; and A third metal wire is connected to the third through-hole conductor.

8. The capacitor device of claim 7, wherein the first metal line is substantially at the same level as the second metal line and the third metal line.

9. The capacitor device of claim 7, further comprising a second metal layer disposed above the first metal layer, the second metal layer comprising: a fourth metal line connected to the first metal line; a fifth metal line connected to the second metal line; and a sixth metal line connected to the third metal line, The fourth metal line is embedded in the interlayer dielectric, and the fifth metal line and the sixth metal line are exposed outside the interlayer dielectric. 10 . The capacitor device of claim 9 , further comprising a first conductive terminal and a second conductive terminal, respectively disposed on the fifth metal line and the sixth metal line.

11. The capacitor device of claim 9, wherein the interlayer dielectric further comprises a fourth via conductor coupled between the first metal line and the fourth metal line, a fifth via conductor coupled between the second metal line and the fifth metal line, and a sixth via conductor coupled between the third metal line and the sixth metal line.

12. The capacitor device of claim 1, wherein the first via conductor comprises tungsten, wherein the lower electrode and the upper electrode comprise titanium.

13. An integrated capacitor device comprising: A capacitor structure comprising a lower electrode and an upper electrode; A first through-hole conductor electrically connected to the lower electrode; and The second via conductor is adjacent to the first via conductor and electrically isolated from the first via conductor, wherein the second via conductor is configured as a sealing ring structure to surround the capacitor structure and the first via conductor.

14. The integrated capacitor device of claim 13, wherein an upper surface of the second via conductor is located at the same level as an upper surface of the first via conductor, and a lower surface of the second via conductor is located at the same level as a lower surface of the first via conductor. 15 . The integrated capacitor device of claim 14 , wherein the upper surface of the second via conductor forms a continuous pattern, and the upper surface of the first via conductor forms a plurality of discrete patterns when viewed from above. 16 . The integrated capacitor device of claim 13 , wherein the second via conductor comprises two adjacent conductive sealing rings surrounding the capacitor structure and the first via conductor when viewed from above.

17. A method of manufacturing an integrated capacitor device, the method comprising: Receiving a capacitor wafer having a capacitor structure and a wire surrounding the capacitor structure, wherein the capacitor structure includes a lower electrode and an upper electrode, and wherein the wire is located at the same level as the lower electrode and is electrically isolated from the lower electrode; and A first through-hole conductor is formed on the conductive line, and the first through-hole conductor laterally surrounds the capacitor structure.

18. The method of claim 17, wherein forming the first via conductor comprises forming a continuous trench in an interlayer dielectric in which the capacitor structure is embedded, and filling a first conductive material into the continuous trench.

19. The method of claim 18, further comprising: A second through-hole conductor is formed on the lower electrode, wherein forming the second through-hole conductor includes forming a plurality of discrete grooves in the interlayer dielectric and filling the discrete grooves with a second conductive material.

20. The method of claim 19, wherein forming the continuous trench and forming the discrete recesses are performed in a single operation.

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