Method and system for updating device firmware while maintaining state and connectivity

Abstract

A system and related method includes a first processor core, a second processor core, and control circuitry to receive a request to update existing firmware of the first processor core to new firmware. The control circuitry loads the existing firmware onto the second processor core and migrates data associated with the existing firmware on the first processor core to the second processor core. The control circuitry stops the first processor core from executing the transaction while causing the second processor core to execute the transaction in place of the first processor core. The control circuit restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data of the existing firmware on the second processor core to the first processor core. The control circuitry stops transaction execution of the second processor core and causes the first processor core to execute the transaction.

Description

Technical Field

[0001] The present disclosure relates to systems and methods for updating existing firmware on a device to new firmware, and more particularly, the present disclosure relates to updating existing firmware on a device to new firmware while maintaining state data and connectivity on the device. Background Art

[0002] The device (e.g., storage device) may be connected to a peripheral component interconnect express (PCIe) interface or other interface. During operation of the device, when at least one core is executing commands or instructions, the firmware of the processor core may need to be updated, which may result in throughput inefficiencies. Summary of the invention

[0003] According to the present disclosure, a system and method are provided for a dynamic firmware update application that operates on a device (such as a solid-state drive (SSD) device) while maintaining operating state, data, and connectivity. For example, an SSD device having a controller, a multi-core processor, existing firmware on a processor core, and currently executing a transaction receives a request to update the existing firmware to a new firmware. The dynamic firmware update application can be implemented at least in part on the controller using software, hardware, or a combination thereof. In some embodiments, the firmware cannot be updated until all outstanding transactions are executed and all cores are available to be reset to load the new firmware. This may require an extended period of time, and therefore problems arise when the firmware needs to be updated immediately. In addition, updating the firmware of a processor core may cause compatibility issues between the processor core and other processor cores.

[0004] According to the present disclosure, in some embodiments, when an unfinished transaction can continue to be executed on the first processor core, the dynamic firmware update application searches for an available processor core that can load the existing firmware to act as an independent processor core when the first processor core is updated to the new firmware. In some embodiments, the dynamic firmware update application further includes determining that the second processor core is available before continuing the firmware update. Data such as unfinished transactions, operating status, and connectivity status are migrated from the first processor core to the second processor core so that the first processor core can stop executing, restart, and replace the existing firmware with the new firmware. In this way, the dynamic firmware update application runs with two data migration handovers to ensure that unfinished transactions are executed while the firmware on the first processor core is being updated.

[0005] In some embodiments, the dynamic firmware update application receives a request to update the existing firmware of the first processor core to the new firmware. The dynamic firmware update application then loads the existing firmware onto the second processor core and migrates data associated with the operating state of the existing firmware on the first processor core to the second processor core. In some embodiments, the dynamic firmware update application further causes the first processor core to stop executing transactions while causing the second processor core to use the existing firmware to replace the first processor core to execute transactions. In some embodiments, the dynamic firmware update application further restarts the first processor core, replaces the existing firmware on the first processor core with the new firmware, and migrates data associated with the operating state of the existing firmware on the second processor core to the first processor core. In some embodiments, the dynamic firmware update application further causes the second processor core to stop executing transactions and causes the first processor core to execute transactions using the new firmware.

[0006] In some embodiments, the dynamic firmware update application can be used to update the firmware of any suitable device having multiple cores coupled to a peripheral component interconnect express (PCIe) interface. In some embodiments, the device can be, for example, any suitable storage device that can communicate through a PCIe interface using a non-volatile memory express (NVMe) standard protocol. The non-volatile memory express (NVMe) industry standard protocol defines a register-level interface for a host system to communicate with a device (e.g., an SSD or HDD) through a peripheral component interconnect express (PCIe) bus. In some embodiments, the dynamic firmware update application can be used to update the firmware of any suitable device having multiple cores coupled to an Ethernet interface.

[0007] In some embodiments, migrating data associated with the operating state of the existing firmware on the first processor core to the second processor core further includes loading the data associated with the operating state of the existing firmware on the first processor core onto an available memory area associated with the second processor core. In some embodiments, the data associated with the operating state of the existing firmware on the first processor core and the new firmware on the second processor core includes a plurality of uncompleted transactions, states of the respective firmware, and input / output connectivity states of the respective firmware, each of which can be migrated between the processor cores. In some embodiments, restarting the first processor core occurs after the second processor core begins executing transactions and before replacing the existing firmware on the first processor core.

[0008] In some embodiments, a solid state drive (SSD) device is provided as having a processor and a controller that are communicatively coupled to each other. In some embodiments, the processor includes at least a first processor core and a second processor core. In some embodiments, the processor is a multi-core processor having more than two processor cores. In some embodiments, the controller is configured to receive a request to update the existing firmware to a new firmware, load the existing firmware onto the second processor core, and migrate data associated with the operating state of the existing firmware on the first processor core to the second processor core. The controller is further configured to stop the first processor core from executing transactions, while causing the second processor core to use the existing firmware to replace the first processor core to execute transactions, and while causing the first processor core to restart. In some embodiments, the controller is further configured to replace the existing firmware on the first processor core with the new firmware, migrate data associated with the operating state of the existing firmware on the second processor core to the first processor core, stop the second processor core from executing transactions, and cause the first processor core to execute transactions using the new firmware. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The following description includes a discussion of the accompanying drawings, which have illustrations given by examples of implementation of embodiments of the present invention. The accompanying drawings should be understood as examples and not as limitations. As used herein, references to one or more "embodiments" should be understood to describe specific features, structures and / or characteristics included in at least one implementation. Therefore, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe various embodiments and implementations, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0010] Figure 1 An illustrative diagram showing a system with a multi-core processor and a controller according to some embodiments of the present disclosure;

[0011] Figure 2 A flowchart illustrating a process for updating existing firmware of a first processor while continuing to execute transactions on a second processor core according to some embodiments of the present disclosure;

[0012] Figure 3 A flow chart illustrating a process for migrating data from a first processor to a second processor is shown according to some embodiments of the present disclosure;

[0013] Figure 4 A flow chart illustrating a process for migrating data from a second processor core to a first processor core and resuming transactional execution on the first processor core is shown according to some embodiments of the present disclosure;

[0014] Figure 5A flowchart illustrating a process for updating existing firmware of a first processor core while continuing to execute transactions on a second processor core according to some embodiments of the present disclosure; and

[0015] Figure 6 A diagram illustrating a chronological data flow between first and second processor cores executing programs or routines simultaneously according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] According to the present disclosure, a system and method for updating the firmware on the first processor core currently processing a transaction is provided. The features of the present disclosure related to updating the firmware on the device are applicable to devices with multiple processors, one or more multi-core processors, or both. For example, in some embodiments, the device is a solid-state drive (SSD) device with a multi-core processor, and the multi-core processor has a buffer for read and write commands executed by the processor core. The multi-core processor allows multiple instructions to be executed simultaneously by using multiple cores with shared data and instruction memories. For example, each processor core can receive commands from the buffer in order and process each command so that there is no data danger or conflict when writing or reading the memory of the SSD device. The multi-core processor is useful for processing multiple instructions of a program at the same time or running multiple programs at the same time. It will be understood that although the present disclosure is mainly described in the context of a device with a multi-core processor, the features of the present disclosure can be similarly applied to different processors (whether single-core processors, multi-core processors, or both).

[0017] In some embodiments, the firmware of the processor core of the example SSD device may need to be updated. The firmware of the processor may include a set of instructions or microcodes required to define the functionality of the processor. The firmware is loaded onto the processor core of the processor as a microcode, which is stored in a reserved area of ​​a local memory accessible to the processor. When, for example, an SSD controller in an SSD device receives a firmware update request, the first processor core may be executing commands or instructions, and additional commands or instructions may be temporarily stored in a buffer waiting to be executed. The firmware of the first processor core cannot be updated while it is processing transactions, because an update of the firmware can change how the processor should manage and execute transactions, and because transactions are sent to be processed by the firmware currently loaded onto the first processor.

[0018] In some embodiments, an available processor core (i.e., a processor core that is not executing any command or instruction) is identified. For example, the SSD device may store an available status bit for each processor core, which indicates whether the corresponding processor core is currently in standby and can be used to process commands or instructions. In some embodiments, the status bit may be stored in a non-volatile memory or a volatile memory as a data structure (e.g., an array, a bitmap, etc.). When the second processor core is determined to be available by checking its available status bit, the data associated with processing the command or instruction and the link to the controller and the connection to the external device are migrated from the first processor core to the second (i.e., available) processor core. In this way, the second processor core mirrors the operating state and role of the first processor core so that the first processor core becomes available for dynamic firmware updates. When the first processor core becomes available by checking its available status bit, the dynamic firmware update application restarts the first processor core. Restarting clears any volatile memory associated with the core and cleans any expired data in the first processor core, the corresponding firmware, and the traffic manager. In some embodiments, in addition to the first processor core, there may be additional processor cores to restart. Once each processor core except the second processor core has been restarted, the controller can update the firmware for each of these restarted processor cores. The existing firmware on the first processor core is replaced by the new firmware. In some embodiments, the new firmware may include a new traffic manager, an input / output port of the first processor core, and an update to a transmission protocol (e.g., PCIe, Ethernet, etc.). Data associated with the operating state of the existing firmware on the second processing core is then migrated to the first processor core. Once the new firmware is loaded onto the first processor core, the first processor core can be used to perform transactions. The operating state of the firmware on the second processor core includes firmware state, connectivity state to external devices (e.g., PCIe devices, Ethernet devices, etc.), a traffic manager, and unfinished transactions of the second processor core. The dynamic firmware update application stops the transaction execution of the second processor core. Finally, the dynamic firmware update application enables the first processor core to perform transactions using the new firmware. The first processor core continues to perform transactions using the new firmware.

[0019] refer to Figure 1-Figure 6 , you can better understand the subject matter of the present disclosure.

[0020] Figure 1An illustrative diagram of a system 100 having a multi-core processor 104 and a controller 110 according to some embodiments of the present disclosure is shown. In some embodiments, the system 100 may include an SSD device 102, the SSD device 102 including a multi-core processor 104 having a first processor core 106, a second processor core 108, and a data bus interface 116. It will be understood that embodiments of the present disclosure are not limited to solid state drives (SSDs). For example, in some embodiments, the system 100 may include a hard disk drive (HDD) device in addition to or in lieu of an SSD.

[0021] An SSD device, such as SSD device 102, is a data storage device that uses integrated circuit assemblies as memory to persistently store data. An SSD device has no moving mechanical components, and this distinguishes an SSD from a traditional electromechanical disk, such as a hard disk drive (HDD) or a floppy disk, which contains a rotating disk and a removable read / write head. Compared to an electromechanical disk, an SSD is generally more resistant to physical shock, operates quietly, has shorter access times, and has shorter latency.

[0022] Many types of SSDs use NAND-based flash memory that retains data in the absence of power and includes a type of non-volatile storage technology. For example, in some embodiments, the SSD may use NAND-based flash memory, NOR-based flash memory, or any other non-volatile memory, or any combination thereof. The quality of service (QoS) of an SSD may be related to the predictability of low latency and the consistency of high input / output operations per second (IOPS) when serving read / write input / output (I / O) workloads. This means that the latency or I / O command completion time needs to be within a specified range without unexpected outliers. The throughput or I / O rate may also need to be tightly regulated without causing a sudden drop in performance levels.

[0023] The first processor core 106 is currently running existing firmware 112, which is the firmware to be updated by the dynamic firmware update application. The existing firmware is also loaded onto the second processor core 108. In some embodiments, the firmware loaded onto the second processor core 108 is referred to as independent firmware 114 because the second processor core 108 is the single available processor core that continues to run when all other processor cores, including the first processor core 106, update the firmware. Additionally, the SSD device 102 includes a controller 110 and a non-volatile memory 118. In some embodiments, the non-volatile memory 118 includes any one or more of a phase change memory (PCM), a PCM and a switch (PCMS), a ferroelectric random access memory (FeRAM) or a ferroelectric transistor random access memory (FeTRAM) and a magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. The first processor core 106, the second processor core 108, and the data bus interface 116 are communicatively coupled to each other via a data bus in the processor 104. In some embodiments, the data bus interface 116 can transmit data packets to a PCIe compatible device using a peripheral component express interconnect (PCIe) protocol. In some embodiments, the data bus interface 116 can transmit data packets to an Ethernet compatible device under an Ethernet protocol. In some embodiments, the data bus interface 116 can utilize a shared processor memory to transmit data packets. The data bus provides a network bus for data migration between the first processor core 106 and the second processor core 108, and reads or writes data from other components such as a non-volatile memory 118 through the data bus interface 116. The migration between the two processor cores includes data associated with the operating state of one of the processor cores. In some embodiments, the data includes a firmware state, a connectivity state to an external device (e.g., a PCIe device, an Ethernet device), and an unfinished transaction of another processor core. The processor 104 may include a hardware processor, a software processor (e.g., a processor using virtual machine emulation) or any combination thereof. The controller 110 (also referred to herein as a control circuit) may include any suitable software, hardware, or both for controlling the data bus interface 116, data migration, and firmware updates. Controller 110 is communicatively coupled to processor 104 to, for example, send instructions for processor firmware updates. Non-volatile memory 118 may include hardware elements for non-transitory storage of commands or instructions that, when executed by processor 104, cause processor 104 to operate in accordance with the embodiments described herein.

[0024] Although the present disclosure is primarily described in the context of a solid-state drive device 102 having, for example, a multi-core processor 104, features of the present disclosure may be similarly applied to different processors (whether single-core processors, multi-core processors, or both). Thus, the solid-state drive device 102 may include multiple processors, wherein each processor core of a first processor loaded with existing firmware requires a firmware update, and the solid-state drive device 102 is capable of migrating data and the existing firmware to a processor core on a second processor.

[0025] The controller 110 includes a control manager 111, which is linked to a traffic manager 113 and an independent traffic manager 115 of the first processor core 106 and the second processor core 108, respectively. The control manager 111 is configured to send control signals from the controller to each of the processor cores 106, 108. When the first processor core 106 and the second processor core 108 receive command or instruction management, respectively, the traffic manager 113 and the independent traffic manager 115 provide command or instruction management. The traffic manager 113 and the independent traffic manager 115 are arranged to comply with a transmission protocol (e.g., PCIe, Ethernet, etc.) compatible with an external device, which is communicatively coupled to the system output 120.

[0026] A solid-state storage device (e.g., an SSD device) may include one or more non-volatile memory die packages, each of which includes a storage unit. In some embodiments, the storage units are organized into pages, and the pages are organized into blocks. Each storage unit may store one or more bits of information. The solid-state storage device may further include a multi-core processor and a storage controller. In some embodiments, an input / output (I / O) command (e.g., a write command) from an external device is buffered in a temporary storage device (buffer) in the SSD storage device before being processed for the memory or storage unit.

[0027] It will be understood that while system 100 depicts an embodiment in which an SSD device on a PCIe interface is configured to have its firmware updated according to the present disclosure, any other suitable device on another suitable interface can have its firmware updated in a similar manner. For example, an Ethernet device can have its firmware updated through a network controller. In some embodiments, other storage devices, peripheral devices, or other devices on a PCIe interface can have their firmware updated on one or more processors or processor cores.

[0028] For purposes of clarity and brevity, and not as a limitation, the present disclosure is provided in the context of a dynamic firmware update application that provides the features and functionality disclosed herein. The dynamic firmware update application may be any suitable software, hardware, or both for implementing such features and functionality. The dynamic firmware update application may be implemented at least in part in, for example, system 100 (e.g., as part of SSD device 102, or any other suitable device on which firmware is being updated). For example, in the example of SSD device 102, the dynamic firmware update application may be implemented in controller 110. In some embodiments, the dynamic firmware update application may be implemented at least in part as part of an operating system of a system in which system 100 is integrated. In some embodiments, the dynamic firmware update application may be implemented at least in part in dedicated circuitry (e.g., as a processor or as one or more processor cores).

[0029] Figure 2 A flow chart of a process 200 for updating existing firmware of a first processor while continuing to execute transactions on a second processor core according to some embodiments of the present disclosure is shown. In some embodiments, the referenced traffic manager, independent traffic manager, first processor core, second processor core, and controller may be implemented as traffic manager 113, independent traffic manager 115, first processor core 106, second processor core 108, and controller 110, respectively. In some embodiments, process 200 may be modified by, for example, having steps rearranged, changed, added, and / or removed.

[0030] At step 202, the dynamic firmware update application receives a request to update the existing firmware to the new firmware. Generally speaking, when the controller receives the firmware update request, the first processor core will have an unfinished transaction to execute. However, the dynamic firmware update application determines when the second processor core has completed execution and is available to perform the dynamic firmware update. For example, in some embodiments, the dynamic firmware update application can use a status bit associated with the second processor core to determine that the second processor core is available. At step 204, the dynamic firmware update application then loads the existing firmware onto the second processor core.

[0031] At step 204, the dynamic firmware update application loads the existing firmware onto the second processor core. The existing firmware that is also currently running on the first processor core is loaded onto the second processor core to ensure firmware compatibility between the first processor core and the second processor core. At step 206, when the dynamic firmware update application migrates data associated with the operating state of the first processor core to the second processor core, both processor cores should have the same existing firmware to avoid any differences in transaction execution.

[0032] At step 206, the dynamic firmware update application migrates data associated with the operational state of the existing firmware on the first processor core to the second processor core. Sending data from the first processor core to the second processor core includes packaging the data into packets to be sent along the data bus interface and received by the second processor core. The operational state of the firmware on the first processor core includes the firmware state, the connectivity state with the external device, and the outstanding transactions of the first processor core.

[0033] At step 208, the dynamic firmware update application stops the first processor core from executing transactions. The dynamic firmware update application has completed the handover from the first processor core to the second processor core, so the first processor core should stop executing transactions so that the second processor core can continue to execute unfinished transactions when the firmware update process resumes. Once the second processor core stops executing transactions, it is available and can remain available until after being updated to the new firmware.

[0034] At step 210, the dynamic firmware update application causes the second processor core to execute transactions using the existing firmware instead of the first processor core. The second processor core continues to execute the unfinished transaction that the first processor core handed over. When the dynamic firmware update application restarts and updates the firmware on the first processor core, the second processor core loaded with the existing firmware is allowed to execute the unfinished transaction. Additionally, while the second processor core is executing, the independent traffic manager of the second processor core will store any newly received transactions into a buffer.

[0035] At step 212, the dynamic firmware update application restarts the first processor core. The restart clears any volatile memory associated with the core and cleans any outdated data within the processor core, the corresponding firmware, and the traffic manager. In some embodiments, there may be additional processor cores to restart in addition to the first processor core. Once each processor core except the second processor core has been restarted, the dynamic firmware update application can update the firmware for each of these restarted processor cores.

[0036] At step 214, the dynamic firmware update application replaces the existing firmware on the first processor core with the new firmware. The new firmware may include a different traffic manager, input / output ports of the first processor core, and updates to a transport protocol (e.g., PCIe, Ethernet, etc.). The new firmware may have been previously stored in a non-volatile memory 118 to which the controller is communicatively coupled, or may be received from a database to which the controller is communicatively coupled via wireless communication. However, the existing firmware does not necessarily need to be overwritten, deleted, or otherwise modified on the first processing core.

[0037] At step 216, the dynamic firmware update application migrates data associated with the operational state of the existing firmware on the second processing core to the first processor core. Once the new firmware is loaded onto the first processor core, the first processor core can be used to execute transactions. The operational state of the firmware on the second processor core includes the firmware state, the connectivity state to external devices (e.g., PCIe devices, Ethernet devices, etc.), the traffic manager, and outstanding transactions of the second processor core.

[0038] The dynamic firmware update application stops the second processor core from executing transactions at step 218. After the data is migrated from the second processor core to the first processor core, the second processor core does not have any outstanding transactions to execute, so it can stop transaction execution.

[0039] At step 220, the dynamic firmware update application causes the first processor core to perform transactions using the new firmware. The first processor core continues to perform transactions using the new firmware. In some embodiments with additional processor cores, the additional processor cores may also be used to perform transactions using the new firmware.

[0040] Figure 3 A flow chart of a process 300 for migrating data from a first processor to a second processor according to some embodiments of the present disclosure is shown. The subprocess 300 is performed as part of a process for updating existing firmware currently operating on a first processor core while continuing to execute transactions. In some embodiments, the referenced traffic manager, independent traffic manager, first processor core, second processor core, control manager, and controller are the traffic manager 113, independent traffic manager 115, first processor core 106, second processor core 108, control manager 111, and controller 110, respectively. In some embodiments, the process 300 may be modified by, for example, having steps rearranged, changed, added, and / or removed.

[0041] At step 302, the dynamic firmware update application disconnects the traffic manager from the control manager. In some embodiments, the control manager is linked to the traffic manager so that control signals are sent from the controller to the first processor core. In the embodiment shown in the flow chart, the existing firmware of the first processor core will be updated to the new firmware while there are still unfinished transactions to be performed. However, when the firmware is updated by replacing the existing firmware with the new firmware, the first processor core cannot process the unfinished transactions. Therefore, the link between the traffic manager and the control manager may be disconnected.

[0042] At step 304, the dynamic firmware update application migrates the traffic manager from the first processor core to the second processor core as a standalone traffic manager. Migrating the traffic manager to the standalone traffic manager includes linking the standalone traffic manager to the control manager and ensuring that the standalone traffic manager is configured to output signals from the system output to the external device using a specific transport protocol (e.g., PCIe, Ethernet).

[0043] At step 306, the dynamic firmware update application migrates data from the first processor core to the second processor core. The migrated data may include uncompleted transactions, operational status, and connectivity status. The data may be used to configure the firmware and independent traffic manager of the second processor core, wherein the second processor core may execute and continue to receive commands or instructions while the firmware of the first processor core is updated.

[0044] At step 308, the dynamic firmware update application resumes the operation of the second processor core. In some embodiments, the second processor core will resume the execution of the transaction at the place where the first processor core last stopped before the first processor core stopped the execution of the transaction. In some embodiments, the instruction pointer can be stored and updated for each command or instruction processed by the core. The instruction pointer can also be moved as part of the data migration between the first processor core and the second processor core. Therefore, by using the same traffic manager configuration, transport layer protocol, and connections to the control manager and external devices, when the firmware of the first processor core is updated, the second processor core should operate as a mirror image of the first processor core.

[0045] At step 310, the dynamic firmware update application resets all cores except the second processor core. When the second processor core is set up and begins executing transactions, the first processor core is reset to clear any volatile memory associated with the first processor core and to purge any expired data within or associated with: the first processor core, the corresponding firmware, and the traffic manager. In some embodiments, there may be additional processor cores to reset in addition to the first processor core. In some embodiments, the resetting of the processor cores may be accomplished by a warm reboot, where the existing firmware and traffic manager for each processor core are reset without removing power to each processor core.

[0046] Although this sub-process 300 is used for data migration and firmware setup of the second processor core, the sub-process 300 only allows each processor core except the second processor core to be reset for firmware update. The method of the present disclosure also allows the second processor core to be used for firmware update by handing over transaction execution back to the first processor core once each processor core except the second processor core has booted the updated firmware.

[0047] Figure 4 A flow chart illustrating a process 400 for migrating data from a second processor core to a first processor core and resuming transactional execution on the first processor core is shown according to some embodiments of the present disclosure. The subprocess 400 is performed as part of a process for updating existing firmware currently operating on the first processor core while continuing to execute transactions. In some embodiments, references to the traffic manager, independent traffic manager, first processor core, second processor core, control manager, and controller are the traffic manager 113, independent traffic manager 115, first processor core 106, second processor core 108, and control manager 111 and controller 110, respectively. Figure 1 In some embodiments, process 400 may be modified by, for example, having steps rearranged, changed, added, and / or removed.

[0048] At step 402, the dynamic firmware update application migrates data from the second processor core to the first processor core. The existing firmware of the first processor core has been updated to the new firmware, and the first processor core is available for transaction execution. The data migration from the second processor core to the first processor core is a transfer of transaction execution responsibility to make the second processor core available for firmware update if necessary. The data migration may include unfinished transactions, instruction pointers, operating status, and connectivity status. The data can be used to configure the new firmware and traffic manager of the first processor core, where the first processor core can execute and continue to receive commands or instructions through the traffic manager, similar to before the firmware update.

[0049] The dynamic firmware update application pauses the second processor core at step 404. The second processor core has already handed over any other outstanding transactions to the first processor core, and thus the second processor core is paused to ensure that there is no further execution of transactions that may cause any conflicts or hazards between the first and second processor cores.

[0050] At step 406, the dynamic firmware update application migrates the traffic manager from the second processor core to the first processor core. The second processor core no longer processes transactions, and thus the independent traffic manager can be migrated from the second processor core to configure the traffic manager of the first processor core. Additionally, the migration includes disconnecting the independent traffic manager from the control manager of the controller.

[0051] At step 408, the dynamic firmware update application connects the traffic manager of the first processor core to the control manager of the controller. The dynamic firmware update application links the control manager to the traffic manager so that the control manager can send control signals to the traffic manager of the first processor core. Linking the traffic manager of the first processor core to the control manager includes configuring the traffic manager to output signals from the system output to an external device having a specific transport layer protocol (e.g., PCIe, Ethernet).

[0052] At step 410, the dynamic firmware update application deasserts the suspend process bit. The suspend process bit is a control signal bit used by the system to easily determine whether a processor core suspends its operation. In some embodiments, the suspend process bit exists for each processor core in the processor. The suspend process bit can be stored in a volatile memory in the form of a searchable data structure (e.g., a lookup table, an array, etc.).

[0053] Figure 5 A flow chart of a process 500 for updating existing firmware of a first processor core while continuing to execute transactions on a second processor core according to some embodiments of the present disclosure is shown. In some embodiments, process 500 may be modified by, for example, having steps rearranged, changed, added, and / or removed.

[0054] The dynamic firmware update application starts an independent traffic manager on the second processor core at step 502. The independent traffic manager is initialized on the second processor core and is available to process transactions when the existing firmware of the first processor core is updated to the new firmware.

[0055] At step 504, the dynamic firmware update application asserts the pause processing bit. The dynamic firmware update application sets and asserts the pause processing bit for the first processor core to indicate that the operation of the first processor core is paused. In an embodiment with more than two processor cores, the dynamic firmware update application sets the pause processing bit for each processor core except the second processor core.

[0056] The dynamic firmware update application halts all processor cores except the second processor core at step 506. The dynamic firmware update application may halt the processor cores in parallel with asserting a halt processing bit for each processor core except the second processor core.

[0057] At sub-process 300 , the dynamic firmware update application performs sub-process 300 , which migrates data from a first processor to a second processor.

[0058] At step 508, the dynamic firmware update application loads the new firmware to all processor cores except the second processor core. The dynamic firmware update application boots the new firmware on each processor core except the second processor core, while the second processor core continues to receive and execute transactions. When the new firmware is fully booted onto the processor cores, each newly updated processor core is available for processing, wherein the suspend processing bit of the processor core is asserted.

[0059] At sub-process 400, the dynamic firmware update application executes sub-process 400, which migrates data from the second processor core to the first processor core and resumes executing transactions on the first processor core.

[0060] Figure 6 A diagram illustrating a chronological data flow between first and second processor cores executing a program or routine simultaneously according to some embodiments of the present disclosure is shown. Each timeline 602, 604 is represented by a column following a vertical sequential order of each processor core, with a time variable indicator. The timeline indicates the relative parallelism between the execution stages of the first processor core and the second processor core. Additionally, Figure 6 Data migrations 606, 608 are shown between two processor cores, which are routines that need to meet timing constraints in order to avoid any write or read conflicts or hazards. For example, the second processor core cannot resume execution until the second processor core has received the first data migration 606. However, the first processor core can reset and load new firmware while the second processor core is executing transactions.

[0061] The terms "an embodiment", "embodiment", "embodiment(s)," "said embodiment", "said embodiment(s)," "one or more embodiments", "some embodiments" and "an embodiment" mean "one or more (but not all) embodiments" unless expressly specified otherwise.

[0062] The terms "including", "comprising", "having" and variations thereof mean "including but not limited to", unless expressly specified otherwise.

[0063] The enumerated listing of items does not imply that any or all of the items are mutually exclusive unless expressly specified otherwise.

[0064] The terms "a", "an" and "the" mean "one or more" unless expressly specified otherwise.

[0065] Devices that are in communication with each other need not be in continuous communication with each other unless expressly specified otherwise. In addition, devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0066] The description of the embodiment that several components communicate with each other does not mean that all such components are needed. On the contrary, various optional components are described to illustrate various possible embodiments. Further, although process steps, method steps, algorithms, etc. can be described in sequential order, such processes, methods and algorithms can be configured to work in alternating order. In other words, any order or order of the steps that may be described does not necessarily indicate the requirement to perform these steps in this order. The steps of the process described herein can be performed in any actual order. In addition, some steps can be performed simultaneously.

[0067] When a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they collaborate) may be used in place of a single device / article. Similarly, where more than one device or article is described herein (whether or not they collaborate), it will be readily apparent that a single device / article may be used in place of more than one device or article, or that a different number of devices / articles may be used in place of the number of devices or programs shown. The functionality and / or features of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such functionality / features. Therefore, other embodiments need not include the device itself.

[0068] At least the specific operations that may have been illustrated in the figure show specific events that occur in a specific order. In alternative embodiments, the specific operations can be performed, modified or removed in different orders. In addition, steps can be added to the above logic and still meet the described embodiments. Further, the operations described herein can occur in sequence, or the specific operations can be processed in parallel. Further, the operations can be performed by a single processing unit or by a distributed processing unit.

[0069] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. A method for updating existing firmware currently operating on a first processor core while continuing to execute transactions, the method comprising: receiving a request to update existing firmware to new firmware; loading the existing firmware onto the second processor core; migrating data associated with an operational state of existing firmware on the first processor core to the second processor core; causing the first processor core to stop executing transactions; causing the second processor core to use the existing firmware to execute transactions instead of the first processor core; Restart the first processor core; replacing existing firmware on the first processor core with new firmware; migrating data associated with an operational state of existing firmware on the second processor core to the first processor core; causing the second processor core to stop executing transactions; and The first processor core is caused to execute transactions using the new firmware.

2. The method of claim 1, wherein the first processor core and the second processor core are coupled to a Peripheral Component Interconnect Express (PCIe) interface.

3. The method of claim 1, wherein the first processor core and the second processor core are coupled to an Ethernet interface. The method of claim 1 , further comprising determining that a second processor core is available.

5. The method of claim 1 , wherein migrating data associated with the operating state of the existing firmware on the first processor core to the second processor core further comprises loading the data associated with the operating state of the existing firmware on the first processor core onto an available memory area associated with the second processor core.

6. The method of claim 1 , wherein the data associated with the operating state of the existing firmware on the first processor core and the data associated with the operating state of the new firmware on the second processor core respectively comprise: Multiple unfinished transactions; The status of the corresponding firmware; and Input / output connectivity status of the corresponding firmware.

7. The method of claim 1, wherein the restarting occurs after the second processor core begins executing transactions and before replacing existing firmware on the first processor core.

8. A system comprising: a first processor core; Second processor core; A control circuit, wherein the first processor core, the second processor core and the control circuit are communicatively coupled, and the control circuit is configured to: receiving a request to update existing firmware to new firmware; loading the existing firmware onto the second processor core; migrating data associated with an operational state of existing firmware on the first processor core to the second processor core; causing the first processor core to stop executing transactions; causing the second processor core to use the existing firmware to execute transactions instead of the first processor core; Restart the first processor core; replacing existing firmware on the first processor core with new firmware; migrating data associated with an operational state of existing firmware on the second processor core to the first processor core; causing the second processor core to stop executing transactions; and The first processor core is caused to execute transactions using the new firmware.

9. The system of claim 8, wherein the first processor core and the second processor core are coupled to a peripheral component interconnect express (PCIe) interface.

10. The system of claim 8, wherein the first processor core and the second processor core are coupled to an Ethernet interface.

11. The system of claim 8, wherein the control circuit is further configured to determine that a second processor core is available.

12. The system of claim 8, wherein the control circuit is to load data associated with an operating state of existing firmware on a first processor core onto an available memory area associated with a second processor core.

13. The system of claim 8, wherein the data associated with the operating state of the existing firmware on the first processor core and the data associated with the operating state of the new firmware on the second processor core respectively include: Multiple unfinished transactions; The status of the corresponding firmware; and Input / output connectivity status of the corresponding firmware.

14. The system of claim 8, wherein the control circuit is to restart the first processor core after the second processor core begins executing transactions and before replacing existing firmware on the first processor core.

15. A solid state drive (SSD) device, comprising: A processor, wherein the processor comprises: a first processor core; and Second processor core; a controller, wherein the controller is communicatively coupled to the processor, the controller being configured to: receiving a request to update existing firmware to new firmware; loading the existing firmware onto the second processor core; migrating data associated with an operational state of existing firmware on the first processor core to the second processor core; causing the first processor core to stop executing transactions; causing the second processor core to use the existing firmware to execute transactions instead of the first processor core; Restart the first processor core; replacing existing firmware on the first processor core with new firmware; migrating data associated with an operational state of existing firmware on the second processor core to the first processor core; causing the second processor core to stop executing transactions; and The first processor core is caused to execute transactions using the new firmware.

16. The SSD device of claim 15, wherein the first processor core and the second processor core are coupled to a Peripheral Component Interconnect Express (PCIe) interface.

17. The SSD device of claim 15, wherein the first processor core and the second processor core are coupled to an Ethernet interface.

18. The SSD device of claim 15, wherein the controller is further configured to determine that a second processor core is available.

19. The SSD device of claim 15, wherein the controller is configured to load data associated with an operating state of existing firmware on the first processor core onto an available memory area associated with the second processor core.

20. The SSD device of claim 15, wherein the data associated with the operating state of the existing firmware on the first processor core and the data associated with the operating state of the new firmware on the second processor core respectively include: Multiple unfinished transactions; The status of the corresponding firmware; and Input / output connectivity status of the corresponding firmware.

21. The SSD device of claim 15, wherein the controller is to restart the first processor core after the second processor core begins executing transactions and before replacing existing firmware on the first processor core.

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