Extended impedance matching broadband LNA architecture

Abstract

A circuit and method for an amplifier, in particular an LNA, that achieves broadband output impedance matching and high gain while simultaneously suppressing out-of-band (OOB) harmonic frequencies. Some embodiments allow for multiple modes of operation to allow for selection of gain and linearity characteristics. One aspect of the invention is to improve the linearity and sensitivity of the entire RF "front end" (RFFE) receiver chain by suppressing OOB gain within LNA components at higher order harmonic frequencies. Another aspect of the invention is a new broadband and ultra-wideband LNA load circuit that maintains in-band high gain and broadband output impedance matching while achieving high frequency OOB suppression. Another aspect of the invention is a new ultra-wideband LNA output impedance matching circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 855,386, filed on June 30, 2022, the contents of which are incorporated herein by reference in their entirety. background (1) Technical field

[0004] The present invention relates to electronic circuits and, more particularly, to radio frequency amplifier circuits. (2) Background technology

[0005] Many modern electronic systems include radio frequency (RF) receivers; examples include cellular phones, personal computers, tablet computers, wireless network components, televisions, cable system "set-top" boxes, and radar systems. Many RF receivers are paired with RF transmitters in the form of transceivers, which are typically fairly complex two-way radios. In some cases, RF transceivers are capable of transmitting and receiving across multiple frequencies in multiple frequency bands.

[0006] Amplifiers are common components in RF transmitters, receivers, and transceivers, and are often used for power amplification of transmitted RF signals and low-noise amplification of received RF signals. For many RF systems, especially those that require low power and / or portability (e.g., cellular phones, WiFi-connected computers, cameras, and other devices), it has become common to use complementary metal oxide semiconductor (CMOS) manufacturing technology to create low-cost, low-power integrated circuits (ICs). CMOS devices include bulk CMOS, silicon-on-insulator (SOI) CMOS, and silicon-on-sapphire (SOS) CMOS (SOS is a type of SOI manufacturing technology).

[0007] FIG1 is a simplified schematic diagram of a general implementation of a prior art low noise amplifier (LNA) circuit 100. In the example shown, the LNA circuit 100 includes an amplifier block 102 that includes two series-connected FETs M in a cascode arrangement. CS , M CG stack. Apply to the RF input terminal RF IN The RF input signal can pass through the input impedance matching circuit 104 and couple to the common source FET M CS The gate of the lower FET M CS The source is usually connected through a damping inductor L DEG Connect to a reference potential, for example, circuit ground.

[0008] Common gate upper FET M CG The source of the lower FET M CSThe drain of the upper FET M CG The drain of the RF output terminal RF passes through the DC blocking capacitor C OUT Provides an amplified RF output signal. Capacitor C can also help provide output impedance matching. Inductor L is connected between the source voltage V DD With the upper FET M CG to help provide impedance matching and provide bias feed to amplifier block 102. In the example shown, the RF output terminal RF OUT is shown coupled to a typical load, which is represented by a resistor R L For many modern RF circuits, R L The value is usually 50 ohms.

[0009] The bias circuit 106 is configured to bias the common gate upper FET M in a known manner. CG Provide a suitable bias voltage CG_V BIAS , and to the common source FET M CS Provide a suitable bias voltage CS_V BIAS Additional well-known circuit elements that may be included in some applications, such as bypass capacitors, have been omitted for clarity.

[0010] Important desired characteristics of LNAs are high gain with low noise, wide bandwidth, good linearity, and good output impedance matching. Therefore, the four important design parameters of LNAs are gain, noise figure (NF), input referred third intercept point (IIP3), and output reflection coefficient. NF is a measure of the degradation of the signal-to-noise ratio (SNR) caused by components in the signal chain, where lower values ​​indicate better performance. IIP3 is a figure of merit that represents the linearity of the amplifier, where higher values ​​indicate better performance. Typically, NF has a tighter specification requirement in high gain mode than in low gain mode, while IIP3 has a tighter specification requirement in low gain mode than in high gain mode. The output reflection coefficient is S 22 Scattering parameters (or "S parameters"), and are an indication of output impedance matching, where lower (more negative when evaluated logarithmically) numbers indicate better impedance matching.

[0011] The increase in the frequency of RF communication bands and channels and the continued increase in the number of bands and channels in use have pushed current LNA architectures to their limits. For example, for some new 5G mobile network bands, particularly in the 3 GHz to 6 GHz NR band, the upcoming 7 GHz to 24 GHz band, and the millimeter wave range (e.g., 24.25 GHz to 52.6 GHz), it is impossible to achieve the stringent requirements for gain, percentage bandwidth, linearity, and output impedance matching using conventional LNA architectures.

[0012] For example, in the LNA architecture shown in FIG1 , output impedance matching is performed by a single-stage LC output impedance matching circuit including L and C. However, this single-stage LC architecture has a tradeoff limitation, which depends on the choice of the values ​​of L and C: narrow-band output impedance matching at high gain, or wider-band output impedance matching at lower gain (e.g., by reducing the Q factor of the LC architecture). Another limitation of the architecture shown is that, since the L and C components form a high-pass filter, it has essentially no high frequency out-of-band (OOB) rejection.

[0013] One way to overcome some of the above limitations of the circuit shown in FIG. 1 is to add a low-pass LC filter to achieve broadband matching and some high frequency OOB suppression. For example, FIG. 2 is a simplified schematic diagram of a general implementation of a prior art LNA circuit 200 having a two-stage LC output impedance matching circuit 202. Similar in most respects to the LNA circuit 100 of FIG. 1, the LNA circuit 200 of FIG. 2 includes a two-stage LC output impedance matching circuit 202 that adds a coupling at the RF OUT The second inductor L' between the terminal and the first capacitor C and the V DD and a second capacitor C' between the nodes between C and L'. The added LC element comprises a low pass filter. Although having a wider band output impedance matching characteristic compared to the LNA circuit 100 of FIG. 1 , the resulting LNA circuit 200 still cannot achieve the high gain required for the 5G mobile network band and other high frequency applications. In addition, the added circuitry of the two-stage LC output impedance matching circuit 202 can compromise linearity due to power loss in the low pass LC filter. To achieve the same gain compared to the single-stage LC output impedance matching, the common gate FET M CG The voltage swing at the drain of the transistor must be large to compensate for the losses in the two-stage LC output impedance matching, which degrades linearity.

[0014] Another possible architecture is to use IN A bandpass filter is inserted between the source of the signal (eg, antenna) and the LNA input to limit the OOB frequency, but this reduces the gain and noise figure, thereby reducing the sensitivity of the receiver.

[0015] Therefore, there is a need for an LNA architecture that overcomes these limitations of conventional LNA architectures. Summary of the invention

[0016] The present invention includes circuits and methods for LNAs that achieve broadband output impedance matching and high gain while simultaneously suppressing OOB harmonic frequencies. Some embodiments allow multiple operating modes to allow selection of gain and linearity characteristics. The circuits and methods of the present invention can also be applied to other types of amplifiers, such as power amplifiers.

[0017] One aspect of the present invention is to improve the linearity and sensitivity of the entire RF "front end" (RFFE) receiver chain by suppressing out-of-band gain within LNA components at higher order harmonic frequencies (e.g., second, third, and higher order harmonic frequencies) that would otherwise be down converted by post-LNA circuitry and degrade receiver performance.

[0018] Another aspect of the present invention is a novel wideband and ultra-wideband LNA load circuit that achieves high frequency OOB suppression while maintaining high in-band gain and wideband output impedance matching.

[0019] Yet another aspect of the present invention is a novel ultra-wideband LNA output impedance matching circuit.

[0020] Some embodiments include a load circuit configured to be coupled between an RF amplifier core and an output terminal, the load circuit comprising: a first LC resonator coupled between the RF amplifier core and a node, the first LC resonator comprising a first inductor and a first capacitor coupled in parallel; a matching and biasing circuit coupled to the node and configured to be coupled to a power supply, the matching and biasing circuit comprising a second inductor and a second capacitor coupled in parallel; and a second LC resonator coupled between the node and the output terminal, the second LC resonator comprising a capacitor coupled to the output terminal, and a third inductor and a third capacitor coupled in parallel to each other and in series with the capacitor.

[0021] Some embodiments include a load circuit configured to be coupled between an RF amplifier core and an output terminal, the load circuit comprising: a first inductor coupled between the RF amplifier core and a node; a first resistor coupled in parallel with the first inductor between the RF amplifier core and the node; a second inductor coupled to the node and configured to be coupled to a power supply; a second resistor coupled in parallel with the second inductor and coupled to the node and configured to be coupled to the power supply; and a capacitor coupled between the node and the output terminal.

[0022] Some embodiments include a load circuit configured to be coupled between an RF amplifier core and an output terminal, the load circuit comprising: a first inductor coupled between the RF amplifier core and a node; a second inductor coupled to the node and configured to be coupled to a power supply; a capacitor coupled between the node and the output terminal; and a feedback circuit coupled between an input terminal and a feedback node in an output signal path of the amplifier core and capable of being selectively switched between enabled and disabled, wherein the feedback circuit comprises a capacitor, a resistor, and a switch coupled in series.

[0023] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG. 1 is a simplified schematic diagram of a general implementation of a prior art low noise amplifier (LNA) circuit.

[0025] 2 is a simplified schematic diagram of a general implementation of a prior art LNA circuit having a two-stage LC output impedance matching circuit.

[0026] Figure 3A is a simplified schematic diagram of a first embodiment of a wideband LNA circuit according to the present invention.

[0027] Figure 3B It is shown Figure 3A A graph of one example of LNA gain / loss as a function of frequency is shown for a modeled implementation of an LNA circuit.

[0028] Figure 3C Yes Figure 3A A graph comparing LNA gain / loss as a function of frequency for a modeled implementation of an LNA circuit and a modeled conventional wideband LNA is shown.

[0029] Figure 4 is a simplified schematic diagram of a second embodiment of a wideband LNA circuit according to the present invention.

[0030] Figure 5A is a simplified schematic diagram of an LNA circuit with broadband output impedance matching.

[0031] Figure 5B Yes Figure 5A FIG. 1 is a diagram of an equivalent circuit in which the LNA circuit is approximately modeled.

[0032] Figure 6 is a simplified schematic diagram of a first embodiment of an ultra-wideband LNA circuit with enhanced output impedance matching according to the present invention.

[0033] Figure 7 is a simplified schematic diagram of a second embodiment of an ultra-wideband LNA circuit with enhanced output impedance matching according to the present invention.

[0034] Fig. 8A is a simplified schematic diagram of a first combined embodiment of an ultra-wideband LNA circuit with enhanced output impedance matching according to the present invention.

[0035] Figure 8Bis a simplified schematic diagram of a second combined embodiment of an ultra-wideband LNA circuit with enhanced output impedance matching according to the present invention.

[0036] Fig. 9 is a schematic diagram of the enhanced input impedance matching circuit.

[0037] Fig.10 is a top plan view of a substrate which may be, for example, a printed circuit board or a chip module substrate (eg, a thin film tile).

[0038] 11 illustrates an exemplary prior art wireless communication environment that includes different wireless communication systems and may include one or more mobile wireless devices.

[0039] Fig.12 is a block diagram of a transceiver that may be used in a wireless device, such as a cellular telephone, and that may beneficially incorporate embodiments of the present invention to improve performance.

[0040] Fig.13 is a process flow diagram illustrating a method of achieving broadband output impedance matching and high gain for a radio frequency amplifier having an amplifier core and output terminals.

[0041] Unless context requires otherwise, like reference numbers and names in the various drawings indicate like elements. DETAILED DESCRIPTION

[0042] The present invention includes circuits and methods for LNAs that achieve broadband output impedance matching and high gain while simultaneously suppressing OOB harmonic frequencies. Some embodiments allow multiple operating modes to allow selection of gain and linearity characteristics. The circuits and methods of the present invention can also be applied to other types of amplifiers, such as power amplifiers.

[0043] General Concepts

[0044] One aspect of the present invention is to improve the linearity and sensitivity of the entire RF "front end" (RFFE) receiver chain by suppressing out-of-band gain within LNA components at higher order harmonic frequencies (e.g., second, third, and higher order harmonic frequencies) that would otherwise be down converted by post-LNA circuitry and degrade receiver performance.

[0045] Another aspect of the present invention is a novel wideband and ultra-wideband LNA load circuit that achieves high frequency OOB suppression while maintaining high in-band gain and wideband output impedance matching.

[0046] Yet another aspect of the present invention is a novel ultra-wideband LNA output impedance matching circuit.

[0047] For the purposes of this disclosure, “narrowband”, “wideband” and “ultra-wideband” may be characterized as being equal to (stop frequency f STOP Subtract the starting frequency f START ) divided by the center frequency f of the band CENTER or (f STOP -f START ) / f CENTER (expressed as a percentage) is the percentage fractional bandwidth, where f CENTER =(f STOP +f START ) / 2. Table 1 below shows typical guidelines (not a strict definition) for characterizing typical percentage bandwidths.

[0048] Nominal frequency band name %Bandwidth Range Narrowband <7.5％ Extended Narrowband 7.5％～15％ broadband 15％～25％ Ultra Wideband >25％

[0049] Table 1

[0050] Table 2 below provides examples of common cellular telephone frequency bands and characterizes them as either wideband or ultra-wideband using the guidelines in Table 1.

[0051] Typical Applications <![CDATA[f START (GHz)]]> <![CDATA[f STOP (GHz)]]> <![CDATA[f CENTER (GHz)]]> %bandwidth Broadband (N77) 3.3 4.2 3.75 24.00％ Broadband (N96) 5.925 7.125 6.525 18.39％ Ultra-Wideband (UWB) 6.2 9 7.6 36.84％

[0052] Table 2

[0053] First embodiment

[0054] Figure 3A 1 is a simplified schematic diagram of a first embodiment of a broadband LNA circuit 300 according to the present invention. The circuitry below the dividing line 302 may be substantially the same as the corresponding circuitry in FIGS. 1 and 2 . Thus, the LNA circuit 300 includes an amplifying core 102 including a common-source FET M in a common-source configuration. CS and common gate FET M CG . Common source FET M CS The gate of the FET M can be regarded as the input terminal INT of the amplification core 102, and the common source FET M CS The source of can be regarded as the attenuation terminal DT of the amplifying core 102, and the common gate FET M CG The drain of can be regarded as the amplified signal terminal AST of the amplifying core 102. Also included below the dividing line 302 are the input impedance matching circuit 104, the bias circuit 106, and the attenuation inductor L coupled to the reference potential. DEG .

[0055] although Figure 3AThe amplifier core 102 is shown as having only a pair of FET devices coupled in series, but may also include additional FET devices. For example, in some embodiments, to overcome the relatively low breakdown voltage of each CMOS FET, multiple common-gate FETs may be coupled in series with the bottom common-gate FET M. CG In other words, the amplifying core 102 may have a plurality of common-gate FETs coupled in series in a common-source common-gate configuration. An example of such a configuration is described below. Figure 4 Shown in.

[0056] Above the dividing line 302 is an improved load circuit, which includes a first LC resonator 304 coupled between the amplified signal terminal AST of the amplifying core 102 and the node X, a first LC resonator 304 coupled to the power supply V DD and a matching and biasing circuit 306 between node X and RF OUT The second LC resonator 308 is located between the RF output terminals. In the example shown, the RF output terminals RF OUT is shown coupled to a typical load, which is represented by a resistor R L .

[0057] The first LC resonator 304 includes an inductor L1 and a capacitor C1 coupled in parallel and between the node X and the amplified signal terminal AST. The matching and biasing circuit 306 includes an inductor L1 and a capacitor C1 coupled in parallel and between the node X and the amplified signal terminal AST. DD and a DC blocking capacitor C2 connected between the node X and the inductor L2. The second LC resonator 308 includes a DC blocking capacitor C2 connected between the node X and the inductor L2 and the capacitor C2. BLK between the inductor L3 and capacitor C3, the DC blocking capacitor C BLK Coupled to RF OUT In an alternative embodiment, C BLK may be located between node X and the second LC resonator 308. Note that capacitor C is a DC blocking capacitor. BLK It is not necessary for the broadband performance supported by the present invention. Instead, capacitor C is usually required. BLK or equivalent because L1 and L3 would otherwise form a direct current from amplifier block 102 to RF OUT However, in some embodiments, if the resistor R L The DC loss in the OUT If the circuit connected at the BLK .

[0058] In an integrated circuit implementation, C1 , C2 , and C3 may be implemented in part as parasitic capacitors of their respective on-chip inductors L1 , L2 , and L3 due to the finite self-resonant frequency (SRF) of the inductors.

[0059] It is worth noting that C2 and L3 form a low-loss low-pass filter (LPF), while L1 and C1 in the first LC resonator 304 and L3 and C3 in the second LC resonator 308 respectively function as low-loss band-stop filters.

[0060] At the frequency of interest (e.g., fo = 3.75 GHz), the combination of L1, L2, C2, and L3 forms a second-order output impedance matching circuit that achieves a wider bandwidth than the circuits of Figures 1 and 2. This topology also shows higher gain due to the series peaking effect of inductors L1 and L3, which increases the load impedance presented at the AST node.

[0061] The improved load circuit achieves high OOB suppression of at least the second to fifth harmonic frequencies (2fo, 3fo, 4fo, and 5fo) as follows:

[0062] In the first LC resonator 304, L1 and C1 create a very high impedance (close to an “open” circuit) in the signal path to achieve OOB suppression at ~2fo;

[0063] The LPF formed by C2 and L3 improves OOB suppression at 3fo and 4fo; and

[0064] • In the second LC resonator 308, L3 and C3 improve the OOB suppression at ~5fo.

[0065] Figure 3B It is shown Figure 3A An example of a graph 350 of LNA gain / loss as a function of frequency for a modeled implementation of an LNA circuit is shown. The modeled circuit uses the inductor and capacitor values ​​shown in Table 3 below, and a value for fo of approximately 3.75 GHz.

[0066]

[0067] Table 3

[0068] Referring to line 352, the combination of L1, L2, C2 and L3 impedances causes the LNA to output RF OUT With load R L(e.g., 50 ohms) and provide high gain at the frequency of interest, fo. L1 and C1 resonate at about 2fo, thus suppressing the OOB harmonic frequencies; the position of the corresponding dip can be adjusted by changing the value of C1. C2 and L3 improve OOB suppression at 3fo and 4fo; C2 will specifically affect the OOB gain at 3fo and 4fo (larger C2 gives greater gain, but larger C2 values ​​may reduce in-band gain flatness). L3 and C3 resonate at about 5fo, thus suppressing the OOB harmonic frequencies.

[0069] Figure 3C Yes Figure 3A A graph 360 is shown comparing the LNA gain / loss of a modeled implementation of the LNA circuit to a modeled conventional wideband LNA as a function of frequency. Graph 362 shows Figure 3A 1, while plot 364 shows the gain / loss of a modeled conventional wideband LNA (e.g., LNA circuit 100 of FIG. 1) (note that the gain / loss used to generate Figure 3C The LC component values ​​differ from those used to generate Figure 3B LC component values, so the harmonic frequencies appear at different points). As the comparison shows, Figure 3A The modeled implementation of the LNA circuit shown exhibits better suppression of OOB harmonic frequencies while achieving broadband high gain at fo.

[0070] Second embodiment

[0071] Figure 4 is a simplified schematic diagram of a second embodiment of a wideband LNA circuit 400 according to the present invention. The illustrated embodiment shows the addition of multiple switches and other components that provide flexibility in programmatically adapting the LNA circuit 400 for operation in multiple different modes that allow tradeoffs between gain, bandwidth, and linearity.

[0072] The LNA circuit 400 includes an amplifying core 402 including a common-source FET M in a cascode configuration. CS and common gate FET M CG Therefore, the common source FET M CS The gate of the amplifying core 402 can be regarded as the input terminal INT, and the common source FET M CS The source of can be regarded as the attenuation terminal DT of the amplifying core 402, and the common gate FET M CG The drain of the amplified core 402 may be considered as the amplified signal terminal AST of the amplified core 402. In some embodiments, in order to overcome the relatively low breakdown voltage of each CMOS FET, multiple common-gate FETs may be coupled in series at the bottom common-gate FET M.CG In other words, the amplifying core 402 may have a plurality of common-gate FETs coupled in series in a common-source common-gate configuration. Then, the amplifying signal terminal AST will be the drain of the uppermost common-gate FET in the amplifying core 402.

[0073] The attenuation terminal DT is typically coupled to a reference potential, such as circuit ground, through the attenuation circuit 406. In some embodiments, the attenuation circuit 406 may include an adjustable attenuation inductor L DEG , for example, a multi-port integrated circuit inductor coil. Adjustable damping inductor L DEG Can be used to improve linearity in low gain mode. For example, the damping inductor L can be used in higher gain mode DEG The smaller value of the damping inductor L can be used in lower gain modes. DEG Some embodiments of the attenuation circuit 406 may include a attenuation inductor L DEG Parallel coupled bypass switch Sw BP .

[0074] Apply to the RF input terminal RF IN The RF input signal can pass through the input impedance matching circuit 104 and be coupled to the common source FET M CS As described above, the bias circuit 106 is configured to bias the common-gate FET M CG Provide a suitable bias voltage CG_V BIAS , and to the common source FET M CS Provide a suitable bias voltage CS_V BIAS .

[0075] Some embodiments may include an input matching feedback circuit 408. The feedback circuit 408 is shown as being coupled between the input terminal INT and the amplified signal terminal AST. More generally, the input matching feedback circuit 408 may be coupled to a feedback node in the output signal path of the amplifying core 402, which may be the drain of any FET in the amplifying core 402. For example, the feedback node for connection to the input matching feedback circuit 408 may be selected based on different desired feedback strengths and different desired input impedances.

[0076] The input matching feedback circuit 408 in the illustrated embodiment includes a DC blocking capacitor C0 coupled in series with a switch Sw0, which is then coupled in series to a resistor R0. In some embodiments, as shown, C0 and / or R0 are adjustable or have fixed values. In an alternative embodiment, the input matching feedback circuit 408 may include one or more parallel switches Sw01...Sw0n (Generally, Sw0 x ), the one or more parallel switches are coupled in series to corresponding parallel resistors R01 . . . R0 n (Generally, R0 x ). In the case of n parallel switch / resistor branches, resistor R0 x The tunability is equal to 2 n (Total number of switch combinations). Note that resistor R0 x The values ​​of do not need to be the same. This can be achieved by disconnecting all feedback switches Sw0 x to disable the input matching feedback circuit 408.

[0077] In an alternative embodiment, capacitor C0, one or more switches Sw0 x A collection of one or more resistors R0 x The set of switches Sw0 can be connected in any series order. In alternative embodiments, a single switch Sw0 can be used in combination with an adjustable or fixed resistor R0. In other embodiments, switch Sw0 can be omitted, thereby permanently coupling one or more resistors R0 between the input terminal INT and the feedback node in the output signal path of the amplification core 402. x A collection of .

[0078] In various gain modes, there are one or more resistors R0 in the circuit x The Q factor, which allows input impedance matching, is reduced, which increases the bandwidth of the enhanced LNA circuit 400 at the expense of gain and NF.

[0079] An advantage of using a variable or multi-state input matching feedback circuit 408 is that multiple resistor values ​​enable multiple gain modes. For example, an LNA in a mobile RF receiver device may require multiple gain modes depending on the range of input signal strengths at the receiver. In addition, by using a variable or multi-state feedback resistor R0 x Implementing multiple gain modes can eliminate the need for output attenuators (common in conventional receiver LNAs).

[0080] More information about the input matching feedback circuit 408 can be found in U.S. patent application Ser. No. 17 / 337,227, filed on June 2, 2021, and entitled “Wideband Multi Gain LNA Architecture,” which has been assigned to the assignee of the present invention and is incorporated herein by reference.

[0081] The LNA circuit 400 includes a modified improved load circuit, which includes a modified first LC resonator 414 coupled between the amplified signal terminal AST of the amplifying core 402 and the node X, a power supply V coupled to the power supply V DD and a modified matching and biasing circuit 416 between node X and RF OUT The modified second LC resonator 418 between the output terminals. In the example shown, the RF output terminals RF OUT is shown coupled to a typical load, which is represented by a resistor R L .

[0082] The modified first LC resonator 414 includes an inductor L1, a capacitor C1, and an additional switch Sw1 coupled in parallel and between the node X and the amplified signal terminal AST. As shown, either or both of L1 and C1 may be adjustable components, or have fixed values. For example, switch Sw1 allows L1 and C1 to be bypassed under program control or when setting performance characteristics of the LNA circuit 400 (e.g., at the time of manufacture or when included in a larger circuit or system).

[0083] The modified matching and biasing circuit 416 includes a circuit coupled to V DD and the inductor L2 between the node X. The capacitor C2 is optionally coupled to V by a switch Sw2a. DD and node X (and therefore in parallel with L2). Resistor R2 is optionally coupled to V DD and node X (and therefore in parallel with L2). As shown, any of L2, C2, and / or R2 may be adjustable components, or have fixed values. Switches Sw2a, Sw2b allow C2 and / or R2 to be configured to be selectively enabled or in circuit (i.e., the switches are closed), or selectively disabled or out of circuit (i.e., the switches are open). For example, the state of switches Sw2a, Sw2b may be set under program control or when setting performance characteristics of the LNA circuit 400. When switch Sw2b is set to place R2 in circuit, or when switch Sw2b is omitted (and therefore R2 is permanently in circuit), then R2 "de-Qs" (i.e., reduces the Q factor of inductor L2) inductor L2, thereby reducing gain but increasing bandwidth. Variable gain reduction is achieved for the tunability of resistor R2, where a smaller resistance provides a wider bandwidth by further "de-Qing" inductor L2. The tunability of capacitor C2 enables better output impedance matching in low gain mode.

[0084] The modified second LC resonator 418 includes a DC blocking capacitor C coupled in parallel and connected at node X. BLKThe inductor L3, capacitor C3 and switch Sw3 between the DC blocking capacitor C BLK Coupled to RF OUT As shown, either L3 or C3 may be an adjustable component, or have a fixed value. For example, switch Sw3 allows L3 and C3 to be bypassed under program control or when setting performance characteristics of LNA circuit 400.

[0085] As described above, C2 and L3 form a low-loss low-pass filter (LPF), while L1 and C1 in the modified first LC resonator 414 and L3 and C3 in the modified second LC resonator 418 respectively function as low-loss band-stop filters. In an integrated circuit implementation, C1, C2, and C3 may be partially implemented as parasitic capacitors of their respective on-chip inductors L1, L2, L3 due to the finite self-resonant frequency (SRF) of the inductors.

[0086] Figure 4 The architecture shown by way of example in FIG. 1 provides programmability, including switching between various modes of component configurations and component values ​​to trade off gain, bandwidth, and linearity while providing broadband output matching and high OOB suppression. For example, in a low gain mode, L1 and C1 are bypassed by closing switch Sw1, and R2 is connected in parallel with L2 and C2 in the circuit by closing switch Sw2b, resulting in a reduction in gain and de-Qing the output network to extend bandwidth. Since the losses in the load circuit in which L1 and C1 are bypassed are smaller, to achieve the same gain, the common gate upper FET M CG The voltage swing at the drain of will be smaller, which results in better linearity. As described above, broadband output impedance matching is achieved by the LC network formed by C2 and L3, which acts as a low-pass filter to achieve OOB suppression even in the low-gain mode of the example. In the low-gain mode of the example, C2 is tunable to achieve better output matching.

[0087] In a high gain mode, switch Sw1 is open, placing L1 and C1 in the circuit, and R2 is disconnected by opening switch Sw2b, resulting in an increase in gain and no de-Q of the output network, but a slight reduction in bandwidth.

[0088] The switch Sw0, Sw1, Sw2a, Sw2b, Sw3 and Sw4 can be selectively opened and closed as needed. BPOther operation modes are realized, so as to achieve a trade-off among gain, bandwidth and linearity by invoking different gain modes. Some or all of the inductors L1, L2, L3, capacitors C0, C1, C2, C3 and / or resistors R0, R2 are made adjustable, in particular dynamically adjustable such as by programming control, and further a trade-off among gain, bandwidth and linearity is achieved by invoking different gain modes.

[0089] Ultra-wideband output impedance matching enhancement

[0090] In applications using a standalone RFFE configured to connect to other circuits (e.g., an antenna-located receiver LNA), the LNA should have a good output impedance match to such other circuits within the operating frequency, typically 50 ohms for many modern RF circuits. In ultra-wideband applications, achieving this design goal at high gain is challenging.

[0091] For a single-stage LNA, wideband output impedance matching can be achieved by the LNA architecture described above and by an LNA architecture as described in U.S. Patent Application No. 17 / 337,227 cited above. To achieve an even wider output impedance match for an ultra-wideband LNA, the Q of the output matching impedance network can be reduced by de-Qing the inductor of the output network, which results in lower gain but better output impedance matching. One aspect of the present invention is a new LNA architecture that implements a new de-Q technique that reduces the Q of the output impedance matching network while achieving a better gain and bandwidth tradeoff to achieve the desired performance for ultra-wideband applications.

[0092] A review of the basic wideband LNA architecture may help better understand the design challenges of achieving good output impedance matching. Figure 5A FIG. 5 is a simplified schematic diagram of an LNA circuit 500 with broadband output impedance matching. The circuit below the dividing line 502 may be substantially the same as the corresponding circuit system in FIG. 1 and FIG. 2 . The common gate upper FET M of the amplifier core 102 CG The impedance Z at the drain DRAIN Indicated by dotted lines. Inductors L1 and L2 and DC blocking capacitor C BLK As shown coupled to a load resistor R L A bypass switch Sw1 coupled in parallel with L1 allows L1 to be bypassed (out of circuit) or connected (in circuit). Placing inductor L1 in circuit (ie, setting Sw1 to an open state) extends the bandwidth of the output impedance matching network.

[0093] Figure 5B Yes Figure 5A A diagram of an equivalent circuit 550 that approximates the LNA circuit 500 is shown. Figure 5A The circuit including the input impedance matching network 104 and the amplifier block 102 can be approximated as a current source I S With resistor R D and capacitor C D FET M on the common gate of the amplifier core 102 CG The impedance Z DRAIN indicated by the dotted line; that is, the resistor R D and capacitor C D Shown and observed FET M CG The drain impedance is the same as the output impedance. C D , L1, L2 and C BLK The combination of forms a second-order output impedance matching network for broadband matching. (Although the inductor L2 is Figure 5A is shown as coupled to V DD , but can be modeled as coupled to circuit ground at the operating frequency, e.g. Figure 5B shown.)

[0094] Transformation of output impedance matching network Q and R D / R L The higher the transformation Q, the lower the impedance matching bandwidth. Once R D and R L Fixed by Figure 5A The impedance matching bandwidth achievable with the architecture shown is limited.

[0095] For ultra-wideband LNAs requiring even wider output matches, the present invention includes two architectures that can be used alone or in combination.

[0096] Figure 6 is a simplified schematic diagram of a first embodiment of an ultra-wideband LNA circuit 600 with enhanced output impedance matching according to the present invention. Figure 5A The circuit shown is similar in some respects, but the added elements include resistor R1 coupled in parallel with inductor L1, and resistor R2 coupled in parallel with inductor L2. As shown, resistors R1 and R2 may have fixed values, but may be adjustable. The values ​​of R1 and R2 may be set under program control or when setting performance characteristics of LNA circuit 600 (e.g., at the time of manufacture or when included in a larger circuit or system).

[0097] Resistors R1 and R2 act as de-Q resistors to selectively lower the Q of the output impedance matching network, thereby achieving wider bandwidth, with the tradeoff being lower gain.

[0098] In an alternative architecture, a resistor can be added in parallel to the equivalent resistance R DTo reduce the conversion Q of the output impedance matching network, rather than Figure 6 The Q of the output impedance matching network is reduced as in the circuit of . For example, Figure 7 is a simplified schematic diagram of a second embodiment of an ultra-wideband LNA circuit 700 with enhanced output impedance matching according to the present invention. Figure 5A The circuit shown is somewhat similar, but the added components include coupling between the amplified signal terminal AST and the common gate FET M CG The output matching feedback circuit 702 between the gates of the switches SW and SW is shown in the embodiment shown. FB The capacitor C FB , the switch Sw FB It is also coupled in series to the resistor R FB In some embodiments, as shown, C FB and / or R FB Can have a fixed value, or can be adjustable. In an alternative embodiment, capacitor C FB , Switch FB and resistor R FB Can be connected in any series order.

[0099] Switching R in or out of the circuit FB Two operation modes are provided, a first mode having a wider output impedance matching bandwidth, and a second mode having a narrower output impedance matching bandwidth but having a higher gain than the first mode.

[0100] When the switch FB When closed, R FB The amplified signal terminal AST is coupled to the common gate FET M CG gate, effectively placing R FB R in the equivalent circuit D in parallel (this assumes that there is eventually CG_V through the bias circuit 106 BIAS line to circuit ground). R FB The presence of in the circuit reduces the Z DRAIN , and reduces the transformed Q of the output impedance matching network, where Q is approximately equal to Z DRAIN The real part of L , or Re(Z DRAIN ) / R L Therefore, the conversion Q is reduced, thereby extending the impedance matching bandwidth of the LNA circuit 700. Compared with other known circuits, this architecture shows a better gain and bandwidth trade-off in various applications.

[0101] On the contrary, when the switch Sw FB When disconnected, RFB Relative to R in the equivalent circuit D It is out of the circuit and the conversion Q of the output impedance matching network is not reduced.

[0102] Notice, Figure 7 An integrated circuit implementation of the circuit shown is compared to Figure 6 An integrated circuit implementation of the circuit shown has the advantages of including R FB The output matching feedback circuit 702 results in much less physical wiring relative to the inductors L1 and L2, resulting in less parasitic inductance and capacitance that may limit bandwidth.

[0103] Combination of implementation modes

[0104] The circuits of the present invention described above can be combined in various ways according to the needs of a specific application. For example, Fig. 8A is a simplified schematic diagram of a first combined embodiment of an ultra-wideband LNA circuit 800 with enhanced output impedance matching according to the present invention. Figure 4 The LNA circuit 800 shown also includes two circuit modifications designed to enhance output impedance matching (note that some embodiments may not include two circuit modifications). The first addition is to couple the amplified signal terminal AST with the common gate FET M CG The output matching feedback circuit 702 (see Figure 7 ). The second addition is a modified first LC resonator circuit 414' which adds a resistor R1 coupled in series with an optional disabling switch Sw1R, where the coupled resistor and switch are coupled in parallel with the inductor L1 (see Figure 6 ).

[0105] The switch Sw can be selectively opened and closed as needed. FB (within the output matching feedback circuit 702), Sw0 (within the input matching feedback circuit 408), Sw1, Sw1R, Sw2a, Sw2b, Sw3 and Sw BP To achieve multiple operation modes, the trade-off between gain, bandwidth and linearity can be achieved by calling different gain modes. FB (within output matching feedback circuit 702), C0 (within input matching feedback circuit 408), C1, C2, C3 and / or resistor R FB Some or all of R0 (within the output matching feedback circuit 702), R1 (within the input matching feedback circuit 408), R2 may be adjustable, in particular dynamically adjustable such as by programming control, and further a compromise between gain, bandwidth and linearity may be achieved by calling different gain modes.

[0106] As another example, Figure 8B is a simplified schematic diagram of a second combined embodiment of an ultra-wideband LNA circuit 850 with enhanced output impedance matching according to the present invention. Fig. 8A In the illustrated embodiment, LNA circuit 850 implements inductors L1 and L2 as asymmetric T-coils, indicated by the points near L1 and L2 connected by the dashed arrow k. The asymmetric T-coil is an inductor peaking circuit that can extend the bandwidth of the amplifier and increase the output signal rise time. As is known, an asymmetric T-coil includes series coupled inductors (equivalent to discrete inductors L1 and L2) and an inherent bridging capacitance (not shown) across the inductors. Since the T-coil inherently includes a bridging capacitance, the T-coil is connected to the inductor by the dashed arrow k. Fig. 8A The LNA circuit 800 in C BLK The value of the DC blocking capacitor C may need to be adjusted compared to BLK The value of .

[0107] An integrated circuit implementation of an asymmetric T-coil can be in the form of a three-tap spiral inductor structure, where the first portion of the spiral (e.g., from the input tap to the middle tap) corresponds to L1, and the second portion of the spiral (e.g., from the middle tap to the output tap) corresponds to L2.

[0108] An advantage of using an asymmetric T-coil instead of discrete inductors L1 and L2 is that an IC implementation (eg, as a three-tap spiral inductor structure) typically saves die area compared to discrete inductors.

[0109] Input impedance matching circuit

[0110] The above-described embodiments of the invention may be further improved by enhancing certain subcircuits and / or adding additional circuits. For example, although many circuits may be used for input impedance matching circuit 104 in the various embodiments described above, it may be useful to utilize an enhanced input impedance matching circuit. For example, Fig. 9 FIG. 4 is a schematic diagram of an enhanced input impedance matching circuit 104 ′. The enhanced input impedance matching circuit 104 ′ includes an RF IN The series inductor L between the terminal and the input terminal INT SER , and coupled to L SER A shunt inductor L between the reference potential (e.g., circuit ground) SH In an alternative embodiment, L SH Can be found in L SER The other side of the RF IN The terminal side is connected to L SER(Note that if the order of the connections is changed, there may be different input match bandwidth and noise figure tradeoffs.) As shown, L SER and L SH Either or both of may be adjustable components, or have fixed values. In embodiments including the attenuation circuit 406, the series-shunt inductor L of the enhanced input impedance matching circuit 104' is SER , L SH and a common source FET M coupled to the attenuation circuit 406. CS Together they form a doubly terminated bandpass filter that increases the input bandwidth of the LNA circuit.

[0111] Circuit Implementation

[0112] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be enclosed in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. Specifically, IC embodiments of the present invention are typically used in modules, where one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possible additional ICs) into a package. Then, the IC and / or module are typically combined with other components on a printed circuit board to form a part of a terminal product such as a cellular phone, a laptop computer, or an electronic tablet, or to form a more advanced module that can be used in various products such as vehicles, test equipment, medical equipment, etc. Through various configurations of modules and components, such ICs typically implement communication modes, typically wireless communications.

[0113] As an example of further integration of the embodiments of the present invention with other components, for example, Fig.10 1 is a top plan view of a substrate 1000, which may be a printed circuit board or a chip module substrate (e.g., a thin film block). In the example shown, substrate 1000 includes a plurality of ICs 1002a to 1002d having terminal pads 1004 that are interconnected by conductive vias and / or traces on substrate 1000 and / or within substrate 1000 or on an opposing (rear) surface of substrate 1000 (to avoid clutter, surface conductive traces are not shown and not all terminal pads are labeled). For example, ICs 1002a to 1002d may be embodied as signal switches, active filters, amplifiers (including one or more LNAs), and other circuits. For example, IC 1002b may incorporate one or more instances of LNA circuits similar to those described in the examples of FIG. 1002 and FIG. 1002, respectively. Figure 3A , Figure 4 , Figure 6 , Figure 7and the circuits 300 , 400 , 600 , 700 and / or 800 shown in FIG. 8 .

[0114] The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and / or secured to the substrate 1000. Although shown as generally rectangular, the passive devices 1006 may be, for example, filters, capacitors, inductors, transmission lines, resistors, planar antenna elements, transducers (e.g., including MEMS-based transducers such as accelerometers, gyroscopes, microphones, pressure sensors, etc.), batteries, etc., interconnected with other passive devices 1006 and / or individual ICs 1002a to 1002d via conductive traces on or in the substrate 1000.

[0115] The front or back surface of substrate 1000 can be used as a location for forming other structures. For example, one or more antennas can be formed on or affixed to the front or back surface of substrate 1000; one example is shown of front surface antenna 1008 coupled to IC die 1002b, which can include RF front end circuitry. Thus, by including one or more antennas on substrate 1000, a complete radio can be created.

[0116] System

[0117] Embodiments of the present invention may be used in a variety of larger radio frequency (RF) circuits and systems, such as radio systems (particularly including cellular radio systems), personal computers, tablet computers, wireless network components, televisions, cable system "set-top" boxes, radar systems (including phased array and automotive radar systems), and test equipment.

[0118] Radio system uses include wireless RF systems (including base stations, relay stations, and handheld transceivers) using various technologies and protocols, including various types of Orthogonal Frequency Division Multiplexing (“OFDM”), Quadrature Amplitude Modulation (“QAM”), Code Division Multiple Access (“CDMA”), Time Division Multiple Access (“TDMA”), Wideband Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G and WiFi (e.g., 802.11a, 802.11b, 802.11g, 802.11ac, 802.11ax), and other radio communication standards and protocols.

[0119] As an example of wireless RF system usage, FIG. 11 shows an exemplary prior art wireless communication environment 1100 that includes different wireless communication systems 1102 and 1104 and may include one or more mobile wireless devices 1106 .

[0120] The wireless device 1106 may be able to communicate with multiple wireless communication systems 1102, 1104 using one or more of the above-mentioned telecommunication protocols. The wireless device 1106 may also be able to communicate with one or more satellites 1108 such as navigation satellites (e.g., GPS) and / or telecommunication satellites. The wireless device 1106 may be equipped with multiple antennas externally and / or internally for operation at different frequencies and / or to provide diversity to combat harmful path effects, such as fading and multipath interference. The wireless device 1106 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer or tablet computer, or some other wireless communication unit or device. The wireless device 1106 may also be referred to as a mobile station, user equipment, access terminal, or some other terminology.

[0121] For example, the wireless system 1102 may be a CDMA-based system that includes one or more base transceiver stations (BSTs) 1110 and at least one switching center (SC) 1112. Each BST 1110 provides over-the-air RF communications for wireless devices 1106 within its coverage area. The SC 1112 couples to one or more BSTs in the wireless system 1102 and provides coordination and control for the BSTs.

[0122] For example, the wireless system 1104 may be a TDMA-based system that includes one or more transceiver nodes 1114 and a network center (NC) 1116. Each transceiver node 1114 provides over-the-air RF communications for wireless devices 1106 within its coverage area. The NC 1116 is coupled to one or more transceiver nodes 1114 in the wireless system 1104 and provides coordination and control for these transceiver nodes 1114.

[0123] Typically, each BST 1110 and transceiver node 1114 is a fixed station that provides communication coverage for wireless devices 1106 and may also be referred to as a base station or some other terminology. SC 1112 and NC 1116 are network entities that provide coordination and control for the base stations and may also be referred to by other terms.

[0124] An important aspect of any wireless system is the details of how the constituent elements of the system perform. Fig.12is a block diagram of a transceiver 1200 that can be used in a wireless device such as a cellular telephone and that can beneficially incorporate embodiments of the present invention to improve performance. As shown, the transceiver 1200 includes a mix of RF analog circuits for transmitting and / or transforming signals directly on the RF signal path, non-RF analog circuits for operating requirements outside the RF signal path (e.g., for bias voltages and switching signals), and digital circuits for control and user interface requirements. In this example, the receiver path Rx includes an RF front-end portion, an intermediate frequency (IF) block portion, a back-end portion, and a baseband portion (note that in some implementations, the distinction between the portions may be different). The various illustrated portions and circuit elements may be embodied in one die or multiple IC dies. For example, the RF front-end in the example shown may include an RFFE module and a hybrid block, which may be implemented in (or as part of) different IC dies or modules. The different dies and / or modules may be connected to each other via transmission lines T IN and T OUT (e.g., microstrip, coplanar waveguide, or equivalent structure or circuit) coupling, e.g., transmission line T IN and T OUT Either or both may have 50Ω impedance.

[0125] The receiver path Rx receives the air RF signal via at least one antenna 1202 and a switch unit 1204, which may be implemented using active switching devices (e.g., field effect transistors or FETs) and / or using passive devices that implement frequency domain multiplexing (e.g., diplexers or duplexers). The RF filter 1206 passes the desired received RF signal to at least one low noise amplifier (LNA) 1208a, the output of which is coupled from the RFFE module to at least one LNA 1208b in the hybrid block (in this example via a transmission line T IN ). The LNA 1208b may provide buffering, input matching, and reverse isolation. The output of the LNA 1208b is combined with the output of the first local oscillator 1212 in a corresponding mixer 1210 to produce an IF signal. The IF signal may be applied to a demodulator 1218 after being amplified by an IF amplifier 1214 and passed through an IF filter 1216, which may be coupled to a second local oscillator 1220. The demodulated output of the demodulator 1218 is converted into a digital signal by an analog-to-digital converter 1222 and provided to one or more system components 1224 (e.g., video graphics circuits, sound circuits, memory devices, etc.). The converted digital signal may represent, for example, a video or still image, a sound, or a symbol (e.g., text or other characters).

[0126] In the example shown, the transmitter path Tx includes a baseband section, a backend section, an IF block section, and an RF front end section (again, in some implementations, the distinction between the sections may be different). Digital data from one or more system components 1224 is converted into an analog signal by a digital-to-analog converter 1226, the output of which is applied to a modulator 1228, which may also be coupled to a second local oscillator 1220. The modulated output of the modulator 1228 may pass through an IF filter 1230 before being amplified by an IF amplifier 1232. The output of the IF amplifier 1232 is then combined with the output of the first local oscillator 1212 in a mixer 1234 to produce an RF signal. The RF signal may be amplified by a driver 1236, the output of which is coupled to a power amplifier (PA) 1238 (in this example via a transmission line T OUT ). The amplified RF signal may be coupled to the RF filter 1240 , and the output of the RF filter 1240 may be coupled to at least one antenna 1202 via the switch unit 1204 .

[0127] The operation of the transceiver 1200 is controlled in a known manner by a microprocessor 1242, which interacts with system control components 1244 (e.g., user interface, memory / storage, application programs, operating system software, power control, etc.). In addition, the transceiver 1200 will typically include other circuits, such as bias circuitry 1246 (which may be distributed throughout the transceiver 1200 near the transistor devices), electrostatic discharge (ESD) protection circuits, test circuits (not shown), a factory programming interface (not shown), etc.

[0128] In modern transceivers, for example, there are typically more than one receiver path Rx and transmitter path Tx to accommodate multiple frequencies and / or signaling modalities. In addition, as should be apparent to one of ordinary skill in the art, some components of the transceiver 1200 may be placed in a different order (e.g., filters) or omitted. Other components may (and often are) added, such as (by way of example only) additional filters, impedance matching networks, variable phase shifters / attenuators, power dividers, etc.

[0129] As will be appreciated by those of ordinary skill in the art, RF system architectures are beneficially impacted by the present invention in key ways, including the ability to select a first operating mode that provides high gain and wide output impedance matching with tradeoffs in current, NF, and linearity, and a second operating mode that provides wideband output impedance matching with improved NF and linearity at lower currents and moderate gains. These system-level improvements are specifically enabled by the present invention and enable embodiments of the present invention to meet the stringent performance specifications of customers and many RF standards. Thus, the present invention is of great benefit to the user. Fig.12 The embodiment of the overall system shown is critical.

[0130] method

[0131] Fig.13 1300 is a flow chart illustrating a method of achieving broadband output impedance matching and high gain for a radio frequency amplifier having an amplifier core and an output terminal. The method includes coupling a first LC resonator between the amplifier core and a node, the first LC resonator including a first inductor and a first capacitor coupled in parallel (block 1302); coupling a matching and biasing circuit to the node and a power supply, the matching and biasing circuit including a second inductor and a second capacitor coupled in parallel (block 1304); and coupling a second LC resonator between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor coupled in parallel to each other (block 1306).

[0132] Additional aspects of the above method may include modifying the implementation as described above and in Figure 3A , Figure 4 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 Circuit components of the method shown.

[0133] Manufacturing Techniques and Options

[0134] Although Figure 3A , Figure 4 , Figure 6 , Figure 7 The example implementation shown in FIG. 8 is an LNA, but the circuits and methods of the present invention may also be applied to other types of amplifiers, such as power amplifiers.

[0135] For clarity, additional known circuit elements that may be included in some applications, such as DC blocking capacitors, additional impedance matching circuitry, and additional filters, are omitted. It should also be noted that a circuit component characterized as "adjustable" may have its value selected from a plurality of possible component value settings and fixed during manufacture, when assembled in a circuit module, during factory testing, or in the field (e.g., by burning or "blowing" a fusible link), or may have its value dynamically changed, tuned, or programmatically set, for example, in response to other circuits (e.g., temperature compensation and / or power control circuits) or in response to a generated or received command signal.

[0136] The operating mode of the LNA circuit of the present invention can be set by a control circuit (not shown) in a known manner. The control circuit can also be connected to the adjustable components to select different component values ​​(e.g., capacitance, resistance, inductance) for different gain states, for example, to help input and / or output impedance matching, or to change gain and linearity in some operating modes.

[0137] The switches shown in the embodiments of the present invention can be implemented as FETs, in particular MOSFETs. As used in the present disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes an insulated gate having a metal or metalloid, insulator and / or semiconductor structure. The term "metal" or "metalloid" includes at least one conductive material (e.g., aluminum, copper or other metal or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material); and "semiconductor" includes at least one semiconductor material.

[0138] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0139] With respect to the drawings cited in this disclosure, the sizes of the various elements are not to scale; some dimensions are greatly exaggerated in the vertical and / or horizontal directions for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "lower," "upper," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the example drawings and are not necessarily absolute orientations or directions.

[0140] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, the selection of appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or hybrid or discrete circuit form. Any suitable substrate and process can be used to manufacture integrated circuit embodiments, including but not limited to standard bulk silicon, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using processes with similar characteristics. The manufacture of SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all units, allowing them to be compensated for).

[0141] Voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be inverted, depending on the particular specifications and / or implementation techniques (e.g., NMOS, PMOS, or CMOS transistor devices, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand greater voltages, and / or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0142] in conclusion

[0143] A number of embodiments of the present invention have been described. It should be appreciated that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the steps described above may be order-independent and thus may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0144] It should be understood that the above description is intended to illustrate but not to limit the scope of the invention, which is limited by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or components of matter set forth in the appended claims. (Note that parenthetical markings of claim elements are for convenience of reference to such elements and do not by themselves indicate a specific required order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements without being considered as starting a conflicting marking sequence).

Claims

1. A load circuit configured to be coupled between a radio frequency amplifier core and an output terminal, the load circuit comprising: (a) a first LC resonator coupled between the RF amplifier core and a node, the first LC resonator comprising a first inductor and a first capacitor coupled in parallel; (b) a matching and biasing circuit coupled to the node and configured to be coupled to a power supply, the matching and biasing circuit comprising a second inductor and a second capacitor coupled in parallel; as well as (c) a second LC resonator coupled between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor coupled in parallel with each other.

2. The invention according to claim 1, further comprising a fourth capacitor coupled in series with the third inductor and the third capacitor connected in parallel.

3. The invention according to claim 1, wherein: The first LC resonator also includes a bypass switch coupled in parallel with the first inductor and the first capacitor.

4. The invention according to claim 1, wherein: The second LC resonator also includes a bypass switch coupled in parallel with the third inductor and the third capacitor.

5. The invention according to claim 1, wherein: The matching and biasing circuit also includes a switch coupled in series with the second capacitor and configured to selectively disable the second capacitor.

6. The invention according to claim 1, wherein: At least one of the first inductor and the first capacitor is adjustable.

7. The invention according to claim 1, wherein: At least one of the third inductor and the third capacitor is adjustable.

8. The invention according to claim 1, wherein: At least one of the second inductor and the second capacitor is adjustable.

9. The invention according to claim 1, wherein: The matching and biasing circuit also includes a second resistor coupled in parallel with the second inductor and the second capacitor.

10. The invention according to claim 9, wherein: The second resistor is adjustable.

11. The invention according to claim 9, wherein: The matching and biasing circuit also includes a first switch coupled in series with the second resistor and configured to selectively disable the second resistor.

12. The invention according to claim 9, wherein: The first LC resonator also includes a first resistor coupled in parallel with the first inductor and the first capacitor.

13. The invention according to claim 12, wherein: The first LC resonator also includes a second switch coupled in series with the first resistor and configured to selectively disable the first resistor.

14. The invention according to claim 12, wherein: The first resistor is adjustable.

15. An amplifier, comprising: (a) an amplifier core comprising: (1) an input terminal configured to receive a radio frequency (RF) signal; and (2) Amplifying signal terminals; (b) output terminals; (c) a load circuit configured to be coupled between the amplified signal terminal and the output terminal, the load circuit comprising: (1) a first LC resonator coupled between the amplified signal terminal and a node, the first LC resonator comprising a first inductor and a first capacitor coupled in parallel; (2) a matching and biasing circuit coupled to the node and configured to be coupled to a power supply, the matching and biasing circuit comprising a second inductor and a second capacitor coupled in parallel; and (3) A second LC resonator coupled between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor coupled in parallel with each other.

16. The invention of claim 15, further comprising a fourth capacitor coupled in series with the third inductor and the third capacitor connected in parallel.

17. The invention according to claim 15, wherein: The first LC resonator also includes a first bypass switch coupled in parallel with the first inductor and the first capacitor.

18. The invention according to claim 15, wherein: The second LC resonator also includes a second bypass switch coupled in parallel with the third inductor and the third capacitor.

19. The invention according to claim 15, wherein: The matching and biasing circuit also includes a switch coupled in series with the second capacitor and configured to selectively disable the second capacitor.

20. The invention according to claim 15, wherein: At least one of the first inductor and the first capacitor is adjustable.

21. The invention according to claim 15, wherein: At least one of the third inductor and the third capacitor is adjustable.

22. The invention according to claim 15, wherein: At least one of the second inductor and the second capacitor is adjustable.

23. The invention according to claim 15, wherein: The matching and biasing circuit also includes a second resistor coupled in parallel with the second inductor and the second capacitor.

24. The invention according to claim 23, wherein: The second resistor is adjustable.

25. The invention according to claim 23, wherein: The matching and biasing circuit also includes a first switch coupled in series with the second resistor and configured to selectively disable the second resistor.

26. The invention according to claim 23, wherein: The first LC resonator also includes a first resistor coupled in parallel with the first inductor and the first capacitor.

27. The invention according to claim 26, wherein: The first LC resonator also includes a second switch coupled in series with the first resistor and configured to selectively disable the first resistor.

28. The invention according to claim 26, wherein: The first resistor is adjustable.

29. The invention of claim 15 further comprising an input impedance matching circuit coupled to the input terminal and configured to receive the RF signal.

30. The invention according to claim 29, wherein: The input impedance matching circuit includes a series inductor coupled to the input terminal and configured to receive the RF signal, and a shunt inductor coupled between the series inductor and a reference potential.

31. The invention according to claim 30, wherein: At least one of the series inductor or the shunt inductor is adjustable.

32. The invention according to claim 15, wherein: The amplifier core includes an attenuation terminal, and the invention further includes an attenuation circuit coupled to the attenuation terminal and configured to be coupled to a reference potential, the attenuation circuit including a attenuation inductor.

33. The invention of claim 32 further comprising a bypass switch coupled in parallel with the damping inductor.

34. The invention according to claim 15, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and the invention further includes a feedback circuit coupled between the input terminal and the feedback node, the feedback circuit being selectively switchable between enabled and disabled.

35. The invention according to claim 34, wherein: The feedback circuit includes a capacitor, a resistor, and a switch coupled in series.

36. The invention according to claim 35, wherein: At least one of the resistor or the capacitor is adjustable.

37. The invention according to claim 15, wherein: The amplifier core also includes a feedback node in an output signal path of the amplifier core, and the invention also includes a feedback circuit coupled between the feedback node and the gate of the common-gate FET within the amplifier core, the feedback circuit being selectively switchable between enabled and disabled.

38. The invention according to claim 37, wherein: The feedback circuit includes a capacitor, a resistor, and a switch coupled in series.

39. The invention according to claim 38, wherein: At least one of the resistor or the capacitor is adjustable.

40. The invention of claim 15, wherein: The amplifier is a low noise amplifier.

41. The invention according to claim 15, wherein: The amplifier is implemented as an integrated circuit fabricated in silicon-on-insulator technology and includes MOS devices.

42. The invention according to claim 15, wherein: The amplifier is implemented as an integrated circuit assembled in a circuit module.

43. The invention according to claim 15, wherein: The amplifier is implemented as an integrated circuit comprising a part of a communication device.

44. The invention according to claim 15, wherein: The amplifier core also includes: (a) a common-source FET having a gate, a source and a drain coupled to the input terminal signal; (b) a stack comprising at least one common-gate FET, each common-gate FET having a gate, a source, and a drain that outputs an amplified version of the received RF signal, wherein the source of one of the at least one common-gate FET is coupled to the drain of the common-source FET, and wherein the drain of one of the at least one common-gate FET is coupled to an amplified signal terminal of the stack.

45. A load circuit configured to be coupled between a radio frequency amplifier core and an output terminal, the load circuit comprising: (a) a first inductor coupled between the RF amplifier core and the output terminal; (b) a first resistor coupled in parallel with the first inductor between the RF amplifier core and the output terminal; (c) a second inductor coupled to the output terminal and configured to be coupled to a power source; as well as (d) a second resistor coupled in parallel with the second inductor and coupled to the output terminal and configured to be coupled to the power source.

46. ​​A load circuit, the load circuit being configured to be coupled between a radio frequency amplifier core and an output terminal, the load circuit comprising: (a) a first inductor coupled between the RF amplifier core and the output terminal; (b) a second inductor coupled to the output terminal and configured to be coupled to a power source; (c) a capacitor coupled between the output terminal and the output terminal; as well as (d) a feedback circuit coupled between an input terminal and a feedback node in an output signal path of the amplifier core and selectively switchable between enabled and disabled, wherein the feedback circuit comprises a capacitor, a resistor, and a switch coupled in series.

47. A method for achieving broadband output impedance matching and high gain of a radio frequency amplifier, the radio frequency amplifier having an amplifier core and an output terminal, the method comprising: (a) coupling a first LC resonator between the amplifier core and a node, the first LC resonator comprising a first inductor and a first capacitor coupled in parallel; (b) coupling a matching and biasing circuit to the node and a power supply, the matching and biasing circuit comprising a second inductor and a second capacitor coupled in parallel; as well as (c) coupling a second LC resonator between the node and the output terminal, the second LC resonator including a third inductor and a third capacitor coupled in parallel with each other.

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