Automatic parameter adjustment method of SPI controller

Abstract

The automatic parameter adjustment method of the SPI controller of the present invention includes pulse excitation of the SPI bus and acquisition of waveform response data to generate a bus characteristic mapping table; sending a self-test instruction sequence to target devices of different batches to generate a device characteristic mapping table; determining intermediate configuration parameters and verifying them to generate transition configuration data; obtaining interference event data and voltage monitoring data, waveform adjustment of the clock signal, and generating interference suppression data; statistics of the bit error rate data and delay data of the target device to generate device aging trend data; grouping the target devices based on the similarity of device characteristics, and performing parallel access control. The present invention can cope with environmental factors such as temperature fluctuations, power spikes and electromagnetic interference in industrial-grade edge computing devices, solve the real-time data interaction problem of devices of different batches and process levels, process the aging phenomenon of devices over time, and avoid intermittent errors or large-scale communication failures during high-load access.

Description

Technical Field

[0001] The present invention relates to the technical field of automatic parameter adjustment of a SPI controller, and in particular to an automatic parameter adjustment method of a SPI controller. Background Art

[0002] The SPI controller (Serial Peripheral Interface Controller) is a core hardware or firmware module that manages serial data interaction between the host and the slave device. It completes bidirectional communication by generating a clock signal (SCLK) and coordinating the two data lines of Master-Output-Slave-In (MOSI) and Master-Input-Slave-Out (MISO), and dynamically controls the target slave device according to the chip select (CS) signal. Due to its small number of communication lines, high bandwidth and relatively simple protocol, the SPI controller is widely used in embedded systems and industrial-grade edge computing. It is particularly suitable for mounting multiple storage devices (such as Flash) and sensor modules of different batches and processes in parallel on a bus to achieve the collection, storage and real-time processing of massive data.

[0003] However, the existing technology usually only performs one-time or preliminary parameter calibration on the SPI controller when the system is powered on or in a single environment, ignoring the reality that the industrial field environment is complex and the device process differences are significant. Under high load, frequent switching or staggered access of multiple devices, if the controller cannot accurately grasp the internal timing characteristics and aging degree of each batch of storage devices and sensors, it is difficult to adjust the key parameters such as clock polarity, phase, and drive strength in time. It is very easy to initiate high-speed reading and writing of certain devices before the steady state, resulting in hidden error codes or data jitter. These errors are often covered up by software error correction in the short term, but may be multiplied in later batch deployment or extreme environments (such as high temperature, low voltage, and high power interference), resulting in difficult-to-track system failure risks. Therefore, how to achieve dynamic and multi-dimensional parameter tuning of the SPI controller under parallel mounting of multiple devices and harsh working conditions, while taking into account high throughput and high reliability, has become a core technical problem that the current industry needs to overcome. Summary of the invention

[0004] The main purpose of the present invention is to solve the technical problem that the prior art cannot achieve dynamic and multi-dimensional parameter tuning of the SPI controller under parallel mounting of multiple devices and harsh working conditions, and take into account both high throughput and high reliability.

[0005] A first aspect of the present invention provides an automatic parameter adjustment method for an SPI controller, the automatic parameter adjustment method for the SPI controller comprising:

[0006] According to a preset duty cycle, a preset edge speed and a preset pulse interval, the SPI bus is pulse-excited in multiple operating temperature ranges, waveform response data is collected, the waveform response data is associated and marked with environmental parameter data, and a bus characteristic mapping table is generated, wherein the environmental parameter data includes temperature data, voltage data and interference intensity data;

[0007] Determine initial clock parameters based on the bus characteristic mapping table, send self-test instruction sequences to target devices of different batches, collect device response data, associate and mark the device response data with the environmental parameter data, and generate a device characteristic mapping table;

[0008] Determine intermediate configuration parameters based on the device characteristic mapping table and the bus characteristic mapping table, collect configuration verification data, adjust clock phase parameters and data sampling parameters according to the configuration verification data, and generate transition configuration data;

[0009] Based on the transition configuration data, interference event data and voltage monitoring data are acquired, waveform adjustment is performed on the clock signal, result data of the waveform adjustment is recorded, and interference suppression data is generated;

[0010] Based on the interference suppression data and the device characteristic mapping table, statistically processing the bit error rate data and delay data of the target device to generate device aging trend data;

[0011] Based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data, the plurality of target devices are grouped based on device characteristic similarity, timing parameter sharing is performed within the group, parallel access control is performed, and access status records are generated.

[0012] Optionally, the SPI bus is pulse-excited in multiple operating temperature ranges according to a preset duty cycle, a preset edge speed, and a preset pulse interval, waveform response data is collected, the waveform response data is associated and marked with environmental parameter data, and a bus characteristic mapping table is generated, wherein the environmental parameter data includes temperature data, voltage data, and interference intensity data, including:

[0013] Based on multiple sets of preset duty cycles, a first round of pulse excitation is performed within a power supply voltage range, and a first round of waveform response data and voltage data are collected, wherein the power supply voltage range is 9V to 36V;

[0014] Determine the minimum distortion duty cycle and the optimal voltage level according to the first round of waveform response data and the voltage data, perform a second round of pulse excitation at multiple sets of preset edge speeds, and collect the second round of waveform response data and the first round of interference intensity data;

[0015] Based on the minimum distortion duty cycle and the optimal voltage level, during the switching of the working state of the industrial equipment, a third round of pulse excitation is performed according to a plurality of groups of preset pulse intervals, and the third round of waveform response data and the second round of interference intensity data are collected;

[0016] Repeating the first round of pulse excitation, the second round of pulse excitation and the third round of pulse excitation in a plurality of operating temperature intervals to collect temperature data, wherein the operating temperature interval ranges from -40°C to 85°C;

[0017] Determining interference intensity data according to the first round of interference intensity data and the second round of interference intensity data;

[0018] Merging the first round of waveform response data, the second round of waveform response data, and the third round of waveform response data to obtain waveform response data;

[0019] The waveform response data, the temperature data, the voltage data and the interference intensity data are associated and marked to generate a bus characteristic mapping table.

[0020] Optionally, determining the initial clock parameters based on the bus characteristic mapping table, sending self-test instruction sequences to target devices of different batches, collecting device response data, associating and marking the device response data with the environmental parameter data, and generating the device characteristic mapping table include:

[0021] Screening multiple groups of clock frequency, polarity and phase combinations according to the voltage data and temperature data in the bus characteristic mapping table to generate an initial clock parameter set;

[0022] Based on the initial clock parameter set, send identification instructions and status reading instructions to target devices of different batches, collect first-round device response data, and record access delay data under different voltage levels and temperature ranges;

[0023] According to the first round of device response data and the access delay data, sending register test instructions and storage unit read and write instructions to different batches of the target devices, and collecting the second round of device response data;

[0024] Based on the second round of device response data, sending data alternation test instructions to the target devices of different batches in different power supply states, and collecting the third round of device response data;

[0025] Sending timing boundary test instructions to the target devices of different batches, recording data latch timing parameters, and collecting fourth round device response data;

[0026] Merging the first-round device response data, the second-round device response data, the third-round device response data, and the fourth-round device response data to obtain device response data;

[0027] The device response data and the environmental parameter data are associated and marked to generate a device characteristic mapping table.

[0028] Optionally, determining intermediate configuration parameters based on the device characteristic mapping table and the bus characteristic mapping table, collecting configuration verification data, adjusting clock phase parameters and data sampling parameters according to the configuration verification data, and generating transition configuration data includes:

[0029] Screening multiple groups of combination parameters of clock frequency, phase and sampling point according to the access delay data in the device characteristic mapping table and the waveform response data, voltage data and interference intensity data in the bus characteristic mapping table to generate intermediate configuration parameters;

[0030] Based on the intermediate configuration parameters, burst read and write test instructions are sent to the target devices of different batches during the process of dynamically switching the working state of the industrial equipment to collect the first round of configuration verification data;

[0031] According to the first round of configuration verification data, the clock phase parameter is adjusted in sections during the power supply voltage fluctuation process, and the second round of configuration verification data is collected;

[0032] Based on the second round of configuration verification data, adjusting the data sampling parameters in sections during the sudden change of power load, and collecting the third round of configuration verification data;

[0033] Combining and analyzing the bit error rate data and timing jitter data in the first round of configuration verification data, the second round of configuration verification data, and the third round of configuration verification data to obtain configuration verification data;

[0034] The clock phase parameter and the data sampling parameter are gradient adjusted according to the configuration verification data to generate transition configuration data.

[0035] Optionally, the step of performing gradient adjustment on the clock phase parameter and the data sampling parameter according to the configuration verification data to generate transition configuration data includes:

[0036] According to the bit error rate data in the configuration verification data, the clock phase parameter is scanned in decreasing steps to generate phase step data;

[0037] Based on the phase step data, a multi-point sampling test is performed on the clock phase parameter, a sampling stable interval is recorded, and phase window data is generated;

[0038] According to the phase window data, performing an offset test on the sampling points of the data sampling parameters to generate sampling offset data;

[0039] Based on the sampling offset data, interpolation test is performed on the data sampling parameters in the sampling stability interval to generate sampling optimization data;

[0040] According to the timing jitter data in the configuration verification data and the sampling optimization data, setting a protection boundary for the clock phase parameter to generate phase protection data;

[0041] Based on the phase protection data, a dynamic adjustment range is set for the data sampling parameter to generate sampling restriction data;

[0042] The phase protection data and the sampling restriction data are associated and marked to generate transition configuration data.

[0043] Optionally, acquiring interference event data and voltage monitoring data based on the transition configuration data, performing waveform adjustment on the clock signal, recording result data of the waveform adjustment, and generating interference suppression data includes:

[0044] According to the transition configuration data, the relay action signal, the power switch signal and the motor start / stop signal of the industrial equipment are monitored to generate interference event data;

[0045] Based on the interference event data, sampling the voltage fluctuation at the power input terminal to generate voltage monitoring data;

[0046] Pre-adjusting the clock signal before the interference event occurs according to the interference event data and the voltage monitoring data to generate pre-adjustment parameter data;

[0047] Based on the pre-adjustment parameter data, the rising edge and the falling edge of the clock signal are subjected to segmented smoothing processing, and the first round of waveform adjustment data is collected;

[0048] According to the first round of waveform adjustment data, the driving strength of the clock signal is adjusted in multiple levels, and the second round of waveform adjustment data is collected;

[0049] Merging the first round of waveform adjustment data and the second round of waveform adjustment data to obtain waveform adjustment result data;

[0050] The waveform adjustment result data is associated with the interference event data and the voltage monitoring data to generate interference suppression data.

[0051] Optionally, pre-adjusting the clock signal before the interference event occurs according to the interference event data and the voltage monitoring data to generate pre-adjustment parameter data includes:

[0052] Extracting features of relay action signals, power switch signals and motor start / stop signals in the interference event data, and combining them with the voltage monitoring data to generate interference prediction data;

[0053] Determine the occurrence time of the interference event according to the interference prediction data, and pre-adjust the clock signal within the reserved time before the occurrence of the interference event to generate adjustment timing data;

[0054] The adjustment timing data is time-aligned with the interference prediction data to generate pre-adjustment parameter data.

[0055] Optionally, the performing statistical processing on the bit error rate data and delay data of the target device based on the interference suppression data and the device characteristic mapping table to generate device aging trend data includes:

[0056] Determine timing boundary parameters according to the waveform adjustment result data in the interference suppression data and the access delay data in the device characteristic mapping table to obtain initial delay data;

[0057] Based on the initial delay data, a timing margin test is performed on the read and write operations of the target device, and current delay data and current bit error rate data are collected;

[0058] According to the initial delay data and the current delay data, counting the delay variation data of the target device under different power supply voltage and temperature conditions to generate delay statistical data;

[0059] Based on the current bit error rate data, collecting bit error distribution data of the target device under different working conditions to generate bit error statistical data;

[0060] Performing time domain distribution analysis on the delay statistical data to obtain delay degradation data;

[0061] Performing spatial distribution analysis on the bit error statistical data to obtain bit error degradation data;

[0062] The delay degradation data and the bit error degradation data are associated and marked to generate device aging trend data.

[0063] Optionally, the step of grouping the plurality of target devices based on device characteristic similarity based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data, performing timing parameter sharing within the group, performing parallel access control, and generating an access status record includes:

[0064] According to the delay degradation data in the device aging trend data and the access delay data in the device characteristic mapping table, matching the manufacturing batches and aging states of the plurality of target devices to generate batch characteristic data;

[0065] Based on the batch characteristic data and the waveform response data in the bus characteristic mapping table, similarity calculation is performed on the timing parameters of the target device in different temperature ranges to generate timing similarity data;

[0066] Classifying the response characteristics of the target device under different voltage fluctuation conditions according to the timing similarity data to obtain a device grouping scheme;

[0067] Based on the device grouping scheme, allocating the clock phase parameters and sampling timing parameters in the transition configuration data to the target devices in the group to generate intra-group shared parameters;

[0068] According to the intra-group shared parameters, the access priority of each group is dynamically adjusted when the working state of the industrial equipment is switched, and the inter-group arbitration data is generated;

[0069] Based on the inter-group arbitration data, performing interleaved access scheduling on the target devices in the group, recording access conflict data in each time window, and generating parallel access data;

[0070] The parallel access data is associated with the intra-group shared parameters to generate an access status record.

[0071] Optionally, performing interleaved access scheduling on the target devices in the group based on the inter-group arbitration data, recording access conflict data in each time window, and generating parallel access data includes:

[0072] Allocate time slots to the target devices in the group according to the inter-group arbitration data, set anti-collision intervals between adjacent time slots, and generate time slot allocation data;

[0073] Based on the time slot allocation data, performing interleaved read and write accesses on the target device within a time window, recording access timing parameters and conflict counts within a group, and generating access monitoring data;

[0074] A time-related analysis is performed on the conflict counts and timing parameters in the access monitoring data, and an anti-collision interval and an interleaving scheduling scheme are generated to obtain parallel access data.

[0075] This solution first uses pulse excitation at the communication line level to measure the line loss, reflection and noise interference that may exist on the SPI bus. By associating the collected waveform response with parameters such as temperature and voltage, a mapping that can fully characterize the real-time environment and line characteristics can be obtained. The advantage of this is that if a temperature increase or voltage mutation is detected during subsequent operation, the system can trace back the previous waveform acquisition results at any time to infer whether the current clock frequency or phase is still applicable, thereby achieving a communication state adjustment capability at the physical layer. Since many traditional methods only measure the communication parameters once at the initial power-on and lack the perception of subsequent environmental changes, timing mismatches are prone to occur during high-load access or parallel switching. In contrast, this solution can dynamically evaluate each memory or sensor to be accessed based on the coupling results of line mapping and real-time environmental data, which can not only ensure the communication rate, but also avoid random errors caused by sudden interference.

[0076] On this basis, this solution also sends self-test instructions to different batches of memories or sensors to collect the response characteristics of these devices under actual working conditions, and generates another mapping that specifically describes the timing, delay, and bit error conditions of each device. Since different manufacturing processes or aging levels will present completely different electrical characteristics under high temperature and low voltage, if only relying on a single test mode, it is likely that the "optimal timing parameters" obtained are not universally applicable to all target devices. However, this solution allows each device to "actively" feedback its own characteristic parameters under various conditions, thereby achieving accurate grasp of the differences between multiple devices. Afterwards, by cross-comparing these two mappings, the line and environment mapping and the device characteristic mapping, a more targeted intermediate configuration can be made for the next step of clock phase, data sampling point, and drive strength. Combined with the tracking of configuration verification results, the system can appropriately fine-tune or gradiently update the phase and sampling window, gradually approaching the optimal settings under current conditions. The principle of this segmented verification and fine-tuning is: when the drive or clock parameters are close to the limit position of certain devices, even if it is feasible in a short period of time, once there is a slight fluctuation in the environment, it will cause intermittent errors; and through segmented adjustment and bit error analysis, potential critical intervals can be avoided in time, significantly reducing the probability of error outbreaks.

[0077] When interference events such as external relays or motor movements are detected, this solution selects the appropriate waveform smoothing or clock buffering strategy from the previously established transition configuration data, and actively completes segmented adjustments before the interference peak occurs. This can reduce the rising edge or drive strength at the moment when the signal is most easily distorted, and quickly restore the high-performance mode after the interference decays. For the aging phenomenon of devices over time, the aging trend table of each device is continuously updated by counting their delays and bit error rates under daily operations. If a batch of memory shows a significant decline, the system will assign it a more conservative clock or phase to ensure that it is not accidentally dragged down during parallel access. Finally, these devices are grouped based on the similarity of characteristics, so that devices in the same group can share similar timing parameters, which not only reduces the waste of repeated switching, but also improves the overall throughput at the physical layer and scheduling level.

[0078] Through such a complete set of dynamic perception, refined mapping, segmented fine-tuning and group management mechanisms, this solution can not only guarantee the communication rate in the concurrent scenarios of multiple memories and sensors, but also effectively resist the temperature fluctuations, power spikes and electromagnetic interference that may occur at any time in the industrial environment; at the same time, it can also respond promptly to the long-term degradation risks caused by device aging, thereby avoiding the outbreak of difficult-to-troubleshoot communication failures in later large-scale deployments, and successfully achieving the core goal of high reliability and high throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0080] Figure 1 The figure is a schematic diagram of an embodiment of the automatic parameter adjustment method of the SPI controller in an embodiment of the present invention.

[0081] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0083] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back...), the directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0084] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, "and / or" in the full text includes three solutions. Taking A and / or B as an example, it includes technical solution A, technical solution B, and technical solution that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, which must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0085] An embodiment of the present application provides an automatic parameter adjustment method for an SPI controller. Figure 1 A flow chart of an automatic parameter adjustment method for an SPI controller provided in an embodiment of the present application. In this embodiment, the method includes:

[0086] See also Figure 1 , pulse excitation of the SPI bus in multiple operating temperature ranges according to a preset duty cycle, a preset edge speed and a preset pulse interval, collecting waveform response data, associating and marking the waveform response data with environmental parameter data, and generating a bus characteristic mapping table, wherein the environmental parameter data includes temperature data, voltage data and interference intensity data;

[0087] In one embodiment of the present invention, the SPI bus is pulse-excited in multiple operating temperature ranges according to a preset duty cycle, a preset edge speed, and a preset pulse interval, waveform response data is collected, the waveform response data is associated and marked with environmental parameter data, and a bus characteristic mapping table is generated, wherein the environmental parameter data includes temperature data, voltage data, and interference intensity data, including: based on multiple groups of preset duty cycles, a first round of pulse excitation is performed in a power supply voltage range, and the first round of waveform response data and voltage data are collected, and the power supply voltage range is 9V to 36V; based on the first round of waveform response data and the voltage data, a minimum distortion duty cycle and an optimal voltage level are determined, a second round of pulse excitation is performed at multiple groups of preset edge speeds, and the second round of waveform response data and the first round of interference intensity data are collected; based on the minimum The distortion duty cycle and the optimal voltage level are determined. During the working state switching process of the industrial equipment, a third round of pulse excitation is performed according to multiple groups of preset pulse intervals, and the third round of waveform response data and the second round of interference intensity data are collected; the first round of pulse excitation, the second round of pulse excitation and the third round of pulse excitation are repeatedly performed in multiple working temperature ranges, and temperature data are collected, wherein the working temperature range is -40°C to 85°C; interference intensity data is determined according to the first round of interference intensity data and the second round of interference intensity data; the first round of waveform response data, the second round of waveform response data and the third round of waveform response data are merged to obtain waveform response data; the waveform response data, the temperature data, the voltage data and the interference intensity data are associated and marked to generate a bus characteristic mapping table.

[0088] Specifically, the process of performing the first round of pulse excitation in the power supply voltage range of 9V to 36V under multiple sets of preset duty cycles is intended to allow the SPI bus to receive pulse signals at different duty cycles and different voltages, thereby collecting the first round of waveform response data and voltage data. In specific implementation, a function signal generator can be set to set the duty cycle to 30%, 50%, 70%, etc., and its output end is connected to the SPI bus (or a coupling channel specifically used for testing). At the same time, the system gradually increases the voltage from 9V to 36V from the power supply end, and each voltage point is maintained for a short time, and a high-speed data acquisition device or oscilloscope is used to capture the peak level, edge changes, and possible distortion amplitude of the pulse at this voltage. In this way, all waveform data under different voltages and different duty cycle combinations can be obtained, and the corresponding voltage values ​​can be recorded synchronously. In industrial production scenarios, if a device bus has time-sharing power switching or instantaneous voltage jumps, such changes must also be marked to ensure that the collected waveform can be accurately matched to the voltage range. In this way, once the analysis is completed, it can be determined whether certain duty cycles will cause significant waveform distortion or whether they will produce large overshoot and undershoot within this voltage range.

[0089] When determining the minimum distortion duty cycle and the optimal voltage level based on the first round of waveform response data and the voltage data, a comprehensive comparison will be made first, that is, the distortion factors under all duty cycle and voltage point combinations will be quantified. The distortion factor can be calculated based on peak overshoot, edge speed deviation or distortion accumulation. If a duty cycle is normal at 9V, but there is an obvious overshoot at 36V, it means that the duty cycle is not matched enough in the high voltage range. By comparing all the results, the duty cycle with the "lowest distortion" and the voltage segment with the "least distortion" can be selected, and the minimum distortion duty cycle and the optimal voltage level can be obtained, and used as a benchmark reference value or interval for subsequent tests. When the power supply of the field equipment enters this interval, the pulse waveform of the SPI bus is relatively more stable, which lays the foundation for subsequent high-reliability communication.

[0090] The second round of pulse excitation at multiple preset edge speeds is to observe the distortion and interference of the same SPI bus at different rising and falling edge speeds. If a duty cycle and a voltage segment have been determined as a benchmark in the previous step, then this stage will focus on the variable of "edge speed". At this time, the edge speed of the function signal generator or dedicated pulse module can be divided into several gears from slower to faster, such as 1V / ns, 2V / ns, etc. (the specific value can be set according to the actual hardware capability), and the pulse signal is injected into the SPI bus one by one, and the interference intensity is recorded through the interference detection module (called the first round of interference intensity data). If the peak distortion or jitter increases significantly at certain edge speeds, overshoot or undershoot can be reflected in the waveform. At this time, if there is a start-stop behavior related to high-power motors or high-load equipment at the industrial site, the interference detection module will also record it synchronously to ensure that the first round of interference intensity data can correspond to the pulse excitation of different edge speeds. During this process, if it is found that some edge speeds conflict with the minimum distortion duty cycle previously screened, for example, the duty cycle itself is not distorted, but large jitter occurs at fast edge speeds, then this needs to be recorded for subsequent comprehensive analysis.

[0091] Based on the minimum distortion duty cycle and the optimal voltage level, during the period of industrial equipment working state switching, a third round of pulse excitation is performed according to multiple groups of preset pulse intervals, and the third round of waveform response data and the second round of interference intensity data are collected. Here, "according to multiple groups of preset pulse intervals" means that the sending interval between pulses can be adjusted on the basis of a relatively fixed duty cycle and edge speed, such as adjusting the pulse frequency from 50kHz to 10MHz or higher depending on the hardware capability, and allowing the equipment to perform working state switching at each frequency point. For example, if an industrial assembly line will produce an instantaneous voltage drop when running at full load, then applying pulse excitation at this moment will allow the system to capture the waveform distortion under large load fluctuations. The second round of interference intensity data is further enriched at this time, because when industrial equipment is in a switching or high impact link, the interference level usually increases significantly. By coordinating with the first round of interference intensity data obtained previously, it can be confirmed whether the peak period and amplitude of the interference during the switching period far exceed the situation during normal operation.

[0092] In order to make the test process comprehensive, the above three steps are repeated in multiple operating temperature ranges from -40°C to 85°C, and the temperature data is recorded. The specific approach is to place the system in different temperature control environments (for example, a low temperature box simulating a -40°C environment or a high temperature box simulating an 85°C environment), repeat the first, second, and third rounds of pulse excitation, and check the changes in the waveform and the derivatives of interference at extreme temperatures. Take an SPI line placed on an outdoor mining operating platform as an example. If large mechanical equipment needs to be started at low temperatures all year round, it is necessary to pay attention to the pulse delay or distortion that may be caused by the cable material and electrical characteristics at -40°C. Only by testing in multiple temperature ranges can we ensure that stable and reliable communication parameters can be found at various external temperatures in the future.

[0093] According to the first round of interference intensity data and the second round of interference intensity data, the overall intensity level of industrial site interference can be comprehensively evaluated, and several typical interference peaks or continuous interference segments can be marked as key focus objects. In some cases, the first round of interference only corresponds to equipment idling or half-load operation, while the second round of interference corresponds to full-load switching. At this time, if the difference between the two rounds of data is very large, it can be shown that the SPI bus needs more conservative operating parameters when switching loads. By merging the first round of waveform response data, the second round of waveform response data, and the third round of waveform response data, a more comprehensive waveform response data set can be obtained. At this time, not only the multi-dimensional results of duty cycle, edge speed, and pulse interval are included, but also the interference intensity and temperature values ​​are included, thus providing a basis for making a detailed prediction of future communication status.

[0094] Finally, the waveform response data, the temperature data, the voltage data and the interference intensity data are associated and marked to generate a bus characteristic mapping table. This mapping table specifically presents the waveform quality indicators generated by different excitation modes (duty cycle, edge speed, pulse interval) under different environmental combinations (temperature range, voltage level, interference intensity). Its beneficial effect is reflected in the subsequent SPI automatic parameter adjustment process. By querying this mapping table in real time, it can be evaluated whether the current environment is suitable for a certain set of communication parameters. If the map shows that a distortion peak or a high error probability appears under similar conditions, it will remind the system to switch to a more stable setting or reduce the communication rate in time. Doing so not only reduces the probability of communication failure under large load switching, extreme temperature or high interference conditions, but also provides data support for the subsequent combination of device characteristic mapping tables to achieve more accurate clock phase, drive strength, sampling point and other parameter tuning. In other words, the bus characteristic mapping table gives the system the ability to perform adaptive regulation in a dynamic environment, greatly improving the reliability of SPI communication and the stability of long-term operation.

[0095] Please continue reading Figure 1, determining initial clock parameters based on the bus characteristic mapping table, sending self-test instruction sequences to target devices of different batches, collecting device response data, associating and marking the device response data with the environmental parameter data, and generating a device characteristic mapping table;

[0096] In one embodiment of the present invention, the initial clock parameters are determined based on the bus characteristic mapping table, self-test instruction sequences are sent to target devices of different batches, device response data is collected, the device response data is associated and marked with the environmental parameter data, and a device characteristic mapping table is generated, including: according to the voltage data and temperature data in the bus characteristic mapping table, multiple groups of clock frequency, polarity and phase combinations are screened to generate an initial clock parameter set; based on the initial clock parameter set, identification instructions and status reading instructions are sent to target devices of different batches, the first round of device response data is collected, and access delay data under different voltage levels and temperature ranges is recorded; according to the first round of device response data and the access delay data , sending register test instructions and storage unit read and write instructions to different batches of the target devices, and collecting the second round of device response data; based on the second round of device response data, sending data alternation test instructions to different batches of the target devices under different power supply states, and collecting the third round of device response data; sending timing boundary test instructions to different batches of the target devices, recording data latch timing parameters, and collecting the fourth round of device response data; merging the first round of device response data, the second round of device response data, the third round of device response data, and the fourth round of device response data to obtain device response data; associating and marking the device response data with the environmental parameter data to generate a device characteristic mapping table.

[0097] Specifically, when screening multiple sets of clock frequency, polarity and phase combinations based on the voltage data and temperature data in the bus characteristic mapping table, it is first necessary to find the record closest to the current temperature and voltage from the bus characteristic mapping table. The mapping table saves the waveform distortion or interference peak information that may appear under each temperature segment (such as -20℃ to 0℃, 0℃ to 40℃, 40℃ to 85℃, etc.) and multiple voltages (such as 9V, 12V, 24V, 36V, etc.), and marks which frequencies, phases and polarities are more stable based on the sampling results obtained from the previous pulse excitation. By screening in this way, parameter combinations that are prone to significant distortion within the corresponding temperature or voltage range can be quickly excluded, and a set of initial clock parameter sets can be obtained for subsequent access to the device. For example, if the mapping table shows that at 24V and 25°C, the combination of a clock frequency of 20MHz, polarity of CPOL=0, and phase of CPHA=1 has low noise and small overshoot, then when the device operating temperature is approximately 20°C to 30°C and the power supply is maintained at around 24V, this combination is expected to become one of the candidates in the initial clock parameter set.

[0098] After obtaining this set of initial clock parameters, identification instructions and status read instructions can be sent to different batches of target devices to obtain the first round of device response data. The identification instruction is used to read the manufacturer ID or version number inside the device, and the status read instruction can check whether the device is in special states such as busy, write protected, or erasing in progress. The implementation process can send commands such as "manufacturer ID read" or "device information read" to the target device through the SPI controller (for Flash devices, it can be 0x9F or 0x90 and other instructions). The oscilloscope or logic analyzer is used to observe whether the returned data frame has invalid bits or too long delays. If the speed of returning information from a batch of devices is significantly slower at low temperatures, its behavioral characteristics under specific temperature and voltage conditions can be confirmed in the first round of access delay records, providing a reference for subsequent in-depth testing.

[0099] Based on the first round of device response data and access delay data, register test instructions and storage unit read and write instructions can be further sent to target devices of different batches to collect the second round of device response data. Register test instructions generally involve writing and reading certain sensitive registers of the device. If the data is inconsistent or there is no response for a long time when reading after writing, it means that the device is potentially incompatible with the current clock or phase. When the storage unit read and write instructions are directed to the storage chip, a small capacity data write and verification read will also be performed to observe whether bit flipping or excessive delay occurs. Assuming that a batch of Flash performs normally in a 0°C environment, but there are multiple write failures or error codes above 40°C, these abnormal phenomena will be recorded in the second round of response data, thereby determining that this batch of devices has more stringent requirements for clock configuration at high temperatures.

[0100] After obtaining the second round of device response data, data alternation test instructions can be sent to the target device under different power supply states to collect the third round of device response data. This step is intended to simulate the voltage fluctuations that occur when the power supply bus is under high and low load peaks or frequently switched. If there is an instantaneous voltage drop of 5V to 10V between the opening and closing of high-power equipment on the industrial site, the SPI controller can be allowed to alternately write a set of predefined data patterns (such as 1010 1010 or 0101 0101) to the target device during this period, and perform verification and reading immediately after writing. If it is found that some devices have obvious read and write timeouts or verification errors during this period of large voltage fluctuations, it means that a more conservative clock frequency or a wider sampling window is required in this power supply state.

[0101] Sending timing boundary test instructions to target devices of different batches, recording data latch timing parameters, and then collecting the fourth round of device response data can further clarify the communication capabilities of each batch of devices under extreme conditions. The implementation method usually includes letting the SPI controller slightly change the clock phase or sampling edge to gradually approach the device to its extreme latch window. If the device error frequency increases significantly after shifting to a certain critical phase, then the critical phase can be recorded as the edge of the "safety margin". Summarizing this type of boundary data, it can be found that the "safety phase margin" of devices from different batches has different deviations. Some devices may still be normal when the phase lags by 1 / 4 clock cycle, while others will crash when they lag by only 1 / 8 clock cycle. By incorporating this critical information into the fourth round of device response data, targeted protection or sufficient transfer time can be reserved for subsequent high loads and multiple devices in parallel.

[0102] After this series of tests, the first, second, third and fourth rounds of device response data are combined to obtain a more detailed device response data. Its content covers the access delay generated in the recognition instruction and status reading stage, the error conditions in the register and storage unit operation stage, the data alternating reading and writing results under power supply fluctuations, and the timing window obtained by the extreme boundary scan. By associating and marking these device response data with environmental parameter data (temperature, voltage, interference intensity, etc.), a device characteristic mapping table can be generated to clearly present the specific performance of each batch of devices under different working conditions, different instruction modes and different clock configurations. For example, the error rate of a batch of Flash at 30℃, 24V power supply, and phase CPHA=1 is only 0.1%, but under the same conditions, if the voltage drops to 18V, the error rate will soar to 5%. Such differences will be significantly marked in the device characteristic mapping table. If the subsequent SPI controller detects that the voltage is in the 18V range and the temperature rises to 30℃, it will automatically switch to a safer clock or phase combination.

[0103] The essential significance of this process is that each batch and each series of devices are subjected to hierarchical and progressive testing under typical industrial environments and multiple access instructions, and finally a device characteristic mapping table based on a large amount of measured data is formed. Because this mapping table already covers key links such as identification instructions, register operations, storage reading and writing, and extreme phases, it can more accurately match the current optimal access mode during actual communication. If a new batch of devices is added to the same SPI bus in the future, a mapping can also be quickly generated through similar tests to further expand the support for parallel access to multiple devices. In this way, industrial systems can maintain a high success rate and throughput under high loads, harsh environments, or multiple interference conditions, making the coexistence of various batches and types of memory or sensors a feasible and stable solution.

[0104] Please continue reading Figure 1 , determining intermediate configuration parameters based on the device characteristic mapping table and the bus characteristic mapping table, collecting configuration verification data, adjusting clock phase parameters and data sampling parameters according to the configuration verification data, and generating transition configuration data;

[0105] In one embodiment of the present invention, the intermediate configuration parameters are determined based on the device characteristic mapping table and the bus characteristic mapping table, configuration verification data is collected, and clock phase parameters and data sampling parameters are adjusted according to the configuration verification data to generate transition configuration data, including: based on the access delay data in the device characteristic mapping table and the waveform response data, voltage data, and interference intensity data in the bus characteristic mapping table, multiple groups of combination parameters of clock frequency, phase, and sampling point are screened to generate intermediate configuration parameters; based on the intermediate configuration parameters, burst read and write test signals are sent to different batches of the target devices during the process of dynamically switching the working state of the industrial equipment. Instructions, collect the first round of configuration verification data; according to the first round of configuration verification data, adjust the clock phase parameters in sections during the power supply voltage fluctuation process, and collect the second round of configuration verification data; based on the second round of configuration verification data, adjust the data sampling parameters in sections during the power supply load mutation process, and collect the third round of configuration verification data; merge and analyze the bit error rate data and timing jitter data in the first round of configuration verification data, the second round of configuration verification data, and the third round of configuration verification data to obtain configuration verification data; according to the configuration verification data, gradient adjust the clock phase parameter and the data sampling parameter to generate transition configuration data.

[0106] Specifically, when screening multiple sets of combination parameters of clock frequency, phase and sampling point according to the access delay data in the device characteristic mapping table and the waveform response data, voltage data and interference intensity data in the bus characteristic mapping table, it is necessary to first cross-check the device access delay information obtained in the previous test process with the mapping information characterizing the overall physical and environmental characteristics of the bus. The device access delay data can reflect the degree of sensitivity of a target device to clock speed and phase under different instruction operations, while the waveform response data, voltage data and interference intensity data can show whether the SPI bus can maintain stable transmission under specific environmental conditions. If the device characteristic mapping table shows that a batch of Flash requires a longer preparation time at 25°C and 24V (such as a significant increase in access delay), and the bus characteristic mapping table also indicates that the distortion is small when supporting medium frequency in a 24V, low interference environment, then in the end, among the multiple sets of clock frequency, phase and sampling point combinations, the "medium clock frequency + moderate phase offset" solution can be preferred to form a set of preliminary intermediate configuration parameters to balance speed and stability in most cases.

[0107] Based on the intermediate configuration parameters, burst read and write test instructions are sent to different batches of target devices during the process of dynamically switching the working state of industrial equipment, which can evaluate whether these parameters maintain the expected performance under a real and drastically fluctuating operating environment. During implementation, the SPI controller can continuously initiate several batch read and write operations to the target device, and monitor the stability of data reception and transmission during the switching of the device's working state (for example, the motor changes from light load to heavy load). The first round of configuration verification data usually includes the real-time number of bit errors, operation success rate, and transmission delay recorded during this burst read and write process. If a certain combination of parameters is found to have a high error rate at this time, it may mean that the combination is not stable enough under dynamic conditions and needs to be further segmented or gradient adjusted in subsequent steps.

[0108] According to the first round of configuration verification data, segmented adjustment of the clock phase parameters during the power supply voltage fluctuation can help the system explore how the regional sensitive parameter "clock phase" affects the correctness of reading and writing during the fluctuation stage. Segmented adjustment refers to the refinement of the originally fixed phase parameters into multiple adjustable intervals, and setting different phase offset values ​​at the beginning, middle, and end of the voltage fluctuation. If the first round of configuration verification data shows that a phase originally used has continuous bit errors when the power supply drops suddenly, a safer offset phase can be enabled during this period. The second round of configuration verification data will record the reading and writing results of these segmented phases during the voltage fluctuation process. If the bit error rate is significantly reduced or the operation delay remains stable, it can be shown that the segmented adjustment idea is effective.

[0109] After obtaining the second round of configuration verification data, the data sampling parameters are adjusted in segments based on the data during the power supply load mutation process, which can further improve the data sampling stability during high-load switching. Assuming that the power supply ripple increases due to a rapid load increase, the rising and falling edges of the bus waveform may also shift. At this time, if the sampling point is still fixed in the original position, the probability of error code will increase. By fine-tuning the sampling point forward or backward in a segmented manner, the third round of configuration verification data can be collected in the test, including the bit error rate or timing jitter value in the high-load mutation interval. If the bit error rate drops significantly after adjustment, it means that the new sampling point has stronger robustness in high-load situations, which lays the foundation for the subsequent practical application of the system.

[0110] The bit error rate data and timing jitter data in the first round of configuration verification data, the second round of configuration verification data, and the third round of configuration verification data are combined and analyzed. The configuration verification data obtained can reveal which group of clock phase and sampling point combinations have the least bit errors and the smallest jitter under specific industrial disturbance conditions. The analysis process can be carried out by marking the bit error distribution on the two-dimensional plane between the phase and the sampling time, and finding the optimal landing point in multiple verification data. If a combination maintains a low number of bit errors and a small jitter fluctuation at different stages, it can be used as a candidate for subsequent core parameters.

[0111] Finally, the clock phase parameters and data sampling parameters are adjusted in a gradient according to the configuration verification data, and transition configuration data is generated, so that a relatively smooth evolution path can be achieved. In this process, when approaching a better phase or sampling area, a small step or segmented interpolation method is adopted to ensure that a new unstable interval will not be caused by a one-time crossing. If there are still intermittent jitters or high bit errors at certain critical points, they will be recorded in the log so that they can be promptly rolled back or fine-tuned again in subsequent communication operations. Such an idea of ​​"segmented adjustment, comprehensive analysis and final gradient correction from multiple sets of combined parameter screening, burst read and write verification, voltage fluctuation and load mutation occasions" can coordinate the balance between power supply, load and communication requirements in complex industrial sites, so that the SPI bus can gradually adjust the clock phase and sampling window even in the event of motor startup, high-power switching or deep sleep wake-up, and finally achieve the communication goal of high stability and high efficiency. Through such transition configuration data, the system can still quickly enter the safe mode when encountering extreme environments or abnormal loads in the later stage, and can maintain higher throughput and lower latency in normal state.

[0112] In one embodiment of the present invention, the step of performing gradient adjustment on the clock phase parameter and the data sampling parameter according to the configuration verification data to generate transition configuration data includes: performing a step-down scanning on the clock phase parameter according to the bit error rate data in the configuration verification data to generate phase step data; performing a multi-point sampling test on the clock phase parameter based on the phase step data, recording a sampling stability interval, and generating phase window data; performing an offset test on the sampling points of the data sampling parameter according to the phase window data to generate sampling offset data; performing an interpolation test on the data sampling parameter in the sampling stability interval based on the sampling offset data to generate sampling optimization data; setting a protection boundary for the clock phase parameter according to the timing jitter data in the configuration verification data and the sampling optimization data to generate phase protection data; setting a dynamic adjustment range for the data sampling parameter based on the phase protection data to generate sampling restriction data; and associating and marking the phase protection data with the sampling restriction data to generate transition configuration data.

[0113] Specifically, when the clock phase parameters are scanned in decreasing steps according to the bit error rate data in the configuration verification data, a set of basic clock frequencies and initial phases can be determined first, so that the system can perform short or fast read and write instruction tests at this phase to obtain the initial bit error rate. Then, the system starts to make several small steps forward or backward based on this phase. The initial step can be set slightly larger (for example, 2 degrees or 5 degrees) to quickly explore the available range of the phase. When a significant increase in the bit error rate or a significant increase in the read and write delay is detected, it means that the phase limit is approaching, and then the step will gradually decrease to 1 degree or 0.5 degree, making the scan more precise. At this time, each step point will execute a small section of the test instruction, and record the bit error results and delay information to generate phase step data. Through this process, not only can the high-risk areas that appear when the phase offset is large be confirmed, but also in which sections the bit error rate shows a steady decline or remains at a low value can be determined.

[0114] Based on the phase step data, the purpose of performing multi-point sampling tests on the clock phase parameters is to obtain more realistic high-load or long-frame communication performance at different phase points. The system can select several discrete phase points within the identified "available interval" and perform relatively intensive burst reads and writes or large data volume instruction interactions on the target device to observe whether a low error rate can be maintained in such a high-stress scenario. If a phase point still only produces a very small amount of error code or jitter after a large amount of data is written, it means that the vicinity of this phase point is more stable and can be marked as a "sampling stable interval" and such information can be saved in subsequent phase window data. Taking some Flash devices as an example, if the phase maintains a bit error rate of 0.1% between +4 degrees and +7 degrees, and instantly rises to 1% when it exceeds +7 degrees, a relatively safe phase window will be defined in this area.

[0115] When performing an offset test on the sampling points of the data sampling parameters according to the phase window data, it is necessary to fine-tune the sampling edge or sampling timing within these confirmed phase safety intervals. Specifically, the phase can be fixed at +5 degrees first, and the sampling point can be gradually moved back or forward at different positions along the clock cycle to see which sampling position can capture a more complete signal upper / lower edge during high-speed operation. If the bit error rate drops significantly after an offset of 2ns, it can be noted in the record that this offset has significant optimization value, thereby generating sampling offset data. Subsequently, based on the sampling offset data, an interpolation test is performed in the sampling stable interval, which allows the system to make the offset value step finer, for example, from 1ns to 0.5ns or 0.2ns, to ensure accurate positioning near the optimal sampling position. After completing this step, the obtained sampling optimization data can be clearly presented: "Under this device and the current phase, if the sampling point is moved to a certain interval, the bit error rate can be reduced to the ideal level again."

[0116] After obtaining the sampling optimization data, the protection boundary of the clock phase parameters is set against the timing jitter information in the configuration verification data to generate phase protection data, which can prevent the system from accidentally exceeding the safety range when encountering a power drop or high interference. If it is detected that some phase points will experience a sharp increase in jitter as the temperature rises or the voltage fluctuation intensifies, the boundary can be tightened to a slightly safer +6 degrees, and the phase is not allowed to cross to +7 degrees or higher at will. In this way, if there is a peak in power consumption or mechanical vibration in the subsequent industrial process, the controller can automatically fall back to the phase value within the protection boundary to reduce the risk of large-scale code errors. Based on the phase protection data, a dynamic adjustment range is set for the data sampling parameters, so that the sampling point can automatically retreat or advance a certain amount in extreme cases (such as interference peaks or sharp load surges), avoiding communication collapse due to the sampling point being too rigid at the critical moment. Finally, by associating the phase protection data with the sampling limit data to generate transition configuration data, high-efficiency and high-speed communication parameters can be retained under normal loads, while also laying the foundation for quickly switching to safer phases and sampling windows in extreme cases.

[0117] Compared with only doing preliminary tests and solidifying parameters at one time, this phased, step-by-step, and interpolation-based parameter adjustment process helps maintain stable communication throughout the entire operation cycle of industrial equipment: if the peripheral environment is detected to be close to critical, the system will first retrieve the phase protection data to prompt that the phase should avoid the critical area; if interference is detected or the voltage drop deteriorates further, the sampling limit data can adjust the sampling position in real time to prevent entering the high error range. In this way, the SPI bus has both high-speed mode and safety redundancy, so that large-scale data loss or communication collapse will not easily occur under extreme conditions, and the potential of devices and lines can be maximized under normal conditions to achieve stable transmission with high throughput.

[0118] Please continue reading Figure 1 , based on the transition configuration data, obtaining interference event data and voltage monitoring data, performing waveform adjustment on the clock signal, recording result data of the waveform adjustment, and generating interference suppression data;

[0119] In one embodiment of the present invention, the method of acquiring interference event data and voltage monitoring data based on the transition configuration data, performing waveform adjustment on the clock signal, recording the result data of the waveform adjustment, and generating interference suppression data includes: monitoring the relay action signal, power switch signal, and motor start / stop signal of the industrial equipment according to the transition configuration data to generate interference event data; sampling the voltage fluctuation at the power input end based on the interference event data to generate voltage monitoring data; pre-adjusting the clock signal before the interference event occurs according to the interference event data and the voltage monitoring data to generate pre-adjustment parameter data; performing segmented smoothing on the rising and falling edges of the clock signal based on the pre-adjustment parameter data to collect the first round of waveform adjustment data; performing multi-level adjustment on the driving strength of the clock signal according to the first round of waveform adjustment data to collect the second round of waveform adjustment data; merging the first round of waveform adjustment data and the second round of waveform adjustment data to obtain the result data of the waveform adjustment; associating and marking the result data of the waveform adjustment with the interference event data and the voltage monitoring data to generate interference suppression data.

[0120] Specifically, when monitoring the relay action signals, power switch signals and motor start-stop signals of industrial equipment according to the transition configuration data, it is necessary to pre-configure a specific signal detection mechanism in the controller or monitoring module to capture the action moments of these key devices. For example, in some high-power occasions, relay closure or motor start-up often produces instantaneous high-amplitude interference. By collecting these action signals from external pins or fieldbuses, they can be recorded in chronological order and associated with the current operating status to form interference event data. If on a production line, the motor frequently switches from no-load to full-load, the event will be detected multiple times and marked as a "motor start-stop event." In this way, the system can accurately know when a large electromagnetic pulse or a sharp voltage fluctuation may occur.

[0121] Based on the interference event data, when sampling the voltage fluctuation at the power input end, a high-speed sampling line or voltage monitoring module can be configured at the bus or power access point to observe the voltage change curve over time. Whenever the triggering moment of the relay action signal or the motor start and stop signal is detected, the system will increase the sampling frequency for a period of time before and after to capture more subtle voltage transient drops or spikes. If the voltage is observed to drop rapidly from 24V to 18V after a power switch action, and then rise back to 22V within hundreds of milliseconds, the process can be recorded as voltage monitoring data. The significance of this is to let the controller understand the amplitude and duration of power supply fluctuations under different types of interference events, and leave a corresponding buffer when adjusting the clock later.

[0122] The process of pre-adjusting the clock signal before the interference event occurs based on the interference event data and the voltage monitoring data is intended to reduce the impact of interference on communication. If the interference event data indicates that the motor is about to start in a few milliseconds, and the voltage monitoring data shows that this action often causes a significant voltage drop or high-frequency coupling, the controller will make necessary pre-adjustments to the clock signal before the start occurs and generate pre-adjustment parameter data. This pre-adjustment can include lowering the clock frequency by one gear or slightly shifting the phase backward to avoid serious waveform distortion when the interference peak arrives at the same time as the clock edge. In this way, as long as the sign of "the motor start-stop signal is about to arrive" is detected, the controller can complete the appropriate correction of the SPI clock within the millisecond idle window.

[0123] Based on the pre-adjustment parameter data, when the rising and falling edges of the clock signal are segmented and smoothed, it is generally necessary to implement segmented modulation of the clock edge at the hardware layer or FPGA area, so that the clock edge is no longer a simple steep rise or fall, but is divided into several small stages to gradually switch levels. For example, if the rising edge originally completes the amplitude jump within 1ns, it can jump to 40% in the first stage, 70% in the second stage, and finally to 100%, so that overshoot can be reduced when significant interference occurs. The first round of waveform adjustment data contains the clock waveform collected under this segmented smoothing condition, including the peak amplitude, edge velocity distribution, and whether there is still sudden distortion when interference arrives. If the data shows that the distortion is significantly reduced, it means that this step has played a positive role in industrial interference suppression.

[0124] According to the first round of waveform adjustment data, when the drive strength of the clock signal is adjusted in multiple levels, attention should be paid to whether the clock output needs to further reduce or increase the drive current to take into account long-distance transmission and interference suppression. If the waveform adjustment data shows that there is still a high overshoot or undershoot after segmented smoothing, the drive strength can be lowered by one gear to observe whether it can better alleviate the interference. At the same time, it is also necessary to prevent the drive from being too weak, causing the signal edge speed to drop too much, which will bring new bit error probability. The second round of waveform adjustment data is composed of the observation results of this stage. If the distortion is indeed reduced at a lower drive strength and the communication speed is not significantly affected, it can be considered that this gear is an ideal choice for motor startup.

[0125] Finally, after merging the first round of waveform adjustment data and the second round of waveform adjustment data, the result data of the waveform adjustment can be obtained, and these results are associated with the interference event data and the voltage monitoring data to generate interference suppression data. The interference suppression data clearly shows how effective the segmented smooth clock edge and multi-level drive strength adjustment are in reducing the error rate and jitter amplitude before or during the triggering of certain interference events. By further cross-checking with the previous transition configuration data, the system can quickly load the optimal waveform adjustment strategy when the same or similar events are detected subsequently, thereby achieving efficient and stable SPI communication. Not only that, when new interference patterns appear, they can also be recorded in the interference suppression data, providing a useful reference for subsequent iterations or new devices.

[0126] In one embodiment of the present invention, the clock signal is pre-adjusted before the interference event occurs based on the interference event data and the voltage monitoring data to generate pre-adjustment parameter data, including: extracting features of the relay action signal, power switch signal and motor start and stop signal in the interference event data, and generating interference prediction data in combination with the voltage monitoring data; determining the occurrence time of the interference event based on the interference prediction data, and pre-adjusting the clock signal within the reserved time before the interference event occurs to generate adjustment timing data; and time-aligning the adjustment timing data with the interference prediction data to generate pre-adjustment parameter data.

[0127] Specifically, when extracting features from relay action signals, power switch signals, and motor start / stop signals in interference event data, it is necessary to extract key factors that may affect clock stability for these different types of trigger sources. Specifically, the relay action signal can be marked with a timestamp and the actual length of time it is closed or disconnected can be recorded; then the power switch signal can be sampled to obtain transient effect indicators caused by it at the moment of connection or disconnection (for example, whether a voltage drop occurs after connection, whether a reflective spike is generated after disconnection); for motor start / stop signals, a wider range of timing features should be collected, such as the time to reach the rated load at start-up, the inertia consumption time when stopping, etc. Combining these trigger source features with voltage monitoring data, it is possible to further determine the voltage drop amplitude, peak size, and duration associated with each type of trigger event. By integrating this information together, a "interference prediction data" can be formed to quantify and record the typical features of different interference events (such as response time and peak intensity).

[0128] According to the interference prediction data, the possible time of occurrence of interference events can be determined more accurately. For example, if it is monitored in the early stage that it takes 1.5 seconds for the motor to go from no-load to full-load, and a voltage drop often occurs at 0.5 seconds, then the interference prediction data will give the conclusion that "voltage attenuation or harmonic jump may occur around 0.5 seconds after the motor start and stop is triggered." Subsequently, the system calculates the time point when the interference is about to come based on this conclusion, so as to pre-adjust the clock signal within the reserved time before the interference event occurs, and finally generate the adjustment timing data. The so-called "reserved time" can be tens of milliseconds or shorter, as long as the controller can complete the corresponding revisions to the clock phase, frequency, drive strength, etc. before the interference peak arrives. In this way, the communication will not be directly impacted by instantaneous overshoot or voltage drop at the most dangerous moment, greatly reducing the bit error rate.

[0129] After completing the above timing prediction and pre-adjustment, it is necessary to time-align the adjustment timing data with the interference prediction data to generate pre-adjustment parameter data. Time alignment refers to the precise matching of "when to start clock pre-adjustment" and "when the interference arrives approximately": if it is inferred from the interference prediction data that the motor will experience a load jump after 500 milliseconds, then the adjustment timing data must ensure that the frequency or phase switching is completed in advance within these 500 milliseconds, and leave enough idle frames or delays to avoid a head-on collision with the interference peak. By recording these alignment processes and writing pre-adjustment parameter data, the system can quickly reuse this set of verified "pre-adjustment schemes" when encountering similar scenarios without having to test any intermediate configurations from scratch again. In other words, the SPI clock is kept in a relatively safe or smoother state before the interference arrives, so that even if there is a voltage drop or harmonic shock, it will not directly disrupt the timing synchronization or cause batch errors. With the help of such a prediction and alignment process, the SPI bus can also perform adaptive parameter adjustment more flexibly when facing complex power events in industrial sites, and the stability is greatly improved.

[0130] Please continue reading Figure 1 , based on the interference suppression data and the device characteristic mapping table, statistically processing the bit error rate data and delay data of the target device to generate device aging trend data;

[0131] In one embodiment of the present invention, the bit error rate data and delay data of the target device are statistically processed based on the interference suppression data and the device characteristic mapping table to generate device aging trend data, including: determining timing boundary parameters according to the waveform adjustment result data in the interference suppression data and the access delay data in the device characteristic mapping table to obtain initial delay data; performing timing margin tests on the read and write operations of the target device based on the initial delay data, and collecting current delay data and current bit error rate data; statistically analyzing the delay variation data of the target device under different power supply voltages and temperature conditions according to the initial delay data and the current delay data to generate delay statistical data; statistically analyzing the bit error distribution data of the target device under different working conditions based on the current bit error rate data to generate bit error statistical data; performing time domain distribution analysis on the delay statistical data to obtain delay degradation data; performing spatial distribution analysis on the bit error statistical data to obtain bit error degradation data; associating the delay degradation data with the bit error degradation data to generate device aging trend data.

[0132] Specifically, when determining the timing boundary parameters based on the waveform adjustment result data in the interference suppression data and the access delay data in the device characteristic mapping table, it is necessary to first compare the bit error rate and read and write delay conditions collected under different interference protection measures (such as adjusting the clock edge, drive strength or segmented smoothing). Specifically, you can retrieve the waveform adjustment records in the interference suppression data to see which configurations still maintain low delays and errors during high interference periods, and at the same time, combined with the access delay information listed in the device characteristic mapping table (such as the time required for erase and write operations, address decoding delays, etc.), identify the "timing boundary" close to the critical failure of the device. If it is found that a certain combination only has a surge in access delay after a large voltage fluctuation or a significant increase in temperature, it can be preliminarily determined that this is one of the critical points, and the corresponding parameters and delay data are packaged and stored in the "initial delay data".

[0133] After obtaining the initial delay data, the timing margin test of the read and write operations of the target device can be performed based on the data to evaluate whether this "near the critical point" is still stable during large-scale reading and writing or long-term operation. During implementation, the system can be allowed to repeatedly perform write, read or erase operations under the critical parameters to observe whether the bit error rate and operation time show a steep rise or jitter. If the test results show that under certain voltage and temperature combinations, the device delay is only slightly higher than the initial data, and the bit error rate remains at an acceptable level, it means that the device still has a certain margin; if the bit error rate soars rapidly, or even a long period of busyness or data loss occurs, it proves that the device limit has been reached, and a conservative strategy needs to be taken in time. The current delay data and current bit error rate data collected at this stage will provide raw materials for subsequent delay statistics and bit error statistics.

[0134] Based on the initial delay data and the current delay data, the target device can be compared longitudinally under different power supply voltage and temperature conditions, and delay statistics can be generated. This can include repeatedly recording the time required for the device to perform the same type of read and write operations at representative temperature points such as -40°C, 25°C, and 85°C, as well as major voltage points such as 12V, 24V, and 36V, and comparing it with the data from the initial test. If the write delay does not increase significantly at 25°C, but suddenly increases significantly at 85°C, it can be inferred that the device will approach its timing limit faster in a high temperature environment, thereby accelerating the degradation process. Ultimately, the system will summarize the differentiated performance of these delays into delay statistics to show the changing trend of delay time under different temperature and voltage combinations.

[0135] When summarizing the current bit error rate data of the device, the bit error rate can be counted for different working states (such as continuous large block reading, frequent small block writing or high-frequency erasing) to form bit error statistics. If it is found that the bit errors are concentrated in a certain state, but are relatively rare in other states, it means that the device is particularly fragile in this state or is more sensitive to clock phase and voltage fluctuations. For example, some Flash devices have a higher tolerance when writing, but are more prone to bit flipping when reading quickly, or vice versa. By distinguishing these states, the bit error statistics can better reflect the performance differences of the device in different operating modes.

[0136] Subsequently, the delay statistics data can be analyzed for time domain distribution to obtain delay degradation data. The so-called time domain distribution analysis is to track multiple measurement results of the same device during long-term use, align its delay evolution curve with the time axis, and observe whether there is a phased mutation or a slowly rising trend. If the delay of the device is stable in the first two months, but suddenly increases significantly after three months, it means that it may have entered the accelerated aging stage, while if the delay increases gently, it means a more gradual degradation mode. Performing spatial distribution analysis on the error statistics data can obtain error degradation data. Spatial distribution here usually refers to the storage address area or different chip areas inside the device. If the same batch of devices has high-density errors on a certain Flash address, while other address areas are basically normal, then it can be preliminarily locked that the address may face more severe wear or threshold drift.

[0137] Finally, the delay degradation data is associated with the error degradation data to generate device aging trend data. In this way, the system will have a clear "timing-error" evolution diagram, which can quickly determine whether the degradation of the device is deepening under high temperature, high load or severe voltage fluctuations. When the degradation index of a device crosses the set threshold in the chart, the system can enable a safer clock or increase the data sampling margin in the next cycle of automatic parameter adjustment to avoid subsequent batch transmission failures or data errors. At the same time, it can also provide operation and maintenance personnel with suggestions for hardware replacement or partition maintenance to prevent sudden large-scale failures in important industrial processes. By gradually tracking the evolution of delays and errors in this way, the SPI controller can maintain stability and reliability for a longer period of time in an industrial environment.

[0138] Please continue reading Figure 1 , based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data, the plurality of target devices are grouped based on device characteristic similarity, timing parameter sharing is performed within the group, parallel access control is performed, and access status records are generated.

[0139] In one embodiment of the present invention, based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data, the plurality of target devices are grouped based on the similarity of device characteristics, timing parameter sharing is performed within the group, parallel access control is performed, and access status records are generated, including: matching the manufacturing batches and aging states of the plurality of target devices according to the delay degradation data in the device aging trend data and the access delay data in the device characteristic mapping table to generate batch characteristic data; based on the batch characteristic data and the waveform response data in the bus characteristic mapping table, similarity calculation is performed on the timing parameters of the target devices in different temperature ranges to generate timing similarity. data; according to the timing similarity data, the response characteristics of the target device under different voltage fluctuation conditions are classified to obtain a device grouping scheme; based on the device grouping scheme, the clock phase parameters and sampling timing parameters in the transition configuration data are allocated to the target devices in the group to generate intra-group shared parameters; according to the intra-group shared parameters, the access priority of each group is dynamically adjusted when the working state of the industrial equipment is switched to generate inter-group arbitration data; based on the inter-group arbitration data, the target device in the group is executed with staggered access scheduling, the access conflict data in each time window is recorded, and parallel access data is generated; the parallel access data is associated with the intra-group shared parameters to generate an access status record.

[0140] Specifically, when matching the manufacturing batches and aging states of multiple target devices according to the delay degradation data in the device aging trend data and the access delay data in the device characteristic mapping table, it is necessary to first associate the delay degradation data with the manufacturing batch information of each device, and identify the commonalities of the devices in the same batch in indicators such as the delay attenuation curve and the bit error rate growth rate. For example, if some devices are in the same manufacturing batch and have a write delay increase from 0.2ms to 0.5ms under similar high temperature environments, it can be preliminarily determined that their aging characteristics have a consistent evolution path. Combined with the initial access delay data or batch write and read delay values ​​in the device characteristic mapping table, it is possible to better lock in whether these devices have reached a certain attenuation critical point in normal operation. By comparing the delay degradation data with the manufacturing batch and initial access delay information, the system can generate "batch characteristic data", which summarizes and describes the devices of the same batch with similar aging performance.

[0141] Based on the batch characteristic data and the waveform response data recorded in the bus characteristic mapping table, the timing parameters of the target device can also be similarly calculated in different temperature ranges to generate timing similarity data. The specific approach is to divide the temperature range into several levels (such as -40℃ to 0℃, 0℃ to 40℃, 40℃ to 85℃, etc.), and compare the waveform response data and the access delay and interference tolerance of the device in each temperature level to find a device group with smaller differences. For example, if two Flashes also show a 10% increase in access delay in the range of -20℃ to 0℃, and the reflection peak and bit error rate change curves in the waveform response data are similar, this means that their aging progress and sensitivity to temperature changes are similar, and they can be recorded as high similarity in the timing similarity data. If the bit error rate of another Flash increases sharply in the same temperature range, it will be judged to be less similar to the former.

[0142] Based on this timing similarity data, the response characteristics of each target device under different voltage fluctuation conditions can be classified, and finally the device grouping scheme can be obtained. Voltage fluctuation conditions can include 12V voltage regulation, 24V load fluctuation, 36V high voltage range and other scenarios. If the device access performance continuously collected in each scenario is also consistent, it can be further confirmed that they have similar timing boundaries and read and write delays in high-voltage mode or severe voltage drop. In this way, devices with high similarity can be grouped into the same group to facilitate subsequent scheduling and parameter allocation. If some devices can still maintain a low bit error rate under high load and low voltage, while other devices perform very poorly, they will be divided into different groups to avoid using inconsistent parameter adjustment schemes in the same group.

[0143] With the device grouping scheme, the system can assign the clock phase parameters and sampling timing parameters in the transition configuration data to the target devices of each group based on the principle of "consistent characteristics within the group", thereby generating shared parameters within the group. The transition configuration data often contains a variety of clock phases, sampling points, and pre-adjustment and protection interval information for drive strength. If the devices in this group need to slightly shift the phase when the motor starts and stops, or it is appropriate to reduce the sampling frequency after the temperature rises to 40°C, then they can be uniformly configured in the shared parameters within the group without having to switch each device individually. Doing so can reduce the redundancy of access switching within the group, and can also significantly reduce conflicts and delays during high-interference periods such as switching of working states of industrial equipment.

[0144] According to the intra-group shared parameters, the access priority of each group is dynamically adjusted when the device is switched or the load is transferred, and inter-group arbitration data will be generated. Dynamic adjustment means that when the external device detects that the device in a group is at the peak of writing or the group is most sensitive to temperature and voltage, the access priority of the group can be increased to ensure that they complete the communication first and avoid cumulative errors in complex environments; conversely, when the similarity characteristics of the devices contained in another group indicate that they are still stable in a large fluctuation environment, their priority can be slightly lowered to make way for more vulnerable devices. This inter-group arbitration data will be recorded in the system scheduling module to clarify which group should receive the SPI access time slot first at the current moment and which group can wait for a while before performing read and write operations.

[0145] Finally, based on the inter-group arbitration data, interleaved access scheduling is performed on the target devices in the group, access conflict data in each time window is recorded, and parallel access data is generated. When multiple devices need to compete for the SPI bus in the same time window, the access order is determined according to the priority set in the inter-group arbitration, and time slots are allocated in an interleaved manner to avoid large-scale collisions or crosstalk. The system will record several indicators in this process: for example, how many clock cycles each device is delayed in the current time window to obtain access rights, or whether the actual bit error rate increases. If there are too many conflicts, they can be fine-tuned and improved in the next round of scheduling. After the parallel access data is associated with the shared parameters in the group, an access status record can be generated, which fully reflects the interaction of each group device in a high load or harsh environment within a certain period of time. This access status record is of great significance for evaluating whether the current grouping strategy is efficient and whether further merging or splitting of groups is needed, and it also provides a solid data foundation for subsequent parameter optimization.

[0146] In one embodiment of the present invention, based on the inter-group arbitration data, interleaved access scheduling is performed on the target devices in the group, access conflict data in each time window is recorded, and parallel access data is generated, including: according to the inter-group arbitration data, time slots are allocated to the target devices in the group, anti-collision intervals are set between adjacent time slots, and time slot allocation data is generated; based on the time slot allocation data, interleaved read and write access is performed on the target devices in the time window, access timing parameters and conflict counts in the group are recorded, and access monitoring data is generated; time-related analysis is performed on the conflict counts and timing parameters in the access monitoring data, and anti-collision intervals and interleaved scheduling schemes are generated to obtain parallel access data.

[0147] Specifically, when allocating time slots to the target devices in the group according to the inter-group arbitration data, it is necessary to first decompose the overall available communication time slots into several smaller time slots according to the priorities and access requirements of different groups, and then allocate these time slots to the target devices in each group in sequence. The purpose of this is to allow the devices in the same group to monopolize the SPI bus resources in their exclusive time slots without having to generate access conflicts with other groups or other devices. In order to improve robustness, it is also necessary to set anti-collision intervals between adjacent time slots to avoid the problem of unfinished data transmission remaining in the next time slot when switching groups quickly, and to reduce the instantaneous coupling interference of high-power devices or high-priority devices during the working phase. The output of this process is the time slot allocation data, which lists in detail "which group has communication rights in which period" and "how long is each communication period" and other information.

[0148] Based on the time slot allocation data, when performing interleaved read and write access to the target device within the time window, the system will schedule the devices under each group to perform communication operations in sequence according to the previously divided time slot order. If there are multiple devices in a group that need to be polled for access, several micro-time slots can be further subdivided in the corresponding time slot to allow them to be interleaved for access, and the access success rate, access delay and possible contention conflicts are recorded. At this time, it is also necessary to monitor the access timing parameters and conflict counts in the group in real time. If it is found that some devices still have data collisions or timing overlaps during interleaving, the system will add this situation to the access monitoring data. The access monitoring data can reflect "whether interleaved access can effectively avoid conflicts under the current time slot strategy" and "whether some devices are piled up due to too long delays". If the conflict count is too high or the access is obviously timed out, it means that it is necessary to increase the anti-collision interval or fine-tune the access order of each device in the next round of scheduling optimization.

[0149] Finally, by performing time-related analysis on the conflict counts and timing parameters in the access monitoring data, anti-collision intervals and interleaved scheduling schemes can be generated, and then parallel access data can be obtained. The meaning of time-related analysis is to compare the conflict records of the same group in different time windows with the timing configuration, and find the law of "whether conflicts occur in certain time periods" or "when the anti-collision intervals of adjacent time slots are less than a certain number of milliseconds, conflicts will surge". If the system finds that a group of devices has a significant increase in conflicts during high-load periods after comparing multiple rounds of access monitoring data, it can allocate a looser anti-collision interval for it; if another group of devices is only accessed during the low-load stage and the bit error rate is not high, the interval between them can be tightened and more resources can be vacated for the high-priority group. The anti-collision intervals and interleaved scheduling schemes generated in this way not only ensure the reduction of collisions during frequent reading and writing, but also make resource allocation more efficient. Finally, the parallel access data will retain a comprehensive record of the actual access status and conflict handling results of each group of devices, help to continuously optimize the parallel scheduling strategy in the future, and provide a reliable basis for the system to call out the existing mature interleaved scheme before the next high-load operation.

[0150] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the inventive concept of the present invention, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An automatic parameter adjustment method for an SPI controller, characterized in that: include: According to a preset duty cycle, a preset edge speed and a preset pulse interval, the SPI bus is pulse-excited in multiple operating temperature ranges, waveform response data is collected, the waveform response data is associated and marked with environmental parameter data, and a bus characteristic mapping table is generated, wherein the environmental parameter data includes temperature data, voltage data and interference intensity data; Determine initial clock parameters based on the bus characteristic mapping table, send self-test instruction sequences to target devices of different batches, collect device response data, associate and mark the device response data with the environmental parameter data, and generate a device characteristic mapping table; Determine intermediate configuration parameters based on the device characteristic mapping table and the bus characteristic mapping table, collect configuration verification data, adjust clock phase parameters and data sampling parameters according to the configuration verification data, and generate transition configuration data; specifically include: according to the access delay data in the device characteristic mapping table and the waveform response data, voltage data, and interference intensity data in the bus characteristic mapping table, screen multiple groups of combination parameters of clock frequency, phase, and sampling point to generate intermediate configuration parameters; based on the intermediate configuration parameters, send burst read and write test instructions to different batches of the target devices in the process of dynamically switching the working state of the industrial equipment, collect the first a round of configuration verification data; according to the first round of configuration verification data, adjusting the clock phase parameter in sections during the power supply voltage fluctuation process, and collecting the second round of configuration verification data; based on the second round of configuration verification data, adjusting the data sampling parameter in sections during the power supply load mutation process, and collecting the third round of configuration verification data; combining and analyzing the bit error rate data and timing jitter data in the first round of configuration verification data, the second round of configuration verification data, and the third round of configuration verification data to obtain configuration verification data; gradient adjusting the clock phase parameter and the data sampling parameter according to the configuration verification data to generate transition configuration data; Based on the transition configuration data, interference event data and voltage monitoring data are acquired, waveform adjustment is performed on the clock signal, result data of the waveform adjustment is recorded, and interference suppression data is generated; Based on the interference suppression data and the device characteristic mapping table, statistically processing the bit error rate data and delay data of the target device to generate device aging trend data; Based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data, the plurality of target devices are grouped based on device characteristic similarity, timing parameter sharing is performed within the group, parallel access control is performed, and access status records are generated.

2. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: According to the preset duty cycle, the preset edge speed and the preset pulse interval, the SPI bus is pulse-excited in multiple operating temperature ranges, waveform response data is collected, the waveform response data is associated and marked with environmental parameter data, and a bus characteristic mapping table is generated, wherein the environmental parameter data includes temperature data, voltage data and interference intensity data, including: Based on multiple sets of preset duty cycles, a first round of pulse excitation is performed within a power supply voltage range, and a first round of waveform response data and voltage data are collected, wherein the power supply voltage range is 9V to 36V; Determine the minimum distortion duty cycle and the optimal voltage level according to the first round of waveform response data and the voltage data, perform a second round of pulse excitation at multiple sets of preset edge speeds, and collect the second round of waveform response data and the first round of interference intensity data; Based on the minimum distortion duty cycle and the optimal voltage level, during the switching of the working state of the industrial equipment, a third round of pulse excitation is performed according to a plurality of groups of preset pulse intervals, and the third round of waveform response data and the second round of interference intensity data are collected; Repeating the first round of pulse excitation, the second round of pulse excitation and the third round of pulse excitation in a plurality of operating temperature intervals to collect temperature data, wherein the operating temperature interval ranges from -40°C to 85°C; Determining interference intensity data according to the first round of interference intensity data and the second round of interference intensity data; Merging the first round of waveform response data, the second round of waveform response data, and the third round of waveform response data to obtain waveform response data; The waveform response data, the temperature data, the voltage data and the interference intensity data are associated and marked to generate a bus characteristic mapping table.

3. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: The method of determining the initial clock parameters based on the bus characteristic mapping table, sending self-test instruction sequences to target devices of different batches, collecting device response data, associating and marking the device response data with the environmental parameter data, and generating the device characteristic mapping table includes: Screening multiple groups of clock frequency, polarity and phase combinations according to the voltage data and temperature data in the bus characteristic mapping table to generate an initial clock parameter set; Based on the initial clock parameter set, send identification instructions and status reading instructions to target devices of different batches, collect first-round device response data, and record access delay data under different voltage levels and temperature ranges; According to the first round of device response data and the access delay data, sending register test instructions and storage unit read and write instructions to different batches of the target devices, and collecting the second round of device response data; Based on the second round of device response data, sending data alternation test instructions to the target devices of different batches in different power supply states, and collecting the third round of device response data; Sending timing boundary test instructions to the target devices of different batches, recording data latch timing parameters, and collecting fourth round device response data; Merging the first-round device response data, the second-round device response data, the third-round device response data, and the fourth-round device response data to obtain device response data; The device response data and the environmental parameter data are associated and marked to generate a device characteristic mapping table.

4. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: The step of performing gradient adjustment on the clock phase parameter and the data sampling parameter according to the configuration verification data to generate transition configuration data includes: According to the bit error rate data in the configuration verification data, the clock phase parameter is scanned in decreasing steps to generate phase step data; Based on the phase step data, a multi-point sampling test is performed on the clock phase parameter, a sampling stable interval is recorded, and phase window data is generated; According to the phase window data, performing an offset test on the sampling points of the data sampling parameters to generate sampling offset data; Based on the sampling offset data, interpolation test is performed on the data sampling parameters in the sampling stability interval to generate sampling optimization data; According to the timing jitter data in the configuration verification data and the sampling optimization data, setting a protection boundary for the clock phase parameter to generate phase protection data; Based on the phase protection data, a dynamic adjustment range is set for the data sampling parameter to generate sampling restriction data; The phase protection data and the sampling restriction data are associated and marked to generate transition configuration data.

5. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: The acquiring interference event data and voltage monitoring data based on the transition configuration data, performing waveform adjustment on the clock signal, recording result data of the waveform adjustment, and generating interference suppression data includes: According to the transition configuration data, the relay action signal, the power switch signal and the motor start / stop signal of the industrial equipment are monitored to generate interference event data; Based on the interference event data, sampling the voltage fluctuation at the power input terminal to generate voltage monitoring data; Pre-adjusting the clock signal before the interference event occurs according to the interference event data and the voltage monitoring data to generate pre-adjustment parameter data; Based on the pre-adjustment parameter data, the rising edge and the falling edge of the clock signal are subjected to segmented smoothing processing, and the first round of waveform adjustment data is collected; According to the first round of waveform adjustment data, the driving strength of the clock signal is adjusted in multiple levels, and the second round of waveform adjustment data is collected; Merging the first round of waveform adjustment data and the second round of waveform adjustment data to obtain waveform adjustment result data; The waveform adjustment result data is associated with the interference event data and the voltage monitoring data to generate interference suppression data.

6. The automatic parameter adjustment method of the SPI controller according to claim 5, characterized in that: The pre-adjusting the clock signal before the interference event occurs according to the interference event data and the voltage monitoring data to generate pre-adjustment parameter data includes: Extracting features of relay action signals, power switch signals and motor start / stop signals in the interference event data, and combining them with the voltage monitoring data to generate interference prediction data; Determine the occurrence time of the interference event according to the interference prediction data, and pre-adjust the clock signal within the reserved time before the occurrence of the interference event to generate adjustment timing data; The adjustment timing data is time-aligned with the interference prediction data to generate pre-adjustment parameter data.

7. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: The step of performing statistical processing on the bit error rate data and delay data of the target device based on the interference suppression data and the device characteristic mapping table to generate device aging trend data includes: Determine timing boundary parameters according to the waveform adjustment result data in the interference suppression data and the access delay data in the device characteristic mapping table to obtain initial delay data; Based on the initial delay data, a timing margin test is performed on the read and write operations of the target device, and current delay data and current bit error rate data are collected; According to the initial delay data and the current delay data, counting the delay variation data of the target device under different power supply voltage and temperature conditions to generate delay statistical data; Based on the current bit error rate data, collecting bit error distribution data of the target device under different working conditions to generate bit error statistical data; Performing time domain distribution analysis on the delay statistical data to obtain delay degradation data; Performing spatial distribution analysis on the bit error statistical data to obtain bit error degradation data; The delay degradation data and the bit error degradation data are associated and marked to generate device aging trend data.

8. The automatic parameter adjustment method of the SPI controller according to claim 1, characterized in that: The method includes grouping the plurality of target devices based on the device aging trend data, the bus characteristic mapping table, the device characteristic mapping table and the transition configuration data based on the device characteristic similarity, performing timing parameter sharing within the group, performing parallel access control, and generating access status records, including: According to the delay degradation data in the device aging trend data and the access delay data in the device characteristic mapping table, matching the manufacturing batches and aging states of the plurality of target devices to generate batch characteristic data; Based on the batch characteristic data and the waveform response data in the bus characteristic mapping table, similarity calculation is performed on the timing parameters of the target device in different temperature ranges to generate timing similarity data; Classifying the response characteristics of the target device under different voltage fluctuation conditions according to the timing similarity data to obtain a device grouping scheme; Based on the device grouping scheme, allocating the clock phase parameters and sampling timing parameters in the transition configuration data to the target devices in the group to generate intra-group shared parameters; According to the intra-group shared parameters, the access priority of each group is dynamically adjusted when the working state of the industrial equipment is switched, and the inter-group arbitration data is generated; Based on the inter-group arbitration data, performing interleaved access scheduling on the target devices in the group, recording access conflict data in each time window, and generating parallel access data; The parallel access data is associated with the intra-group shared parameters to generate an access status record.

9. The automatic parameter adjustment method of the SPI controller according to claim 8, characterized in that: The method of performing interleaved access scheduling on the target devices in the group based on the inter-group arbitration data, recording access conflict data in each time window, and generating parallel access data includes: Allocate time slots to the target devices in the group according to the inter-group arbitration data, set anti-collision intervals between adjacent time slots, and generate time slot allocation data; Based on the time slot allocation data, performing interleaved read and write accesses on the target device within a time window, recording access timing parameters and conflict counts within a group, and generating access monitoring data; A time-related analysis is performed on the conflict counts and timing parameters in the access monitoring data, and an anti-collision interval and an interleaving scheduling scheme are generated to obtain parallel access data.

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