A low leakage current enabling control circuit and method suitable for high voltage LDO

Abstract

The present invention discloses a low leakage current enabling control circuit and method suitable for high voltage LDO, comprising a bias unit, a shutdown unit and an output unit, wherein the output end of the bias unit is connected to the input end of the shutdown unit to provide a static bias current for the shutdown unit, the output end of the shutdown unit is connected to the input end of the output unit to provide a controllable high voltage domain power supply for the output unit, the first output end of the output unit is connected to the first input end of the low voltage circuit module to provide a low voltage domain power supply for the low voltage circuit module, and the second output end of the output unit is connected to the second input end of the low voltage circuit module to control the enabling and shutting down of the low voltage circuit module. The present invention improves the isolation of the chip when it is disabled, and effectively reduces the leakage current of the chip in the disabled state.

Description

Technical Field

[0001] The present invention relates to an enabling control circuit and method, in particular to a low leakage current enabling control circuit and method suitable for a high voltage LDO, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Figure 2 The schematic diagram of the enabling control circuit of a high-voltage circuit in the prior art is mainly divided into two parts, namely, a bias unit and a shutdown unit. The bias unit is composed of a resistor R1, a current mirror NM5 and NM6, wherein the resistor R1 is used to generate a static current, which is mirrored to the shutdown unit through current mirrors NM5, NM6, PM4, PM5 and PM6, and two low-voltage power supplies LVDD2 and LVDD3 are generated on Zener diodes Z5 and Z4 respectively. LVDD2 is also controlled by the enabling switch tube NM4, and LVDD3 is used to provide a power supply voltage for the Schmitt inverter smit2 to ensure that smit2 can work normally. In addition, the two low-voltage power supplies usually do not exceed the reverse breakdown voltage of the diode (about 5.5V), ensuring that the digital circuit module Smit2 does not work in a high-voltage state, thereby ensuring the safety of the device.

[0003] The specific working principle of the circuit is: when the enable signal EN is high, LVDD2 is low, and the output EN_OUT is high, which can provide an enable signal for the subsequent low-voltage circuit module; when EN is low, LVDD2 is high, and the output EN_OUT is low, which can shut down the subsequent low-voltage circuit module to save static power consumption. At this time, the leakage current Ileakage generated by the low-voltage circuit module is:

[0004] ;

[0005] Among them, Reff is the equivalent resistance after the low-voltage circuit module is turned off. Under normal circumstances, Reff is very large after the circuit is turned off, and the leakage current Ileakage is very small and can be ignored. However, under some extreme conditions (such as process drift, high working environment temperature), Reff will be significantly reduced, thereby increasing the leakage current Ileakage, which will cause the chip to still consume power in the disabled state. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a low leakage current enabling control circuit and method suitable for high voltage LDO, so as to reduce the leakage current of the chip in the disable state.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A low leakage current enabling control circuit suitable for a high voltage LDO comprises a bias unit, a shutdown unit and an output unit, wherein the output end of the bias unit is connected to the input end of the shutdown unit to provide a static bias current for the shutdown unit, the output end of the shutdown unit is connected to the input end of the output unit to provide a controllable high voltage domain power supply for the output unit, the first output end of the output unit is connected to the first input end of a low voltage circuit module to provide a low voltage domain power supply for the low voltage circuit module, and the second output end of the output unit is connected to the second input end of the low voltage circuit module to control the enabling and shutting down of the low voltage circuit module.

[0009] Furthermore, the bias unit includes a constant current source I0 and a PMOS tube PM0, the source of the PMOS tube PM0 is connected to the power supply HVDD, the gate of the PMOS tube PM0 is connected to the drain of the PMOS tube PM0 and one end of the constant current source I0 and serves as the output end of the bias unit, and the other end of the constant current source I0 is grounded.

[0010] Further, the shutdown unit comprises a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, an NMOS tube NM0, an NMOS tube NM1, an NMOS tube NM2, a Zener diode Z0, a Zener diode Z1, a Zener diode Z2, a Zener diode Z3 and a resistor R0, a source of the PMOS tube PM1 is connected to a cathode of the Zener diode Z2, a source of the PMOS tube PM2, a cathode of the Zener diode Z3 and a source of the PMOS tube PM3 and connected to a power supply HVDD, a gate of the PMOS tube PM1 is connected to an anode of the Zener diode Z2 and a gate of the PMOS tube PM2, a drain of the PMOS tube PM1 is connected to a drain of the NMOS tube NM2, a source of the NMOS tube PM2, a cathode of the Zener diode Z3 and a source of the PMOS tube PM3 and connected to a power supply HVDD, a gate of the PMOS tube PM1 is connected to an anode of the Zener diode Z2 and a gate of the PMOS tube PM2, and a drain of the PMOS tube PM1 is connected to a drain of the NMOS tube NM2, a drain of the NMOS tube The gate of the transistor NM2, the gate of the NMOS transistor NM1 and the cathode of the Zener diode Z1 are connected, the drain of the PMOS transistor PM2 and the anode of the Zener diode Z3, the gate of the PMOS transistor PM3 and the drain of the NMOS transistor NM1 are connected to generate a voltage signal net1, the drain of the PMOS transistor PM3 serves as the output end of the shutdown unit, the source of the NMOS transistor NM1 is connected to the drain of the NMOS transistor NM0, the gate of the NMOS transistor NM0 is connected to one end of the resistor R0 and the cathode of the Zener diode Z0, the other end of the resistor R0 is connected to the enable signal EN, the source of the NMOS transistor NM2, the anode of the Zener diode Z1, the anode of the Zener diode Z0 and the source of the NMOS transistor NM0 are grounded.

[0011] Furthermore, the PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 form a first current mirror, wherein the ratio of the width to length of the PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 is 1:1:N.

[0012] Furthermore, the NMOS transistor NM2 and the NMOS transistor NM1 form a second current mirror, wherein the ratio of the width to length of the NMOS transistor NM2 to the NMOS transistor NM1 is 1:M.

[0013] Furthermore, the PMOS transistor PM2 and the NMOS transistor NM1 form a current comparison circuit to control the PMOS transistor PM3, and N<M makes the pull-down capability of the NMOS transistor NM1 stronger than the pull-up capability of the PMOS transistor PM2.

[0014] Further, the output unit includes a pre-regulator module, an NMOS tube NM3, an inverter INV1 and a Schmitt inverter Smit1, the input end of the pre-regulator module serves as the input end of the output unit, the output end of the pre-regulator module is connected to the gate of the NMOS tube NM3, the power supply end of the inverter INV1, and the power supply end of the Schmitt inverter Smit1 and serves as the first output end of the output unit to generate an internal power supply voltage LVDD1, the drain of the NMOS tube NM3 is connected to the enable signal EN, the source of the NMOS tube NM3 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the input end of the Schmitt inverter Smit1, the output end of the Schmitt inverter Smit1 serves as the second output end of the output unit and generates an enable output signal EN_OUT, and the ground end of the inverter INV1, the ground end of the Schmitt inverter Smit1 and the ground end of the low-voltage circuit module are grounded.

[0015] A control method for a low leakage current enabling control circuit applicable to a high voltage LDO comprises the following steps:

[0016] When the enable signal EN is at a high level, the NMOS tube NM0 is turned on. Since the size of the NMOS tube NM1 is larger than that of the PMOS tube PM2, the pull-down capability of the NMOS tube NM1 is stronger than the pull-up capability of the PMOS tube PM2, the voltage signal net1 is pulled low, and the PMOS tube PM3 is turned on, so that the power supply HVDD can provide the power supply voltage for the output unit; even if the voltage value of the power supply HVDD is high, due to the existence of the Zener diode Z3, the voltage of the voltage signal net1 is HVDD-Vzener, where Vzener is the reverse breakdown voltage of the Zener diode Z3, which can still ensure that the PMOS tube PM3 is in a safe working state and is not broken down;

[0017] The pre-regulator module provides the internal power supply voltage LVDD1 of the low voltage domain for the output unit, and provides the bias voltage for the NMOS tube NM3. When the enable signal EN is high, the source voltage of the NMOS tube NM3 is LVDD1-VGS3, where VGS3 is the gate-source voltage of the NMOS tube NM3. The source voltage of the NMOS tube NM3 is sufficient to turn on the inverter INV1, so that the inverter INV1 outputs a low level, and the Schmitt inverter Smit1 outputs a high level, that is, the enable output signal EN_OUT is a high level;

[0018] When the enable signal EN is at a low level, the NMOS tube NM0 is turned off, the NMOS tube NM1 loses its pull-down capability, the voltage of the voltage signal net1 is pulled up by the PMOS tube PM2, and the PMOS tube PM3 is turned off. The output unit stops working due to the lack of power supply HVDD, the internal power supply voltage LVDD1 is reset to zero, and the output enable signal EN_OUT is also at a low level, turning off the low-voltage circuit module. At this time, the leakage current I generated by the low-voltage circuit module leakage for:

[0019] ;

[0020] Among them, R eff is the equivalent resistance after the low voltage circuit module is turned off;

[0021] Since the internal power supply voltage LVDD1 is set to zero when the enable signal EN is at a low level, even if the low-voltage circuit module is turned off, the equivalent resistance R eff Under extreme working conditions, the leakage current I leakage It will not increase significantly either.

[0022] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a low leakage current enable control circuit and method suitable for high-voltage LDO, adds a switch isolation tube to the power path, and the switch isolation tube is controlled by an enable signal. When the circuit needs to work, the switch isolation tube is turned on, and when the circuit is disabled, the switch isolation tube is disconnected, the power path is cut off, and the internal power supply LVDD is set to zero. Therefore, even if the off equivalent resistance Reff of the low-voltage circuit module is significantly reduced under extreme working conditions, since the internal power supply LVDD is zero, a large leakage current Ileakage cannot be generated, that is, the present invention improves the isolation of the chip when it is disabled, and effectively reduces the leakage current of the chip in the disabled state. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 The present invention is a schematic diagram of a low leakage current enabling control circuit suitable for a high voltage LDO.

[0024] Figure 2 is a schematic diagram of an enabling control circuit in the prior art. DETAILED DESCRIPTION

[0025] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0026] like Figure 1 As shown, a low leakage current enabling control circuit suitable for a high-voltage LDO of the present invention comprises a bias unit, a shutdown unit and an output unit, wherein the output end of the bias unit is connected to the input end of the shutdown unit to provide a static bias current for the shutdown unit, the output end of the shutdown unit is connected to the input end of the output unit to provide a controllable high-voltage domain power supply for the output unit, the first output end of the output unit is connected to the first input end of the low-voltage circuit module to provide a low-voltage domain power supply for the low-voltage circuit module, and the second output end of the output unit is connected to the second input end of the low-voltage circuit module to control the enabling and shutting down of the low-voltage circuit module.

[0027] The bias unit includes a constant current source I0 and a PMOS tube PM0, the source of the PMOS tube PM0 is connected to the power supply HVDD, the gate of the PMOS tube PM0 is connected to the drain of the PMOS tube PM0 and one end of the constant current source I0 and serves as the output end of the bias unit, and the other end of the constant current source I0 is grounded.

[0028] The shutdown unit includes a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, an NMOS tube NM0, an NMOS tube NM1, an NMOS tube NM2, a Zener diode Z0, a Zener diode Z1, a Zener diode Z2, a Zener diode Z3 and a resistor R0. The source of the PMOS tube PM1 is connected to the cathode of the Zener diode Z2, the source of the PMOS tube PM2, the cathode of the Zener diode Z3 and the source of the PMOS tube PM3 and connected to the power supply HVDD. The gate of the PMOS tube PM1 is connected to the anode of the Zener diode Z2 and the gate of the PMOS tube PM2. The drain of the PMOS tube PM1 is connected to the drain of the NMOS tube NM2 and the drain of the NMOS tube NM2. The gate of the NMOS tube NM1 is connected to the cathode of the Zener diode Z1, the drain of the PMOS tube PM2 is connected to the anode of the Zener diode Z3, the gate of the PMOS tube PM3 and the drain of the NMOS tube NM1 are connected to generate a voltage signal net1, the drain of the PMOS tube PM3 serves as the output end of the shutdown unit, the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM0, the gate of the NMOS tube NM0 is connected to one end of the resistor R0 and the cathode of the Zener diode Z0, the other end of the resistor R0 is connected to the enable signal EN, the source of the NMOS tube NM2, the anode of the Zener diode Z1, the anode of the Zener diode Z0 and the source of the NMOS tube NM0 are grounded.

[0029] The PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 form a first current mirror, wherein the ratio of the width to length of the PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 is 1:1:N.

[0030] The NMOS transistor NM2 and the NMOS transistor NM1 form a second current mirror, wherein the ratio of the width to length of the NMOS transistor NM2 to the NMOS transistor NM1 is 1:M.

[0031] The PMOS transistor PM2 and the NMOS transistor NM1 form a current comparison circuit to control the PMOS transistor PM3, and N<M makes the pull-down capability of the NMOS transistor NM1 stronger than the pull-up capability of the PMOS transistor PM2.

[0032] The output unit includes a pre-stabilizing module, an NMOS tube NM3, an inverter INV1 and a Schmitt inverter Smit1, the input end of the pre-stabilizing module is used as the input end of the output unit, the output end of the pre-stabilizing module is connected to the gate of the NMOS tube NM3, the power end of the inverter INV1, and the power end of the Schmitt inverter Smit1 and is used as the first output end of the output unit to generate an internal power supply voltage LVDD1, the drain of the NMOS tube NM3 is connected to the enable signal EN, the source of the NMOS tube NM3 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the input end of the Schmitt inverter Smit1, the output end of the Schmitt inverter Smit1 is used as the second output end of the output unit and generates an enable output signal EN_OUT, and the ground end of the inverter INV1, the ground end of the Schmitt inverter Smit1 and the ground end of the low-voltage circuit module are grounded. The pre-stabilizing module can be a voltage stabilizing module of the prior art, so it is not repeated here.

[0033] A control method for a low leakage current enabling control circuit applicable to a high voltage LDO comprises the following steps:

[0034] When the enable signal EN is at a high level, the NMOS tube NM0 is turned on. Since the size of the NMOS tube NM1 is larger than that of the PMOS tube PM2, the pull-down capability of the NMOS tube NM1 is stronger than the pull-up capability of the PMOS tube PM2, the voltage signal net1 is pulled low, and the PMOS tube PM3 is turned on, so that the power supply HVDD can provide the power supply voltage for the output unit; even if the voltage value of the power supply HVDD is high, due to the existence of the Zener diode Z3, the voltage of the voltage signal net1 is HVDD-Vzener, where Vzener is the reverse breakdown voltage of the Zener diode Z3, which can still ensure that the PMOS tube PM3 is in a safe working state and is not broken down.

[0035] The pre-regulator module provides the internal power supply voltage LVDD1 of the low voltage domain for the output unit, and provides a bias voltage for the NMOS tube NM3. When the enable signal EN is high, the source voltage of the NMOS tube NM3 is LVDD1-VGS3, where VGS3 is the gate-source voltage of the NMOS tube NM3. The source voltage of the NMOS tube NM3 is sufficient to turn on the inverter INV1, so that the inverter INV1 outputs a low level, and the Schmitt inverter Smit1 outputs a high level, that is, the enable output signal EN_OUT is a high level.

[0036] When the enable signal EN is at a low level, the NMOS tube NM0 is turned off, the NMOS tube NM1 loses its pull-down capability, the voltage of the voltage signal net1 is pulled up by the PMOS tube PM2, and the PMOS tube PM3 is turned off. The output unit stops working due to the lack of power supply HVDD, the internal power supply voltage LVDD1 is reset to zero, and the output enable signal EN_OUT is also at a low level, turning off the low-voltage circuit module. At this time, the leakage current I generated by the low-voltage circuit module leakage for:

[0037] ;

[0038] Among them, R eff It is the equivalent resistance after the low voltage circuit module is turned off.

[0039] Since the internal power supply voltage LVDD1 is set to zero when the enable signal EN is at a low level, even if the low-voltage circuit module is turned off, the equivalent resistance R eff Under extreme working conditions, the leakage current I leakage It will not increase significantly either.

[0040] The present invention provides a low leakage current enabling control circuit and method suitable for high voltage LDO, wherein a switch isolating tube is added to the power path, and the switch isolating tube is controlled by an enabling signal, and when the circuit needs to work, the switch isolating tube is turned on, and when the circuit is disabled, the switch isolating tube is disconnected, the power path is cut off, and the internal power supply LVDD is set to zero at this time. Therefore, even if the off equivalent resistance Reff of the low voltage circuit module is significantly reduced under extreme working conditions, since the internal power supply LVDD is zero, a large leakage current Ileakage cannot be generated, that is, the present invention improves the isolation of the chip when it is disabled, and effectively reduces the leakage current of the chip in the disabled state.

[0041] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low leakage current enabling control circuit suitable for a high voltage LDO, characterized in that: It comprises a bias unit, a shutdown unit and an output unit, wherein the output end of the bias unit is connected to the input end of the shutdown unit to provide a static bias current for the shutdown unit, the output end of the shutdown unit is connected to the input end of the output unit to provide a controllable high-voltage domain power supply for the output unit, the first output end of the output unit is connected to the first input end of the low-voltage circuit module to provide a low-voltage domain power supply for the low-voltage circuit module, and the second output end of the output unit is connected to the second input end of the low-voltage circuit module to control the enabling and shutting down of the low-voltage circuit module; The shut-off unit comprises a PMOS tube PM1, a PMOS tube PM2, a PMOS tube PM3, an NMOS tube NM0, an NMOS tube NM1, an NMOS tube NM2, a Zener diode Z0, a Zener diode Z1, a Zener diode Z2, a Zener diode Z3 and a resistor R0. The source of the PMOS tube PM1 is connected to the cathode of the Zener diode Z2, the source of the PMOS tube PM2, the cathode of the Zener diode Z3 and the source of the PMOS tube PM3 and connected to the power supply HVDD. The gate of the PMOS tube PM1 is connected to the anode of the Zener diode Z2 and the gate of the PMOS tube PM2. The drain of the PMOS tube PM1 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM3 and the drain of the NMOS tube NM4. The gate of the NMOS tube NM2, the gate of the NMOS tube NM1 and the cathode of the Zener diode Z1 are connected, the drain of the PMOS tube PM2 is connected to the anode of the Zener diode Z3, the gate of the PMOS tube PM3 and the drain of the NMOS tube NM1 are connected to generate a voltage signal net1, the drain of the PMOS tube PM3 serves as the output end of the shutdown unit, the source of the NMOS tube NM1 is connected to the drain of the NMOS tube NM0, the gate of the NMOS tube NM0 is connected to one end of the resistor R0 and the cathode of the Zener diode Z0, the other end of the resistor R0 is connected to the enable signal EN, the source of the NMOS tube NM2, the anode of the Zener diode Z1, the anode of the Zener diode Z0 and the source of the NMOS tube NM0 are grounded.

2. A low leakage current enabling control circuit suitable for high voltage LDO according to claim 1, characterized in that: The bias unit includes a constant current source I0 and a PMOS tube PM0, the source of the PMOS tube PM0 is connected to the power supply HVDD, the gate of the PMOS tube PM0 is connected to the drain of the PMOS tube PM0 and one end of the constant current source I0 and serves as the output end of the bias unit, and the other end of the constant current source I0 is grounded.

3. A low leakage current enabling control circuit suitable for high voltage LDO according to claim 2, characterized in that: The PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 form a first current mirror, wherein the ratio of the width to length of the PMOS transistor PM0 , the PMOS transistor PM1 , and the PMOS transistor PM2 is 1:1:N.

4. The low leakage current enabling control circuit suitable for high voltage LDO according to claim 3, characterized in that: The NMOS transistor NM2 and the NMOS transistor NM1 form a second current mirror, wherein the ratio of the width to length of the NMOS transistor NM2 to the NMOS transistor NM1 is 1:M.

5. The low leakage current enabling control circuit suitable for high voltage LDO according to claim 4, characterized in that: The PMOS transistor PM2 and the NMOS transistor NM1 form a current comparison circuit to control the PMOS transistor PM3, and N<M makes the pull-down capability of the NMOS transistor NM1 stronger than the pull-up capability of the PMOS transistor PM2.

6. The low leakage current enabling control circuit suitable for high voltage LDO according to claim 1, characterized in that: The output unit includes a pre-regulator module, an NMOS tube NM3, an inverter INV1 and a Schmitt inverter Smit1, the input end of the pre-regulator module serves as the input end of the output unit, the output end of the pre-regulator module is connected to the gate of the NMOS tube NM3, the power end of the inverter INV1, and the power end of the Schmitt inverter Smit1 and serves as the first output end of the output unit to generate an internal power supply voltage LVDD1, the drain of the NMOS tube NM3 is connected to the enable signal EN, the source of the NMOS tube NM3 is connected to the input end of the inverter INV1, the output end of the inverter INV1 is connected to the input end of the Schmitt inverter Smit1, the output end of the Schmitt inverter Smit1 serves as the second output end of the output unit and generates an enable output signal EN_OUT, and the ground end of the inverter INV1, the ground end of the Schmitt inverter Smit1 and the ground end of the low-voltage circuit module are grounded.

7. A control method for a low leakage current enabling control circuit applicable to a high voltage LDO according to any one of claims 1 to 6, characterized in that The following steps are involved: When the enable signal EN is at a high level, the NMOS tube NM0 is turned on. Since the size of the NMOS tube NM1 is larger than that of the PMOS tube PM2, the pull-down capability of the NMOS tube NM1 is stronger than the pull-up capability of the PMOS tube PM2, the voltage signal net1 is pulled low, and the PMOS tube PM3 is turned on, so that the power supply HVDD can provide the power supply voltage for the output unit; even if the voltage value of the power supply HVDD is high, due to the existence of the Zener diode Z3, the voltage of the voltage signal net1 is HVDD-Vzener, where Vzener is the reverse breakdown voltage of the Zener diode Z3, which can still ensure that the PMOS tube PM3 is in a safe working state and is not broken down; The pre-regulator module provides the internal power supply voltage LVDD1 of the low voltage domain for the output unit, and provides the bias voltage for the NMOS tube NM3. When the enable signal EN is high, the source voltage of the NMOS tube NM3 is LVDD1-VGS3, where VGS3 is the gate-source voltage of the NMOS tube NM3. The source voltage of the NMOS tube NM3 is sufficient to turn on the inverter INV1, so that the inverter INV1 outputs a low level, and the Schmitt inverter Smit1 outputs a high level, that is, the enable output signal EN_OUT is a high level; When the enable signal EN is at a low level, the NMOS tube NM0 is turned off, the NMOS tube NM1 loses its pull-down capability, the voltage of the voltage signal net1 is pulled up by the PMOS tube PM2, and the PMOS tube PM3 is turned off. The output unit stops working due to the lack of power supply HVDD, the internal power supply voltage LVDD1 is reset to zero, and the output enable signal EN_OUT is also at a low level, turning off the low-voltage circuit module. At this time, the leakage current I generated by the low-voltage circuit module leakage for: ； Among them, R eff is the equivalent resistance after the low voltage circuit module is turned off; Since the internal power supply voltage LVDD1 is set to zero when the enable signal EN is at a low level, even if the low-voltage circuit module is turned off, the equivalent resistance R eff Under extreme working conditions, the leakage current I leakage It will not increase significantly either.

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