Reference voltage source with high order curvature compensation function

Abstract

The application discloses a reference voltage source with high-order curvature compensation function, comprising a bandgap core circuit, a common-mode feedback circuit and a high-order curvature correction circuit. The bandgap core circuit is used for generating a reference voltage; the common-mode feedback circuit is used for generating a common-mode voltage according to the reference voltage, and returning the common-mode voltage to the bandgap core circuit through negative feedback to increase the stability of the bandgap core circuit; and the high-order curvature correction circuit is used for extracting or injecting current to the bandgap core circuit according to the reference voltage, and eliminating high-order errors generated in the bandgap core circuit due to temperature. In the application, the high-order curvature correction circuit can perform high-order curvature compensation on temperature, so that the precision of the output reference voltage can be effectively improved, the temperature coefficient can be reduced, and the temperature stability of the reference voltage can be improved. Meanwhile, the circuit structure is simple, the chip area is small, and the application has high practicability.

Description

Technical Field

[0001] The present invention belongs to the field of reference voltage sources, and in particular relates to a reference voltage source with a high-order curvature compensation function. Background Art

[0002] Voltage references generate a stable voltage that remains stable over temperature. They are commonly used in various high-precision mixed-analog circuit systems, such as analog-to-digital converters, digital-to-analog converters, and low-dropout (LDO) circuits. Their stability directly determines the accuracy of the system. Traditional first-order compensation uses a positive temperature coefficient voltage generated by ΔVBE to compensate for the negative temperature coefficient of the first-order VBE term. However, the optimal temperature drift can only reach 20 to 30 ppm / °C. High-order curvature correction technology further reduces temperature drift by compensating for the quadratic and higher-order VBE terms, achieving a temperature drift of less than 10 ppm / °C. Therefore, it is necessary to propose a circuit that uses high-order curvature correction technology to further reduce temperature drift. Summary of the Invention

[0003] In view of the above-mentioned deficiencies in the prior art, the technical problem to be solved by the present invention is to provide a reference voltage source with a high-order curvature compensation function.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] A reference voltage source with high-order curvature compensation function, comprising:

[0006] Bandgap core circuit, used to generate reference voltage V REF ;

[0007] Common-mode feedback circuit, used to adjust the reference voltage V REF generating a common-mode voltage and returning the common-mode voltage to the bandgap core circuit through negative feedback to increase the stability of the bandgap core circuit; and

[0008] The high-order curvature correction circuit is used to adjust the curvature according to the reference voltage V REF Current is extracted or injected into the bandgap core circuit to eliminate high-order errors caused by temperature in the bandgap core circuit.

[0009] Furthermore, the bandgap core circuit includes an eighth MOS transistor, a second triode, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and N first triodes connected in parallel, where N is an integer greater than or equal to 1;

[0010] The source of the eighth MOS transistor is connected to the external power supply voltage, the gate is electrically connected to the output terminal of the common-mode feedback circuit, and the drain is electrically connected to the first ends of the seventh resistor and the eighth resistor respectively; the second end of the seventh resistor is electrically connected to the inverting input terminal of the first operational amplifier and the collectors of the N first transistors respectively; the second end of the eighth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier and the collector of the second transistor respectively; the base of the second transistor and the bases of the N first transistors are both electrically connected to the output terminal of the first operational amplifier;

[0011] The non-inverting input terminal of the first operational amplifier is electrically connected to the first input terminal of the common-mode feedback circuit, and the inverting input terminal of the first operational amplifier is electrically connected to the second input terminal of the common-mode feedback circuit; the output terminal of the first operational amplifier is used to generate a reference voltage V REF , the output terminal of the first operational amplifier is electrically connected to the third input terminal of the common-mode feedback circuit and the input terminal of the high-order curvature correction circuit respectively;

[0012] The emitters of the N first transistors are all electrically connected to the first end of the ninth resistor, and the emitter of the second transistor is electrically connected to the second end of the ninth resistor; the second end of the ninth resistor is grounded through the tenth resistor, and the second end of the ninth resistor is also electrically connected to the correction end of the high-order curvature correction circuit.

[0013] Furthermore, the eighth MOS transistor is a PMOS transistor; the second transistor and the N first transistors are all NPN transistors.

[0014] Furthermore, the seventh resistor and the eighth resistor are of the same type and size.

[0015] Furthermore, the ratio of the sum of the saturation currents of the N first transistors to the saturation current of the second transistor is N:1.

[0016] Furthermore, the emitter area of ​​each of the first transistors is the same as the emitter area of ​​the second transistors.

[0017] Furthermore, the common-mode feedback circuit includes a second operational amplifier, wherein the first input terminal of the second operational amplifier is electrically connected to the non-inverting input terminal of the first operational amplifier as the first input terminal of the common-mode feedback circuit, the second input terminal of the second operational amplifier is electrically connected to the inverting input terminal of the first operational amplifier as the second input terminal of the common-mode feedback circuit, the third input terminal of the second operational amplifier is electrically connected to the output terminal of the first operational amplifier as the third input terminal of the common-mode feedback circuit, and the output terminal of the second operational amplifier is electrically connected to the gate of the eighth MOS transistor as the output terminal of the common-mode feedback circuit.

[0018] Further, the high-order curvature correction circuit includes a third operational amplifier, a fourth operational amplifier, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode, a thirteenth triode, an eleventh triode, a twelfth triode, a tenth triode, a fourteenth triode, a fifteenth triode, a sixteenth triode, a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twentieth triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor;

[0019] The non-inverting input terminal of the third operational amplifier, the non-inverting input terminal of the fourth operational amplifier, and the base of the twentieth triode are electrically connected to the output terminal of the first operational amplifier, the emitter of the twentieth triode is grounded through the first resistor, the inverting input terminal of the third operational amplifier is electrically connected to the collector of the twenty-second triode and the collector of the twentieth triode respectively, the output terminal of the third operational amplifier is electrically connected to the base of the twelfth triode and the base of the twenty-second triode respectively, and the emitter of the twelfth triode and the emitter of the twenty-second triode are connected to an external supply voltage.

[0020] The inverting input terminal of the fourth operational amplifier is grounded through the second resistor, the output terminal of the fourth operational amplifier is electrically connected to the base of the third triode, the base of the fourth triode, and the base of the thirteenth triode respectively, the emitter of the third triode, the emitter of the fourth triode, and the emitter of the thirteenth triode are connected to an external supply voltage, and the collector of the third triode is electrically connected to the inverting input terminal of the fourth operational amplifier.

[0021] The collector of the fourth triode is electrically connected to the collector of the fifth triode, the base of the fifth triode, the base of the sixth triode, and the base of the seventh triode respectively, the emitter of the fifth triode, the emitter of the sixth triode, and the emitter of the seventh triode are grounded, and the collector of the sixth triode is electrically connected to the collector of the seventh triode through the third resistor.

[0022] The collector of the sixth triode is further electrically connected to the drain of the first MOS transistor and the base of the thirteenth triode respectively; the gate of the first MOS transistor is electrically connected to the gate of the sixth MOS transistor, the drain of the sixth MOS transistor, and the gate of the seventh MOS transistor respectively; the source of the first MOS transistor is electrically connected to the collector of the eighth triode; the base of the eighth triode is electrically connected to the base of the seventeenth triode, the collector of the seventeenth triode, the base of the eighteenth triode, and the base of the twenty-third triode respectively; the emitter of the eighth triode, the emitter of the seventeenth triode, the emitter of the eighteenth triode, and the emitter of the twenty-third triode are all connected to an external power supply voltage;

[0023] The collector of the seventh triode is further electrically connected to the drain of the second MOS transistor and the base of the eleventh triode, respectively; the gate of the second MOS transistor is electrically connected to the gate of the third MOS transistor and the drain of the third MOS transistor, respectively; the source of the second MOS transistor is electrically connected to the collector of the ninth triode; the base of the ninth triode is electrically connected to the base of the fifteenth triode, the base of the sixteenth triode, and the collector of the sixteenth triode, respectively; the emitters of the ninth triode, the fifteenth triode, and the sixteenth triode are all connected to an external power supply voltage; and the source of the third MOS transistor is electrically connected to the collector of the fifteenth triode;

[0024] The emitter of the thirteenth transistor is grounded, the collector of the thirteenth transistor is electrically connected to the collector of the twelfth transistor and the base of the nineteenth transistor respectively, the emitter of the nineteenth transistor is grounded via a fifth resistor, the collector of the nineteenth transistor is electrically connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor respectively; the drain of the fifth MOS transistor is grounded, the source of the fifth MOS transistor is electrically connected to the collector of the seventeenth transistor, and the source of the sixth MOS transistor is electrically connected to the collector of the eighteenth transistor;

[0025] The emitter of the eleventh triode is grounded, the collector of the eleventh triode is electrically connected to the collector of the tenth triode, the base of the fourteenth triode, and the base of the twenty-first triode respectively, the emitter of the fourteenth triode is grounded via a fourth resistor, the collector of the fourteenth triode is electrically connected to the gate of the third MOS transistor and the gate of the fourth MOS transistor respectively; the drain of the fourth MOS transistor is grounded, and the source of the fourth MOS transistor is electrically connected to the collector of the sixteenth triode;

[0026] The emitter of the twenty-first transistor is grounded through a sixth resistor, the collector of the twenty-first transistor is electrically connected to the drain of the seventh MOS transistor, the drain of the seventh MOS transistor is electrically connected to the second end of the ninth resistor as a correction end of the high-order curvature correction circuit, and the source of the seventh MOS transistor is electrically connected to the collector of the twenty-third transistor.

[0027] Furthermore, the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are all PMOS transistors;

[0028] The third triode, the fourth triode, the eighth triode, the ninth triode, the tenth triode, the twelfth triode, the fifteenth triode, the sixteenth triode, the seventeenth triode, the eighteenth triode, the twenty-third triode and the twenty-second triode are all PNP triodes;

[0029] The fifth triode, the sixth triode, the seventh triode, the eleventh triode, the thirteenth triode, the fourteenth triode, the nineteenth triode, the twenty-first triode and the twenty-third triode are all NPN triodes.

[0030] Furthermore, the emitter area ratio of the third, fourth, and tenth triodes is 4:1:1; the emitter area ratio of the fifth, sixth, and seventh triodes is 2:1:1; the emitter area ratio of the eighth, seventeenth, eighteenth, and twenty-third triodes is 2:1:1:4; the emitter area ratio of the ninth, fifteenth, and sixteenth triodes is 2:1:1; the emitter area ratio of the twelfth and twenty-second triodes is 1:2; and the emitter area ratio of the fourteenth and twenty-first triodes is 1:4; the width-to-length ratio of the first, fifth, sixth, and seventh MOS transistors is 2:1:1:4; the width-to-length ratio of the second, third, and fourth MOS transistors is 2:1:1; and the resistance values ​​of the fourth and fifth resistors are both four times the resistance value of the sixth resistor.

[0031] In the present invention, a high-order curvature correction circuit can be used to compensate for high-order curvature over temperature, thereby effectively improving the accuracy of the output reference voltage, reducing the temperature coefficient, and improving the temperature stability of the reference voltage. Furthermore, the circuit structure is simple, occupies a small chip area, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 FIG. 4 is a structural diagram of an embodiment of a reference voltage source with a high-order curvature compensation function according to the present invention.

[0034] Figure 2 This is the circuit diagram of the high-order curvature correction circuit.

[0035] Figure 3 FIG. 4 is a schematic diagram of a reference voltage simulation result of performing high-order curvature compensation using the circuit of this embodiment.

[0036] Figure 4 Schematic diagram of the temperature coefficient simulation results of the first-order curvature correction circuit.

[0037] The accompanying drawings in this specification are numeraled as follows:

[0038] Bandgap core circuit: 100, common-mode feedback circuit: 200, high-order curvature correction circuit: 300;

[0039] First operational amplifier: A1, second operational amplifier: A2, third operational amplifier: A3, fourth operational amplifier: A4;

[0040] First MOS tube: M1, second MOS tube: M2, third MOS tube: M3, fourth MOS tube: M4, fifth MOS tube: M5, sixth MOS tube: M6, seventh MOS tube: M7, eighth MOS tube: M8;

[0041] The first transistor: Q1_1-Q1_8, the second transistor: Q2, the third transistor: Q3, the fourth transistor: Q4, the fifth transistor: Q5, the sixth transistor: Q6, the seventh transistor: Q7, the eighth transistor: Q8, the ninth transistor: Q9, the tenth transistor: Q10, the eleventh transistor: Q11, the twelfth transistor: Q12, the thirteenth transistor: Q13, the fourteenth transistor: Q14, the fifteenth transistor: Q15, the sixteenth transistor: Q16, the seventeenth transistor: Q17, the eighteenth transistor: Q18, the nineteenth transistor: Q19, the twenty-third transistor: Q20, the twenty-first transistor: Q21, the twenty-second transistor: Q22, the twenty-third transistor: Q23;

[0042] The first resistor is R1, the second resistor is R2, the third resistor is R3, the fourth resistor is R4, the fifth resistor is R5, the sixth resistor is R6, the seventh resistor is R7, the eighth resistor is R8, the ninth resistor is R9, and the tenth resistor is R10. DETAILED DESCRIPTION

[0043] The following describes the implementation of the present invention through specific examples. The illustrations provided in the following embodiments are only used to schematically illustrate the basic concept of the present invention. The following embodiments and features in the embodiments may be combined with each other unless there is any conflict.

[0044] See also Figure 1 , Figure 1Schematic diagram of the structure of an embodiment of a reference voltage source with high-order curvature compensation function of the present invention. The reference voltage source with high-order curvature compensation function of this embodiment includes a bandgap core circuit 100, a common-mode feedback circuit 200 and a high-order curvature correction circuit 300. The bandgap core circuit 100 is used to generate a reference voltage V REF The common mode feedback circuit 200 is used according to the reference voltage V REF Generates a common mode voltage and returns the common mode voltage to the bandgap core circuit 100 through negative feedback to increase the stability of the bandgap core circuit 100; the high-order curvature correction circuit 300 is used to adjust the curvature of the bandgap core circuit 100 according to the reference voltage V REF Current is extracted or injected into the bandgap core circuit 100 to eliminate high-order errors in the bandgap core circuit 100 due to temperature.

[0045] Please continue reading Figure 1 The bandgap core circuit 100 includes an eighth MOS transistor M8, a second transistor Q2, a first operational amplifier A1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and N first transistors connected in parallel. N is an integer greater than or equal to 1. The eighth MOS transistor M8 can be a PMOS transistor. The eight first transistors (Q1_1-Q1_8) and the second transistor Q2 can all be NPN transistors. The seventh resistor R7 and the eighth resistor R8 are generally of the same type and size.

[0046] In this embodiment, N=8 is used as an example for description. Thus, a total of eight first transistors are provided, namely, transistor Q1_1, transistor Q1_2, transistor Q1_3, transistor Q1_4, transistor Q1_5, transistor Q1_6, transistor Q1_7, and transistor Q1_8. The ratio of the sum of the saturation currents of the eight first transistors (Q1_1-Q1_8) to the saturation current of the second transistor Q2 is 8:1. Of course, in other embodiments, N may also be another integer greater than or equal to 1. Alternatively, more than one second triode may be provided. In this case, the number of first triodes needs to be multiplied so that the ratio of the number of first triodes to the second triodes is maintained at N:1. For example, when the bandgap core circuit 100 is provided with two second triodes connected in parallel, 16 first triodes connected in parallel are required to maintain the ratio of 8:1 in this embodiment, which is essentially the same as providing one second triode and eight first triodes.

[0047] The source of the eighth MOS transistor M8 is connected to the supply voltage VDD, the gate is electrically connected to the output end of the common-mode feedback circuit 200, and the drain is electrically connected to the first ends of the seventh resistor R7 and the eighth resistor R8, respectively. The second end of the seventh resistor R7 is electrically connected to the inverting input end of the first operational amplifier A1 and the collectors of the eight first transistors (Q1_1-Q1_8), respectively. The second end of the eighth resistor R8 is electrically connected to the non-inverting input end of the first operational amplifier A1 and the collector of the second transistor Q2, respectively. The base of the second transistor Q2 and the bases of the eight first transistors (Q1_1-Q1_8) are both electrically connected to the output end of the first operational amplifier A1.

[0048] The non-inverting input terminal of the first operational amplifier A1 is electrically connected to the first input terminal of the common-mode feedback circuit 200, and the inverting input terminal of the first operational amplifier A1 is electrically connected to the second input terminal of the common-mode feedback circuit 200; the output terminal of the first operational amplifier A1 is used to generate a reference voltage V REF The output terminal of the first operational amplifier A1 is electrically connected to the third input terminal of the common-mode feedback circuit 200 and the input terminal of the high-order curvature correction circuit 300 respectively.

[0049] The emitters of the eight first transistors (Q1_1-Q1_8) are all electrically connected to the first end of the ninth resistor R9, and the emitter of the second transistor Q2 is electrically connected to the second end of the ninth resistor R9; the second end of the ninth resistor R9 is grounded through the tenth resistor R10, and the second end of the ninth resistor R9 is also electrically connected to the correction end of the high-order curvature correction circuit 300.

[0050] Please continue reading Figure 1 The common-mode feedback circuit 200 includes a second operational amplifier A2. A first input terminal of the second operational amplifier A2 serves as the first input terminal of the common-mode feedback circuit 200 and is electrically connected to the non-inverting input terminal of the first operational amplifier A1. A second input terminal of the second operational amplifier A2 serves as the second input terminal of the common-mode feedback circuit 200 and is electrically connected to the inverting input terminal of the first operational amplifier A1. A third input terminal of the second operational amplifier A2 serves as the third input terminal of the common-mode feedback circuit 200 and is electrically connected to the output terminal of the first operational amplifier A1. An output terminal of the second operational amplifier A2 serves as the output terminal of the common-mode feedback circuit 200 and is electrically connected to the gate of the eighth MOS transistor M8.

[0051] See also Figure 2The high-order curvature correction circuit 300 includes a third operational amplifier A3, a fourth operational amplifier A4, a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, and an eleventh transistor Q11. transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twenty-third transistor Q20, a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

[0052] The first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 can all be PMOS transistors. The third transistor Q3, the fourth transistor Q4, the eighth transistor Q8, the ninth transistor Q9, the tenth transistor Q10, the twelfth transistor Q12, the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, the eighteenth transistor Q18, the twenty-third transistor Q20, and the twenty-second transistor Q22 can all be PNP transistors. The fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eleventh transistor Q11, the thirteenth transistor Q13, the fourteenth transistor Q14, the nineteenth transistor Q19, the twenty-first transistor Q21, and the twenty-third transistor Q23 can all be NPN transistors.

[0053] The emitter area ratio of the third transistor Q3, the fourth transistor Q4 and the tenth transistor Q10 is generally 4:1:1; the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is generally 2:1:1; the emitter area ratio of the eighth transistor Q8, the seventeenth transistor Q17, the eighteenth transistor Q18 and the twenty-third transistor Q20 is generally 2:1:1:4; the emitter area ratio of the ninth transistor Q9, the fifteenth transistor Q15 and the sixteenth transistor Q16 is generally 2:1:1; the emitter area ratio of the twelfth transistor Q17 is generally 2:1:1; The emitter area ratio of the transistor Q12 to the twenty-second transistor Q22 is generally 1:2; the emitter area ratio of the fourteenth transistor Q14 to the twenty-first transistor Q21 is generally 1:4; the width-to-length ratio of the first MOS transistor M1, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 is generally 2:1:1:4; the width-to-length ratio of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 is generally 2:1:1; the resistance values ​​of the fourth resistor R4 and the fifth resistor R5 are generally 4 times the resistance value of the sixth resistor R6.

[0054] The non-inverting input terminal of the third operational amplifier A3, the non-inverting input terminal of the fourth operational amplifier A4, and the base of the twenty-third transistor Q23 are all electrically connected to the output terminal of the first operational amplifier A1, the emitter of the twenty-third transistor Q23 is grounded via the first resistor R1, the inverting input terminal of the third operational amplifier A3 is electrically connected to the collector of the twenty-second transistor Q22 and the collector of the twenty-third transistor Q23, respectively, the output terminal of the third operational amplifier A3 is electrically connected to the base of the twelfth transistor Q12 and the base of the twenty-second transistor Q22, respectively, and the emitter of the twelfth transistor Q12 and the emitter of the second-second transistor Q22 are both connected to the supply voltage VDD.

[0055] An inverting input terminal of the fourth operational amplifier A4 is grounded via a second resistor R2, and an output terminal of the fourth operational amplifier A4 is electrically connected to the base of the third transistor Q3, the base of the fourth transistor Q4, and the base of the tenth transistor Q10, respectively; an emitter of the third transistor Q3, the emitter of the fourth transistor Q4, and the emitter of the tenth transistor Q10 are all connected to a supply voltage VDD, and a collector of the third transistor Q3 is electrically connected to the inverting input terminal of the fourth operational amplifier A4.

[0056] The collector of the fourth transistor Q4 is electrically connected with the collector of the fifth transistor Q5, the base of the fifth transistor Q5, the base of the sixth transistor Q6 and the base of the seventh transistor Q7 respectively, the emitter of the fifth transistor Q5, the emitter of the sixth transistor Q6 and the emitter of the seventh transistor Q7 are grounded; the collector of the sixth transistor Q6 is electrically connected with the collector of the seventh transistor Q7 through the third resistor R3.

[0057] The collector of the sixth transistor Q6 is also electrically connected with the drain of the first MOS transistor M1 and the base of the tenth transistor Q13 respectively, the gate of the first MOS transistor M1 is electrically connected with the gate of the sixth MOS transistor M6, the drain of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7 respectively, the source of the first MOS transistor M1 is electrically connected with the collector of the eighth transistor Q8, the base of the eighth transistor Q8 is electrically connected with the base of the seventeenth transistor Q17, the collector of the seventeenth transistor Q17, the base of the eighteenth transistor Q18 and the base of the twenty-third transistor Q20 respectively, the emitter of the eighth transistor Q8, the emitter of the seventeenth transistor Q17, the emitter of the eighteenth transistor Q18 and the emitter of the twenty-third transistor Q20 are all connected with the power supply voltage VDD.

[0058] The collector of the seventh transistor Q7 is also electrically connected with the drain of the second MOS transistor M2 and the base of the eleventh transistor Q11 respectively, the gate of the second MOS transistor M2 is electrically connected with the gate of the third MOS transistor M3 and the drain of the third MOS transistor M3 respectively, the source of the second MOS transistor M2 is electrically connected with the collector of the ninth transistor Q9, the base of the ninth transistor Q9 is electrically connected with the base of the fifteenth transistor Q15, the base of the sixteenth transistor Q16 and the collector of the sixteenth transistor Q16 respectively, the emitter of the ninth transistor Q9, the emitter of the fifteenth transistor Q15 and the emitter of the sixteenth transistor Q16 are all connected with the power supply voltage VDD, the source of the third MOS transistor M3 is electrically connected with the collector of the fifteenth transistor Q15.

[0059] The emitter of the tenth transistor Q13 is grounded, the collector of the tenth transistor Q13 is electrically connected with the collector of the twelfth transistor Q12 and the base of the nineteenth transistor Q19 respectively, the emitter of the nineteenth transistor Q19 is grounded through the fifth resistor R5, the collector of the nineteenth transistor Q19 is electrically connected with the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6 respectively; the drain of the fifth MOS transistor M5 is grounded, the source of the fifth MOS transistor M5 is electrically connected with the collector of the seventeenth transistor Q17, the source of the sixth MOS transistor M6 is electrically connected with the collector of the eighteenth transistor Q18.

[0060] The emitter of the eleventh triode Q11 is grounded, and the collector of the eleventh triode Q11 is electrically connected to the collector of the tenth triode Q10, the base of the fourteenth triode Q14, and the base of the twenty-first triode Q21 respectively. The emitter of the fourteenth triode Q14 is grounded via the fourth resistor R4, and the collector of the fourteenth triode Q14 is electrically connected to the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 respectively. The drain of the fourth MOS transistor M4 is grounded, and the source of the fourth MOS transistor M4 is electrically connected to the collector of the sixteenth triode Q16.

[0061] An emitter of the twenty-first transistor Q21 is grounded via a sixth resistor R6. A collector of the twenty-first transistor Q21 is electrically connected to a drain of a seventh MOS transistor M7. The drain of the seventh MOS transistor M7 serves as a correction terminal of the high-order curvature correction circuit 300 and is electrically connected to a second end of a ninth resistor R9. A source of the seventh MOS transistor M7 is electrically connected to a collector of the twenty-third transistor Q20.

[0062] The working principle of this embodiment is as follows:

[0063] See also Figure 1 and Figure 2 When the high-order curvature correction circuit 300 injects current into the bandgap core circuit 100, the reference voltage V generated by the bandgap core circuit 100 is REF The expression is as follows:

[0064]

[0065] Among them, V BE Represents the voltage between the base and emitter of the second transistor Q2; V T Indicates thermal voltage; N indicates the ratio of the number of the first transistor to the second transistor, that is, I IN represents the current value injected by the high-order curvature correction circuit 300.

[0066] When the high-order curvature correction circuit 300 draws current from the bandgap core circuit 100, the reference voltage V generated by the bandgap core circuit 100 REF The expression is as follows:

[0067]

[0068] Among them, I OUT represents the current value drawn by the high-order curvature correction circuit 300.

[0069] Thermal voltage V T It is the potential difference that occurs due to the temperature difference between two points in a closed circuit, also known as the voltage equivalent of temperature. Its calculation formula is as follows:

[0070]

[0071] Where k represents the Boltzmann constant; T represents the actual ambient temperature (T is the thermodynamic temperature, unit is K); q represents the charge of the electron.

[0072] V BE The expression is as follows:

[0073]

[0074] Among them, V g0 Indicates V when the temperature is 0K BE T0 represents the selected temperature; V BE (T0) indicates the temperature V when T0 BE The value of; η, m are process-related constants that do not change with temperature.

[0075] according to Figure 2 It can be seen that since the non-inverting input terminals of the third operational amplifier A3 and the fourth operational amplifier A4 are connected to the reference voltage V output by the bandgap core circuit 100, REF , then the current I flowing through the first resistor R1 PTAT for:

[0076]

[0077] The current I flowing through the second resistor R2 REF for:

[0078]

[0079] Among them, V BE23 It represents the voltage between the base and the emitter of the twenty-third transistor Q23. REF With zero temperature coefficient, V BE has a negative temperature coefficient, so I PTAT Has a positive temperature coefficient, I REF Has zero temperature coefficient.

[0080] Since the emitter area of ​​the 22nd transistor Q22 is twice the emitter area of ​​the 12th transistor Q12, the current flowing through the 12th transistor Q12 and the 13th transistor Q13 is I PTAT / 2, the voltage V at the base point A of the thirteenth transistor Q13 A for:

[0081]

[0082] Among them, I S13represents the current flowing through the thirteenth transistor Q13 (i.e., the current of the collector or emitter of the thirteenth transistor Q13); since the emitter area ratio of the third transistor Q3, the fourth transistor Q4, and the tenth transistor Q10 is 4:1:1, the current flowing through the fourth transistor Q4, the fifth transistor Q5, the tenth transistor Q10, and the eleventh transistor Q11 is I REF / 4, the voltage V at the base voltage point B of the eleventh transistor Q11 B for

[0083]

[0084] Among them, I S11 represents the current flowing through the eleventh transistor Q11.

[0085] The current flowing through the twenty-third transistor Q20 and the seventh MOS transistor M7 is marked as I1. Since the emitter area ratio of the eighth transistor Q8, the seventeenth transistor Q17, the eighteenth transistor Q18, and the twenty-third transistor Q20 is 2:1:1:4, and the width-to-length ratio of the first MOS transistor M1, the fifth MOS transistor M5, the sixth MOS transistor M6, and the seventh MOS transistor M7 is 2:1:1:4, the current flowing through the eighteenth transistor Q18, the seventeenth transistor Q17, the fifth MOS transistor M5, the sixth MOS transistor M6, the nineteenth transistor Q19, and the fifth resistor R5 is I1 / 4. Since the resistance of the fifth resistor R5 is four times that of the sixth resistor R6, the current flowing through the eighth transistor Q8 and the first MOS transistor M1 is I1 / 2.

[0086] The current flowing through the twenty-first transistor Q21 and the sixth resistor R6 is labeled as I2. Since the emitter area ratio of the fourteenth transistor Q14 to the twenty-first transistor Q21 is 1:4, and the resistance ratio of the fourth resistor R4 to the sixth resistor R6 is 4:1, the current flowing through the fourteenth transistor Q14, the fourth resistor R4, the third MOS transistor M3, and the fifteenth transistor Q15 is I2 / 4. Since the emitter area ratio of the ninth transistor Q9, the fifteenth transistor Q15, and the sixteenth transistor Q16 is 2:1:1, and the width-to-length ratio of the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 is 2:1:1, the current flowing through the sixteenth transistor Q16 and the fourth MOS transistor M4 is I2 / 4, and the current flowing through the ninth transistor Q9 and the second MOS transistor M2 is I2 / 2.

[0087] If I PTAT / 2<I REF / 4, then the voltage at point B is higher than that at point A, and the current I flowing from point B to point A BA for

[0088]

[0089] Since the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is 2:1:1, the current flowing through the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is I REF / 4, I REF / 8 and I REF / 8, respectively, then

[0090] I REF / 8 ＝ I1 / 2+I BA

[0091] I2 / 2 ＝ I REF / 8+I BA

[0092] It is calculated that

[0093]

[0094] The current I OUT extracted from the bandgap core circuit 100 is

[0095]

[0096] The reference voltage V REF output by the bandgap core circuit 100 is

[0097]

[0098] Substituting I PTAT and I REF , we have

[0099]

[0100] The second term and the third term in the above formula are linear terms of temperature, and the fourth term is a high-order term of temperature, so it can be seen that the second-order term of temperature in V BE can be offset by adjusting the resistance values of the first resistor R1, the second resistor R2, the third resistor R3, the ninth resistor R9 and the tenth resistor R10, and the high-order term of temperature in V BE can be offset by adjusting the resistance values of the third resistor R3 and the tenth resistor R10.

[0101] If I PTAT / 2>I REF / 4, the voltage at point A is higher than that at point B, and the current I BA flowing from point A to point B is

[0102]

[0103] Since the emitter area ratio of the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 is 2:1:1, the currents flowing through the fifth transistor Q5, the sixth transistor Q6 and the seventh transistor Q7 are I REF / 4、I REF / 8 and I REF / 8, then

[0104] I REF / 8 ＝ I1 / 2-I BA

[0105] I2 / 2 ＝ I REF / 8-I BA

[0106] Calculated

[0107]

[0108] The current I injected into the bandgap core circuit 100 IN for

[0109]

[0110] The reference voltage V output by the bandgap core circuit 100 REF for

[0111]

[0112] Will I PTAT and I REF Substitute, and we get

[0113]

[0114] The second and third terms in the above formula are linear terms of temperature, and the fourth term is a high-order term of temperature. It can be seen that by adjusting the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, the ninth resistor R9 and the tenth resistor R10, the V BE The second-order temperature term in V can be offset by adjusting the resistance of the third resistor R3 and the tenth resistor R10. BE The temperature high-order terms in .

[0115] In summary, if I PTAT / 2≠I REF / 4, the circuit structure of this embodiment can be used to achieve high-order curvature compensation correction.

[0116] This embodiment also uses SMIC 0.35um CMOS process to carry out simulation, and the reference voltage after high-order curvature compensation is simulated. The simulation results are as follows: Figure 3As shown in Figure 4, the output voltage deviation is only 401uV within the range of -55°C to 125°C, with a temperature coefficient of 1.84ppm / °C. Simulation results for the first-order curvature correction circuit are shown in Figure 4, showing that the output voltage deviation is 3.45mV within the range of -55°C to 125°C, with a temperature coefficient of 15.4ppm / °C. This demonstrates that the high-order curvature correction circuit 300 proposed in this embodiment significantly improves the temperature characteristics of the reference voltage.

[0117] This embodiment proposes a novel high-order curvature correction technique that can compensate for high-order curvature over temperature, thereby effectively improving the accuracy of the output reference voltage, reducing the temperature coefficient, and improving the temperature stability of the reference voltage. Furthermore, this embodiment has a simple circuit structure, occupies a small chip area, and is highly practical.

[0118] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A reference voltage source with a high-order curvature compensation function, characterized in that: include Bandgap core circuit for generating reference voltage V REF ; Common mode feedback circuit for reference voltage V REF Generate a common-mode voltage and return the common-mode voltage to the bandgap core circuit through negative feedback to increase the stability of the bandgap core circuit; as well as High-order curvature correction circuit for adjusting the reference voltage V REF Extracting or injecting current into the bandgap core circuit to eliminate high-order errors caused by temperature in the bandgap core circuit; The bandgap core circuit includes an eighth MOS transistor, a second triode, a first operational amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and N first triodes connected in parallel, where N is an integer greater than or equal to 1; The source of the eighth MOS transistor is connected to the external power supply voltage, the gate is electrically connected to the output terminal of the common-mode feedback circuit, and the drain is electrically connected to the first ends of the seventh resistor and the eighth resistor respectively; the second end of the seventh resistor is electrically connected to the inverting input terminal of the first operational amplifier and the collectors of the N first transistors respectively; the second end of the eighth resistor is electrically connected to the non-inverting input terminal of the first operational amplifier and the collector of the second transistor respectively; the base of the second transistor and the bases of the N first transistors are both electrically connected to the output terminal of the first operational amplifier; The non-inverting input terminal of the first operational amplifier is electrically connected to the first input terminal of the common-mode feedback circuit, and the inverting input terminal of the first operational amplifier is electrically connected to the second input terminal of the common-mode feedback circuit; the output terminal of the first operational amplifier is used to generate a reference voltage V REF , the output terminal of the first operational amplifier is electrically connected to the third input terminal of the common-mode feedback circuit and the input terminal of the high-order curvature correction circuit respectively; The emitters of the N first transistors are all electrically connected to the first end of the ninth resistor, and the emitter of the second transistor is electrically connected to the second end of the ninth resistor; the second end of the ninth resistor is grounded through the tenth resistor, and the second end of the ninth resistor is also electrically connected to the correction end of the high-order curvature correction circuit.

2. The reference voltage source with high-order curvature compensation function according to claim 1, wherein: The eighth MOS transistor is a PMOS transistor; the second transistor and the N first transistors are all NPN transistors.

3. The reference voltage source with high-order curvature compensation function according to claim 1, wherein: The seventh resistor and the eighth resistor are of the same type and size.

4. The reference voltage source with high-order curvature compensation function according to claim 1, wherein: The ratio of the sum of the saturation currents of the N first transistors to the saturation current of the second transistor is N:

1.

5. The reference voltage source with high-order curvature compensation function according to claim 1, wherein: The emitter area of ​​each of the first transistors is the same as the emitter area of ​​the second transistors.

6. The reference voltage source with high-order curvature compensation function according to any one of claims 1 to 5, characterized in that: The common-mode feedback circuit includes a second operational amplifier, a first input terminal of the second operational amplifier being electrically connected to the non-inverting input terminal of the first operational amplifier as the first input terminal of the common-mode feedback circuit, a second input terminal of the second operational amplifier being electrically connected to the inverting input terminal of the first operational amplifier as the second input terminal of the common-mode feedback circuit, a third input terminal of the second operational amplifier being electrically connected to the output terminal of the first operational amplifier as the third input terminal of the common-mode feedback circuit, and an output terminal of the second operational amplifier being electrically connected to the gate of the eighth MOS transistor as the output terminal of the common-mode feedback circuit.

7. The reference voltage source with high-order curvature compensation function according to claim 6, wherein: The high-order curvature correction circuit includes a third operational amplifier, a fourth operational amplifier, a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode, a tenth triode, an eleventh triode, a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode, a sixteenth triode, a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twenty-third triode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor; The non-inverting input terminal of the third operational amplifier, the non-inverting input terminal of the fourth operational amplifier, and the base of the twenty-third triode are all electrically connected to the output terminal of the first operational amplifier, the emitter of the twenty-third triode is grounded via a first resistor, the inverting input terminal of the third operational amplifier is electrically connected to the collector of the twenty-second triode and the collector of the twenty-third triode, respectively, the output terminal of the third operational amplifier is electrically connected to the base of the twelfth triode and the base of the twenty-second triode, respectively, and the emitter of the twelfth triode and the emitter of the twenty-second triode are both connected to an external power supply voltage; The inverting input terminal of the fourth operational amplifier is grounded via a second resistor, and the output terminal of the fourth operational amplifier is electrically connected to the base of the third transistor, the base of the fourth transistor, and the base of the tenth transistor, respectively; the emitter of the third transistor, the emitter of the fourth transistor, and the emitter of the tenth transistor are all connected to an external power supply voltage, and the collector of the third transistor is electrically connected to the inverting input terminal of the fourth operational amplifier; The collector of the fourth transistor is electrically connected to the collector of the fifth transistor, the base of the fifth transistor, the base of the sixth transistor, and the base of the seventh transistor, respectively; the emitter of the fifth transistor, the emitter of the sixth transistor, and the emitter of the seventh transistor are all grounded; the collector of the sixth transistor is electrically connected to the collector of the seventh transistor via a third resistor; The collector of the sixth triode is further electrically connected to the drain of the first MOS transistor and the base of the thirteenth triode respectively; the gate of the first MOS transistor is electrically connected to the gate of the sixth MOS transistor, the drain of the sixth MOS transistor, and the gate of the seventh MOS transistor respectively; the source of the first MOS transistor is electrically connected to the collector of the eighth triode; the base of the eighth triode is electrically connected to the base of the seventeenth triode, the collector of the seventeenth triode, the base of the eighteenth triode, and the base of the twenty-third triode respectively; the emitter of the eighth triode, the emitter of the seventeenth triode, the emitter of the eighteenth triode, and the emitter of the twenty-third triode are all connected to an external power supply voltage; The collector of the seventh triode is further electrically connected to the drain of the second MOS transistor and the base of the eleventh triode, respectively; the gate of the second MOS transistor is electrically connected to the gate of the third MOS transistor and the drain of the third MOS transistor, respectively; the source of the second MOS transistor is electrically connected to the collector of the ninth triode; the base of the ninth triode is electrically connected to the base of the fifteenth triode, the base of the sixteenth triode, and the collector of the sixteenth triode, respectively; the emitters of the ninth triode, the fifteenth triode, and the sixteenth triode are all connected to an external power supply voltage; and the source of the third MOS transistor is electrically connected to the collector of the fifteenth triode; The emitter of the thirteenth transistor is grounded, the collector of the thirteenth transistor is electrically connected to the collector of the twelfth transistor and the base of the nineteenth transistor respectively, the emitter of the nineteenth transistor is grounded via a fifth resistor, the collector of the nineteenth transistor is electrically connected to the gate of the fifth MOS transistor and the gate of the sixth MOS transistor respectively; the drain of the fifth MOS transistor is grounded, the source of the fifth MOS transistor is electrically connected to the collector of the seventeenth transistor, and the source of the sixth MOS transistor is electrically connected to the collector of the eighteenth transistor; The emitter of the eleventh triode is grounded, the collector of the eleventh triode is electrically connected to the collector of the tenth triode, the base of the fourteenth triode, and the base of the twenty-first triode respectively, the emitter of the fourteenth triode is grounded via a fourth resistor, the collector of the fourteenth triode is electrically connected to the gate of the third MOS transistor and the gate of the fourth MOS transistor respectively; the drain of the fourth MOS transistor is grounded, and the source of the fourth MOS transistor is electrically connected to the collector of the sixteenth triode; The emitter of the twenty-first transistor is grounded through a sixth resistor, the collector of the twenty-first transistor is electrically connected to the drain of the seventh MOS transistor, the drain of the seventh MOS transistor is electrically connected to the second end of the ninth resistor as a correction end of the high-order curvature correction circuit, and the source of the seventh MOS transistor is electrically connected to the collector of the twenty-third transistor.

8. The reference voltage source with high-order curvature compensation function according to claim 7, wherein: The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor and the seventh MOS transistor are all PMOS transistors; The third triode, the fourth triode, the eighth triode, the ninth triode, the tenth triode, the twelfth triode, the fifteenth triode, the sixteenth triode, the seventeenth triode, the eighteenth triode, the twenty-third triode and the twenty-second triode are all PNP triodes; The fifth triode, the sixth triode, the seventh triode, the eleventh triode, the thirteenth triode, the fourteenth triode, the nineteenth triode, the twenty-first triode and the twenty-third triode are all NPN triodes.

9. The reference voltage source with high-order curvature compensation function according to claim 7, wherein: The emitter area ratio of the third, fourth and tenth triodes is 4:1:1; the emitter area ratio of the fifth, sixth and seventh triodes is 2:1:1; the emitter area ratio of the eighth, seventeenth, eighteenth and twenty-third triodes is 2:1:1:4; the emitter area ratio of the ninth, fifteenth and sixteenth triodes is 2:1:1; the emitter area ratio of the twelfth and twenty-second triodes is 1:2; the emitter area ratio of the fourteenth and twenty-first triodes is 1:4; the width-to-length ratio of the first, fifth, sixth and seventh MOS transistors is 2:1:1:4; the width-to-length ratio of the second, third and fourth MOS transistors is 2:1:1; and the resistance values ​​of the fourth and fifth resistors are both four times that of the sixth resistor.

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