Controller and storage device

Abstract

The present disclosure relates to a controller and a storage device that beforehand starts loading mapping data before outputting a signal corresponding to a read buffer command of a host device, encodes the mapping data using a plurality of mapping loading regions and a plurality of encoding regions, and provides the encoded mapping data to the host device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0103873, filed on August 9, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the disclosed technology generally relate to a controller and a storage device. Background Art

[0004] The storage device may include a memory including a plurality of memory cells and storing data. The storage device may include a controller controlling the operation of the memory.

[0005] For example, the controller may control an operation of writing data to the memory according to a command input from a host device located outside the storage device. The controller may control an operation of reading or erasing data written to the memory according to a command input from the host device.

[0006] The operation of the storage device according to the command of the host device may require a certain amount of time. Therefore, measures that can reduce the amount of time are sought to improve the performance of the storage device. Summary of the invention

[0007] Various embodiments of the disclosed technology are directed to providing measures capable of reducing the time required for a storage device to operate according to a command of a host device and improving data processing speed when viewed from the host device side.

[0008] In an embodiment of the disclosed technology, a storage device may include: a memory including multiple storage areas; and a controller configured to transmit a read buffer recommendation signal to a host device based on a read count of data stored in each of the multiple storage areas, and start a load operation of storing mapping data associated with the read buffer recommendation signal in a buffer memory before receiving a read buffer command corresponding to the read buffer recommendation signal from the host device.

[0009] In an embodiment of the disclosed technology, a controller may include: a buffer memory; a first processor configured to output a read buffer prompt signal when a read count is greater than or equal to a preset value, and start a load operation to store mapping data associated with the read buffer prompt signal in the buffer memory, the read count being for data stored in each of a plurality of storage areas included in an external memory; and a second processor configured to transmit a read buffer recommendation signal to a host device in response to the read buffer prompt signal, the read buffer recommendation signal being transmitted after the loading operation starts.

[0010] In an embodiment of the disclosed technology, a controller may include: a buffer memory; a first processor configured to output a read buffer prompt signal when a read count is greater than or equal to a preset value, and store mapping data associated with the read buffer prompt signal in a mapping loading area of ​​the buffer memory, the read count being for data stored in each of a plurality of storage areas included in an external memory; and a second processor configured to transmit a read buffer recommendation signal to a host device in response to the read buffer prompt signal, wherein the second processor transmits a first read buffer recommendation signal and a second read buffer recommendation signal to the host device, encodes first mapping data stored in a first mapping loading area of ​​the buffer memory and stores the encoded first mapping data in a first encoding area of ​​the buffer memory in response to a first read buffer command corresponding to the first read buffer recommendation signal, and encodes second mapping data stored in a second mapping loading area of ​​the buffer memory and stores the encoded second mapping data in a second encoding area of ​​the buffer memory in response to a second read buffer command corresponding to the second read buffer recommendation signal.

[0011] According to an embodiment of the disclosed technology, the time required for a storage device to operate according to a command of a host device can be reduced, thereby improving the performance of the storage device and the data processing speed of the host device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing an example of a schematic configuration of a storage device based on an embodiment of the disclosed technology.

[0013] Figure 2 is a diagram illustrating an example of a method in which a storage device provides mapping data to a host device based on an embodiment of the disclosed technology.

[0014] Figure 3 and Figure 4 is a diagram illustrating an example of a process in which a storage device loads mapping data to provide the mapping data to a host device based on an embodiment of the disclosed technology.

[0015] Figures 5 to 9 is a diagram illustrating an example of a method in which a storage device according to an embodiment of the disclosed technology provides a plurality of mapping data elements (or chunks or items) to a host device.

[0016] Fig.10 is a diagram illustrating an example of a method in which a storage device loads and encodes mapping data based on an embodiment of the disclosed technology. DETAILED DESCRIPTION

[0017] In the following description of examples or embodiments of the disclosed technology, the description will be made with reference to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown in a schematic manner, and even if the same reference numerals and symbols are shown in different drawings from each other, they can also be used to specify the same or similar components. Further, in the following description of examples or embodiments of the disclosed technology, when it is determined that a detailed description of the well-known functions and components incorporated herein may make the subject matter in some embodiments of the disclosed technology quite unclear, the description will be omitted. Terms such as "including", "having", "comprising", "consisting of", "consisting of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only". Unless the context clearly indicates otherwise, as used herein, the singular form is also intended to include the plural form.

[0018] Terms such as "first", "second", "A", "B", "(A)", and "(B)" may be used herein to describe elements of the disclosed technology. Each of these terms is not used to define the nature, order, sequence, or quantity of the elements, but is only used to distinguish the corresponding element from other elements.

[0019] When it is mentioned that a first element is “connected or coupled”, “contacted or overlapped”, etc. with a second element, it should be understood that not only the first element can be “directly connected or coupled” or “directly contacted or overlapped” with the second element, but also a third element can be “inserted” between the first element and the second element, or the first element and the second element can be “connected or coupled”, “contacted or overlapped”, etc. with each other via a fourth element. Here, the second element can be included in at least one of the two or more elements that are “connected or coupled”, “contacted or overlapped”, etc. with each other.

[0020] When time-related terms such as “after,” “subsequently,” “next,” “before,” etc. are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or method of manufacture, these terms may be used to describe non-sequential or non-sequential processes or operations unless used with the terms “directly” or “immediately.”

[0021] In addition, when referring to any size, relative size, etc., even if the relevant description is not detailed, it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Further, the term "may" fully includes all meanings of the term "can".

[0022] Hereinafter, various embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 is a diagram showing an example of a schematic configuration of a storage device 100 based on an embodiment of the disclosed technology.

[0024] Reference Figure 1 , a storage device 100 based on an embodiment of the disclosed technology may include a memory 110 and a controller 120 that controls an operation of the memory 110 .

[0025] For example, the memory 110 may be implemented as various types of nonvolatile memories, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and spin transfer torque random access memory (STT-RAM). The memory 110 may be implemented in a three-dimensional array structure. The embodiments of the disclosed technology may be applied not only to a flash memory in which a charge storage layer is configured by a floating gate, but also to a charge capture flash memory in which a charge storage layer is configured by an insulating film.

[0026] The memory 110 may include a plurality of memory blocks. A memory block may also be referred to as a storage block. The memory 110 may include a memory cell array including a plurality of memory cells storing data, and the memory cell array may exist in a memory block.

[0027] The memory 110 may operate in response to the control of the controller 120. The operation of the memory 110 may include, for example, a program operation (also referred to as a "write operation"), an erase operation, and a read operation.

[0028] The controller 120 may control a program operation, an erase operation, a read operation, and a background operation on the memory 110. The background operation may include, for example, at least one of garbage collection, wear leveling, read reclamation, and bad block management.

[0029] The controller 120 may control the operation of the memory 110 according to a request of a host device located outside the memory device 100. Alternatively, the controller 120 may control the operation of the memory 110 regardless of the request of the host device.

[0030] In the illustrated example, the controller 120 may control the operation of the memory 110 according to a request of the host device 200. The memory device 100 and the host device 200 may be collectively referred to as a computing system.

[0031] For example, the host device 200 may be a computer, an ultra mobile PC (UMPC), a workstation, a personal digital assistant (PDA), a tablet computer, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configuring a data center, one of various electronic devices configuring a home network, one of various electronic devices configuring a telematics network, an RFID (radio frequency identification) device, and a mobile device (e.g., a vehicle, a robot, or a drone) capable of traveling under human control or driving automatically, etc. Alternatively, the host device 200 may be a virtual / augmented reality (VR / AR) device that provides 2D or 3D virtual reality images or augmented reality images. In addition, the host device 200 may be any of various electronic devices that require a storage device 100 capable of storing data.

[0032] The host device 200 may include at least one operating system. The operating system may manage and control the overall functions and operations of the host device 200, and may control the interoperation between the host device 200 and the storage device 100. According to the mobility of the host device 200, the operating system may be divided into a general operating system and a mobile operating system.

[0033] The controller 120 and the host device 200 may be separate devices. In one embodiment, the controller 120 and the host device 200 may be implemented by being integrated into one device. Below, the controller 120 and the host device 200 are described as separate devices.

[0034] The controller 120 may include a host interface providing an interface for communicating with the host device 200. The controller 120 may include a memory interface providing an interface for communicating with the memory 110.

[0035] The controller 120 may include a control circuit that controls the overall operation of the controller 120. The control circuit may include, for example, at least one of a processor, a working memory, etc., and may optionally include an error detection and correction circuit.

[0036] The control circuit may communicate with the host device 200 through the host interface, and may communicate with the memory 110 through the memory interface.

[0037] The control circuit may perform a function of interpreting a command input from the host device 200 and transferring the command to the memory 110. This function may be performed by a processor included in the control circuit.

[0038] exist Figure 1 In the example shown, the control circuit may include a first processor 121 and a second processor 122 .

[0039] The first processor 121 and the second processor 122 may be physically different circuits, or may be functionally different configurations in a single circuit. For example, the first processor 121 and the second processor 122 may be implemented in the form of separate chips, or may be implemented in the form of a single chip.

[0040] The first processor 121 may correspond to a flash translation layer (FTL), for example. The first processor 121 may convert a logical block address provided by the host device 200 into a physical block address. The first processor 121 may receive a logical block address and convert the logical block address into a physical block address using a mapping table.

[0041] The second processor 122 may correspond to, for example, a host interface layer (HIL) The second processor 122 may interpret a command input from the host device 200 to the storage device 100 , and may transfer the command to the first processor 121 .

[0042] Furthermore, the control circuit may include a flash interface layer (FIL) that transmits a command instructed by the first processor 121 to the memory 110 .

[0043] The control circuit may, for example, run firmware to control the operation of the controller 120. The control circuit may run (drive) the firmware contained in the working memory at startup. The operation of the storage device 100 described in the embodiment of the disclosed technology may be implemented in a manner that the control circuit runs firmware that defines the corresponding operation.

[0044] The firmware is a program to be executed in the storage device 100 to drive the storage device 100, and may include various functional layers corresponding to the above-mentioned processor. For example, the firmware may include binary data respectively defining codes for executing corresponding functional layers.

[0045] For example, the firmware may be loaded into the working memory from the memory 110 or a separate nonvolatile memory (e.g., ROM or NOR flash memory) located outside the memory 110. The control circuit may first load all or part of the firmware into the working memory when running a startup operation after power-on.

[0046] The control circuit may execute the logic operations defined in the firmware loaded into the working memory to control the overall operation of the controller 120. The control circuit may control the controller 120 to generate commands or signals according to the result of executing the logic operations defined in the firmware. When a portion of the firmware defining the logic operations to be executed is not loaded into the working memory, the control circuit may generate an event (e.g., an interrupt) for loading the corresponding portion of the firmware into the working memory.

[0047] The working memory may store firmware, program code, commands, or data required to drive the controller 120 .

[0048] The working memory may be located inside or outside the controller 120. In one embodiment, the working memory may be located inside and outside the controller 120.

[0049] exist Figure 1 In the example shown, the working memory may be a buffer memory 123. Alternatively, the buffer memory 123 may be provided separately from the working memory. The buffer memory 123 may be located inside or outside the controller 120.

[0050] The working memory or buffer memory 123 may include, for example, at least one of volatile memories such as static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM).

[0051] In controlling the operation of the memory 110 according to the command of the host device 200 , the controller 120 may perform control to improve the operation performance of the memory device 100 according to the type of the command of the host device 200 or the operation state of the memory 110 .

[0052] For example, the storage device 100 may control an operation of providing the host device 200 with mapping data associated with data having a large read count of the host device 200. The mapping data may be, for example, data indicating a mapping relationship between a logical block address transmitted from the host device 200 and a physical block address of the memory 110. By providing the mapping data to the host device 200, the performance of the read operation of the host device 200 may be improved. If the mapping data is not provided to the host device 200, the controller 120 needs to read the mapping data stored in the memory 110 to process the read command of the host device 200. However, if the mapping data is provided to the host device 200, the controller 120 may provide user data according to the read command without reading the mapping data from the memory 110.

[0053] Figure 2 is a diagram illustrating an example of a method in which the storage device 100 provides mapping data to the host device 200 based on an embodiment of the disclosed technology.

[0054] Reference Figure 2 , the controller 120 of the storage device 100 may control an operation of reading data stored in the memory 110 according to a command received from the host device 200. The controller 120 may read the data stored in the memory 110 and transmit the data to the host device 200.

[0055] The memory 110 may include a plurality of storage areas SA, for example, SA1 - SA4 , and the plurality of storage areas SA may correspond to at least one memory block.

[0056] The controller 120 may control the read operation according to the command of the host device 200, and may count the read count of the storage area SA included in the memory 110. When the read count of the storage area SA is greater than or equal to a preset value, the controller 120 may control the operation of providing the host device 200 with mapping data associated with the corresponding storage area SA.

[0057] For example, the first processor 121 of the controller 120 may count the read count according to the read operation, and when the read count is greater than or equal to a preset value, may output a read buffer prompt signal to provide mapping data of the corresponding storage area SA. The first processor 121 may transmit the read buffer prompt signal to the second processor 122.

[0058] In response to the read buffer hint signal, the second processor 122 may transmit a read buffer recommendation signal to the host device 200 .

[0059] In response to the read buffer recommendation signal, the host device 200 may transmit a read buffer command corresponding to the read buffer recommendation signal to the controller 120. The read buffer command may be a command requesting provision of mapping data of the storage area SA according to the read buffer recommendation signal.

[0060] In response to the read buffer command, the second processor 122 of the controller 120 may transmit a map load request signal requesting to load corresponding map data to the first processor 121 .

[0061] The first processor 121 may perform an operation of loading the mapping data stored in the memory 110 according to the mapping load request signal. The first processor 121 may read the mapping data stored in the memory 110 and store the mapping data in the buffer memory 123.

[0062] When loading of the map data into the buffer memory 123 is completed, the first processor 121 may transmit a map loading completion signal to the second processor 122 .

[0063] In response to the map loading completion signal, the second processor 122 may perform an operation of encoding the map data loaded into the buffer memory 123. The second processor 122 may store the encoded map data in an area different from an area storing the map data in the buffer memory 123. In this specification, the encoded map data may be referred to as encoded data.

[0064] When encoding of the mapping data is completed, the second processor 122 may transmit an encoding data ready signal to the host device 200. Further, the second processor 122 may transmit an encoding completion signal to the first processor 121.

[0065] In response to the encoded data ready signal, the host device 200 may perform an operation of moving the encoded data stored in the buffer memory 123 to a host memory included in the host device 200. The host device 200 may transmit a read command to the storage device 100 based on the mapping data stored in the host memory, thereby reducing the time required for the read operation and improving the performance of the read operation.

[0066] In order to improve the performance of the control operation of providing the map data to the host device 200 , the controller 120 may variously control a time point of loading the map data into the buffer memory 123 .

[0067] For example, before transmitting the read buffer hint signal to the second processor 122, the first processor 121 of the controller 120 may start a load operation of storing the mapping data stored in the memory 110 in the buffer memory 123. Alternatively, the first processor 121 may start the load operation at a time point of transmitting the read buffer hint signal or before receiving a mapping load request signal after transmitting the read buffer hint signal.

[0068] Since the first processor 121 starts the loading operation of mapping data before the second processor 122 receives a read buffer command corresponding to a read buffer prompt signal or before the first processor 122 receives a mapping load request signal according to the read buffer command, the time delay of the loading operation of mapping data can be prevented or reduced.

[0069] The time point at which the first processor 121 loads the mapping data into the buffer memory 123 can be advanced, and the time point at which the mapping data is provided to the host device 200 can be advanced. Since the delay in the time point at which the mapping data of the storage area SA with a large read count is provided to the host device 200 is prevented or reduced, the performance of the read operation can be improved.

[0070] Figure 3 and Figure 4is a diagram illustrating an example of a process in which the storage device 100 loads mapping data to provide the mapping data to the host device 200 based on an embodiment of the disclosed technology.

[0071] Reference Figure 3 When it is determined that the storage area SA has a read count greater than or equal to the preset value, the first processor 121 may output a read buffer prompt signal to the second processor 122. When it is determined to output the read buffer prompt signal, the first processor 121 may start a load operation of storing the mapping data of the corresponding storage area SA in the buffer memory 123 before outputting the read buffer prompt signal. Alternatively, the first processor 121 may start the load operation after outputting the read buffer prompt signal.

[0072] The second processor 122 may transmit a read buffer recommendation signal to the host device 200 in response to the read buffer hint signal. The second processor 122 may receive a read buffer command from the host device 200 corresponding to the read buffer recommendation signal.

[0073] In response to the read buffer command, the second processor 122 may transmit a map load request signal to the first processor 121 .

[0074] Figure 3 The illustrated example represents a case where map loading is being performed at the point in time when the first processor 121 receives the map loading request signal.

[0075] When loading of the map data is completed after receiving the map load request signal, the first processor 121 may transmit a map load completion signal to the second processor 122. In response to the map load completion signal, the second processor 122 may encode the map data stored in the buffer memory 123. When encoding is completed, the second processor 122 may transmit an encoding data ready signal to the host device 200, and transmit an encoding completion signal to the first processor 121.

[0076] like Figure 3 As shown at time t1 in FIG. 1 , the first processor 121 starts the loading operation of the mapping data before outputting the read buffer prompt signal. Therefore, compared with the case where the loading operation of the mapping data is started after receiving the mapping load request signal, the loading operation of the mapping data is started earlier at time t1. Therefore, the time point of completing the loading of the mapping data can be advanced.

[0077] The time to be reduced may be increased according to a time point at which the read buffer command is transmitted from the host device 200 to the controller 120 .

[0078] In such Figure 4In the example shown, the first processor 121 may output a read buffer hint signal and may start a load operation of the mapping data.

[0079] The time point at which the host device 200 that has received the read buffer recommendation signal from the second processor 122 transmits the read buffer command may vary according to the operation of the host device 200. For example, the time point at which the host device 200 transmits the read buffer command may be the time point at which the first processor 121 completes the load operation of the mapping data.

[0080] In this case, the time point at which the first processor 121 receives the map load request signal corresponding to the read buffer command may correspond to a state in which the load operation of the map data is completed. The first processor 121 may transmit a map load completion signal corresponding to the map load request signal to the second processor 122. The process of encoding the map data and the process of providing the encoded data to the host device 200 may be performed without delay.

[0081] Since the load operation of the mapping data is completed before receiving the read buffer command or the mapping load request signal (corresponding to Figure 4 The time t2 shown in the figure can thus shorten the process of providing the mapping data to the host device 200.

[0082] By reducing the time required for the operation of providing the host device 200 with mapping data, the performance of the read operation for data stored in the storage area SA having a large read count can be improved.

[0083] In an embodiment of the disclosed technology, when there are multiple storage areas SA whose read counts are greater than or equal to a preset value, multiple mapping data elements (or blocks or items) can be loaded and encoded, thereby further improving the performance of the operation of providing mapping data to the host device 200.

[0084] Figures 5 to 9 is a diagram illustrating an example of a method in which the storage device 100 loads mapping data to provide a plurality of mapping data elements to the host device 200 based on an embodiment of the disclosed technology.

[0085] Reference Figure 5 , which corresponds to a case where the read count of the first storage area SA1 among the plurality of storage areas SA1 , SA2 , SA3 , SA4 , . . . included in the memory 110 is greater than or equal to a preset value.

[0086] When the read count of the first storage area SA1 is greater than or equal to a preset value, the controller 120 may perform an operation of providing the host device 200 with the mapping data of the first storage area SA1.

[0087] For example, the first processor 121 may transmit a first read buffer hint signal to the second processor 122. Before transmitting the first read buffer hint signal, the first processor 121 may start a load operation of storing the first mapping data MD1 of the first storage area SA1 in the buffer memory 123. In one embodiment, the first processor 121 may start the load operation while outputting the first read buffer hint signal or after outputting the first read buffer hint signal.

[0088] The cache memory 123 may include a plurality of mapping load areas 500. For example, the cache memory 123 may include n mapping load areas 500_1, 500_2, 500_3, ..., 500_n, where n is an integer greater than or equal to 2, ie, n≥2.

[0089] The first processor 121 may perform a load operation of storing the first map data MD1 in the first map load area 500_1 of the buffer memory 123 .

[0090] In response to the first read buffer hint signal, the second processor 122 may transmit a first read buffer recommendation signal to the host device 200. The second processor 122 may receive, from the host device 200, a first read buffer command corresponding to the first read buffer recommendation signal.

[0091] In response to the first read buffer command, the second processor 122 may transmit a first map load request signal corresponding to the first read buffer command to the first processor 121 .

[0092] At the time point when the first processor 121 receives the first mapping load request signal, the loading operation of the first mapping data MD1 may be in progress or the loading operation of the first mapping data MD1 may be completed.

[0093] When the loading operation of the first mapping data MD1 is completed, the first processor 121 may transmit a first mapping loading completion signal to the second processor 122. Since the first processor 121 starts the loading operation of the first mapping data MD1 in advance, the time point of transmitting the first mapping loading completion signal to the second processor 122 is not delayed.

[0094] In response to the first map load completion signal, the second processor 122 may encode the first map data MD1 stored in the first map load area 500_1 , and thus may store the encoded data in the encoding area 600 of the buffer memory 123 .

[0095] The buffer memory 123 may include, for example, M encoding regions 600, where M is an integer satisfying the relationship n≥M≥2. Figure 5The case where the buffer memory 123 includes two encoding areas 600_1 and 600_2 is shown.

[0096] The second processor 122 may encode the first mapping data MD1 and store the encoded data in the first encoding area 600_1.

[0097] When the first encoded data ED1 obtained by encoding the first mapped data MD1 is stored in the first encoding area 600_1 , the second processor 122 may transmit a first encoded data ready signal to the host device 200 .

[0098] The second processor 122 may transmit a first encoding completion signal to the first processor 121. In response to the first encoding completion signal, the first processor 121 may recognize the first mapping loading area 500_1 as an available area.

[0099] The host device 200 can acquire the first encoded data ED1 stored in the first encoding area 600_1 at a necessary time point and use the first encoded data ED1 when transmitting a read command. Therefore, before the host device 200 acquires the first encoded data ED1 stored in the first encoding area 600_1, the first encoding area 600_1 is an unavailable area.

[0100] In an embodiment of the disclosed technology, since a plurality of map loading areas 500 and a plurality of encoding areas 600 are provided, a delay caused by a time for encoding map data in providing the map data to the host device 200 may be reduced.

[0101] Reference Figure 6 For example, the first processor 121 may count the read counts of the storage areas SA, and may check the storage areas SA where the read counts are greater than or equal to a preset value.

[0102] For example, in a state where the first mapping data MD1 of the first storage area SA1 is encoded and the first encoding data ED1 is stored in the first encoding area 600_1 , the read count of the second storage area SA2 may be greater than or equal to a preset value.

[0103] The first processor 121 may output a second read buffer hint signal to the second processor 122 according to the second storage area SA2. In addition, the first processor 121 may start a load operation of storing the second mapping data MD2 of the second storage area SA2 in the mapping load area 500 of the buffer memory 123. The load operation may be started before the second read buffer hint signal is output.

[0104] For example, the first processor 121 may store the second map data MD2 in the second map load area 500_2 of the buffer memory 123 .

[0105] The second processor 122 may transmit a second read buffer recommendation signal to the host device 200 in response to the second read buffer hint signal. The second processor 122 may receive a second read buffer command corresponding to the second read buffer recommendation signal from the host device 200. In response to the second read buffer command, the second processor 122 may transmit a second map load request signal to the first processor 121.

[0106] The first processor 121 may transmit a second map load completion signal corresponding to the second map load request signal to the second processor 122 .

[0107] In response to the second map load completion signal, the second processor 122 may encode the second map data MD2 stored in the second map load area 500_2 so that the encoded data ED2 may be stored in the second encoding area 600_2.

[0108] When storage of the second encoded data ED2 in the second encoding area 600_2 is completed, the second processor 122 may transmit a second encoded data ready signal to the host device 200 .

[0109] The second processor 122 may transmit a second encoding completion signal to the first processor 121. In response to the second encoding completion signal, the first processor 121 may recognize the second mapping loading area 500_2 as an available area.

[0110] In a state where the first encoded data ED1 obtained by encoding the first mapping data MD1 is stored in the first encoding area 600_1, the second encoded data ED2 obtained by encoding the second mapping data MD2 may be stored in the second encoding area 600_2. A delay caused by the time required for encoding in providing mapping data to the host device 200 may be prevented or reduced.

[0111] When the time required to transmit the first encoded data ED1 of the first encoded region 600_1 to the host device 200 is longer than the time required to encode the second mapped data MD2, or when the sum of the standby time until the first encoded data ED1 of the first encoded region 600_1 is transmitted to the host device 200 and the transmission time is longer than the time required to encode the second mapped data MD2, the time required to encode the second mapped data MD2 may overlap with the standby time and / or the transmission time of the first mapped data MD1. The transmission time may correspond to the time when the encoded data of the encoded region is transmitted to the host device 200. The standby time may correspond to the time between the time point when the storage of the encoded data is completed and the time point when the transmission of the encoded data is started.

[0112] The time required to encode the second mapping data MD2 does not affect the total time in providing the first mapping data MD1 and the second mapping data MD2 to the host device 200. The total operation time may be the time that reduces at least a portion of the time required to encode the second mapping data MD2.

[0113] In this way, according to an embodiment of the disclosed technology, the time point of starting the loading operation of the mapping data is adjusted, and the operation of providing the mapping data to the host device 200 is performed by setting a plurality of mapping loading areas 500 and a plurality of encoding areas 600. Therefore, the delay in the process of providing the mapping data to the host device 200 can be prevented or reduced, and the performance of the read operation can be improved.

[0114] After the encoded data is stored in the first and second encoding areas 600_1 and 600_2, loading and encoding operations of mapping data for the new storage area SA may be performed, and processing of additional mapping data may be performed in various ways according to the states of the first and second encoding areas 600_1 and 600_2.

[0115] Reference Figure 7 For example, the first processor 121 can check that the read count of the third storage area SA3 of the memory 110 is greater than or equal to the preset value. The first processor 121 can transmit the third read buffer prompt signal to the second processor 122, and can start the load operation of storing the third mapping data MD3 of the third storage area SA3 in the buffer memory 123.

[0116] For example, the third map data MD3 may be stored in the third map loading area 500_3 of the buffer memory 123. Optionally, after the first processor 121 receives the first encoding completion signal or the second encoding completion signal, the third map data MD3 may be stored in the first map loading area 500_1 or the second map loading area 500_2.

[0117] The second processor 122 may transmit the third read buffer recommendation signal to the host device 200. The second processor 122 may receive the third read buffer command from the host device 200, and may transmit the third map load request signal to the first processor 121. In response to the third map load completion signal from the first processor 121, the second processor 122 may perform encoding of the third map data MD3.

[0118] The second processor 122 may check whether the encoded data stored in the first encoding area 600_1 or the second encoding area 600_2 is transmitted. The encoded data stored in the first encoding area 600_1 or the second encoding area 600_2 may be transmitted according to a command of the host device 200, and the physical layer of the controller 120 may check whether the transmission of the encoded data to the host device is completed.

[0119] The second processor 122 may encode the third mapping data MD3 and store the encoded data in the encoding area 600 where the transmission of the encoded data in the first encoding area 600_1 and the second encoding area 600_2 is completed. For example, when the transmission of the first encoded data ED1 stored in the first encoding area 600_1 is completed, the second processor 122 may store the third encoded data ED3 obtained by encoding the third mapping data MD3 in the first encoding area 600_1.

[0120] Since the second processor 122 can sequentially perform encoding and the host device 200 can obtain encoded data by alternately using the two encoding areas 600 or continuously using one of the two encoding areas 600, the influence of the time required for encoding to be performed on the total operation time can be prevented or reduced.

[0121] In one embodiment, the second processor 122 may perform an operation of encoding the mapping data by modifying the encoding area 600 included in the buffer memory 123 .

[0122] Reference Figure 8 , a state in which first encoded data ED1 obtained by encoding first mapping data MD1 is stored in the first encoding region 600_1 and second encoded data ED2 obtained by encoding second mapping data ED2 is stored in the second encoding region 600_2 is shown as an example.

[0123] Through the first processor 121 , a third read buffer prompt signal may be output, and a load operation of the third mapping data MD3 may be performed. For example, the third mapping data MD3 may be stored in a third mapping load area 500_3 of the buffer memory 123 .

[0124] The second processor 122 may transmit a third read buffer recommendation signal to the host device 200 , and the host device 200 may transmit a third read buffer command to the second processor 122 .

[0125] The second processor 122 may transmit a third map load request signal to the first processor 121 , and may receive a third map load completion signal from the first processor 121 .

[0126] In response to the third map load completion signal, the second processor 122 may encode the third map data MD3 stored in the third map load area 500_3.

[0127] When encoding the third mapping data MD3, the second processor 122 may check whether the transmission of the encoded data stored in the first encoding area 600_1 and the second encoding area 600_2 is completed.

[0128] Refer to above Figure 7 In the depicted example, when there is an available encoding region 600 in the first encoding region 600_1 and the second encoding region 600_2 , the second processor 122 may use the corresponding encoding region 600 to store encoded data obtained by encoding the third mapping data MD3 .

[0129] When the transmission of the encoded data stored in the first encoding region 600_1 or the second encoding region 600_2 is not completed, the second processor 122 may allocate an additional encoding region 610 .

[0130] The additional code area 610 may be a part of the buffer memory 123 that is set to be used variably.

[0131] The second processor 122 may encode the third mapping data MD3 and store the encoded data ED3 in the additional encoding area 610 .

[0132] When encoding of the third map data MD3 is completed, the second processor 122 may transmit a third encoding data ready signal to the host device 200. The second processor 122 may transmit a third encoding completion signal to the first processor 121. The first processor 121 may recognize a state in which map data may be loaded into the third map loading area 500_3.

[0133] When the second processor 122 performs encoding of the mapping data using the first encoding region 600_1 and the second encoding region 600_2, a delay in the overall operation caused by the time required for encoding may be prevented or reduced.

[0134] In addition, since the second processor 122 variably sets the additional coding area 610 according to the use status of the first coding area 600_1 and the second coding area 600_2, a delay caused by the encoding operation in providing the plurality of mapped data elements to the host device 200 can be minimized.

[0135] In a state where the additional coding area 610 is set, the second processor 122 may perform encoding of the mapping data using the basically set coding areas 600_1 and 600_2 or the additional coding area 610 according to whether the transmission of the coded data is completed.

[0136] Reference Fig. 9 An example is shown in Figure 8 The illustrated example shows a case where a load operation of new mapping data is performed in a state where the additional coding area 610 is set.

[0137] The first processor 121 may output a fourth read buffer prompt signal and load the fourth mapping data MD4 of the fourth storage area SA4 into the buffer memory 123. When the first processor 121 recognizes that encoding of the first mapping data MD1 is completed, the first processor 121 may load the fourth mapping data MD4 into the first mapping loading area 500_1.

[0138] The second processor 122 may transmit a fourth read buffer recommendation signal to the host device 200 , and the host device 200 may transmit a fourth read buffer command to the second processor 122 .

[0139] The second processor 122 may transmit the fourth map load request signal to the first processor 121 , and may start encoding the fourth map data MD4 in response to the fourth map load completion signal.

[0140] The second processor 122 may check the use status of the first encoding area 600_1, the second encoding area 600_2, and the additional encoding area 610. When the encoded data of the first encoding area 600_1 is completely transmitted to the host device 200, the second processor 122 may store the fourth encoded data ED4 obtained by encoding the fourth mapping data MD4 in the first encoding area 600_1.

[0141] Optionally, as in the above reference Figure 8 As in the described example, when the existing coding areas 600_1 and 600_2 and the additional coding area 610 are being used, the second processor 122 may additionally set a separate additional coding area 610 and may store the fourth encoded data ED4 obtained by encoding the fourth mapping data MD4 in the set additional coding area 610 .

[0142] As described above, according to an embodiment of the disclosed technology, the loading operation of the mapping data can be started before receiving a read buffer command or a mapping load request signal, and multiple mapping load areas and multiple encoding areas can be used to perform loading and encoding of the mapping data. Therefore, the delay of the operation of providing the mapping data to the host device 200 can be reduced.

[0143] Furthermore, since loading and encoding of a plurality of map data elements may be performed, a loading operation or an encoding operation of the map data may be performed continuously.

[0144] Fig.10 is a diagram illustrating an example of a method in which the storage device 100 loads and encodes mapping data based on an embodiment of the disclosed technology.

[0145] Reference Fig.10 , the controller 120 of the storage device 100 may transmit a read buffer recommendation signal to the host device 200 according to the read count of the storage area SA of the memory 110 .

[0146] When the read buffer recommendation signal is transmitted, the controller 120 may start an operation of loading corresponding map data into the buffer memory 123 regardless of whether a read buffer command is received. As in the above example, the loading operation of map data may be started before the read buffer hint signal is output.

[0147] Before receiving a read buffer command corresponding to the read buffer recommendation signal, the controller 120 may perform a load operation on the mapping data according to the generation of the read buffer hint signal.

[0148] For example, the controller 120 may transmit a read buffer recommendation signal (e.g., ①, ②, and ③), and may perform a load operation (e.g., ①, ②, and ③) on the mapping data. The load operation may be performed on multiple mapping data elements, and the load operation on at least two mapping data elements may be performed continuously.

[0149] The controller 120 may receive a read buffer command corresponding to the read buffer recommendation signal from the host device 200 .

[0150] The controller 120 may perform an operation of encoding the map data in response to the read buffer command.

[0151] Since the loading operation of the map data is started before the read buffer command is received, there may be a time interval (eg, t3) between a time point when the loading operation of the map data is completed and a time point when encoding of the corresponding map data is started.

[0152] Since the load operation on the mapping data is performed by the first processor 121 of the controller 120, the load operation on the mapping data may be performed each time the read buffer hint signal is generated. Therefore, the load operation on a plurality of mapping data elements may be performed continuously.

[0153] Since the encoding operation on the map data is performed by the second processor 122 of the controller 120, the encoding operation on the map data corresponding to the received read buffer command may be continuously performed.

[0154] Since at least a portion of the loading operation of the mapping data is completed before the read buffer command is received, the time point of starting the encoding operation on the mapping data can be advanced. In addition, since the encoding operation on multiple mapping data elements can be continuously performed by using multiple encoding areas 600 before the host device 200 obtains the encoded data, the delay of the total operation time caused by the encoding operation can be prevented or reduced.

[0155] Since the map data can be efficiently provided while reducing the delay of the time required for the operation of the memory device 100 to provide the map data to the host device 200, the performance of the read operation according to the read command of the host device 200 can be improved.

[0156] Although various embodiments of the disclosed technology have been described with specific details and different details for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions may be made based on the contents disclosed or described in the disclosed technology without departing from the idea and scope of the disclosed technology defined in the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A storage device, comprising: A memory, including a plurality of storage areas; as well as A controller transmits a read buffer recommendation signal to a host device based on a read count of data stored in each of the plurality of storage areas, and starts a load operation of storing mapping data associated with the read buffer recommendation signal in a buffer memory before receiving a read buffer command corresponding to the read buffer recommendation signal from the host device.

2. The storage device according to claim 1, wherein: The controller transmits a first read buffer recommendation signal and a second read buffer recommendation signal to the host device, and stores first map data associated with the first read buffer recommendation signal and second map data associated with the second read buffer recommendation signal in a map loading area of ​​the buffer memory.

3. The storage device according to claim 2, wherein: In a state where the first map data is stored in the map load area of ​​the buffer memory, the second map data is stored in the map load area.

4. The storage device according to claim 2, wherein: In response to a first read buffer command corresponding to the first read buffer recommendation signal from the host device, the controller encodes the first mapping data and stores the encoded first mapping data in a first encoding area of ​​the buffer memory.

5. The storage device according to claim 4, wherein: There is a time interval between a time point at which the first map data is stored in the map load area of ​​the buffer memory and a time point at which the first map data is encoded.

6. The storage device according to claim 4, wherein: In response to a second read buffer command corresponding to the second read buffer recommendation signal from the host device, the controller encodes the second mapping data and stores the encoded second mapping data in a second encoding area of ​​the buffer memory.

7. The storage device according to claim 6, wherein: The controller transmits a third read buffer recommendation signal to the host device, and stores third map data associated with the third read buffer recommendation signal in a map loading area of ​​the buffer memory.

8. The storage device according to claim 7, wherein: After transmitting at least one of the first mapping data and the second mapping data to the host device, in response to a third read buffer command corresponding to the third read buffer recommendation signal from the host device, the controller encodes the third mapping data and stores the encoded third mapping data in the first encoding area or the second encoding area.

9. The storage device according to claim 7, wherein: Before transmitting at least one of the first mapping data and the second mapping data to the host device, in response to a third read buffer command corresponding to the third read buffer recommendation signal from the host device, the controller encodes the third mapping data and stores the encoded third mapping data in an additional encoding area of ​​the buffer memory.

10. The storage device according to claim 1, wherein: The controller comprises: a first processor, outputting a read buffer prompt signal when a read count of data stored in each of the plurality of storage areas is greater than or equal to a preset value; and The second processor transmits the read buffer recommendation signal to the host device in response to the read buffer prompt signal.

11. The storage device according to claim 10, wherein: The first processor starts the load operation before outputting the read buffer hint signal.

12. The storage device according to claim 10, wherein: The second processor transmits a map load request signal to the first processor in response to a read buffer command corresponding to the read buffer recommendation signal from the host device.

13. The storage device according to claim 12, wherein: The load operation is completed before the first processor receives the map load request signal.

14. The storage device according to claim 12, wherein: The second processor starts an operation of encoding the map data in response to a map load completion signal corresponding to the map load request signal from the first processor.

15. The storage device according to claim 1, wherein: The buffer memory includes n map load areas storing the map data and M encoding areas storing encoded data obtained by encoding the map data, and n and M are integers satisfying a relationship of n≥M≥2.

16. A controller comprising: Buffer memory; a first processor that outputs a read buffer prompt signal when a read count is greater than or equal to a preset value, and starts a load operation of storing mapping data associated with the read buffer prompt signal in the buffer memory, the read count being for data stored in each of a plurality of storage areas included in the external memory; as well as The second processor transmits a read buffer recommendation signal to a host device in response to the read buffer hint signal, wherein the read buffer recommendation signal is transmitted after the loading operation starts.

17. The controller according to claim 16, wherein: The load operation is started before the read buffer hint signal is output.

18. The controller according to claim 16, wherein: The second processor transmits a map load request signal to the first processor in response to a read buffer command corresponding to the read buffer recommendation signal from the host device, and completes the load operation before transmitting the map load request signal to the first processor.

19. A controller comprising: Buffer memory; a first processor that outputs a read buffer prompt signal when a read count is greater than or equal to a preset value, and stores mapping data associated with the read buffer prompt signal in a mapping load area of ​​the buffer memory, the read count being for data stored in each of a plurality of storage areas included in the external memory; as well as a second processor, in response to the read buffer prompt signal, transmitting a read buffer recommendation signal to a host device, The second processor transmits a first read buffer recommendation signal and a second read buffer recommendation signal to the host device, encodes first mapping data stored in a first mapping loading area of ​​the buffer memory and stores the encoded first mapping data in a first encoding area of ​​the buffer memory in response to a first read buffer command corresponding to the first read buffer recommendation signal, and encodes second mapping data stored in a second mapping loading area of ​​the buffer memory and stores the encoded second mapping data in a second encoding area of ​​the buffer memory in response to a second read buffer command corresponding to the second read buffer recommendation signal.

20. The controller according to claim 19, wherein: A time point at which the first mapping data is encoded and a time point at which the second mapping data is encoded are continuous.

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