Read-write request scheduling method and device, computer equipment and storage medium

Abstract

The invention relates to the technical field of computers, and discloses a read-write request scheduling method and device, computer equipment and a storage medium, and the method comprises the following steps: simulating to generate a cache mapping table of the storage equipment; judging whether a target table item corresponding to the to-be-scheduled read-write request exists in a cache mapping table or not; if yes, the read-write request to be scheduled is distributed to a first preset queue, and if not, the read-write type of the read-write request to be scheduled is obtained, and the read-write request to be scheduled is distributed to a second preset queue corresponding to the read-write type. The problem that in the read-write request scheduling process, queuing waiting time of other read-write requests is increased, and the overall performance of a storage system is affected is solved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a read / write request scheduling method, device, computer equipment and storage medium. Background Art

[0002] With the performance improvement of NVMe (non-volatile memory Express) SSD (Solid State Disk) devices, NVMe multi-queue I / O (Input / Output) software stack has gradually become the standard for fast storage devices. The current NVMe multi-queue I / O software stack adopts a streamlined software stack design, bypassing the complex sorting and waiting operations in the traditional software stack, and directly provides services in the order of request arrival, thereby reducing the performance overhead of the software stack.

[0003] In the NVMe multi-queue I / O software stack architecture, most of the current host-side I / O scheduling strategies only perform related scheduling based on the basic feature patterns of I / O requests (read and write requests), such as read and write features, sequential random features, etc., ignoring the underlying NVMeSSD device component status. In the processing of I / O requests, CMT (Cached Mapping Table) may be missing during NVMe SSD device processing, making it time-consuming to process the I / O request, increasing the queue waiting time of other I / O requests, limiting the performance of high-performance storage devices, and affecting the overall performance of the storage system. In particular, the current NVMe queue depth can reach 64K, so it is more difficult to avoid the problem of increased queue waiting time for I / O requests.

[0004] Therefore, the related art has the problem that the process of scheduling read and write requests will increase the queuing waiting time of other read and write requests, thereby affecting the overall performance of the storage system. Summary of the invention

[0005] In view of this, the present invention provides a read / write request scheduling method, apparatus, computer device and storage medium to solve the problem that the queuing waiting time of other read / write requests will increase during the scheduling of read / write requests, thereby affecting the overall performance of the storage system.

[0006] In a first aspect, the present invention provides a read / write request scheduling method, comprising:

[0007] Simulate and generate a cache mapping table of a storage device;

[0008] Determine whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table;

[0009] If it exists, the read / write request to be scheduled is distributed to the first preset queue; if it does not exist, the read / write type of the read / write request to be scheduled is obtained, and the read / write request to be scheduled is distributed to the second preset queue corresponding to the read / write type.

[0010] The read / write request scheduling method provided in this embodiment simulates and generates a cache mapping table for a storage device, and uses the cache mapping table to predict in advance whether the read / write request to be scheduled will hit the CMT on the device side. According to the prediction information of whether it hits or not and the read / write type of the read / write request to be scheduled, the read / write request to be scheduled is distributed to different queues, reducing the queuing delay of the CMT hit request, and combining the read / write queue separation strategy to perform weighted priority, thereby further alleviating the queuing waiting of I / O requests in the multi-queue software stack and improving the overall performance of the system. The problem that the queuing waiting time of other read / write requests will increase during the scheduling of read / write requests, affecting the overall performance of the storage system, is solved.

[0011] In some optional implementations, simulating and generating a cache mapping table of a storage device includes:

[0012] Use the preset simulator to simulate the storage device;

[0013] In the preset cache, a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request, and the mapping entries are inserted into an intermediate list in the preset cache to obtain a cache mapping table, wherein the number of mapping entries generated by the preset cache mapping algorithm is the same as the number of mapping entries of the preset simulator.

[0014] In this embodiment, a preset simulator is used to simulate a storage device, and a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request with the same number of mapping entries as the preset simulator, so as to reasonably simulate the CMT behavior on the device side in terms of cache algorithm and cache size. According to the generated cache mapping table, it is possible to accurately predict whether the scheduled read and write request will hit the CMT on the device side.

[0015] In some optional implementations, after simulating the storage device using a preset simulator, the method further includes:

[0016] Determine the data block corresponding to the storage device;

[0017] A preset binding strategy is adopted to bind the data block with the corresponding read-write queue and the central processing unit core, wherein the read-write queue includes a first preset queue and a second preset queue, and the read-write queue and the central processing unit core are used to process the read-write requests to be scheduled.

[0018] In some optional implementations, determining whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table includes:

[0019] Get the logical page number corresponding to the read and write request to be scheduled;

[0020] It is determined whether the cache mapping table contains the logical page number. If so, it is determined that the cache mapping table has a target table entry. If not, it is determined that the cache mapping table does not have a target table entry.

[0021] In this embodiment, by judging whether the cache mapping table contains the logical page number corresponding to the read / write request to be scheduled, it is determined whether the read / write request to be scheduled hits the CMT on the device side, which facilitates the subsequent writing of the read / write request to be scheduled into the corresponding queue. The method is simple and efficient.

[0022] In some optional implementations, if it exists, the read / write request to be scheduled is distributed to the first preset queue; if it does not exist, the read / write type of the read / write request to be scheduled is obtained, and the read / write request to be scheduled is distributed to the second preset queue corresponding to the read / write type, including:

[0023] Get the read / write type of the read / write request to be scheduled;

[0024] When the target entry exists in the cache mapping table, the request identifier, read / write type and logical page number of the read / write request to be scheduled are obtained;

[0025] Generate a first request item including a request identifier, a read / write type, and a logical page number;

[0026] Obtain the tail of the first queue of the first preset queue, and distribute the first request item to the tail of the first queue of the first preset queue;

[0027] When the target entry does not exist in the cache mapping table and the read / write type is a write request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0028] Generate a second request item including a request identifier, a read / write type, and a logical page number;

[0029] Determine an address translation page corresponding to the logical page number, and determine a target request item combination corresponding to the address translation page in a first sub-queue, wherein the first sub-queue is included in a second preset queue;

[0030] Distribute the second request item to the target request item combination of the first subqueue;

[0031] When the target entry does not exist in the cache mapping table and the read / write type is a read request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0032] Generate a third request item including a request identifier, a read / write type, and a logical page number;

[0033] A second queue tail of the second subqueue is obtained, and the third request item is distributed to the second queue tail of the second subqueue, wherein the second subqueue is included in the second preset queue.

[0034] In this embodiment, the read and write requests to be scheduled are distributed to different queues based on whether there is a target table entry in the cache mapping table, that is, whether the read and write requests to be scheduled hit the CMT on the device side and the read and write types of the read and write requests to be scheduled, and the read and write queue separation strategy is adopted to distribute the read requests and write requests to different queues, further alleviating the queuing waiting of I / O requests in the multi-queue software stack and improving the overall system performance.

[0035] In some optional implementations, determining an address translation page corresponding to a logical page number, and determining a target request item combination corresponding to the address translation page in a first subqueue includes:

[0036] Performing a preset operation on the logical page number to obtain an operation result, wherein the operation result is used to determine the address translation page corresponding to the logical page number;

[0037] Determine whether there is a request item combination corresponding to the operation result in the first sub-queue. If so, use the request item combination corresponding to the operation result as the target request item combination. If not, create a new request item combination in the first sub-queue as the target request item combination and save the new request item combination.

[0038] In this embodiment, a preset operation is performed on the logical page number to obtain an operation result, and a target request item combination corresponding to the write request is determined based on the operation result, so that write requests with the same address translation page are placed in the same combination, thereby increasing the sequentiality of the write requests and alleviating the garbage collection performance degradation caused by random write requests.

[0039] In some optional implementations, before simulating and generating a cache mapping table of a storage device, the method further includes:

[0040] Create a read and write request scheduling layer based on the Storage Performance Development Kit event framework;

[0041] A perception module is created in the read / write request scheduling layer, wherein the perception module is used to obtain a cache mapping table of a storage device.

[0042] In this embodiment, a read and write request scheduling layer is created based on the storage performance development toolkit event framework, and a perception module is created in the read and write request scheduling layer to obtain the cache mapping table of the storage device. According to the generated cache mapping table, it is possible to accurately predict whether the read and write requests to be scheduled will hit the CMT on the device side.

[0043] In a second aspect, the present invention provides a read / write request scheduling device, comprising:

[0044] A simulation generation module, used for simulating and generating a cache mapping table of a storage device;

[0045] A determination module, used to determine whether there is a target table entry corresponding to the read and write request to be scheduled in the cache mapping table;

[0046] The scheduling module is used to distribute the read / write requests to be scheduled to the first preset queue if it exists, and if it does not exist, obtain the read / write type of the read / write request to be scheduled, and distribute the read / write request to be scheduled to the second preset queue corresponding to the read / write type.

[0047] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the read and write request scheduling method of the first aspect or any corresponding embodiment thereof by executing the computer instructions.

[0048] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the read / write request scheduling method of the first aspect or any corresponding embodiment thereof.

[0049] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to enable a computer to execute the read and write request scheduling method of the above-mentioned first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0051] Figure 1 is a flow chart of a method for scheduling read and write requests according to an embodiment of the present invention;

[0052] Figure 2 is a schematic diagram of a multi-queue mapping aware I / O scheduling method according to an embodiment of the present invention;

[0053] Figure 3 is a schematic diagram of a multi-queue mapping-aware scheduling strategy according to an embodiment of the present invention;

[0054] Figure 4 is a comparison diagram of overall I / O latency optimization of real loads according to an embodiment of the present invention;

[0055] Figure 5is a structural block diagram of a read / write request scheduling device according to an embodiment of the present invention;

[0056] Figure 6 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] The I / O latency of a computer system includes software latency and hardware latency. As the performance gap between a computer's CPU and hardware storage devices narrows, the I / O software stack overhead in software latency accounts for a large proportion of I / O latency, and becomes a bottleneck for storage access to a greater extent. Currently, most I / O software stacks are designed for traditional low-speed rotating devices such as HDDs (Hard Disk Drives), such as SPDK (Storage Performance Development Kit). In order to give full play to the performance of underlying storage devices, user-mode design and streamlined I / O software stacks are adopted to eliminate performance bottlenecks such as interrupts and context switching of traditional kernel I / O software stacks. However, how to design reasonable I / O scheduling for the characteristics of NVMeSSD fast storage devices to give full play to the low-latency performance of underlying storage is still an urgent problem to be solved.

[0059] In the case of limited CMT capacity, that is, in a real storage device environment, since it is impossible to cache all mapping entries of NVMeSSD in the device's embedded SRAM, CMT may be missing after the I / O request reaches the underlying storage device, causing the device access delay of the request to increase rapidly, which in turn increases the queuing waiting time of other I / O requests, ultimately limiting the performance of high-performance storage devices and affecting the overall performance of the storage system. Therefore, in order to reduce the delay overhead caused by complex I / O scheduling strategies, the current multi-queue software stack directly processes requests in the order of arrival, without considering the status of the underlying device components, and without considering the resource contention and delay waiting of I / O requests in the underlying hardware devices. CMT may be missing in the processing of I / O requests by NVMeSSD devices, resulting in an increase in the queuing waiting delay of subsequent I / O requests, especially since the current NVMe queue depth can reach 64K, making it more difficult to avoid the problem of I / O request delay waiting.

[0060] Based on the above content, the embodiment of the present invention provides a method for scheduling read and write requests, which is based on the SPDK user-mode NVMe multi-queue software stack framework and combined with the SPDK lock-free thread processing mechanism. By simulating the perception of CMT information in the NVMe SSD device in the multi-queue software stack on the host side, it is possible to predict in advance whether the I / O request hits the CMT on the device side, and distribute the I / O request to different queues based on the predicted information of whether it hits or not. In order to reduce the queuing delay of CMT hit requests, and combine the read and write queue separation strategy to perform weighted priority scheduling, thereby further alleviating the queuing waiting of I / O requests in the multi-queue software stack and improving the overall performance of the system.

[0061] According to an embodiment of the present invention, a read and write request scheduling embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer device with data processing capabilities, such as a computer, a server, etc., and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0062] In this embodiment, a read / write request scheduling method is provided. Figure 1 is a flow chart of a method for scheduling read and write requests according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0063] Step S101, simulating and generating a cache mapping table of a storage device.

[0064] Specifically, this embodiment is based on the background of Flame high-performance block storage system, with the help of SPDK user-mode NVMe software stack and event framework, and designs ShadowPiece module in the host-side multi-queue software stack to simulate the perception of CMT information in NVMe SSD device, so as to predict in advance whether I / O request hits CMT on the device side, and distribute I / O request to Dispatch / Wait Queue module according to the prediction information of hit or not, and combine with read-write queue separation strategy to perform weighted priority scheduling, so as to alleviate the queuing waiting time of I / O request in multi-queue software stack and improve the overall performance of the system. Figure 2As shown, the multi-queue mapping perception I / O scheduling method mainly includes two modules in the I / O scheduling layer: Dipatch / WaitQueue module (scheduling / waiting queue module) and ShadowPiece module (simulation perception module), wherein the Dispatch / Wait Queue module predicts in advance whether the I / O request hits the CMT on the device side by utilizing the CMT cache information perceived on the host side, and distributes the I / O request to different queues based on the predicted information of whether it hits or not. If the predicted hit is achieved, the I / O request is sent to the DispatchQueue, otherwise it is sent to the WaitQueue. The ShadowPiece module is mainly based on the SPDK multi-queue core binding framework, and simulates the perception of the CMT information in the NVMe SSD device on the host side, that is, without destroying the high parallelism of the SPDK multi-queue I / O software stack, the accuracy of the simulation is still guaranteed.

[0065] Storage devices such as NVMe SSD devices use the ShadowPiece module to simulate and perceive the CMT (cache mapping table) information in the NVMe SSD device.

[0066] Step S102: determine whether there is a target entry corresponding to the read or write request to be scheduled in the cache mapping table.

[0067] Specifically, the Dipatch / WaitQueue module determines whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table, for example: whether there is a table entry containing the LPN (logical page number) of the read or write request to be scheduled in the cache mapping table, if so, the table entry is the target table entry. The table entry in the cache mapping table is the mapping entry from the logical page number (LPN) to the physical page number (PPN).

[0068] Step S103: if it exists, distribute the read / write request to be scheduled to the first preset queue; if it does not exist, obtain the read / write type of the read / write request to be scheduled, and distribute the read / write request to be scheduled to the second preset queue corresponding to the read / write type.

[0069] Specifically, if the Dispatch / Wait Queue module determines that there is a target table entry for the read and write requests to be scheduled, the read and write requests to be scheduled are distributed to the first preset queue, for example: DispatchQueue (dispatching queue); if it does not exist, the read and write type of the read and write requests to be scheduled is obtained, and the read and write requests to be scheduled are distributed to the second preset queue corresponding to the read and write type, for example: WaitQueue (waiting queue), and the waiting queue can be further divided into a read request waiting queue and a write request waiting queue according to the read and write type of the read and write request.

[0070] The read / write request scheduling method provided in this embodiment simulates and generates a cache mapping table for a storage device, and uses the cache mapping table to predict in advance whether the read / write request to be scheduled will hit the CMT on the device side. According to the prediction information of whether it hits or not and the read / write type of the read / write request to be scheduled, the read / write request to be scheduled is distributed to different queues, reducing the queuing delay of the CMT hit request, and combining the read / write queue separation strategy to perform weighted priority, thereby further alleviating the queuing waiting of I / O requests in the multi-queue software stack and improving the overall performance of the system. The problem that the queuing waiting time of other read / write requests will increase during the scheduling of read / write requests, affecting the overall performance of the storage system, is solved.

[0071] In some optional implementations, simulating and generating a cache mapping table of a storage device includes:

[0072] Use the preset simulator to simulate the storage device;

[0073] In the preset cache, a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request, and the mapping entries are inserted into an intermediate list in the preset cache to obtain a cache mapping table, wherein the number of mapping entries generated by the preset cache mapping algorithm is the same as the number of mapping entries of the preset simulator.

[0074] Specifically, the preset simulator is, for example, the MQSim simulator. The preset cache is, for example, the Shadow cache. First, a Shadow cache is designed on the host side to simulate and generate the cache mapping table (CMT information) of the storage device. The MQSim simulator is used on the device side to simulate the storage device, for example, the NVMe SSD. The default cache mapping algorithm in the MQSim simulator is DFTL. Therefore, the LRU algorithm is used as the preset cache mapping algorithm for the host-side Shadow cache to insert, replace, and manage the heat of the mapping entries. On the one hand, the LRU algorithm and the DFTL algorithm have similar locality principles, which enables them to better match the replacement strategy of the device-side CMT; on the other hand, the LRU algorithm is simple enough that the update operation of the Shadow cache will not affect the overall I / O latency of the system due to complex data statistics. In the NVMe SSD, the write request adopts an out-of-place update method, first writing the data to other free physical pages, and at the same time updating the corresponding logical page number (LPN) to physical page number (PPN) mapping entry in the device-side CMT. Although the write operation changes the PPN of its CMT mapping entry, the original LPN is not changed. Since the host-side layer only needs to determine whether the LPN of the request is in the mapping cache table, that is, to predict whether there will be a CMT miss wait after the I / O request reaches the device, it does not need to obtain the complete mapping of its logical page number to the physical page number. Therefore, in the host-side Shadow cache, all cache entries only need to record the LPN attribute information and manage a series of operations such as the insertion and replacement of LPN through the LRU algorithm.

[0075] A storage device is simulated using a preset simulator; in a preset cache, a mapping entry corresponding to each read and write request is generated using a preset cache mapping algorithm, and the mapping entry is inserted into an intermediate list in the preset cache to obtain a cache mapping table.

[0076] In the MQSim simulator, the device's CMT cache size is generally controlled by setting the number of mapping entries in the CMT. Therefore, only the same number of LPN entries need to be set in the host-side Shadow cache, thereby reasonably simulating the device-side CMT behavior in terms of cache algorithm and cache size. Therefore, the number of mapping entries generated by the preset cache mapping algorithm is the same as the number of mapping entries of the preset simulator.

[0077] In this embodiment, a preset simulator is used to simulate a storage device, and a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request with the same number of mapping entries as the preset simulator, so as to reasonably simulate the CMT behavior on the device side in terms of cache algorithm and cache size. According to the generated cache mapping table, it is possible to accurately predict whether the scheduled read and write request will hit the CMT on the device side.

[0078] In some optional implementations, after simulating the storage device using a preset simulator, the method further includes:

[0079] Determine the data block corresponding to the storage device;

[0080] A preset binding strategy is adopted to bind the data block with the corresponding read-write queue and the central processing unit core, wherein the read-write queue includes a first preset queue and a second preset queue, and the read-write queue and the central processing unit core are used to process the read-write requests to be scheduled.

[0081] Specifically, considering the switching and copying overhead of I / O requests between threads, a Chunk (data block) binding strategy is adopted, that is, all access requests to the Chunk are served by the I / O queue and CPU Core to which it is bound. Therefore, the LPNs of I / O requests served by different queues are independent of each other.

[0082] Determine the data block corresponding to the storage device, for example: Figure 2 Meta Chunk, Chunk1, ..., ChunkN in. Preset binding strategy, for example: Chunk binding strategy.

[0083] like Figure 2 As shown, each data block has a corresponding read-write queue and a CPU core, such as the read-write queues: Admin Queue, DispatchQueue, WaitQueue, etc. The CPU cores are such as Admin Core, I / OCore1, ..., I / OCoreN. A preset binding strategy is adopted to bind the data block with the corresponding read-write queue and the CPU core, wherein the read-write queue includes a first preset queue and a second preset queue, and the read-write queue and the CPU core are used to process the read-write requests to be scheduled.

[0084] In some optional implementations, determining whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table includes:

[0085] Get the logical page number corresponding to the read and write request to be scheduled;

[0086] It is determined whether the cache mapping table contains the logical page number. If so, it is determined that the cache mapping table has a target table entry. If not, it is determined that the cache mapping table does not have a target table entry.

[0087] Specifically, although the physical page number of the read / write request to be scheduled may be changed during the scheduling process, its logical page number will not be modified. For example, in NVMe SSD, for write requests, data is first written to other free physical pages, and the corresponding logical page number (LPN) to physical page number (PPN) mapping entry in the device-side CMT is updated at the same time. Although the write operation changes the PPN of its CMT mapping entry, the original LPN is not changed. Therefore, it is possible to determine whether the LPN of the read / write request to be scheduled is in the mapping cache table, that is, to predict whether the CMT missing wait will occur after the I / O request arrives at the device end, without the need to obtain the complete mapping of its logical page number to the physical page number.

[0088] Get the logical page number (LPN) corresponding to the read and write request to be scheduled, and determine whether the cache mapping table contains the logical page number. If it does, it is determined that the cache mapping table has a target entry, and the I / O request will not have a CMT miss wait after reaching the device. If it does not, it is determined that the cache mapping table does not have a target entry, and the I / O request will have a CMT miss wait after reaching the device.

[0089] In this embodiment, by judging whether the cache mapping table contains the logical page number corresponding to the read / write request to be scheduled, it is determined whether the read / write request to be scheduled hits the CMT on the device side, which facilitates the subsequent writing of the read / write request to be scheduled into the corresponding queue. The method is simple and efficient.

[0090] In some optional implementations, if it exists, the read / write request to be scheduled is distributed to the first preset queue; if it does not exist, the read / write type of the read / write request to be scheduled is obtained, and the read / write request to be scheduled is distributed to the second preset queue corresponding to the read / write type, including:

[0091] Get the read / write type of the read / write request to be scheduled;

[0092] When the target entry exists in the cache mapping table, the request identifier, read / write type and logical page number of the read / write request to be scheduled are obtained;

[0093] Generate a first request item including a request identifier, a read / write type, and a logical page number;

[0094] Obtain the tail of the first queue of the first preset queue, and distribute the first request item to the tail of the first queue of the first preset queue;

[0095] When the target entry does not exist in the cache mapping table and the read / write type is a write request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0096] Generate a second request item including a request identifier, a read / write type, and a logical page number;

[0097] Determine an address translation page corresponding to the logical page number, and determine a target request item combination corresponding to the address translation page in a first sub-queue, wherein the first sub-queue is included in a second preset queue;

[0098] Distribute the second request item to the target request item combination of the first subqueue;

[0099] When the target entry does not exist in the cache mapping table and the read / write type is a read request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0100] Generate a third request item including a request identifier, a read / write type, and a logical page number;

[0101] A second queue tail of the second subqueue is obtained, and the third request item is distributed to the second queue tail of the second subqueue, wherein the second subqueue is included in the second preset queue.

[0102] Specifically, the read / write type of the read / write request to be scheduled is obtained, and the read / write type is, for example, write (write request) and read (read request).

[0103] When the target table entry exists in the cache mapping table, the request identifier (request ID), read / write type, and logical page number (LPN) of the read / write request to be scheduled are obtained. For example, the request ID of the read / write request to be scheduled is 10, the read / write type is write, and the LPN is 124. A first request item including the request identifier, the read / write type, and the logical page number is generated. The first preset queue is, for example, DispatchQueue. The first request item is, for example: Figure 3 In the first row of the DispatchQueue, the request ID is 10, the read / write type is write, and the LPN is 124; the second row, the request ID is 9, the read / write type is read, and the LPN is 185. Each row is a first request item. Get the first queue tail of the first preset queue and distribute the first request item to the first queue tail of the first preset queue. For example, write the first request item to Figure 3 The first line in the DispatchQueue.

[0104] The first subqueue is, for example, Wait WQueue. When the target entry does not exist in the cache mapping table and the read / write type is a write request, obtain the request identifier, read / write type, and logical page number of the read / write request to be scheduled, for example, the request ID is 5, the read / write type is write, and the LPN is 280. Generate a second request item containing the request identifier, read / write type, and logical page number, for example: Figure 3The first row of the DispatchQueue has a request ID of 12, a read / write type of write, and an LPN of 930; the second row has a request ID of 5, a read / write type of write, and an LPN of 280. Each row is a second request item. Determine the address translation page corresponding to the logical page number, for example: logical page numbers with LPNs between 0 and 255 correspond to the same address translation page. Determine the target request item combination corresponding to the address translation page in the first sub-queue, for example: the target request item combination with request ID 5 is Group1, and the target request item combination with request ID 12 is Group2. Distribute the second request item to the target request item combination of the first sub-queue, for example: distribute the second request item "request ID is 12, read / write type is write, and LPN is 930" to Group2.

[0105] The second subqueue is for example: Wait RQueue. When the target entry does not exist in the cache mapping table and the read / write type is a read request, obtain the request identifier, read / write type, and logical page number of the read / write request to be scheduled, for example: the request ID is 11, the read / write type is read, and the LPN is 266. Generate a third request item containing the request identifier, read / write type, and logical page number, for example: Figure 3 In the first row of the DispatchQueue, the request ID is 11, the read / write type is read, and the LPN is 2; in the second row, the request ID is 7, the read / write type is read, and the LPN is 245. Each row is a third request item. Get the second queue tail of the second subqueue and distribute the third request item to the second queue tail of the second subqueue. For example, write the third request item to Figure 3 The first line in the WaitRQueue.

[0106] In this embodiment, the read and write requests to be scheduled are distributed to different queues based on whether there is a target table entry in the cache mapping table, that is, whether the read and write requests to be scheduled hit the CMT on the device side and the read and write types of the read and write requests to be scheduled, and the read and write queue separation strategy is adopted to distribute the read requests and write requests to different queues, further alleviating the queuing waiting of I / O requests in the multi-queue software stack and improving the overall system performance.

[0107] In some optional implementations, determining an address translation page corresponding to a logical page number, and determining a target request item combination corresponding to the address translation page in a first subqueue includes:

[0108] Performing a preset operation on the logical page number to obtain an operation result, wherein the operation result is used to determine the address translation page corresponding to the logical page number;

[0109] Determine whether there is a request item combination corresponding to the operation result in the first sub-queue. If so, use the request item combination corresponding to the operation result as the target request item combination. If not, create a new request item combination in the first sub-queue as the target request item combination and save the new request item combination.

[0110] Specifically, the preset operation is, for example, a hash operation, which puts I / O requests with logical page numbers (LPN) in the same address translation page into the same group (Group), such as write requests with LPNs in the range of 0 to 255 having the same address translation page.

[0111] Perform a preset operation on the LPN to be scheduled for the read / write request to obtain an operation result, such as a hash value. The operation result is used to determine the address translation page corresponding to the logical page number. For example, if the LPN is 280 and the operation result is 1, the address translation page of the read / write request is the address translation page corresponding to Group1.

[0112] The first subqueue, for example, Wait Wqueue, determines whether there is a request item combination corresponding to the operation result in the first subqueue. If so, the request item combination corresponding to the operation result is used as the target request item combination, for example: Figure 3 For a read / write request with request ID 5, if there is a request item combination Group1 corresponding to the operation result of request 5 in the first subqueue, the target request item combination of request 5 is Group1. If it does not exist, a new request item combination is created in the first subqueue as the target request item combination and the new request item combination is saved, for example: Figure 3 For the read / write request with request ID 12, there is no request item combination corresponding to the operation result of request 12 in the first subqueue, and Group2 is created as the target request item combination of request 12.

[0113] In this embodiment, a preset operation is performed on the logical page number to obtain an operation result, and a target request item combination corresponding to the write request is determined based on the operation result, so that write requests with the same address translation page are placed in the same combination, thereby increasing the sequentiality of the write requests and alleviating the garbage collection performance degradation caused by random write requests.

[0114] In some optional implementations, before simulating and generating a cache mapping table of a storage device, the method further includes:

[0115] Create a read and write request scheduling layer based on the Storage Performance Development Kit event framework;

[0116] A perception module is created in the read / write request scheduling layer, wherein the perception module is used to obtain a cache mapping table of a storage device.

[0117] Specifically, the storage performance development toolkit event framework, for example: user-mode NVMe software stack and event framework.

[0118] This embodiment is based on the background of Flame high-performance block storage system, and uses the SPDK user-mode NVMe software stack and event framework to create a read and write request scheduling layer (I / O scheduling layer) on the host side.

[0119] A perception module (ShadowPiece module) is created in the I / O scheduling layer to simulate the perception of CMT (cache mapping table) information in the NVMe SSD device, so as to predict in advance whether the I / O request hits the CMT on the device side. Based on the predicted information of whether it hits or not, the I / O request is distributed to the Dispatch / Wait Queue module, and combined with the read-write queue separation strategy, weighted priority scheduling is performed to alleviate the queuing waiting time of I / O requests in the multi-queue software stack and improve the overall system performance.

[0120] In this embodiment, a read and write request scheduling layer is created based on the storage performance development toolkit event framework, and a perception module is created in the read and write request scheduling layer to obtain the cache mapping table of the storage device. According to the generated cache mapping table, it is possible to accurately predict whether the read and write requests to be scheduled will hit the CMT on the device side.

[0121] It should be noted that this application tests the performance of the multi-queue mapping-aware I / O scheduling scheme under different loads. The host side is based on the Flame storage system framework, and the device side uses MQSim to simulate the NVMe SSD. In order to avoid the impact of data cache in the SSD on the scheme test, the data cache is set to closed. In the test, four real trace loads (Financial1, Financial2, TPCC, Websearch) were used to test the performance of the multi-queue mapping-aware I / O scheduling scheme (abbreviated as Shadow). The None scheduling strategy (abbreviated as None) widely used in the current NVMe multi-queue I / O software stack and the Read / WriteQueue separation strategy (abbreviated as R / W) are used as comparison schemes. In the None scheduling strategy, all I / O requests are first-in-first-out in the order of request arrival, and there is no sorting and merging operation. The Read / WriteQueue separation strategy is a queue strategy commonly used in the current NVMe multi-queue I / O software stack to reduce system I / O latency. As Figure 4As shown in the figure, the overall I / O latency comparison of four loads under three multi-queue scheduling strategies is tested respectively. Since the Shadow scheduling strategy can reduce the waiting time of I / O request queues, reduce the request queue depth, and alleviate the interference of write requests on read requests, the I / O latency performance improvement effect is more excellent in workloads with I / O request bursts and workloads with a high proportion of read requests, such as F2 and Websearch. Compared with the None strategy, the Shadow scheduling strategy improves the overall I / O latency performance of F1, F2, TPCC and Websearch by 11%, 18%, 13% and 23% respectively.

[0122] In some optional implementations, before using CMT (cache mapping table) information to determine whether the CMT on the device side is hit, the read-write queue separation strategy can be applied to the CMT information, and the CMT information can be divided into three parts: W-CMT, R-CMT, and GTD: W-CMT is used to store high-access frequency write request mapping information; R-CMT is used to store high-access frequency read request mapping information, and GTD is used to record address mapping items in the mapping block. At this time, the specific process of scheduling the read and write requests to be scheduled may include steps 1 to 12.

[0123] Step 1, determine whether the read and write requests to be scheduled hit the W-CMT. If the read and write requests to be scheduled hit the W-CMT, execute step 2; otherwise, execute step 4.

[0124] Step 2: Migrate the mapping information to the MRU (most recently used) position of the W-CMT.

[0125] Step 3, determine the request type: if the request type is a write request, execute step 15.

[0126] Step 4, determine whether the read and write requests to be scheduled hit the R-CMT: If the read and write requests to be scheduled hit the R-CMT, execute step 5; otherwise, execute step 8.

[0127] Step 5, determine the request type: if the request type is a write request, execute step 6; otherwise, execute step 7.

[0128] Step 6, determine whether the W-CMT is idle, if not, perform the W-CMT removal operation; then migrate the mapping information from the R-CMT to the MRU position of the W-CMT.

[0129] Step 7: Migrate the mapping information to the MRU position of the R-CMT.

[0130] Step 8, determine the request type: if the request type is a write request, execute step 9; otherwise, execute step 11.

[0131] Step 9, determine whether the free size of W-CMT is larger than the size of the read and write requests to be scheduled. If it is smaller, perform the W-CMT elimination operation until W-CMT can accommodate the mapping information of the requested size, and then execute step 10; otherwise, directly execute step 10.

[0132] Step 10: Load the requested size mapping information into the MRU position of W-CMT through GTD.

[0133] Step 11: Obtain the read / write type of the read / write request to be scheduled, and distribute the read / write request to be scheduled to a second preset queue corresponding to the read / write type.

[0134] Step 12: Distribute the read and write requests to be scheduled to the tail of the read request subqueue or the write request subqueue in the first preset queue according to the mapping information of the MRU position.

[0135] In this embodiment, the mapping cache area is partitioned into read and write partitions, and different mapping cache partitions are selected according to different characteristics of different requests, thereby fully utilizing the temporal and spatial locality of the load.

[0136] In the present embodiment, a read / write request scheduling device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the device described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceived.

[0137] This embodiment provides a read / write request scheduling device, such as Figure 5 As shown, including:

[0138] A simulation generation module 501, used for simulating and generating a cache mapping table of a storage device;

[0139] A determination module 502 is used to determine whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table;

[0140] The scheduling module 503 is used to distribute the read / write request to be scheduled to the first preset queue if it exists, and if not, obtain the read / write type of the read / write request to be scheduled and distribute the read / write request to be scheduled to the second preset queue corresponding to the read / write type.

[0141] In some optional implementations, the simulation generation module 501 simulates and generates a cache mapping table of a storage device, including:

[0142] Use the preset simulator to simulate the storage device;

[0143] In the preset cache, a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request, and the mapping entries are inserted into an intermediate list in the preset cache to obtain a cache mapping table, wherein the number of mapping entries generated by the preset cache mapping algorithm is the same as the number of mapping entries of the preset simulator.

[0144] In some optional implementations, after simulating the storage device using a preset simulator, the apparatus is used to:

[0145] Determine the data block corresponding to the storage device;

[0146] A preset binding strategy is adopted to bind the data block with the corresponding read-write queue and the central processing unit core, wherein the read-write queue includes a first preset queue and a second preset queue, and the read-write queue and the central processing unit core are used to process the read-write requests to be scheduled.

[0147] In some optional implementations, the determination module 502 determines whether there is a target entry corresponding to the read or write request to be scheduled in the cache mapping table, including:

[0148] Get the logical page number corresponding to the read and write request to be scheduled;

[0149] It is determined whether the cache mapping table contains the logical page number. If so, it is determined that the cache mapping table has a target table entry. If not, it is determined that the cache mapping table does not have a target table entry.

[0150] In some optional implementations, if the scheduling module 503 exists, the scheduling read / write request is distributed to the first preset queue; if it does not exist, the scheduling read / write type of the scheduling read / write request is obtained, and the scheduling read / write request is distributed to the second preset queue corresponding to the read / write type, including:

[0151] Get the read / write type of the read / write request to be scheduled;

[0152] When the target entry exists in the cache mapping table, the request identifier, read / write type and logical page number of the read / write request to be scheduled are obtained;

[0153] Generate a first request item including a request identifier, a read / write type, and a logical page number;

[0154] Obtain the tail of the first queue of the first preset queue, and distribute the first request item to the tail of the first queue of the first preset queue;

[0155] When the target entry does not exist in the cache mapping table and the read / write type is a write request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0156] Generate a second request item including a request identifier, a read / write type, and a logical page number;

[0157] Determine an address translation page corresponding to the logical page number, and determine a target request item combination corresponding to the address translation page in a first sub-queue, wherein the first sub-queue is included in a second preset queue;

[0158] Distribute the second request item to the target request item combination of the first subqueue;

[0159] When the target entry does not exist in the cache mapping table and the read / write type is a read request, obtaining a request identifier, a read / write type, and a logical page number of the read / write request to be scheduled;

[0160] Generate a third request item including a request identifier, a read / write type, and a logical page number;

[0161] A second queue tail of the second subqueue is obtained, and the third request item is distributed to the second queue tail of the second subqueue, wherein the second subqueue is included in the second preset queue.

[0162] In some optional implementations, the scheduling module 503 determines the address translation page corresponding to the logical page number, and determines the target request item combination corresponding to the address translation page in the first subqueue, including:

[0163] Performing a preset operation on the logical page number to obtain an operation result, wherein the operation result is used to determine the address translation page corresponding to the logical page number;

[0164] Determine whether there is a request item combination corresponding to the operation result in the first sub-queue. If so, use the request item combination corresponding to the operation result as the target request item combination. If not, create a new request item combination in the first sub-queue as the target request item combination and save the new request item combination.

[0165] In some optional implementations, before simulating and generating a cache mapping table of a storage device, the apparatus is further configured to:

[0166] Create a read and write request scheduling layer based on the Storage Performance Development Kit event framework;

[0167] A perception module is created in the read / write request scheduling layer, wherein the perception module is used to obtain a cache mapping table of a storage device.

[0168] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0169] The read and write request scheduling device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0170] The embodiment of the present invention also provides a computer device having the above Figure 5 The read and write request scheduling device is shown.

[0171] See also Figure 6 , Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0172] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include an integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0173] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0174] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0175] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0176] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0177] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0178] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0179] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined in this application.

Claims

1. A read and write request scheduling method, characterized in that: The method comprises: Simulate and generate a cache mapping table of a storage device; Determine whether there is a target table entry corresponding to the read or write request to be scheduled in the cache mapping table; If it exists, the read / write request to be scheduled is distributed to the first preset queue; if it does not exist, the read / write type of the read / write request to be scheduled is obtained, and the read / write request to be scheduled is distributed to the second preset queue corresponding to the read / write type.

2. The method according to claim 1, characterized in that The simulation generates a cache mapping table of a storage device, including: Simulating the storage device using a preset simulator; In the preset cache, a preset cache mapping algorithm is used to generate mapping entries corresponding to each read and write request, and the mapping entries are inserted into an intermediate list in the preset cache to obtain the cache mapping table, wherein the number of mapping entries generated by the preset cache mapping algorithm is the same as the number of mapping entries of the preset simulator.

3. The method according to claim 2, characterized in that After simulating the storage device using a preset simulator, the method further includes: Determining a data block corresponding to the storage device; A preset binding strategy is adopted to bind the data block with the corresponding read-write queue and the central processing unit core, wherein the read-write queue includes the first preset queue and the second preset queue, and the read-write queue and the central processing unit core are used to process the read-write request to be scheduled.

4. The method according to claim 1, characterized in that The step of determining whether the cache mapping table has a target table entry corresponding to the read / write request to be scheduled includes: Obtaining the logical page number corresponding to the read / write request to be scheduled; It is determined whether the cache mapping table contains the logical page number. If so, it is determined that the cache mapping table contains the target entry. If not, it is determined that the cache mapping table does not contain the target entry.

5. The method according to claim 1, characterized in that If the request exists, the read / write request to be scheduled is distributed to the first preset queue; if the request does not exist, the read / write type of the read / write request to be scheduled is obtained, and the read / write request to be scheduled is distributed to the second preset queue corresponding to the read / write type, including: Obtaining the read / write type of the read / write request to be scheduled; In the case where the target entry exists in the cache mapping table, obtaining the request identifier, the read / write type and the logical page number of the read / write request to be scheduled; Generate a first request item including the request identifier, the read / write type, and a logical page number; Obtain a first queue tail of the first preset queue, and distribute the first request item to the first queue tail of the first preset queue; When the target entry does not exist in the cache mapping table and the read / write type is a write request, obtaining a request identifier, the read / write type, and a logical page number of the read / write request to be scheduled; Generate a second request item including the request identifier, the read / write type, and a logical page number; Determine an address translation page corresponding to the logical page number, and determine a target request item combination corresponding to the address translation page in a first sub-queue, wherein the first sub-queue is included in the second preset queue; Distributing the second request item to the target request item combination of the first subqueue; When the target entry does not exist in the cache mapping table and the read / write type is a read request, obtaining a request identifier, the read / write type, and a logical page number of the read / write request to be scheduled; Generate a third request item including the request identifier, the read / write type, and a logical page number; Obtain a second queue tail of a second subqueue, and distribute the third request item to the second queue tail of the second subqueue, wherein the second subqueue is included in the second preset queue.

6. The method according to claim 5, characterized in that The determining the address translation page corresponding to the logical page number, and determining the target request item combination corresponding to the address translation page in the first subqueue, includes: Performing a preset operation on the logical page number to obtain an operation result, wherein the operation result is used to determine an address translation page corresponding to the logical page number; Determine whether there is a request item combination corresponding to the operation result in the first sub-queue. If so, use the request item combination corresponding to the operation result as the target request item combination. If not, create a new request item combination in the first sub-queue as the target request item combination and save the new request item combination.

7. The method according to claim 1, characterized in that Before the simulation generates a cache mapping table of the storage device, the method further includes: Create a read and write request scheduling layer based on the Storage Performance Development Kit event framework; A perception module is created in the read / write request scheduling layer, wherein the perception module is used to obtain the cache mapping table of the storage device.

8. A read / write request scheduling device, characterized in that: The device comprises: A simulation generation module, used for simulating and generating a cache mapping table of a storage device; A determination module, used to determine whether the cache mapping table has a target table entry corresponding to the read and write request to be scheduled; The scheduling module is used to distribute the read / write request to be scheduled to the first preset queue if it exists, and if it does not exist, obtain the read / write type of the read / write request to be scheduled, and distribute the read / write request to be scheduled to the second preset queue corresponding to the read / write type.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the read / write request scheduling method according to any one of claims 1 to 7 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the read-write request scheduling method according to any one of claims 1 to 7.

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