Controller with distributed sequencer assembly

Abstract

The invention relates to a controller with a distributed sequencer component. A host operation to be performed may be received. A sub-operation associated with the received host operation may be determined. A memory component of the plurality of memory components may be identified for each sub-operation. Further, each sub-operation may be transmitted to a media sequencer component associated with a respective one of the memory components.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application of the invention patent application with application date of September 13, 2019, application number 201980064131.7, and invention name “Controller with distributed sequencer component”. Technical Field

[0003] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to memory subsystems including a controller having a distributed sequencer component. Background Art

[0004] The memory subsystem may be a storage system, such as a solid-state drive (SSD), and may include one or more memory components that store data. The memory components may be, for example, non-volatile memory components and volatile memory components. In general, a host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the invention

[0005] In one aspect, the present disclosure provides a system comprising: a first memory device having a first media type; a second memory device having a second media type, the second media type being different from the first media type; and a processing device operably coupled to the first memory device and the second memory device to perform operations including: receiving a host operation to be performed at the system; determining a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a respective one of the first memory device or the second memory device; and based on the first media type and the second media type, allocating each of the plurality of sub-operations to a respective one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device.

[0006] On the other hand, the present disclosure provides a method, which includes: receiving a host operation to be performed at a memory subsystem; determining multiple sub-operations associated with the host operation, each sub-operation corresponding to a corresponding one of a first memory device having a first media type or a second memory device having a second media type, the second media type being different from the first media type; and based on the first media type and the second media type, assigning each of the multiple sub-operations to a corresponding one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device.

[0007] On the other hand, the present disclosure provides a non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations including: receiving a host operation to be performed at a memory subsystem; determining a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a respective one of a first memory device having a first media type or a second memory device having a second media type, the second media type being different from the first media type; and based on the first media type and the second media type, allocating each of the plurality of sub-operations to a respective one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description provided below and the accompanying drawings of various embodiments of the present disclosure.

[0009] Figure 1 An example computing environment including a memory subsystem according to some embodiments of the present disclosure is described.

[0010] Figure 2 An example controller with distributed components according to some embodiments of the present disclosure is described.

[0011] Figure 3 is a flow chart of an example method of transmitting subcommands to a distributed media sequencer component of a controller according to some embodiments.

[0012] Figure 4 An example controller with distributed components for use with different types of media is described in accordance with some embodiments of the present disclosure.

[0013] Figure 5AAn error correction scheme by a controller having distributed components according to some embodiments is described.

[0014] Figure 5B Another error correction scheme by a controller having distributed components according to some embodiments is described.

[0015] Figure 6 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0016] Aspects of the present disclosure are directed to a memory subsystem comprising a controller having a distributed sequencer component. The memory subsystem is also referred to as a "memory component" hereinafter. An example of a memory subsystem is a storage system, such as a solid-state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. Typically, a host system can utilize a memory subsystem comprising one or more memory components. The host system can provide data to be stored at the memory subsystem, and can request to retrieve data from the memory subsystem.

[0017] The memory subsystem may include a controller that performs various operations at specific memory components of the memory subsystem. For example, the controller may perform a read operation, a write operation, or an erase operation at one or more of the memory components. The controller may include multiple channels for controlling different groups of memory components. Each channel may correspond to a portion of the controller and an interface component for communicating with a corresponding group of memory components and performing operations at the corresponding group. For example, a first channel may be used to perform an operation at a first group of memory components and a second channel may be used to perform an operation at a second group of memory components. Thus, different channels of the controller may access different groups of memory components of the memory subsystem.

[0018] In a conventional memory subsystem, a controller may include a centralized scheduler and sequencer component to facilitate the execution of operations at different groups of memory components through different channels. The centralized scheduler and sequencer component may receive operations to be performed at the memory subsystem and may further receive data corresponding to the operations when the operations correspond to write operations. For example, the centralized scheduler and sequencer component may separate the operations into sub-operations to be performed at different groups of memory components through different channels. Thus, the centralized scheduler and sequencer component may determine sub-operations for various memory components at the controller's channels when the memory subsystem receives the operations.

[0019] The centralized scheduler and sequencer components of a conventional memory subsystem may determine sub-operations for a single type of operation at a particular time. For example, a single operation to be performed by the memory subsystem may be received, and corresponding sub-operations may be determined for each respective memory component from which data is to be read or erased or to which data is to be written. After the sub-operations have been determined, the centralized scheduler and sequencer components may determine page operations for a particular memory component. The respective memory components may be organized into hierarchies, wherein a particular memory component from a controller may be included in a single hierarchy. The controller may use the centralized scheduler and sequencer components to operate on memory components in the same hierarchy in a synchronized manner. For example, the controller may use the resulting page operations of the sub-operations from the centralized scheduler and sequencer components to perform a particular type of operation (e.g., a read operation, a write operation, or an erase operation) at a memory component in a hierarchy at a particular time, and may not simultaneously perform another type of operation at other memory components in another hierarchy.

[0020] Aspects of the present disclosure address the above and other deficiencies by utilizing a controller having a distributed sequencer component. For example, a controller may include a command manager component to generate sub-operations, and may include a distributed media sequencer component to determine page operations for different channels of the controller, in contrast to a single centralized scheduler and sequencer component that generates sub-operations and page operations for all channels of the controller. For example, the distributed media sequencer component may determine a specific page operation to be performed at a corresponding memory component at each channel based on the sub-operations provided to the distributed media sequencer component. In some embodiments, a command manager may receive an operation to be performed at a memory subsystem and may derive multiple sub-operations for different memory components. As an example, the received operation may be to write 6 kilobytes (kb) of data to a memory component, and the sub-operations may correspond to three write operations of 2kb of data at different memory components.

[0021] Each of the sub-operations may then be forwarded to a corresponding media sequencer component of a channel containing a respective memory component corresponding to the sub-operation. The media sequencer component may then determine a page operation based on the received sub-operation. The media component operation may specify a page operation or location of a physical block of a memory component, or may determine additional commands to be executed at the memory component to store, retrieve, or erase data for the sub-operation.

[0022] Advantages of the present disclosure include, but are not limited to, operation of memory components in different channels in an asynchronous manner. For example, a first type of operation (e.g., a read operation) may be performed at a memory component of a first channel while a second type of operation (e.g., a write operation) may be performed at a memory component of a second channel. Thus, the performance of a memory subsystem may be improved because a write operation may be performed at a particular memory component while a read operation is performed at other memory components. Thus, a write operation is not stopped or paused until a read operation is completed, resulting in the execution of more operations of the memory subsystem in a particular time period.

[0023] Additional advantages include increased throughput of the memory subsystem. For example, because each channel can include a separate media sequencer component, different media sequencer components can support smaller granularity of data to store or retrieve data in parallel at the memory components of the memory subsystem. In addition, because each media sequencer component receives a separate queue of sub-operations, each media sequencer component can optimize the execution of sub-operations based on the workload of the corresponding media sequencer component. Therefore, each media sequencer component can achieve improved execution of sub-operations, resulting in improved performance of the memory subsystem.

[0024] Figure 1 An example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure is described. The memory subsystem 110 may include media, such as memory components 112A to 112N. The memory components 112A to 112N may be volatile memory components, non-volatile memory components, or a combination of such components. In some embodiments, the memory subsystem is a storage system. An example of a storage system is an SSD. In some embodiments, the memory subsystem 110 is a hybrid memory / storage device subsystem. In general, the computing environment 100 may include a host system 120 that uses the memory subsystem 110. For example, the host system 120 may write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0025] The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such computing devices that include a memory and a processing device. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from the memory subsystem 110 or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. As used herein, "coupled to" or "coupled with..." generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc. Examples of physical host interfaces include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a fiber channel, a serial attached SCSI (SAS), etc. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a PCIe interface, the host system 120 may further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0026] The memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include negative-and (NAND) type flash memory. Each of the memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC) or four-level cells (QLC)). In some embodiments, a particular memory component may include both an SLC portion and an MLC portion of a memory cell. Each of the memory cells may store one or more data bits (e.g., data blocks) used by the host system 120. Although non-volatile memory components such as NAND type flash memory are described, the memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetic random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. The cross-point array of non-volatile memory may be combined with a stackable cross-grid data access array to store bits based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform write-in-place operations, where non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. Furthermore, the memory cells of the memory components 112A through 112N may be grouped into memory pages or data blocks, which may refer to cells of the memory component used to store data.

[0027] The memory subsystem controller 115 (hereinafter referred to as the "controller") can communicate with the memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at the memory components 112A to 112N, and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the example shown, the local memory 119 of the controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110 (including handling communications between the memory subsystem 110 and the host system 120). In some embodiments, the local memory 119 may include memory registers that store memory pointers, extracted data, etc. Local memory 119 may also include a read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 may not include the controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0028] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses and physical block addresses associated with the memory components 112A to 112N. The controller 115 may additionally include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory components 112A to 112N, and convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0029] The memory subsystem 110 may also include additional circuits or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that may receive addresses from the controller 115 and decode the addresses to access the memory components 112A-112N.

[0030] The memory subsystem 110 includes a distributed component 113 that can be used to receive operations and generate sub-operations associated with the memory components 112A to 112N. In some embodiments, the controller 115 includes at least a portion of the distributed component 113. For example, the controller 115 may include a processor 117 (processing device) that is configured to execute instructions stored in the local memory 119 for performing the operations described herein. In some embodiments, some or all of the functionality of the distributed component 113 is part of the host system 120, the application, or the operating system. For example, any combination of a command manager and a media sequencer may be executed by the host system 120, the application, or the operating system.

[0031] Distributed components 113 may receive operations to be performed at memory subsystem 110. Distributed components 113 may determine sub-operations and page operations for different channels corresponding to the received operations. For example, distributed components 113 may include a media sequencer and error correction components for each channel of controller 115. Additional details regarding the operation of distributed components 113 are described below.

[0032] Figure 2 An example controller 200 with distributed components according to some embodiments of the present disclosure is illustrated. The controller 200 corresponds to Figure 1 Controller 115.

[0033] like Figure 2As shown, the controller 200 may include a distributed component 113 and various memory components. The distributed component 113 may receive an indication of an operation 201 to be performed. In some embodiments, the distributed component 113 may receive data 202 when the operation 201 is a write operation. The data 202 may be stored at a buffer 211. In some embodiments, the buffer 211 may be a volatile memory of the controller 200. The command manager 210 may receive the operation 201 and may determine sub-operations that may be performed at various memory components to implement the operation 201. For example, the operation 201 may correspond to a write operation to program six kilobytes of data at a memory subsystem including the controller 200. The command manager 210 may then determine a first sub-operation to program two kilobytes of the six kilobytes at a first memory component, a second sub-operation to program two kilobytes of the six kilobytes at a second memory component, and a third sub-operation to program the last two kilobytes of the six kilobytes at a third memory component. The first, second, and third sub-operations may then be transmitted from the command manager 210 to the media sequencer in a channel containing the corresponding first, second, or third memory component. Thus, the sub-operations may identify a specific memory component on which an operation (eg, a read operation or a write operation) is to be performed.

[0034] Each channel of the controller 200 may include a media sequencer (or media sequencer component) and an error correction component for the memory components of the channel. For example, as shown, the first channel may include a media sequencer 220A and an error correction component 225A to be used with memory components 230A and 231A. The second channel may include a media sequencer 220B and an error correction component 225B to be used with memory components 230B and 231B, and the third channel may include a media sequencer 220C and an error correction component 225C to be used with memory components 230C and 231C. The media sequencer for the channel may receive a sub-operation specifying a memory component to be used with the channel or controlled by the channel. The media sequencer may determine a page operation that may be used to perform the sub-operation. The page operation may specify the physical location of the specified memory component to be used to implement the sub-operation. In some embodiments, the page operation may specify a page of the corresponding memory component, wherein a page may be the smallest unit of the memory component that can be addressed (e.g., read from or written to). Thus, command manager 210 may divide operation 201 into sub-operations for memory components between multiple channels, and the media sequencer of the channel may then further divide the sub-operations into page operations for each of the memory components. Thus, operation 201 may specify data of a first size, the sub-operations may each specify data of a second size that is smaller than the first size (e.g., a portion of the first size of data), and the page operation may specify data of a third size that is smaller than the second size. Thus, operation 201, the sub-operations, and the page operation may specify different amounts or granularities of data.

[0035] As shown, each channel may also include an error correction component (e.g., error correction component 225A, 225B, or 225C) for use with data written to or read from the memory components of the corresponding channel. The error correction component may perform an error correction code (ECC) operation or any other type of error detection and correction operation for data stored at the memory components. In some embodiments, the error correction code operation may result in data being stored at the memory component that is encoded by adding additional information (e.g., an ECC payload) to the data. The error correction component may apply any error detection and correction operation to the data stored at the memory component and the data retrieved from the memory component. Thus, data stored at memory components of different channels may be used in error correction operations by different error correction components.

[0036] The distributed components 113 may also include redundant subcomponents 212 that may perform redundant operations, such as redundant array of independent disks (RAID) operations that may be applied to different memory components on different channels. Figure 5A and 5B Additional details regarding error control operations and redundancy operations are described in conjunction.

[0037] Figure 3 is a flow chart of an example method 300 of transmitting a subcommand to a distributed sequencer component of a controller according to some embodiments. The method 300 may be performed by processing logic that may include hardware (e.g., a processing device, a circuit, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by Figure 1 The distributed components 113 of the embodiment of the present invention are executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in different orders, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in each embodiment. Other process flows are also possible.

[0038] At block 310, processing logic receives an operation to be performed at a memory subsystem. The operation may correspond to a write operation, a read operation, or an erase operation associated with data at the memory subsystem. The received operation may be referred to as a host operation. In some embodiments, a host operation is a command or instruction received from a host system utilizing the memory subsystem. At block 320, processing logic determines a sub-operation for the received operation. The sub-operation may be based on a memory component of the memory subsystem. A sub-operation may be determined for each memory component of the memory subsystem associated with the data of the operation. For example, the command manager may divide the operation between multiple memory components and may determine each sub-operation for each memory component. For example, the operation may be to read 15 kilobytes of data and the command manager may determine that five kilobytes of data are stored at a first memory component, another five kilobytes of data are stored at a second memory component, and the last five kilobytes of data are stored at a third memory component. Each of the memory components may be part of a different channel of a controller of the memory subsystem. In another example, the operation may be to write 15 kilobytes of data and the command manager may determine to divide the 15 kilobytes of data into 5 kilobyte groups, each of which is programmed or written to a different memory component of a different channel of the controller. At block 330, the processing logic identifies a specific memory component of the memory subsystem for each sub-operation. For example, each channel of the controller may include a separate media sequencer component. A first sub-operation for a first memory component may be identified to be provided to a first media sequencer component of the first channel, a second sub-operation for a second memory component may then be identified to be provided to a second media sequencer component of the second channel, and a third sub-operation for a third memory component may be identified to be provided to a third media sequencer component. At block 340, the processing logic transmits each sub-operation to a specific media sequencer component associated with each respective memory component to determine a page operation for the memory component. For example, the media sequencer component of the different channel receiving the sub-operation may determine a page operation for the received sub-operation. A page operation may specify a specific physical location of a memory component from which the data of the operation is to be retrieved, written to, or erased. Page operations may be used for memory components used by or controlled by a channel that includes a particular media sequencer component. Thus, different media sequencer components may be used to generate page operations for different groups of memory components in different channels and for the same received operation. A sub-operation may specify a portion of the data of a received operation and a page operation may specify portions of different sub-operations.

[0039] In some embodiments, each media sequencer component may apply a scheduling process to determine an order for determining page operations for receiving a queue of sub-operations. In some embodiments, the scheduling process may determine the order of sub-operations based on a media type or media state of a memory component coupled to the media sequencer component and a workload (e.g., sub-operations in a queue) of the media sequencer component. For example, a media sequencer component may schedule a particular type of sub-operation for determining a corresponding page operation earlier than another type of sub-operation based on one or more characteristics of a memory component coupled to the media sequencer component and / or other sub-operations that have not yet been processed by the media sequencer component.

[0040] Figure 4 An example controller having distributed components for use with different types of media according to some embodiments of the present disclosure is described. Figure 4 , controller 400 may include different channels 440A, 440B, and 440N for performing operations at memory components having different types of media. The memory components in channel 440A may be cross-point non-volatile memory, the memory components in channel 440B may be NAND non-volatile memory, and the memory components in channel 440N may be DRAM memory. Thus, different channels of controller 400 as well as different media sequencer components and different error correction components may be used to perform operations at different types of memory components. Although three channels are shown, any number of channels and memory components may be used.

[0041] In operation, the command manager 210 may receive operations and may transmit sub-operations to the media sequencers 220A, 220B, and 220N. The command manager 210 may transmit sub-operations to a specific media sequencer 220A, 220B, or 220N based on the media type of the memory component in the channel 440A, 440B, or 440N. For example, a certain media type may have different characteristics than another media type. For example, a first media type may have better reliability or shorter latency (e.g., less time to retrieve stored data) than another media type. The command manager 210 may transmit sub-operations to the media sequencer based on the characteristics or type of the media of the memory component in the channel containing the corresponding media sequencer. In some embodiments, the sub-operation may be transmitted to the media sequencer based on the characteristics of the media type of the memory component that meets the requirements of the data to be stored at the memory component. For example, the operation received by the command manager 210 may be a write operation to write 10 kilobytes of data to the memory subsystem. The command manager 210 may determine that the 2 kilobytes of data to be written are metadata or system data, which are associated with another 8 kilobytes as user data. User data may be accessed or retrieved more frequently than metadata or system data. In response, the command manager may generate a sub-operation to store 8 kilobytes of user data to a media sequencer used with a memory component of a media type that has a smaller latency than other media types, while the other two kilobytes may be stored at another memory component of another media type with a larger latency. Subsequently, different media sequencers may generate page operations to store corresponding metadata or system data and user data at corresponding memory components. In some embodiments, since the memory components may be different types of media, the size and address of the pages in the memory components may be different. Therefore, the page operation generated by a first media sequencer used with a memory component of a first media type may specify that the size of the data to be stored at the page of the memory component is different from the page operation generated by a second media sequencer used with other memory components of a second media type different from the first media type.

[0042] Figure 5A An error correction scheme by a controller having distributed components according to some embodiments is described. The error correction scheme may be Figure 2 The error correction components 225A, 225B and / or 225N are implemented.

[0043] like Figure 5AAs shown, each of the memory components 510A, 510B, and 510N can be associated with a different channel as previously described. Each of the different channels can include a separate error correction component, where each of the error correction components is used to store a codeword (e.g., an ECC codeword) across the memory components 510A, 510B, and 510N. For example, a portion of an ECC payload (e.g., data) and a corresponding ECC parity can be stored at each of the memory components of the different channels. Thus, each error correction component in the different channels can be used to generate an ECC codeword that is stored across the memory components 510A, 510B, and 510N.

[0044] Figure 5B Another error correction scheme by a controller having distributed components according to some embodiments is described. The error correction scheme may be Figure 2 The error correction components 225A, 225B and / or 225N are implemented.

[0045] like Figure 5B As shown, the error correction components of different channels can each store a separate codeword (e.g., an ECC codeword) at each respective memory component 510A, 510B, and 510C. For example, a first error correction component of a first channel can be used to generate and store a codeword (e.g., payload 1 and ECC parity 1) at memory component 510A, and a separate second error correction component of a second channel can be used to generate and store another codeword (e.g., payload 2 and ECC parity 2) at memory component 510B. In addition, a third error correction component of a third channel can be used to generate and store a third codeword at memory component 510N. Thus, each error correction component of a channel can be used to generate and store a separate codeword at a separate memory component.

[0046] In some embodiments, redundant subcomponents (eg, redundant subcomponent 212) may further be used to generate parity data for different memory components. For example, different parity data may be used based on data stored at respective memory components.

[0047] Figure 6 An example machine illustrating a computer system 600 may be executed within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 600 may correspond to a host system (e.g., Figure 1 ) that includes or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, execute the operating system to execute the corresponding Figure 1In some embodiments, the machine may be connected (e.g., using a network) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or in the capacity of a peer machine in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a cloud computing infrastructure or environment.

[0048] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0049] The example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0050] Processing device 602 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. Processing device 602 can also be one or more special processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 to communicate on a network 620.

[0051] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets or software of instructions 626 embodying any one or more of the methodologies or functions described herein. The instructions 626 may also reside, in whole or in part, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, with the main memory 604 and the processing device 602 also constituting machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may correspond to Figure 1 Memory subsystem 110.

[0052] In one embodiment, instructions 626 include instructions for implementing instructions corresponding to distributed components (e.g., Figure 1 The functionality of any and all components of the distributed components 113 of the present invention. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but not limited to, solid-state memory, optical media, and magnetic media.

[0053] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. In this article, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0054] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device to control and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0055] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0056] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0057] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium on which is stored instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. The machine-readable medium includes any mechanism for storing information in a machine (e.g., computer) readable form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a disk storage medium, an optical storage medium, a flash memory component, etc.

[0058] In the foregoing description, the embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications and variations may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A system comprising: a first memory device having a first media type; a second memory device having a second media type, the second media type being different from the first media type; as well as a processing device operably coupled to the first memory device and the second memory device to perform operations including: receiving a host operation to be performed at the system; determining a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a respective one of the first memory device or the second memory device; as well as Based on the first media type and the second media type, each of the plurality of sub-operations is assigned to a corresponding one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device.

2. The system of claim 1, wherein the processing device performs operations further comprising: transmitting a first sub-operation of the plurality of sub-operations to the first media sequencer associated with the first memory device; and A second sub-operation of the plurality of sub-operations is transmitted to the second media sequencer associated with the second memory device.

3. A system according to claim 2, wherein the first media sequencer determines a first page operation for the first memory device having the first media type based on the first sub-operation among the multiple sub-operations, and wherein the second media sequencer determines a second page operation for the second memory device having the second media type based on the second sub-operation among the multiple sub-operations.

4. A system according to claim 1, wherein each of the first memory device and the second memory device is associated with a corresponding channel among a plurality of channels of the processing device, and wherein each of the first media sequencer and the second media sequencer is associated with a different corresponding channel among the plurality of channels.

5. The system according to claim 3, further comprising: A plurality of error correction components, wherein each error correction component is included in a different one of the plurality of channels.

6. The system of claim 1, wherein the first memory device having the first media type comprises a cross-point array of non-volatile memory.

7. The system of claim 1, wherein the second memory device having the second media type comprises a NAND memory device.

8. A method comprising: receiving a host operation to be performed at a memory subsystem; determining a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a respective one of a first memory device having a first media type or a second memory device having a second media type, the second media type being different from the first media type; as well as Based on the first media type and the second media type, each of the plurality of sub-operations is assigned to a corresponding one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device.

9. The method according to claim 8, further comprising: transmitting a first sub-operation of the plurality of sub-operations to the first media sequencer associated with the first memory device; as well as A second sub-operation of the plurality of sub-operations is transmitted to the second media sequencer associated with the second memory device.

10. The method of claim 9, wherein the first media sequencer determines a first page operation for the first memory device having the first media type based on the first sub-operation of the plurality of sub-operations.

11. The method of claim 9, wherein the second media sequencer determines a second page operation for the second memory device having the second media type based on the second sub-operation of the plurality of sub-operations.

12. The method of claim 8, wherein each of the first memory device and the second memory device is associated with a corresponding channel among a plurality of channels of a processing device, and wherein each of the first media sequencer and the second media sequencer is associated with a different corresponding channel among the plurality of channels.

13. The method of claim 8, wherein the first memory device having the first media type comprises a cross-point array of non-volatile memory.

14. The method of claim 8, wherein the second memory device having the second media type comprises a NAND memory device.

15. A non-transitory computer-readable storage medium storing instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a host operation to be performed at a memory subsystem; determining a plurality of sub-operations associated with the host operation, each sub-operation corresponding to a respective one of a first memory device having a first media type or a second memory device having a second media type, the second media type being different from the first media type; and Based on the first media type and the second media type, each of the plurality of sub-operations is assigned to a corresponding one of a first media sequencer or a second media sequencer in a system-level memory controller, wherein the first media sequencer is associated with the first memory device and the second media sequencer is associated with the second memory device.

16. The non-transitory computer-readable storage medium of claim 15, wherein the instructions cause the processing device to perform operations further comprising: transmitting a first sub-operation of the plurality of sub-operations to the first media sequencer associated with the first memory device; and A second sub-operation of the plurality of sub-operations is transmitted to the second media sequencer associated with the second memory device.

17. A non-transitory computer-readable storage medium according to claim 16, wherein the first media sequencer determines a first page operation for the first memory device having the first media type based on the first sub-operation of the plurality of sub-operations, and wherein the second media sequencer determines a second page operation for the second memory device having the second media type based on the second sub-operation of the plurality of sub-operations.

18. The non-transitory computer-readable storage medium of claim 15, wherein each of the first memory device and the second memory device is associated with a corresponding channel among a plurality of channels of the processing device, and wherein each of the first media sequencer and the second media sequencer is associated with a different corresponding channel among the plurality of channels.

19. The non-transitory computer-readable storage medium of claim 15, wherein the first memory device having the first media type comprises a cross-point array of non-volatile memory.

20. The non-transitory computer-readable storage medium of claim 15, wherein the second memory device having the second media type comprises a NAND memory device.

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