Variable-length instruction storage controller, control method, terminal and storage medium

Abstract

This invention discloses a variable-length instruction storage controller, control method, terminal, and storage medium, relating to the field of integrated circuit design technology. The variable-length instruction storage controller includes: an address determination module, a dual-port array, an adder, an instruction fetch shift module, and an instruction cache module. The address determination module outputs the address of the instruction to be fetched, where the lower L bits of the address are control signals, and the remaining higher H bits are the instruction read address. The first read port of the dual-port array outputs a first port instruction at the address with the higher H bits, and the second read port outputs a second port instruction at the address with the higher H bits incremented by 1. Based on the control signals, a first instruction is selected from the first port instructions, and a second instruction is selected from the second port instructions to form a cached instruction. The shift switch array included in the instruction fetch shift module transmits the cached instruction to the instruction cache module, from which instructions of arbitrary length can be fetched, thus realizing variable-length instruction storage control.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, specifically to a variable-length instruction storage controller, control method, terminal, and storage medium. Background Technology

[0002] In traditional CPU architectures, the instruction memory controller typically stores instructions with a fixed bit width (e.g., 32 bits). This design simplifies the hardware logic for instruction fetching and execution, but it also leads to some efficiency issues. Some instructions may only require a short code length, and the traditional 32-bit instruction storage method wastes storage space. In some operations, the CPU frequently uses certain instructions. If a variable-length instruction memory controller is used, a shorter code length can be selected for frequently used instructions. This will significantly reduce the space requirements for instruction memory, thereby saving valuable instruction memory space, helping to reduce the overall size and cost of the instruction memory, and improving the utilization efficiency of storage resources.

[0003] Existing technologies provide a method and apparatus for caching variable-length instructions, using auxiliary memory to store duplicate copies of instruction data at cache boundary locations. Their primary purpose is to address access efficiency issues when variable-length instructions cross cache line boundaries, but they do not reduce the overall size and cost of the instruction memory. Existing technologies also provide an instruction cache with a fixed number of variable-length instructions. This method requires the number of instructions to be stored to be known and necessitates pre-processing instructions using a pre-decoder, making it unsuitable for scenarios where the number of instructions is unknown, and the pre-decoding operation increases the computational burden.

[0004] In summary, existing instruction memories suffer from drawbacks such as high size and cost, low resource utilization, and unsuitability for scenarios with unknown storage requirements. Summary of the Invention

[0005] This invention provides a variable-length instruction storage controller, control method, terminal, and storage medium. It uses a dual-port array to obtain instructions from adjacent addresses and can control the retrieval of variable-length instructions using known instruction lengths. This invention has low size and cost, high resource utilization, and can realize automatic instruction retrieval, making it suitable for scenarios with unknown storage quantities.

[0006] In a first aspect, the present invention provides a variable length instruction storage controller, comprising: an address determination module, a dual-port array, an adder, an instruction fetch shift module, and an instruction cache module;

[0007] The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port, and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data.

[0008] When in use, multiple instructions of different lengths are pre-stored into the dual-port array;

[0009] The address determination module outputs the address of the instruction to be fetched. The lower L bits of the address to be fetched are control signals, where L equals 1 or 2. The remaining upper H bits of the address are simultaneously transmitted to the first read port and the adder. The first read port outputs the first port instruction based on the upper H bits of the address. The adder adds 1 to the upper H bits of the address and transmits the result to the second read port. The second read port outputs the second port instruction of the address after adding 1. The first port instruction and the second port instruction are transmitted to the instruction fetch and shift module.

[0010] Based on the control signal, a first instruction is selected from the first port instruction, and a second instruction is selected from the second port instruction; the first instruction and the second instruction are combined to form a cached instruction;

[0011] The shift switch array included in the instruction fetch and shift module transmits cached instructions to the instruction cache module, and can retrieve instructions of arbitrary length from the instruction cache module, realizing storage control of variable length instructions.

[0012] As one possible implementation, the variable-length instruction storage controller has an automatic mode and a manual mode; in automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction sequentially according to the storage order based on the instruction length.

[0013] In manual mode, input the specified address to the address determination module, and the variable-length instruction storage controller reads the variable-length instruction from the specified address.

[0014] As one possible implementation, the address determination module includes a first multiplexer, a flip-flop, and an adder, which are switched to automatic or manual mode by a switch signal variable length instruction storage controller. The first multiplexer is used to output the address of the instruction to be retrieved.

[0015] In automatic mode, the trigger buffers the current instruction address, the adder adds the current instruction address to the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained by the above addition as the instruction address to be retrieved;

[0016] In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be retrieved.

[0017] As one possible implementation, the instruction fetch and shift module also includes a second multiplexer, which controls the displacement switch array to output instructions at the corresponding positions of the first port instruction and the second port instruction based on the control signal.

[0018] As one possible implementation, the instruction length is N bits, 1≤N≤5; the specified address length is S bits, 8≤S≤16; the dual-port array capacity is R bits, 256≤R≤64K; and the instruction cache module capacity is P bits, 16≤P≤40.

[0019] In a second aspect, the present invention provides a variable-length instruction storage control method, which applies the variable-length instruction storage controller provided in the first aspect, and includes the following steps:

[0020] S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be retrieved;

[0021] S2. Divide the address of the instruction to be fetched into low L bits and high H bits, where L equals 1 or 2;

[0022] S3. Based on the high H bit read instruction, generate control signals based on the low L bit;

[0023] S4. The control signal controls the displacement switch array to output the corresponding position instruction to the instruction cache module;

[0024] S5. Retrieve variable-length instructions from the instruction cache module.

[0025] As one possible implementation, in automatic mode, the instruction length is input, and each instruction is read sequentially according to the storage order based on the instruction length; in manual mode, a specified address is input, and variable-length instructions in the specified address are read.

[0026] As one possible implementation, in automatic mode, the address to be fetched is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address to be fetched is the specified address.

[0027] Thirdly, the present invention provides a terminal including a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the variable-length instruction storage control method provided in the first aspect.

[0028] Fourthly, the present invention provides a computer-readable storage medium including a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the variable-length instruction storage control method provided in the first aspect.

[0029] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0030] 1. Using the variable-length instruction storage controller provided by this invention, users can store instructions according to their actual length, instead of uniformly using a longer fixed length. This saves storage space, improves the utilization efficiency of storage resources, and helps reduce the overall cost and size of the hardware.

[0031] 2. The variable-length instruction storage controller provided by this invention is applicable to scenarios where the storage quantity is unknown, and can cope with more flexible instruction usage and requirements.

[0032] 3. The variable-length instruction storage controller provided by this invention reduces pre-decoding operations, thereby reducing the computational burden.

[0033] 4. The variable-length instruction storage controller provided by this invention has good compatibility and can adapt to instruction sets of different lengths and types. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0035] Figure 1 This is a schematic diagram of a variable-length instruction storage controller in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of the control logic of the variable-length instruction storage controller in automatic mode in an embodiment of the present invention;

[0037] Figure 3 This is a schematic diagram of the control logic of the variable-length instruction storage controller in manual mode in an embodiment of the present invention;

[0038] Figure 4 This is a flowchart of the variable-length instruction storage control method in an embodiment of the present invention. Detailed Implementation

[0039] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0040] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0041] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one of a, b, or c" can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0042] In traditional CPU instruction fetching, the instruction length for each fetch is a fixed 32 bits. Since some instructions are used frequently, using 8-bit, 16-bit, or 24-bit encoding for these instructions can save more instruction storage space. This invention provides a variable-length instruction storage controller, control method, terminal, and storage medium. It uses a dual-port array to fetch instructions from adjacent addresses, and the fetching of variable-length instructions can be controlled using a known instruction length.

[0043] In a first aspect, the present invention provides a variable-length instruction storage controller, see [link to relevant documentation]. Figure 1 It includes: an address determination module, a dual-port array, an adder, an instruction fetch and shift module, and an instruction cache module;

[0044] In use, multiple instructions of different lengths are pre-stored into the dual-port array; the variable-length instruction storage controller provided by this invention can be applied to scenarios where the number of instructions to be stored is unknown, and can cope with more flexible instruction usage and requirements.

[0045] The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port, and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data.

[0046] As one possible implementation, the variable-length instruction storage controller has an automatic mode and a manual mode; in automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction sequentially according to the storage order based on the instruction length.

[0047] In manual mode, input the specified address to the address determination module, and the variable-length instruction storage controller reads the variable-length instruction from the specified address.

[0048] The address determination module outputs the address of the instruction to be retrieved.

[0049] As one possible implementation, the address determination module includes a first multiplexer, a flip-flop, and an adder. The variable-length instruction storage controller is controlled by a switch signal to switch between automatic and manual modes. When the switch signal is 0, it switches to automatic mode, and when the switch signal is 1, it switches to manual mode. The first multiplexer is used to output the address of the instruction to be retrieved.

[0050] In automatic mode, the trigger buffers the current instruction address, the adder adds the current instruction address to the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained by the above addition as the instruction address to be retrieved;

[0051] In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be retrieved.

[0052] As an example of automatic mode, if the instruction length input to the address determination module is 3 bits, then the instruction length can be 001, 010, 011, 100, or 101, corresponding to instruction lengths of 8 bits, 16 bits, 24 bits, 32 bits, and 40 bits, respectively. Assuming the value is 001, meaning the instruction length is 8 bits, and assuming the current instruction address in the trigger cache is 11001100110, the adder will add the current instruction address 11001100110 to the instruction length 001 in binary to obtain 11001100111. The first multiplexer will output 11001100111 as the address of the instruction to be fetched.

[0053] As an example of manual mode, the address 11001100110 is input to the address judgment module, and the first multiplexer directly outputs 11001100110 as the address of the instruction to be retrieved.

[0054] The lower L bits of the address to be fetched are control signals, where L equals 1 or 2; the remaining higher H bits of the address are simultaneously transmitted to the first read port and the adder. The first read port outputs the first port instruction based on the higher H bits of the address; the adder adds 1 to the higher H bits of the address and transmits the result to the second read port; the second read port outputs the second port instruction at the address after the addition; the first port instruction and the second port instruction are transmitted to the instruction fetch and shift module.

[0055] As an example, suppose the address of the instruction to be retrieved is 11001100110. Divide 11001100110 into the high 9 bits 110011001 and the low 2 bits 10. The first read port outputs the first port instruction at address 110011001. The adder adds 1 to 110011001 to obtain 110011010. The second port outputs the second port instruction at address 110011010.

[0056] Based on the control signal, a first instruction is selected from the first port instruction, and a second instruction is selected from the second port instruction; the first instruction and the second instruction are combined to form a cached instruction;

[0057] As an example, the instruction cache module is set to 40 bits. When the lower two bits of the instruction address to be fetched are 00, the 32 bits of data from port 1 and the 8 bits of data from port 2 are combined into a 40-bit cached instruction; when the lower two bits of the instruction address to be fetched are 01, the 24 bits of data from port 1 and the 16 bits of data from port 2 are combined into a 40-bit cached instruction; when the lower two bits of the instruction address to be fetched are 10, the 16 bits of data from port 1 and the 32 bits of data from port 2 are combined into a 40-bit cached instruction; when the lower two bits of the instruction address to be fetched are 11, the 8 bits of data from port 1 and the 32 bits of data from port 2 are combined into a 40-bit cached instruction.

[0058] For example, the control signal is 10 for the lower two bits, combining the high 16 bits of the first port instruction and the low 32 bits of the second port instruction into a 40-bit buffered instruction. The shift switch array included in the instruction fetch shift module transmits the buffered instruction to the instruction buffer module, and instructions of arbitrary length can be fetched from the instruction buffer module, realizing the storage control of variable-length instructions.

[0059] As an example, the displacement switch array transmits 40 bits of cached instructions to the instruction cache module, and can retrieve 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module to achieve variable-length instruction storage control.

[0060] The variable-length instruction storage controller provided by this invention reduces pre-decoding operations, thereby reducing the computational burden.

[0061] As one possible implementation, the instruction fetch and shift module also includes a second multiplexer, which controls the displacement switch array to output instructions at the corresponding positions of the first port instruction and the second port instruction based on the control signal.

[0062] As one possible implementation, the instruction length is N bits, 1≤N≤5, for example: N=1, N=2, N=3, N=4, N=5; the specified address length is S bits, 8≤S≤16, for example: S=8, S=9, S=10, S=11, S=12, S=13, S=14, S=15, S=16; the dual-port array capacity is R bits, 256≤R≤64K; and the instruction cache module capacity is P bits, 16≤P≤40, for example: P=16, P=24, P=32, P=40.

[0063] The variable-length instruction storage controller provided by this invention has good compatibility and can adapt to instruction sets of different lengths and types.

[0064] To facilitate understanding of the technical solution of this application, further explanation will be provided below with reference to specific embodiments.

[0065] See Figure 2 This is a schematic diagram of the control logic of the variable-length instruction storage controller provided by the present invention in automatic mode. The instruction length 001 (i.e., 8 bits) is input to the address determination module. Assuming the current instruction address in the trigger cache is 11001100110, the adder adds the current instruction address 11001100110 to the instruction length 001 in binary to obtain 11001100111. The first multiplexer outputs 11001100111 as the address of the instruction to be fetched.

[0066] The instruction address to be fetched, 11001100111, is divided into the high 9 bits (110011001) and the low 2 bits (11). The high 9 bits (110011001) are transmitted to the first read port. An adder increments 1 by 1 to obtain 110011010, which is then transmitted to the second read port. The instruction fetch / shift module receives the instruction from the first port at address 110011001 and the instruction from the second port at address 110011010.

[0067] Use the lower two bits (11) as the control signal input, see [link / reference]. Figure 2 At this point, 8 bits of the instruction from the first port and 32 bits of the instruction from the second port are selected and combined into a 40-bit cached instruction. The displacement switch array transmits this 40-bit cached instruction to the instruction cache module. Users can retrieve 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module according to their own needs to realize the storage control of variable-length instructions.

[0068] See Figure 3This is a schematic diagram of the control logic of the variable-length instruction storage controller provided by the present invention in manual mode. When the specified address 11001100110 is input to the address determination module, the first multiplexer directly outputs 11001100110 as the address of the instruction to be retrieved.

[0069] The instruction address to be fetched, 11001100110, is divided into the high 9 bits (110011001) and the low 2 bits (10). The high 9 bits (110011001) are transmitted to the first read port. An adder increments 1 by 1 to obtain 110011010, which is then transmitted to the second read port. The instruction fetch / shift module receives the instruction from the first port at address 110011001 and the instruction from the second port at address 110011010.

[0070] Use the lower two bits (10) as the control signal input, see [link / reference]. Figure 3 At this point, 16 bits of the instruction from the first port and 24 bits of the instruction from the second port are selected and combined into a 40-bit cached instruction. The displacement switch array transmits this 40-bit cached instruction to the instruction cache module. Users can retrieve 8 bits, 16 bits, 24 bits, 32 bits or 40 bits from the instruction cache module according to their own needs to realize the storage control of variable-length instructions.

[0071] Using the variable-length instruction storage controller provided by this invention, users can store instructions according to their actual length, instead of uniformly using a longer fixed length. This saves storage space, improves the utilization efficiency of storage resources, and helps reduce the overall cost and size of the hardware.

[0072] Secondly, this invention provides a variable-length instruction storage control method, which applies the variable-length instruction storage controller provided in the first aspect, see [link to first aspect]. Figure 4 It includes the following steps:

[0073] S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be retrieved;

[0074] S2. Divide the address of the instruction to be fetched into low L bits and high H bits, where L equals 1 or 2;

[0075] S3. Based on the high H bit read instruction, generate control signals based on the low L bit;

[0076] S4. The control signal controls the displacement switch array to output the corresponding position instruction to the instruction cache module;

[0077] S5. Retrieve variable-length instructions from the instruction cache module.

[0078] As one possible implementation, in automatic mode, the instruction length is input, and each instruction is read sequentially according to the storage order based on the instruction length; in manual mode, a specified address is input, and variable-length instructions in the specified address are read.

[0079] As one possible implementation, in automatic mode, the address to be fetched is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address to be fetched is the specified address.

[0080] Thirdly, the present invention provides a terminal including a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the variable-length instruction storage control method provided in the first aspect.

[0081] Fourthly, the present invention provides a computer-readable storage medium including a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the variable-length instruction storage control method provided in the first aspect.

[0082] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and other materials. In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several of the functions listed in the specification. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0083] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A variable-length instruction storage controller, characterized in that, The variable-length instruction storage controller includes: an address determination module, a dual-port array, an adder, an instruction fetch and shift module, and an instruction cache module; The dual-port array includes a first read port, a second read port, a first write port, a second write port, a first enable port, and a second enable port; the first enable port is used to control the first write port to write data or the first read port to read data; the second enable port is used to control the second write port to write data or the second read port to read data. When in use, multiple instructions of different lengths are pre-stored into the dual-port array; The address determination module outputs the address to be fetched, where the lower L bits of the address to be fetched are control signals, and L equals 1 or 2; the remaining upper H bits of the address are simultaneously transmitted to the first read port and the adder. The first read port outputs a first port instruction based on the upper H bits of the address; the adder adds 1 to the upper H bits of the address and transmits the result to the second read port; the second read port outputs a second port instruction for the address after adding 1; the first port instruction and the second port instruction are transmitted to the instruction fetch and shift module. Based on the control signal, a first instruction is selected from the first port instruction, and a second instruction is selected from the second port instruction; the first instruction and the second instruction are combined to form a cached instruction; The shift switch array included in the instruction fetching and shifting module transmits the cached instructions to the instruction cache module, and instructions of arbitrary length can be retrieved from the instruction cache module to realize the storage control of variable length instructions.

2. The variable-length instruction storage controller according to claim 1, characterized in that, The variable-length instruction storage controller has an automatic mode and a manual mode; in automatic mode, the instruction length is input to the address determination module, and the variable-length instruction storage controller reads each instruction sequentially according to the storage order based on the instruction length. In manual mode, a specified address is input to the address determination module, and the variable-length instruction storage controller reads the variable-length instruction from the specified address.

3. The variable-length instruction storage controller according to claim 2, characterized in that, The address determination module includes a first multiplexer, a trigger, and an adder. The variable length instruction storage controller is controlled by a switch signal to switch between automatic mode and manual mode. The first multiplexer is used to output the address of the instruction to be retrieved. In automatic mode, the trigger caches the current instruction address, the adder adds the current instruction address to the instruction length and transmits the result to the first multiplexer, and the first multiplexer outputs the address obtained by the addition as the instruction address to be retrieved. In manual mode, the first multiplexer outputs the specified address as the address of the instruction to be retrieved.

4. The variable-length instruction storage controller according to claim 1, characterized in that, The instruction fetching and shifting module further includes a second multiplexer, which controls the displacement switch array to output instructions at the corresponding positions of the first port instruction and the second port instruction based on the control signal.

5. The variable-length instruction storage controller according to claim 2, characterized in that, The instruction length is N bits, 1≤N≤5; the specified address length is S bits, 8≤S≤16; the dual-port array capacity is R bits, 256≤R≤64K; the instruction cache module capacity is P bits, 16≤P≤40.

6. A variable-length instruction storage control method, employing the variable-length instruction storage controller according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Pre-store multiple instructions into the dual-port array to generate the address of the instruction to be retrieved; S2. Divide the address of the instruction to be retrieved into low L bits and high H bits, where L equals 1 or 2; S3. Based on the high H bit read instruction, generate a control signal based on the low L bit; S4. The control signal controls the displacement switch array to output the corresponding position instruction to the instruction cache module; S5. Retrieve variable-length instructions from the instruction cache module.

7. The variable-length instruction storage control method according to claim 6, characterized in that, In automatic mode, input the instruction length, and read each instruction sequentially according to the storage order based on the instruction length; in manual mode, input a specified address, and read the variable-length instructions in the specified address.

8. The variable-length instruction storage control method according to claim 7, characterized in that, In automatic mode, the address to be retrieved is the address obtained by adding the current instruction address and the instruction length; in manual mode, the address to be retrieved is the specified address.

9. A terminal, characterized in that, It includes a processor and a communication interface coupled to the processor, the processor being used to run computer programs or instructions to implement the variable-length instruction storage control method according to any one of claims 6 to 8.

10. A computer-readable storage medium comprising a processor and a communication interface coupled to the processor, the processor being configured to execute a computer program or instructions to implement the variable-length instruction storage control method of any one of claims 6 to 8.

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