Communication method and device

Abstract

The communication method is applied to a bus network, and comprises the following steps: a network management unit sends a request message to bus equipment, the request message is used for requesting to access a first configuration space register of the bus equipment, and the request message comprises a network address of the bus equipment, first indication information and information of the first configuration space register, the network address is an address allocated to the bus device by a network management unit, the first indication information is used for indicating the operation type of the first configuration space register, and the network management unit receives a response message which is from the bus device and responds to the request message. The access of the configuration space register of the bus equipment is realized through the network address of the bus equipment and the information of the configuration space register, and the problem of high time delay requirement caused by a memory address access mode is avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of information technology, and in particular to a communication method and device. Background Art

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect processors and external devices, which are called PCIe devices.

[0003] Generally speaking, the PCIe protocol uses a 32-bit PCIe identifier (ID) to identify PCIe devices in the system. The 32 bits include: 16-bit domain, 8-bit bus, 5-bit device, and 3-bit function. The 8-bit bus ID, 5-bit device ID, and 3-bit function ID are referred to as BDF (BDF stands for bus, device, and function). The Bus ID provides 256 bus numbers for each PCIe domain. Normally, a computer system supports one PCIe domain, which means that the entire computer system provides 256 bus numbers.

[0004] Specifically, there are generally two ways to access the PCIe device configuration space register: memory access and input output (I / O) access. I / O access can be simply understood as the user accessing the PCIe device configuration space register through the input or output (IN / OUT) instruction. Specifically, the first 256 bytes of the PCIe device can be accessed through the I / O port. Memory access is to map the entire PCIe device configuration space to the memory. After determining the device memory address, the PCIe device configuration space register can be accessed through memory reading and writing.

[0005] When accessing the configuration space registers of bus devices (such as PCIe devices) through memory access, the processor is in a waiting state after the access instruction is issued, which has constraints on the access delay and cannot implement the access to the configuration space registers across hosts. How to improve the performance of accessing the configuration space registers of bus devices has become an urgent problem to be solved. Summary of the invention

[0006] The embodiment of the present application provides a communication method, so as to access the configuration space register of the bus device through the network address of the bus device and the information of the configuration space register, thereby avoiding the problems caused by the memory address access method.

[0007] In a first aspect, a communication method is provided, which is applied to a bus network. The method can be executed by a network management unit, or can also be executed by a circuit or chip configured in the network management unit, which is not limited in the present application.

[0008] The communication method includes: sending a request message to a bus device, the request message is used to request access to a first configuration space register of the bus device, the request message includes a network address of the bus device, first indication information and information of the first configuration space register, the network address is an address allocated to the bus device by a network management unit, and the first indication information is used to indicate the type of operation on the first configuration space register; receiving a response message from the bus device in response to the request message.

[0009] Based on the above technical solution, when the network management unit needs to access the configuration space register of the bus device, the network management unit can carry the network address of the bus device and the information of the configuration space register to be accessed in the request message to access the configuration space register of the bus device. There is no need to access it through memory reading and writing. Therefore, the technical solution provides a method of accessing the configuration space register of the bus device through a request message, which can avoid the high latency requirements and the inability to access across hosts brought by the memory reading and writing method.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the request message also includes a task identifier, the response message includes the task identifier, and the task identifier is used to determine that the response message is a message in response to the request message.

[0011] Based on the above technical solution, the request message sent by the network management unit carries a task identifier, so that when the bus device feeds back a response message to the request message, the response message also carries the task identifier, representing the response message as a response to a certain request message, so that the network management unit can clearly know the response message corresponding to the request message based on the task identifier.

[0012] In combination with the first aspect, in some implementations of the first aspect, the operation type of the first configuration space register includes: a read operation or a write operation.

[0013] Based on the above technical solution, the network management unit can perform read or write operations on the configuration space register of the bus device, thereby improving the flexibility of the solution and enriching the application scenarios of the solution.

[0014] In combination with the first aspect, in some implementations of the first aspect, if the operation type of the first configuration space register is a write operation, the request message also includes data to be written into the first configuration space register.

[0015] Based on the above technical solution, when the network management unit performs a write operation on the configuration space register of the bus device, the network management unit can carry the data to be written into the configuration space register of the bus device in the request message to implement the write operation. The write operation can be implemented through a request message without the need to transmit the data to be written separately, thus saving signaling overhead.

[0016] In combination with the first aspect, in some implementations of the first aspect, the request message also includes second indication information, and the second indication information is used to indicate that the data is written into at least one byte in the first configuration space register.

[0017] Based on the above technical solution, when the network management unit performs a write operation on the configuration space register of the bus device, the network management unit can notify the bus device through the second indication information that the data to be written can be written into some bytes in the configuration space register of the bus device.

[0018] In combination with the first aspect, in some implementations of the first aspect, the information of the first configuration space register includes at least one of the following: type information of the first configuration space register, an index of the first configuration space register, or an address of the first configuration space register.

[0019] In combination with the first aspect, in certain implementations of the first aspect, the response message is used to indicate whether the operation on the first configuration space register is successful; or, if the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

[0020] In combination with the first aspect, in some implementations of the first aspect, the response message further includes information indicating that the response message is in response to a read operation or a write operation. The request message is also used to request access to a second configuration space register of the bus device, and the request message further includes third indication information and information about the second configuration space register, and the third indication information is used to indicate a type of operation on the second configuration space register.

[0021] Based on the above technical solution, the network management unit can access multiple configuration space registers of the bus device through one message, thereby improving access efficiency.

[0022] In combination with the first aspect, in some implementations of the first aspect, the bus network includes a network management unit and a plurality of bus devices, and the bus device is any one of the plurality of bus devices.

[0023] In a second aspect, a communication method is provided, which is applied to a bus device. The method can be executed by the bus device, or can also be executed by a circuit configured in the bus device, which is not limited in the present application.

[0024] The communication method includes: receiving a request message from a network management unit, the request message is used to request access to a first configuration space register of a bus device, the request message includes a network address of the bus device, first indication information and information of the first configuration space register, the network address is an address allocated by the network management unit to the bus device, and the first indication information is used to indicate the type of operation on the first configuration space register; and sending a response message in response to the request message to the network management unit.

[0025] In combination with the second aspect, in certain implementations of the second aspect, the request message also includes a task identifier, the response message includes the task identifier, and the task identifier is used to determine that the response message is a message in response to the request message.

[0026] In combination with the second aspect, in some implementations of the second aspect, the operation type of the first configuration space register includes: a read operation or a write operation.

[0027] In combination with the second aspect, in some implementations of the second aspect, if the operation type of the first configuration space register is a write operation, the request message also includes data to be written into the first configuration space register.

[0028] In combination with the second aspect, in some implementations of the second aspect, the request message also includes second indication information, and the second indication information is used to indicate that the data is written into at least one byte in the first configuration space register.

[0029] In combination with the second aspect, in some implementations of the second aspect, the information of the first configuration space register includes at least one of the following: type information of the first configuration space register, an index of the first configuration space register, or an address of the first configuration space register.

[0030] In combination with the second aspect, in certain implementations of the second aspect, the response message is used to indicate whether the operation on the first configuration space register is successful; or, if the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

[0031] In combination with the second aspect, in some implementations of the second aspect, the response message also includes information indicating that the response message is in response to a read operation or a write operation.

[0032] In combination with the second aspect, in certain implementations of the second aspect, the request message is also used to request access to a second configuration space register of the bus device, and the request message also includes third indication information and information of the second configuration space register, and the third indication information is used to indicate the type of operation on the second configuration space register.

[0033] In combination with the second aspect, in some implementations of the second aspect, the bus network includes the network management unit and multiple bus devices, and the bus device is any one of the multiple bus devices.

[0034] The technical effects of the method shown in the above second aspect and its possible design can refer to the technical effects in the first aspect and its possible design.

[0035] In a third aspect, a communication device is provided, which includes: a storage module for storing programs; a processing module for executing the programs stored in the storage module, and when the programs stored in the storage module are executed, the processing module is used to execute the methods provided by the above aspects.

[0036] According to a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable medium stores a program code for execution by a device, wherein the program code includes code for executing the methods provided in the above aspects.

[0037] According to a fifth aspect, a computer program product comprising instructions is provided. When the computer program product is run on a computer, the computer is used to execute the methods provided in the above aspects.

[0038] In a sixth aspect, a chip is provided, which includes a processing module and a communication interface. The processing module reads instructions stored in a memory through the communication interface to execute the methods provided in the above aspects.

[0039] Optionally, as an implementation method, the chip may also include a storage module, in which instructions are stored, and the processing module is used to execute the instructions stored on the storage module. When the instructions are executed, the processing module is used to execute the methods provided by the above aspects.

[0040] In a seventh aspect, a chip is provided, comprising a network management unit for executing the method provided in the first aspect and a bus device for executing the method provided in the second aspect.

[0041] In an eighth aspect, a computer system is provided, which includes the chip shown in the seventh aspect.

[0042] In a ninth aspect, a terminal device is provided, the terminal device comprising the chip shown in the seventh aspect. For example, the terminal device includes but is not limited to mobile phones, vehicles and other terminals.

[0043] In a tenth aspect, a system for accessing a configuration space is provided, the system comprising a network management unit for executing the method provided in the first aspect and a bus device for executing the method provided in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 A schematic diagram of the structure of a computer system provided in an embodiment of the present application.

[0045] Figure 2 A schematic diagram of a data center provided in an embodiment of the present application.

[0046] Figure 3 It is a schematic diagram of a universal bus protocol message format provided in an embodiment of the present application.

[0047] Figure 4 It is a structural diagram of a host provided in an embodiment of the present application.

[0048] Figure 5 It is a schematic diagram of bus number allocation in a PCIe system.

[0049] Figure 6 It is a schematic diagram of the device configuration space register provided in an embodiment of the present application.

[0050] Figure 7 (a) is a schematic diagram of the device configuration space register address provided in an embodiment of the present application.

[0051] Figure 7 (b) is a schematic diagram of a bus network provided in an embodiment of the present application.

[0052] Figure 8 It is a schematic flow chart of a communication method provided by the present application.

[0053] Fig. 9 It is a schematic diagram of a transaction layer message provided by this application.

[0054] Fig.10 This is a schematic diagram of a message header of a transaction layer message provided by this application.

[0055] Fig.11 This is a schematic diagram of the payload part of a request message provided by this application.

[0056] Fig.12This is a schematic diagram of the payload portion of a response message provided by this application.

[0057] Fig.13 A schematic structural diagram of a communication device 1300 provided in an embodiment of the present application is shown.

[0058] Fig.14 A schematic structural diagram of a chip system 1400 provided in an embodiment of the present application is shown.

[0059] Fig.15 A conceptual partial view of a computer program product provided by an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0061] The present application relates to a processor in a computer system accessing a configuration space of an external device. The computer system may be a server or a terminal. The terminal includes but is not limited to user systems such as desktop computers, laptop computers, and smart phones. For ease of understanding, the structure of the computer system is introduced below.

[0062] See also Figure 1 As shown in the structural diagram of the computer system, the computer system includes a processor 101, an input output device (I / O device) 102, a memory 103, a cache 104, a memory management unit (MMU) 105, an input output memory management unit (IOMMU) 106, an external memory 107 and a bus 108.

[0063] The processor 101 includes at least one core. The core is also called a computing engine. Each core can independently execute tasks. When the processor 101 includes multiple cores, tasks from applications can be divided so that the application can make full use of multiple cores and execute more tasks within a specific time. In this embodiment, the processor 101 can be a main processor, such as a central processing unit (CPU).

[0064] The input / output device 102 refers to a hardware device that has the ability to input data and / or output data. The input / output device 102 can be divided into input devices and output devices. Among them, the input device can include devices such as a mouse, a keyboard, a joystick, a stylus, a microphone, etc., and the output device can include devices such as a display and a speaker.

[0065] The memory 103 is also called internal memory or main memory, and is used to temporarily store the operation data in the processor 101. Furthermore, the memory 103 is also used to temporarily store the data exchanged with the external memory 107. The memory 103 can usually be implemented by a storage medium such as a dynamic random access memory DRAM or a static random access memory (SRAM).

[0066] The cache 104 (in this embodiment, it refers to the processor cache, such as the CPU cache) is a component used to reduce the average time required for the processor 101 to access the memory 103. Figure 1 In the pyramid storage system, the cache 104 is located in the second layer from top to bottom, second only to the registers of the processor 101 ( Figure 1 103 (not shown), which is higher than the memory 103 (the memory 103 is located in the third layer from the top). Generally, the capacity of the cache 104 is much smaller than the memory 103, but the access speed can be close to the frequency of the processor 101.

[0067] The memory management unit 105 is a computer hardware for processing data access requests. The memory management unit 105 is specifically used to map the virtual address (VA) in the data access request. The memory management unit 105 can intercept the data access request issued by the core of the processor 101, and map (or translate) the virtual address in the data access request into a physical address (PA) so as to access the memory 103 according to the physical address.

[0068] The I / O memory management unit 106 is essentially a memory management unit. Similar to the memory management unit 105 mapping the virtual addresses visible to the processor 101 to physical addresses, the I / O memory management unit 106 is used to map the virtual addresses (also called device addresses or I / O addresses) visible to the input and output devices 102 to physical addresses.

[0069] The external memory 107 is also called external memory or auxiliary memory, and is usually used to persist data. For example, the external memory 107 can persist the operation data in the storage processor 101. Even if the power supply is abnormal, the data written into the external memory 107 can still be saved, thus avoiding data loss. In specific implementation, the external memory 107 includes at least one non-volatile memory 1071. When the external memory includes multiple non-volatile memories, these multiple non-volatile memories can be of the same type or different types. For example, in Figure 1In the example, the external memory 107 may include two types of non-volatile memories, such as storage class memory (SCM) and solid state drive (SSD).

[0070] The bus 108 is used to connect the various functional components of the computer system. The bus 108 is a common communication trunk for transmitting information between the various functional components of the computer system. The bus 108 can be a transmission line bundle formed by wires. Depending on the connection object, the bus 108 can also be divided into an internal bus and an external bus.

[0071] The internal bus uses an internal bus protocol to transmit information. The internal bus protocol includes a bus protocol for accessing the memory space of the computer system. The external bus uses an external bus protocol to transmit information. The external bus protocol includes a bus protocol for accessing the external memory space of the computer system. The memory space refers to the address space of the internal memory, and the external memory space refers to the address space of the external memory.

[0072] In some embodiments, the internal bus protocol includes but is not limited to the peripheral component interconnect (PCI) bus, the peripheral component interconnect (PCI Express, PCIe) protocol, the IntelTM Quick Path Interconnect (QPI) protocol, and the universal bus protocol. The external bus protocol includes but is not limited to the small computer system interface (SCSI) protocol or the serial attached SCSI (SAS) protocol.

[0073] It should be noted that Figure 1 The computer system shown is illustrated by taking the external memory 107 as a remote external memory. Figure 1 As shown, the external memory 107 includes a network card 1072. The network card 1072 may be, for example, a smart NIC network interface card (i.e., a network adapter card). The external memory 107 is connected to the network through the network card 1072, and then connected to other components of the computer system 101 through the network. The network may be a wired communication network, such as an optical fiber communication network, or a wireless communication network, such as a wireless local area network (WLAN) or a fifth generation (5G) mobile communication network.

[0074] In some possible implementations, the external memory 107 of the computer system may also be a local external memory, and other components of the computer system, such as the processor 101, may be connected to the local external memory via the bus 108. In other possible implementations, the computer system may include both remote external memory and local external memory. In addition, the embodiments of the present application may be applicable to centralized storage or distributed storage scenarios, which are not limited in this embodiment.

[0075] Exemplarily, the method for accessing the configuration space register of the bus device provided in the embodiment of the present application can also be applied to Figure 2 A server cluster communicating across a network, such as Figure 2 The data center shown. Figure 2 The internal structure of the switch or server shown in the above Figure 1 as shown in .

[0076] In addition, the internal bus protocol supported by the computer system involved in this application includes a universal bus protocol, and a transport layer connection can be established between computer systems. Among them, the universal bus protocol can also be called Lingqu bus protocol or unified bus protocol, a bus protocol standard, and this application does not limit the name of the universal bus protocol.

[0077] The universal bus protocol breaks down the existing barriers of various protocols and removes unnecessary conversion overhead in the middle, thereby achieving extremely low latency. The universal bus protocol defines independent transaction layers and transport layers. There is a connection between the transport layers, but no connection between the transaction layers. All transactions within a host are carried on a transport layer. The universal bus protocol includes a transport layer and a transaction layer. The transport layer is responsible for network packet loss and retransmission to ensure reliable transmission, and the transaction layer handles different transactions. The transport layer receives the packet from the network, strips off the transport layer header, and forwards it to the transaction layer.

[0078] The general bus protocol message format is as follows Figure 3 Specifically, the fields in the universal bus protocol message format are defined as shown in Table 1 below:

[0079] Table 1

[0080]

[0081] Figure 4 is a schematic diagram of the structure of a host provided in an embodiment of the present application. Figure 4 The host A shown in the figure can be applied to Figure 2 In the application scenario of cross-network communication shown in Figure 4 As shown, host A includes a network management unit, a double data rate (DDR) memory, and bus devices (such as Figure 4Device 1 (device 1, Dev1) and Dev2 shown in ). After the system is powered on, the network management unit can scan and discover Dev1 and Dev2, and assign network address 1 (network address 1) and network address 2 to Dev1 and Dev2. The specific manner in which the network management unit assigns network addresses to Dev1 and Dev2 is not limited in this application. The network management unit can scan the device ports of the entire network, for example, by a hop-by-hop mechanism or by managing the network.

[0082] Specifically, Figure 4 The network management unit shown includes a processing core and a controller, wherein there is an entry engine of a device bus on the controller, and the system reserves an address space for the entry engine during design (e.g., address space required for information such as doorbell, send queue entry (Send Queue Entry, SQE), receive queue entry (receive Queue Entry, SQE) and complete queue entry (Complete Queue Entry, CQE)).

[0083] Combined with the above Figures 1 to 4 The application scenarios of the present application and the internal logic units of the host involved are briefly introduced. In order to facilitate the understanding of the embodiments of the present application, some basic concepts involved in the present application are briefly explained.

[0084] 1. PCIe bus:

[0085] The PCIe bus is an I / O bus of the processor system. Its function is similar to that of the Peripheral Component Interconnect (PCI) bus. Its main purpose is to connect external devices in the processor system. The PCIe bus uses an end-to-end connection method. A device is connected at each end of a PCIe link. These two devices are the data transmitter and receiver of each other.

[0086] A typical PCIe system includes a root complex (RC), a PCIe switch, and a PCIe bus device. Among them, the RC can be located on the processor, and the RC itself occupies a bus number. The PCIe switch contains an upstream port and a downstream port. The upstream port is used to connect to the root port (RP) of the RC or the downstream port of other PCIe switches. The root port of the RC, the upstream port and the downstream port of the PCIe switch can also be called bridge devices. The bridge device is used to connect to other bridge devices or bus devices.

[0087] It should be noted that the PCIe switch can be a separate physical device, such as a physical switch or a switching chip; it can also be a hardware functional module implemented in a chip, for example, it can be a hardware functional module integrated in a processor chip to implement the function of a PCIe switch.

[0088] like Figure 5 As shown in the figure, it is a schematic diagram of bus number allocation in a PCIe system, wherein there are multiple root ports (RP) on the central processing unit (CPU), and two RPs are taken as an example in the figure, and multiple RPs can be located on one or more RCs (not shown in the figure). Exemplarily, RP0 can be connected to a bus device or a bridge device (not shown in the figure), and RP1 is connected to the upstream port (UP) of the PCIe switch (switch). The PCIe switch includes m+1 downstream ports (DP), marked as DP_0, DP_1, ..., DP_m, and each downstream port is connected to a bus device. Figure 1The bus devices shown are labeled EP_0, EP_1, ..., EP_m. Exemplarily, the root port RP1 connected to the upstream port UP occupies bus X, and the link between RP1 and UP occupies bus N. At this time, the connection from the upstream port to the m+1 downstream ports inside the PCIe switch occupies bus N+1, and the connection between each downstream port and the corresponding bus device occupies bus N+2, bus N+3, ..., bus N+2+m respectively. Wherein, X is an integer greater than or equal to 0, and N is an integer greater than X. Exemplarily, when the two RPs shown in the figure are located in different RCs and the left RC where RP0 is located is enumerated first, the value of X depends on the bus number occupied by the PCIe structure under the left RC. For example, when the PCIe structure under the left RC occupies 5 bus numbers (that is, bus 0-4 is occupied by the left RC and the PCIe structure under it), the value of X is 5 and the value of N is 6; when the two RPs shown in the figure are located in the same RC and the RC is the RC enumerated first by the processor, the value of X is 0. If the PCIe structure under the left RC occupies 5 bus numbers (that is, bus 0-4 is occupied by the RC and the PCIe structure under RP0), the value of N is 5.

[0089] PCIe devices can be divided into two types, one is a bridge device, such as a root port RP, an upstream port, and a downstream port, and the other is a bus device (Endpoint, EP). At both ends of the PCI bridge, two buses are connected, namely the upstream bus (Primary Bus) and the downstream bus (Secondary Bus). The PCIe bridge can manage the PCIe subtree under it. The bridge device has Subordinate Bus Number, Secondary Bus Number and Primary Bus Number registers. The Primary Bus Number register stores the PCIe bus number upstream of the bridge device, the Secondary Bus Number register stores the PCIe bus number downstream of the bridge device, and the Subordinate Bus Number register stores the PCIe bus number with the largest number in the PCIe subtree downstream of the bridge device. The Subordinate Bus Number is called the subordinate bus number.

[0090] Generally speaking, the PCIe protocol uses a 32-bit PCIe identifier (ID) to identify PCIe devices in the system. The 32 bits include: 16-bit domain, 8-bit bus, 5-bit device, and 3-bit function. The 8-bit bus ID, 5-bit device ID, and 3-bit function ID are referred to as BDF. The Bus ID provides 256 bus numbers for each PCIe domain. Normally, a computer system supports one PCIe domain, which means that the entire computer system provides 256 bus numbers.

[0091] Figure 5 This is just an example of possible bus allocation in a PCIe system to illustrate the bus number allocation situation, and does not constitute any limitation on the protection scope of this application.

[0092] 2. PCIe device enumeration: The process of scanning and discovering all devices on the PCIe bus is called the PCIe device enumeration process. Since the personal computer (PC) was invented by International Business Machines (IBM) in 1981, there have been expansion slots on the motherboard to expand computer functions. The most common expansion slot now is the PCIe slot. Inside the computer motherboard chip, most of the hardware control modules are mounted on one or several PCI or PCIe device trees in the form of PCIe devices. It is by enumerating the device tree that the firmware and operating system can discover most plug-and-play devices.

[0093] After the computer system is reset or powered on, the software must first scan the PCIe bus to enumerate all devices connected to the bus. Before scanning, the device that the software can perceive is the Host / PCI bridge, and it also knows that the bus number under the Host / PCI bridge is 0.

[0094] Each PCIe Function's configuration space register has a read-only register for the vendor identifier (ID). The Vendor ID is a 16-bit specific value assigned to each vendor by the Peripheral Component Interconnect Special Interest (PCI-SIG). During the PCIe device enumeration process, the system software will traverse all possible combinations of Bus&Device&Function and try to read the Vendor ID register at each Bus&Device&Function location. Based on the read results, it can be determined whether the Function located by a Bus&Device&Function actually exists. In short, the PCIe device enumeration process is the process of system software accessing the PCIe device configuration space register.

[0095] 3. Configuration space: In the early PCI era, the system allocated 256 bytes of configuration space for each PCIe device. In the PCIe era, as device performance increased, the configuration space of PCIe devices expanded to 4K bytes. It should be noted that PCIe supports a total of 256 buses, 32 devices, and 8 functions. Under full load, the required configuration space size = 4K*256*32*8 = 256M. This 256M configuration space is prepared for PCIe devices and is not available to the system. Specifically, PCIe devices are developed to be forward compatible with PCI. The first 256 bytes of the configuration space of each PCIe device are PCI space, and the last (256-4K) bytes are PCIe expansion space.

[0096] Each PCIe device has its own independent configuration space. This configuration space belongs to the PCIe device. The system will configure a memory space for this device. When the CPU accesses this memory space, it accesses the configuration space of the PCIe device.

[0097] Exemplarily, when the PCIe device leaves the factory, the configuration space has a default initial value.

[0098] 4. I / O access and memory access: In the X86 system, the address mapping of the configuration space of the PCIe device includes I / O mapping and memory mapping. The configuration space of the PCIe device can be accessed through I / O access and memory access.

[0099] Specifically, the access to the configuration space of the PCIe device is inseparable from the numbering of the bus, device, and function of the PCIe device. Bit [23:16] represents the bus number, which is used to store the bus number, with a total of 8 bits (bits), which can store 256 bus numbers; bit [15:11] represents the device number, which is used to store the device number, with a total of 5 bits (bits), which can store 32 device numbers; bit [10:8] represents the function number, which is used to store the function number, with a total of 3 bits (bits), which can store 8 function numbers. This can also explain why PCIe supports a total of 256 buses, 32 devices, and 8 functions. In addition, bit

[31] represents the enable bit; bit [7:2] represents the register number of the configuration space; bit [1:0] is always "00".

[0100] According to the protocol, two I / O port registers are used on X86: config_address (physical address is 0CF8h) and config_data (physical address is CFCh) to access the configuration space of PCIe devices. Among them, OUT and IN are port read and write operation instructions in assembly. Ports are used by the host and peripherals to exchange data. They are divided into data ports, status ports and control ports. The PC assigns an address to each port. All ports are arranged linearly to form an I / O address space independent of the memory space, which is generally expressed in hexadecimal. For example, the range of port addresses is 0000H-FFFFH.

[0101] Exemplarily, by filling BDF in the CF8h port, the content of the configuration space of the PCIe device can be written or read on CFCh.

[0102] I / O access can be simply understood as a user accessing a section of storage space through input or output (IN / OUT) instructions. Some PCIe devices can be mapped to I / O space, and developers access them through I / O ports. For example, the first 256 bytes of a PCIe device can be accessed through the CF8h / CFCh port.

[0103] It should be understood that the I / O access mechanism can only access the first 256 bytes of the 4K bytes configuration space of the function.

[0104] To facilitate understanding, a specific example is given to illustrate how to access the configuration space of a PCI device through I / O access:

[0105] Example 1:

[0106] Step 1: The bus number of the PCI device is filled in the [23:16] bits of the I / O address CF8h, the device number of the PCI device is filled in the [15:11] bits of the I / O address CF8h, the function number of the PCI device is filled in the [10:8] bits of the I / O address CF8h, the double-word address of the register to be accessed is filled in the [7:2] bits of the I / O address CF8h, and the highest bit of CF8h is the configuration bit, which is set to 1.

[0107] Step 2: For write operations, combine the device-specific information into a double word (4 bytes) and write it to the CFCh address; for read operations, combine the device-specific information into a double word and read the data back from CFCh.

[0108] The I / O access method can access the first 255 bytes of configuration space of the PCIe device.

[0109] Memory mapping maps the entire PCIe device configuration space to memory. After determining the device address, the user can access the PCIe device configuration space by reading and writing memory. The memory mapping method can access the 4K bytes address space, but the access operation is a memory access operation.

[0110] Specifically, when the software accesses the configuration space of a specified PCIe device, it needs to correctly calculate the specific address of the configuration space mapped to the memory. Among them, the address of bus No=0, device No=0, func No=0 is exactly BAR. The maximum space occupied by a bus is calculated as follows:

[0111] SIZEPERBUS=4K*32*8=256K=1M=100000h

[0112] SIZE_PER_DEVICE=4K*8=8000h

[0113] SIZE_PER_FUNC=4K=1000h

[0114] The calculation formula for software access to the configuration space of a PCIe device with bus number bus No, device number Dev No, and function number func No is:

[0115] Memory Address=PCIe Configuration Register Base Address Register(BAR)+busNo*SIZE_PER_BUS+devNo*SIZE_PER_DEVICE+funcNo*SIZE_PER_FUNC+offset

[0116] To facilitate understanding, a specific example is given to illustrate how to access the configuration space of a PCI device through memory access:

[0117] Example 2: The software accesses the configuration space of a PCIe device whose bus No is 15h, device No is 00h, function No is 05h, and register offset is 84h.

[0118] Step 1: Calculate the memory address to be accessed using the calculation formula of the configuration space of the PCIe device mentioned above:

[0119] Memory Address=F0000000h+15h*100000h+00h*8000h+05h*1000h+84h=F1505084h

[0120] Step 2: After determining the device memory address, you can access the PCIe device configuration space by reading and writing memory.

[0121] 5. Bus device enumeration: The process of scanning and discovering all devices on the universal bus is called bus device enumeration. Similar to the above PCIe device enumeration process, the bus device enumeration process can also be understood as the process of system software accessing the bus device configuration space register.

[0122] 6. Bus device configuration space register: In this application, the bus device configuration space register can also be referred to as the bus device space register, or simply referred to as the bus configuration space, bus device space, etc. It should be understood that the resources, configuration and management of the bus device mainly include the public configuration management of the physical device, resource configuration management, interconnection configuration management, internal task queue resources, memory resources, network resources, etc. When the device resources are pooled, each host does not need to manage the public configuration, resource configuration and interconnection configuration of the device. The host can use the memory, network and other resources inside the device.

[0123] For ease of understanding, combined Figure 6 and Figure 7 (a) in the figure briefly introduces the bus device configuration space registers.

[0124] like Figure 6 As shown, the bus device configuration space register includes different types of registers, and different types of registers correspond to different address blocks. Specifically, the configuration space register is divided into different address blocks (such as Figure 6Different address blocks correspond to different types of configuration space registers; or, different types of registers correspond to different address ranges.

[0125] like Figure 7 As shown in (a), the address block corresponding to a certain type of register can be divided into different segments. Different segments correspond to different address spaces. A segment includes a reserved bit and a register corresponding to a 4Kbyte address space.

[0126] In addition, in order to facilitate understanding of the embodiments of the present application, the following explanations are made.

[0127] First, "at least one" shown in the present application refers to one or more, and "multiple" refers to two or more. In addition, in the embodiments of the present application, "first", "second" and various digital numbers (for example, "#1", "#2", etc.) are only for the convenience of description, and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of each process below does not mean the order of execution. The execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. It should be understood that the objects described in this way can be interchanged in appropriate circumstances, so that the schemes outside the embodiments of the present application can be described. In addition, in the embodiments of the present application, words such as "S810" are only for the convenience of description, and are not to limit the order of execution steps.

[0128] Second, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0129] Third, the "storage" involved in the embodiments of the present application may refer to storage in one or more memories. The one or more memories may be separately set or integrated in an encoder or decoder, a processor, or a communication device. The one or more memories may also be partially separately set and partially integrated in a decoder, a processor, or a communication device. The type of memory may be any form of storage medium, and the present application is not limited thereto.

[0130] Fourth, the term “comprising” (also referred to as “includes”, “including”, “comprises” and / or “comprising”) involved in the embodiments of the present application when used in this specification specifies the existence of stated features, integers, steps, operations, elements, and / or parts, but does not exclude the existence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0131] Fifth, the "if" involved in the embodiments of the present application can be interpreted as meaning "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if it is determined that..." or "if [the stated condition or event] is detected" can be interpreted as meaning "when determining..." or "in response to determining..." or "when [the stated condition or event] is detected" or "in response to detecting [the stated condition or event]".

[0132] Sixth, the terms used in the description of various examples in the embodiments of the present application are only for describing specific examples and are not intended to be limiting. As used in the description of various examples and in the appended claims, the number forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise.

[0133] Seventh, the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0134] Combination of the above Figure 1 The application scenarios of the communication method provided by the present application are briefly introduced, as well as the basic concepts involved in the present application. I / O access and memory access are introduced in the basic concepts. When accessing the configuration space register of a bus device (such as a PCIe device) through memory access, the processor is in a waiting state after the access instruction is issued, which has constraints on the access delay, and the access to the configuration space register cannot be implemented across hosts. For example, the above-mentioned memory access method is not suitable for multiple host application scenarios, because one host has one set of bus numbers, and two hosts have two sets of bus numbers. The memory access method is only suitable for configuration space register access in a single host service scenario.

[0135] The present application proposes a communication method, when a network management unit needs to access the configuration space register of a bus device, the network management unit can carry the network address of the bus device and the information of the configuration space register to be accessed in the request message to access the configuration space register of the bus device. There is no need to access through memory reading and writing. Therefore, the technical solution provides a method of accessing the configuration space register of the bus device through a request message, which can avoid the disadvantages of high latency requirements and inability to access across hosts brought by the memory reading and writing method.

[0136] The communication method provided by the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the communication method provided by the embodiment of the present application can be applied to a computer system, for example, Figure 2 Systems accessed across a network are shown.

[0137] It should also be understood that the embodiments shown below do not specifically limit the specific structure of the execution subject of the method provided in the embodiments of the present application, as long as the method provided in the embodiments of the present application can be implemented by running a program that records the code of the method provided in the embodiments of the present application. For example, the execution subject of the method provided in the embodiments of the present application may be a device, or a functional module in the device that can call and execute a program.

[0138] Figure 8 is a schematic flow chart of a communication method provided by the present application. The communication method can be applied to Figure 7 In the bus network shown in (b), the bus network includes a network management unit and at least one bus device (such as Figure 7 In (b), the bus device #1, line device #2, ..., line device #n) are shown, and the network management unit and the bus devices are connected via a universal bus. The bus network may include multiple hosts, and the bus network may be understood as a wired bus network as distinct from a wireless network.

[0139] Specifically, the communication method comprises the following steps:

[0140] S810, the network management unit sends a request message to the bus device, or the bus device receives a request message from the network management unit.

[0141] Specifically, in this embodiment, the network management unit and the bus devices are connected via a universal bus. Exemplarily, in this embodiment, the universal bus serves as a local bus of the bus network, connecting bus devices (also referred to as external devices, endpoint devices, etc.) in the bus network.

[0142] The request message includes the network address of the bus device, the first indication information and the information of the first configuration space register.

[0143] The network address of the bus device is the address assigned to the bus device by the network management unit. Specifically, the bus network may include at least one bus device. It should be noted that in this embodiment, before the network management unit accesses the configuration space register of the bus device, the network management unit can discover the bus device in the bus network and assign a network address to the bus device.

[0144] For example, the bus network includes a network management unit and bus device #1, bus device #2, and bus device #3. The network management unit can allocate network address #1 to bus device #1, allocate network address #2 to bus device #2, and allocate network address #3 to bus device #3. When the network management unit needs to access bus device #1, the network management unit sends a request message #1 to bus device #1, and carries network address #1 in the request message #1; similarly, when the network management unit needs to access bus device #2, the network management unit sends a request message #2 to bus device #2, and carries network address #2 in the request message #2; when the network management unit needs to access bus device #3, the network management unit sends a request message #3 to bus device #3, and carries network address #3 in the request message #3.

[0145] The first indication information is used to indicate the type of operation on the first configuration space register. For example, when the network management unit performs a read operation on the first configuration space register of the bus device through a request message, the first indication information is used to indicate a read; when the network management unit performs a write operation on the first configuration space register of the bus device through a request message, the first indication information is used to indicate a write, wherein the write operation includes but is not limited to adding or modifying.

[0146] Exemplarily, when the first indication information indicates that the operation type for the first configuration space register is a write operation, the request message may further include data to be written into the first configuration space register.

[0147] For example, the network management unit requests to write data #1 into the first configuration space register of the bus device through a request message, and the request message carries the data #1.

[0148] Exemplarily, when the first indication information indicates that the operation type for the first configuration space register is a write operation, the request message may further include second indication information, where the second indication information is used to indicate that data is written into at least one byte in the first configuration space register.

[0149] For example, the size of the first configuration space register is 4 bytes. The network management unit can request to write data #1 into two bytes in the first configuration space register of the bus device through a request message. The request message carries data #1 and second indication information, and the second indication information indicates that data #1 is written into any two bytes in the first configuration space register.

[0150] The information of the first configuration space register is used to indicate the first configuration space register, and is information related to the first configuration space register.

[0151] Exemplarily, the information of the first configuration space register includes at least one of the following:

[0152] Type information of a first configuration space register, an index of a first configuration space register, or an address of a first configuration space register.

[0153] The type information of the first configuration space register is used to identify the type of the first configuration space register of the bus device to be accessed. Figure 6 As shown in , the configuration space registers configured locally by the bus device in this application may include different types, and different types of configuration space registers correspond to different types of address blocks. Therefore, by carrying the type information of the configuration space register in the request message, the address corresponding to the configuration space register to be accessed can be accurately indicated. For example, if the type information of the first configuration space register indicates that the type of the first configuration space register of the bus device to be accessed is a basic register, then the address block accessed by the access message is Figure 6 The basic block shown in FIG. 1 corresponds to segment 0.

[0154] In addition, the address of the first configuration space register is used to indicate the address of the first configuration space register of the bus device to be accessed. It should be understood that a configuration space register may include multiple address segments, such as the above Figure 7 As shown in (a), the address block corresponding to a certain configuration space register includes multiple fragments, and the addresses of different fragments are different. The address of the first configuration space register of the accessed bus device can be indicated in detail through the address information of the first configuration space register.

[0155] It should be understood that in this embodiment, no limitation is imposed on the specific form of the information of the first configuration space register, and any information that can be used to indicate the first configuration space register is within the protection scope of this application.

[0156] Furthermore, the request message also includes a task identifier (ID), which is used to identify the request message. Different request messages may carry different task identifiers. For example, the task identifier carried in request message #1 may be identifier #1; and the task identifier carried in request message #2 may be identifier #2. The task identifier may also be a tag.

[0157] Exemplarily, in this embodiment, the network management unit can access multiple configuration space registers of the bus device through the request message to improve access efficiency. For ease of description, the following is an example in which the request message is also used to request access to the second configuration space register of the bus device.

[0158] Specifically, when the request message is also used to request access to the second configuration space register of the bus device, the request message also includes third indication information and information of the second configuration space register, and the third indication information is used to indicate the type of operation on the second configuration space register.

[0159] The third indication information is used to indicate the type of operation on the second configuration space register. For example, when the network management unit performs a read operation on the second configuration space register of the bus device through a request message, the third indication information is used to indicate a read operation; when the network management unit performs a write operation on the second configuration space register of the bus device through a request message, the third indication information is used to indicate a write operation.

[0160] Exemplarily, when the third indication information indicates that the operation type for the second configuration space register is a write operation, the request message may further include data to be written into the second configuration space register.

[0161] For example, the network management unit requests to write data #2 into the second configuration space register of the bus device through a request message, and the request message carries the data #2.

[0162] Exemplarily, when the third indication information indicates that the operation type for the second configuration space register is a write operation, the request message may further include fourth indication information, where the fourth indication information is used to indicate that data is written into at least one byte in the second configuration space register.

[0163] For example, the size of the second configuration space register is 4 bytes. The network management unit can request to write data #2 into two bytes in the second configuration space register of the bus device through a request message. The request message carries data #2 and fourth indication information. The fourth indication information indicates that data #2 is written into any two bytes in the second configuration space register.

[0164] Optionally, when the network management unit performs the same operation on different configuration space registers in the bus device through a request message, the first indication information and the third indication information may be the same information, and the second indication information and the fourth indication information may also be the same information.

[0165] Exemplarily, the information of the second configuration space register includes at least one of the following:

[0166] The type information of the second configuration space register, the index of the second configuration space register, or the address of the second configuration space register. The information related to the second configuration space register can refer to the above description of the information of the first configuration space register, which will not be repeated here.

[0167] Optionally, when the network management unit requests access to multiple configuration space registers of a bus device through a request message, the information for accessing the multiple configuration space registers carried in the request message constitutes multiple access requests respectively. For example, when the request message requests access to a first configuration space register and a second configuration space register, the information supporting access to the first configuration space register carried in the request message (such as the above-mentioned first indication information, the information of the first configuration space register, and the second indication information, etc.) is called access request #1, and the information supporting access to the first configuration space register carried in the request message (such as the above-mentioned third indication information, the information of the second configuration space register, and the fourth indication information, etc.) is called access request #2.

[0168] It should be understood that the above-mentioned network management unit requests access to the first configuration space register and the second configuration space register of the bus device through the request message. It is just an example that the network management unit can access multiple configuration space registers through a request message, and does not constitute any limitation on the protection scope of the present application. In this embodiment, the network management unit can request access to other configuration space registers of the bus device through the request message. For example, the request message also includes an access request #3 that supports access to the third configuration space register, which will not be repeated here.

[0169] Exemplarily, in this embodiment, the network management unit includes a processing core and a controller, and the network management unit sending a request message to the bus device includes: the controller in the network management unit sends a request message to the bus device. It should be noted that the operations performed by the network management unit in this embodiment can be implemented by system software, and the operations performed by the processing core and the controller described below can be implemented by system software.

[0170] In this embodiment, before the controller sends an access request message to the bus device, the internal message transmission of the network management unit includes the following steps:

[0171] Step 1: The processing core sends the descriptor of the request message to the DDR.

[0172] Specifically, the processing core uses the configuration space register related information of the bus device to be accessed as the descriptor of the request message, and the descriptor of the request message is carried by a send queue entry (Send Queue Entry, SQE) in the DDR.

[0173] Step 2: The processing core sends an indication message #1 to the controller. The indication message #1 is used to notify the controller that there is a task to be executed. Specifically, the indication message #1 is used to instruct the controller to obtain a descriptor of the request message from the DDR.

[0174] For example, there is an entry engine in the controller. When designing the system, an address space is reserved for the entry engine (for example, the address space required to obtain and save information such as doorbell, SQE, receive queue entry (receive QueueEntry, SQE) and complete queue entry (Complete Queue Entry, CQE)). The processing core sends a doorbell to notify the entry engine in the controller that there is a task to be executed.

[0175] Step 3: The controller obtains the descriptor of the request message from the DDR.

[0176] Specifically, the ingress engine in the controller obtains the descriptor of the request message from the DDR. For example, the ingress engine in the controller reads the SQE in the DDR and obtains the descriptor of the request message from the SQE.

[0177] Step 4: The controller generates a request message.

[0178] In this embodiment, after the inlet engine in the controller obtains the descriptor of the request message, it encapsulates the descriptor of the request message into a request message on the device bus. The description of the request message can refer to the description of the request message in the above step S810, which will not be repeated here.

[0179] In this embodiment, the processing core is supported to continuously issue multiple descriptor tasks, and multiple software and hardware interface queues are also supported in the controller. Both the controller and the bus device support the sending and receiving of multiple request messages to improve performance.

[0180] Furthermore, in this embodiment, after receiving the access request message, the bus device parses and executes the corresponding operation request and returns an access response message. Figure 8 The method shown also includes:

[0181] S820, the bus device sends a response message to the network management unit, or the network management unit receives a response message from the bus device.

[0182] Specifically, the response message carries a task identifier. The bus device carries the task identifier in the response message, so that the network management unit can determine whether the response message is a message in response to a request message according to the task identifier carried in the response message.

[0183] For example, the task identifier carried in the request message #1 sent by the network management unit to the bus device #1 is identifier #1; the task identifier carried in the request message #2 sent by the network management unit to the bus device #2 is identifier #2. After receiving the request message #1, the bus device #1 can send a response message #1 in response to the request message #1 to the network management unit, and the response message #1 carries identifier #1, and identifier #1 is used to indicate that the response message #1 is a message in response to the request message #1;

[0184] Similarly, after receiving request message #2, bus device #2 can send response message #2 in response to request message #2 to the network management unit, and the response message #2 carries identifier #2, which is used to indicate that response message #2 is a message in response to request message #2. Thus, the network management unit can determine that response message #1 is a message in response to request message #1 based on identifier #1 carried in response message #1, and determine that response message #2 is a message in response to request message #2 based on identifier #2 carried in response message #2.

[0185] As a possible implementation manner, the response message is used to indicate whether the operation on the configuration space register is successful.

[0186] For example, the request message requests a write operation on the first configuration space register. If the bus device successfully writes the data #1 to be written into the first configuration space register carried in the request message into the first configuration space register, the response message is used to indicate that the write operation on the first configuration space register is successful.

[0187] For example, a request message requests a write operation on a first configuration space register and a second configuration space register. If the bus device successfully writes the data #1 to be written to the first configuration space register carried in the request message into the first configuration space register, and successfully writes the data #2 to be written to the second configuration space register carried in the request message into the second configuration space register, then the response message is used to indicate that the write operation on the first configuration space register and the second configuration space register is successful.

[0188] For another example, a request message requests a write operation to a first configuration space register and a second configuration space register. If the bus device successfully writes data #1 to be written to the first configuration space register carried in the request message into the first configuration space register, and fails to write data #2 to be written to the second configuration space register carried in the request message into the second configuration space register, then the response message is used to indicate that the write operation to the first configuration space register is successful and the write operation to the second configuration space register fails (e.g., the response message includes two response fields, respectively indicating whether the operations on the two configuration space registers are successful).

[0189] It should be understood that the above is only an example of how the response message indicates whether the operation on the configuration space register is successful, and does not constitute any limitation on the scope of protection of the present application. The response message can also indicate whether the operation on different configuration space registers is successful in other ways, which will not be explained one by one here.

[0190] As another possible implementation manner, if the operation type of the configuration space register is a read operation, the response message includes information read from the configuration space register.

[0191] For example, the request message requests a read operation on a first configuration space register, and the response message includes information read from the first configuration space register.

[0192] For another example, the request message requests a read operation on the first configuration space register and the second configuration space register, and the response message includes information read from the first configuration space register and the second configuration space register.

[0193] Optionally, the response message also includes information indicating that the response message is in response to a read operation or a write operation.

[0194] Optionally, when the bus device responds to the network management unit accessing multiple configuration space registers of the bus device through a response message, there are multiple access responses in the response message. For example, when a request message requests access to a first configuration space register and a second configuration space register, and a response message responds to the request message, the response to the access to the first configuration space register in the response message is called access response #1, and the response to the access to the second configuration space register in the response message is called access response #2.

[0195] In addition, this embodiment does not limit the specific operation of the network management unit after receiving the response message. For example, after receiving the response message, the network management unit can write the information carried in the response message to the RQE, and the RQE is carried by the CQE. The controller reports an interrupt to the processing core, indicating that there is an RQE to be processed, and then the processing core reads the CQE, processes the RQE, and determines the descriptor execution status through task identification matching.

[0196] Figure 8 In the communication method shown, when the network management unit needs to access the configuration space register of the bus device, the network management unit can carry the network address of the bus device and the information of the configuration space register to be accessed in the request message to access the configuration space register of the bus device. There is no need to access through memory reading and writing. Therefore, the technical solution provides a method for accessing the configuration space register of the bus device through a request message, which can avoid the disadvantages of high latency requirements and inability to access across hosts brought about by the memory reading and writing method.

[0197] For example, when accessing the configuration space register of a bus device through a request message, the network management unit issues an access message instead of a memory access instruction, and the latency requirement is relatively low. For another example, when accessing the configuration space register of a bus device through a request message, because the bus device is routed to the bus device through the network address of the bus device, rather than the memory address of the bus device, it is not restricted by the memory address allocation in a single host, so when accessing the configuration space register of the bus device through a request message, it can be accessed across hosts.

[0198] For example, the configuration space register access of the bus device is implemented through the network address of the bus device. Compared with the memory access method introduced in the basic concepts above, it does not require hardware logic to implement the decoding logic from the memory address to the Bus number, Device number and Function number, thus reducing the consumption of hardware resources. In addition, memory access is a synchronous access. When the CPU issues an access, it is always waiting for the access to be completed. Therefore, there is a requirement for the response return time of the access, which cannot be too long, usually within 1us. Figure 8 The message access shown is an asynchronous access, that is, the CPU does not need to wait, and has low latency requirements, supporting latency of several to tens of us. Figure 8 The messages shown are more suitable for large-scale networking.

[0199] It should be noted that the above request message and response message are transaction layer messages, and the format of the transaction layer message can refer to the provisions in the current protocol (such as shown in Table 1 above), which will not be repeated here. This embodiment mainly involves the design of the message header and payload of the transaction layer message.

[0200] Combine the following Figures 9 to 12 The design of the Header and Payload parts of the transaction layer message in this embodiment is introduced in detail.

[0201] The transaction layer message consists of two parts: Header and Payload. The Header is fixed at 4 bytes in size, and the Payload is N*4 bytes in size, where N is a positive integer. Fig. 9 As shown in the figure, the transaction layer message is divided into two parts: Header and Payload.

[0202] Exemplarily, when the transaction layer message is the above-mentioned request message, the Header of the transaction layer message indicates that the transaction layer message is a message for accessing the configuration space register through a message code (Message Code) and a sub-message code (Sub-Message Code). Among them, the Sub-Message Code is optional, that is, the Header of the transaction layer message may not carry the Sub-Message Code.

[0203] The task ID is used to match the request message with the response message.

[0204] The message payload length in the header of the transaction layer message specifies the length of the message payload.

[0205] like Fig.10 As shown, the Header of the transaction layer message includes Message Code, Sub-Message Code, Task ID and Message Payload length fields.

[0206] As a possible implementation, the transaction layer message is the above request message, and the payload of the request message may include multiple access requests to access different configuration space registers of the bus device respectively. Optionally, each of the multiple access requests in the request message may occupy a fixed 4-byte size.

[0207] In this implementation, each access request structure is as follows Fig.11 As shown in the figure, the access request includes the Opcode, ByteEnable, Block type, Function Entity Index, Request Address, and Write Data fields, where the function of each field is as follows:

[0208] Opcode: describes the read or write type of the request; for example, indicating a read or write operation, which can be understood as the first indication information or the third indication information mentioned above.

[0209] It should be noted that if the read / write types requested by multiple access requests in the request message are the same, the read / write type can be indicated by the Sub-Message Code in the message header, that is, the Opcode in the access request is optional. For example, if the request message includes an access request, and the access request is used to request a read, the Sub-Message Code can be used to indicate that the read / write type is a read operation; for another example, if the request message includes multiple access requests, and the multiple access requests are all used to request a read, the Sub-Message Code can be used to indicate that the read / write type is a read operation.

[0210] Byte Enable: describes which bytes the request accesses; for example, indicating access to two bytes in the first configuration space register can be understood as the second indication information or the fourth indication information mentioned above.

[0211] Block type, Function Entity Index and Request Address: describe the device configuration space register; can be understood as the information of the first configuration space register or the second configuration space register mentioned above

[0212] Write Data: describes the data to be written. If the request message is a request to write data #1 into the first configuration space register, the access request for the first configuration space register carries the data #1.

[0213] As another possible implementation, the transaction layer message is the above-mentioned response message, and the Payload of the response message may include multiple access responses, respectively responding to the multiple access requests in the request message. Optionally, each of the multiple access responses in the response message may occupy a fixed 4-byte size.

[0214] In this implementation, each access response structure is as follows Fig.12 As shown, the access response includes the Opcode, Status, and Read Data fields, where the function of each field is as follows:

[0215] Opcode: describes the read or write type of the request to which the response corresponds. For example, if access request #1 in the request message is a read operation request, then access response #1 in the response message in response to access request #1 is a read operation response.

[0216] Status: describes the execution status of the request corresponding to the response; for example, indicates whether the operation is successful.

[0217] Read Data: describes the read data of the response request. If the access request #1 in the request message is a read operation request, the access response #1 in the response message that responds to the access request #1 carries the read data.

[0218] In this embodiment, the access request message and the access response message correspond one to one.

[0219] It should be understood that the Figure 8 The specific examples shown are only to help those skilled in the art better understand the embodiments of the present application, and are not intended to limit the scope of the embodiments of the present application. It should also be understood that the sequence numbers of the above-mentioned processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0220] It should also be understood that in the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between different embodiments are consistent and can be referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0221] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of the method. In order to realize the above functions, it includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0222] The following, combined Figures 13 to 15 The communication device provided in the embodiment of the present application is described in detail. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, so the contents not described in detail can be referred to the method embodiment above, and some contents will not be repeated for the sake of brevity.

[0223] The embodiment of the present application can divide the functional modules of the transmitting end device or the receiving end device according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. There may be other division methods in actual implementation. The following is an example of dividing each functional module corresponding to each function.

[0224] Fig.13 A schematic structural diagram of a communication device 1300 provided in an embodiment of the present application is shown.

[0225] In one example, the communication device 1300 may be the above-mentioned network management unit, and the communication device 1300 may be used to execute the above-mentioned communication method, for example, to execute Figure 8 The communication device 1300 may include a transceiver unit 1310 and a processing unit 1320 .

[0226] The transceiver unit 1310 is used to send a request message to a bus device, wherein the request message is used to request access to a first configuration space register of the bus device, wherein the request message includes a network address of the bus device, first indication information, and information of the first configuration space register, wherein the network address is an address assigned to the bus device by a network management unit, and the first indication information is used to indicate an operation type on the first configuration space register. The transceiver unit 1310 is used to receive a response message from the bus device in response to the request message.

[0227] As an example, combining Figure 8 The transceiver unit 1310 may be configured to execute S810 and S820.

[0228] In another example, the communication device 1300 may be the above-mentioned bus device, and the communication device 1300 may be used to execute the above-mentioned communication method, for example, to execute Figure 8 The method shown.

[0229] The transceiver unit 1310 is configured to receive a request message from a network management unit, wherein the request message is used to request access to a first configuration space register of a bus device, wherein the request message includes a network address of the bus device, first indication information, and information of the first configuration space register, wherein the network address is an address assigned by the network management unit to the bus device, and the first indication information is used to indicate an operation type on the first configuration space register. The transceiver unit 1310 is configured to send a response message in response to the request message to the network management unit.

[0230] As an example, combining Figure 8 The transceiver unit 1310 may be configured to execute S810 and S820.

[0231] The present application embodiment also provides a chip system 1400, such as Fig.14 As shown, the chip system 1400 includes at least one processor and at least one interface circuit. As an example, when the chip system 1400 includes a processor and an interface circuit, the processor may be Fig.14 The processor 1410 shown in the solid line frame (or the processor 1410 shown in the dotted line frame) may be Fig.14 The interface circuit 1420 is shown in the solid line box (or the interface circuit 1420 is shown in the dotted line box).

[0232] When the chip system 1400 includes two processors and two interface circuits, the two processors include Fig.14 The processor 1410 shown in the solid line frame and the processor 1410 shown in the dotted line frame, the two interface circuits include Fig.14 The interface circuit 1420 shown in the solid line frame and the interface circuit 1420 shown in the dotted line frame. This is not limited. The processor 1410 and the interface circuit 1420 can be interconnected through a line. For example, the interface circuit 1420 can be used to receive a signal (such as an instruction stored in a memory). For another example, the interface circuit 1420 can be used to send a signal to another device (such as the processor 1410).

[0233] Exemplarily, the interface circuit 1420 may read the instruction stored in the memory and send the instruction to the processor 1410. When the instruction is executed by the processor 1410, the communication device or the device accessing the memory may perform the various steps in the above embodiments. Of course, the chip system 1400 may also include other discrete devices, which are not specifically limited in the embodiments of the present application.

[0234] Another embodiment of the present application further provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a communication device, the communication device executes each step performed by the communication device in the method flow shown in the above method embodiment. In some embodiments, the disclosed method can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or products.

[0235] Fig.15 A conceptual partial view of a computer program product provided by an embodiment of the present application is schematically shown, where the computer program product includes a computer program for executing a computer process on a computing device.

[0236] In one embodiment, the computer program product is provided using a signal bearing medium 1000. The signal bearing medium 1500 may include one or more program instructions, which when executed by one or more processors may provide the above-mentioned Figure 8 Thus, for example, reference to Figure 8 One or more of the features may be borne by one or more instructions associated with the signal bearing medium 1500. In addition, Fig.15 The program instructions in also describe example instructions.

[0237] In some examples, the signal bearing medium 1500 may include a computer readable medium 1501, such as, but not limited to, a hard drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), and the like.

[0238] In some implementations, signal bearing medium 1500 may include computer recordable medium 1502 such as, but not limited to, memory, read / write (R / W) CD, R / W DVD, and the like.

[0239] In some embodiments, the signal bearing medium 1500 may include a communication medium 1503, such as, but not limited to, a digital and / or analog communication medium (e.g., a fiber optic cable, a waveguide, a wired communication link, a wireless communication link, etc.). The signal bearing medium 1500 may be communicated by a wireless form of the communication medium 1503 (e.g., a wireless communication medium complying with the IEEE 1502.11 standard or other transmission protocol). The one or more program instructions may be, for example, computer executable instructions or logic implementation instructions.

[0240] In some examples, such as for Figure 8 The illustrated communication device may be configured to provide various operations, functions, or actions in response to one or more program instructions via computer-readable medium 1501 , computer-recordable medium 1502 , and / or communication medium 1503 .

[0241] It should be understood that the arrangement described here is only for illustrative purposes. Thus, it will be appreciated by those skilled in the art that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and functional groups, etc.) can be used instead, and some elements can be omitted together according to the desired result. In addition, many of the described elements can be implemented as discrete or distributed components, or in any appropriate combination and position to combine other components to implement functional entities.

[0242] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer executes the instructions on the computer and when the computer executes the instructions, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices.

[0243] Computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media integrated therein. Available media can be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid state drives (SSDs)).

[0244] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A communication method, characterized in that: Applied to a bus network, the method comprises: Sending a request message to a bus device, the request message being used to request access to a first configuration space register of the bus device, the request message including a network address of the bus device, first indication information, and information of the first configuration space register, the network address being an address assigned to the bus device by a network management unit, and the first indication information being used to indicate a type of operation on the first configuration space register; A response message is received from the bus device in response to the request message.

2. The method according to claim 1, characterized in that The request message also includes a task identifier, and the response message includes the task identifier, and the task identifier is used to determine that the response message is a message in response to the request message.

3. The method according to claim 1 or 2, characterized in that: The operation type of the first configuration space register includes: a read operation or a write operation.

4. The method according to claim 3, characterized in that If the operation type of the first configuration space register is a write operation, the request message also includes data to be written into the first configuration space register.

5. The method according to claim 4, characterized in that The request message also includes second indication information, where the second indication information is used to indicate that the data is written into at least one byte in the first configuration space register.

6. The method according to any one of claims 1 to 5, characterized in that The information of the first configuration space register includes at least one of the following: The type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

7. The method according to any one of claims 1 to 6, characterized in that The response message is used to indicate whether the operation on the first configuration space register is successful; or, If the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

8. The method according to any one of claims 1 to 7, characterized in that The response message also includes information indicating that the response message is in response to a read operation or a write operation.

9. The method according to any one of claims 1 to 8, characterized in that The request message is also used to request access to a second configuration space register of the bus device. The request message also includes third indication information and information of the second configuration space register. The third indication information is used to indicate a type of operation on the second configuration space register.

10. The method according to any one of claims 1 to 9, characterized in that The bus network includes a network management unit and a plurality of bus devices, and the bus device is any one of the plurality of bus devices.

11. A communication method, characterized in that: Applied to a bus network, the method comprises: receiving a request message from a network management unit, the request message being used to request access to a first configuration space register of a bus device, the request message comprising a network address of the bus device, first indication information, and information of the first configuration space register, the network address being an address allocated by the network management unit to the bus device, and the first indication information being used to indicate a type of operation on the first configuration space register; A response message in response to the request message is sent to the network management unit.

12. The method according to claim 11, characterized in that The request message also includes a task identifier, and the response message includes the task identifier, and the task identifier is used to determine that the response message is a message in response to the request message.

13. The method according to claim 11 or 12, characterized in that: The operation type of the first configuration space register includes: a read operation or a write operation.

14. The method according to claim 13, characterized in that If the operation type of the first configuration space register is a write operation, the request message also includes data to be written into the first configuration space register.

15. The method according to claim 14, characterized in that The request message also includes second indication information, where the second indication information is used to indicate that the data is written into at least one byte in the first configuration space register.

16. The method according to any one of claims 11 to 15, characterized in that The information of the first configuration space register includes at least one of the following: The type information of the first configuration space register, the index of the first configuration space register, or the address of the first configuration space register.

17. The method according to any one of claims 11 to 16, characterized in that The response message is used to indicate whether the operation on the first configuration space register is successful; or, If the operation type of the first configuration space register is a read operation, the response message includes information read from the first configuration space register.

18. The method according to any one of claims 11 to 17, characterized in that The response message also includes information indicating that the response message is in response to a read operation or a write operation.

19. The method according to any one of claims 11 to 18, characterized in that The request message is also used to request access to a second configuration space register of the bus device. The request message also includes third indication information and information of the second configuration space register. The third indication information is used to indicate a type of operation on the second configuration space register.

20. The method according to any one of claims 11 to 19, characterized in that The bus network includes the network management unit and a plurality of bus devices, and the bus device is any one of the plurality of bus devices.

21. A communication method, characterized in that: Applied to a bus network, the method comprises: The network management unit sends a request message to the bus device, the request message is used to request access to a first configuration space register of the bus device, the request message includes a network address of the bus device, first indication information and information of the first configuration space register, the network address is an address allocated by the network management unit to the bus device, and the first indication information is used to indicate an operation type on the first configuration space register; The bus device sends a response message in response to the request message to the network management unit.

22. A communication system, characterized in that: Including network management unit and bus equipment, The network management unit is used to send a request message to the bus device, wherein the request message is used to request access to a first configuration space register of the bus device, and the request message includes a network address of the bus device, first indication information, and information of the first configuration space register, wherein the network address is an address allocated by the network management unit to the bus device, and the first indication information is used to indicate a type of operation on the first configuration space register; The bus device is used to send a response message in response to the request message to the network management unit.

23. A communication device, characterized in that: include: A processor, configured to read instructions stored in a memory, wherein when the processor executes the instructions, the communication device implements the method described in any one of claims 1 to 10; or, the communication device implements the method described in any one of claims 11 to 20.

24. A chip, characterized in that: include: at least one processing core for executing the method according to any one of claims 1 to 10; Or, used to perform the method as claimed in any one of claims 11 to 20.

25. A computer system, characterized in that: include: A chip as claimed in claim 24.

26. A computer program product, characterized in that The computer program product comprises a computer program code, and when the computer program code is run on a computer, the method of any one of claims 1 to 10 is executed; or when the computer program code is run on a computer, the method of any one of claims 11 to 20 is executed.

27. A computer-readable storage medium, characterized in that: Comprising a computer program, which, when running on a computer system, causes a processing module in the computer system to execute a method as described in any one of claims 1 to 10; or, when running on a computer system, causes a processing module in the computer system to execute a method as described in any one of claims 11 to 20.

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