Method for simulating watchdog by universal timer
By initializing the timer in the first processor core of the multi-core processor and monitoring its overflow, the problem of limited number of watchdog timers in the prior art is solved, and real-time status monitoring and exceptions of a single processor core are realized Recovery improves the reliability of multi-core processors.
Patent Information
- Application Number
- CN202411286284.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-02-18
AI Technical Summary
The number of watchdog timers in existing multi-core processors is limited, and the status monitoring of a single processor core cannot be monitored, resulting in the inability to detect the working status of the processor core in real time.
When the first processor core of the multi-core processor is started and run, the timer corresponding to the processor core is initialized, the timer is the first time, and the timer is executed every second time (the second time is less than the first time). Clear operation. By monitoring whether the timer overflows, detect whether the processor core is working properly, and perform reset operations by monitoring the kernel when overflows.
Without adding a watchdog timer, real-time monitoring of the working status of a single processor core is achieved, the reliability of multi-core processors is improved, and the processor core can restore normal working status in abnormal situations.
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Figure CN119473670A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of multi-core processors, and in particular to a method for simulating a watchdog using a general timer. Background Art
[0002] The multi-core processor includes a plurality of processor cores arranged in an array. During the operation of the multi-core processor, the working state of the multi-core processor can be monitored by a watchdog timer (WDT).
[0003] In the related art, during the operation of the multi-core processor, a dog feeding signal is output to the watchdog timer at regular intervals, and the watchdog timer is reset according to the dog feeding signal. If the dog feeding signal is not output within the specified time, the watchdog timer will trigger the multi-core processor to reset.
[0004] In the related art, since the number of watchdog timers is limited, it can only monitor the status of the entire multi-core processor, but cannot monitor the status of a single processor core in the multi-core processor. Summary of the invention
[0005] The present application proposes a method for simulating a watchdog using a general timer.
[0006] In a first aspect, an embodiment of the present application provides a method for simulating a watchdog with a general timer, which is applied to a multi-core processor, wherein the multi-core processor includes at least two processor cores, and the method includes: when a first processor core among the at least two processor cores starts running, initializing a timer corresponding to the first processor core, wherein the timing duration of the timer corresponding to the first processor core is a first duration; performing a clearing operation on the timer corresponding to the first processor core every second duration, wherein the second duration is less than the first duration; if the timer corresponding to the first processor core overflows, the monitoring core performs a reset operation on the first processor core.
[0007] In a second aspect, an embodiment of the present application provides a device for simulating a watchdog with a general timer, the device comprising: a timer initialization module, for initializing a timer corresponding to a first processor core when a first processor core among at least two processor cores starts running, the timing duration of the timer corresponding to the first processor core being a first duration; a clearing module, for performing a clearing operation on the timer corresponding to the first processor core every second duration, the second duration being less than the first duration; and a reset module, for causing the monitoring core to perform a reset operation on the first processor core if the timer corresponding to the first processor core overflows.
[0008] In a third aspect, an embodiment of the present application provides a multi-core processor, which is configured to execute the method of simulating a watchdog with a general timer as in the first aspect.
[0009] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising a multi-core processor as in the third aspect.
[0010] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer program instructions are stored. The computer program instructions can be called by a processor to execute the method of the first aspect.
[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, which, when instructions in the computer program product are executed, is used to implement the method of the first aspect.
[0012] Compared with the prior art, the technical solution provided by the embodiment of the present application is that when the first processor core in the multi-core processor starts to run, the timer corresponding to the first processor core is initialized, the timing duration of the timer corresponding to the first processor core is the first duration, and the first processor core performs a clearing operation on the timer every second duration. Since the first duration is greater than the second duration, the timer corresponding to the first processor core will not overflow when the first processor core works normally. Therefore, by monitoring whether the timer corresponding to the first processor core overflows, it is possible to detect whether the first processor core works normally. Without adding a watchdog, a watchdog is simulated by a timer to achieve real-time monitoring of the working status of the first processor core. When the timer corresponding to the first processor core overflows, it is determined that the first processor core is in an abnormal working state. At this time, the monitoring core performs a reset operation on the first processor core, so that the first processor core can resume a normal working state, thereby improving the reliability of the multi-core processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0014] Figure 1 It is a schematic diagram of the implementation environment provided by the embodiment of the present application.
[0015] Figure 2 This is a flow chart of a method for simulating a watchdog using a universal timer provided by an embodiment of the present application.
[0016] Figure 3 This is a flow chart of a method for simulating a watchdog using a universal timer provided in another embodiment of the present application.
[0017] Figure 4This is a flow chart of a method for simulating a watchdog using a universal timer provided in another embodiment of the present application.
[0018] Figure 5 It is a block diagram of a device for simulating a watchdog using a universal timer provided in one embodiment of the present application.
[0019] Figure 6 It is a structural block diagram of an electronic device provided by an embodiment of the present application.
[0020] Figure 7 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION
[0021] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0022] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.
[0023] In view of the technical problem that the number of watchdogs corresponding to a multi-core processor in the related art is insufficient, resulting in the inability to monitor the status of a single processor core in the multi-core processor, the inventor of the present application has designed a new technical solution. When the first processor core in the multi-core processor starts running, the timer corresponding to the first processor core is initialized, the timing duration of the timer corresponding to the first processor core is a first duration, and the first processor core performs a clearing operation on the timer every second duration. Since the first duration is greater than the second duration, the timer corresponding to the first processor core will not overflow when the first processor core works normally. Therefore, by monitoring whether the timer corresponding to the first processor core overflows, it is possible to detect whether the first processor core works normally. Without adding a watchdog, a watchdog is simulated by a timer to achieve real-time monitoring of the working status of the first processor core. When the timer corresponding to the first processor core overflows, it is determined that the first processor core is in an abnormal working state. At this time, the monitoring core performs a reset operation on the first processor core, so that the first processor core can resume a normal working state, thereby improving the reliability of the multi-core processor.
[0024] Please refer to Figure 1 , which shows a schematic diagram of an implementation environment provided by an embodiment of the present application. The implementation environment includes a multi-core processor 100.
[0025] The multi-core processor 100 includes at least two processor cores arranged in an array, such as four, eight, etc. Among the at least two processor cores, there is a processor master core, and the rest are processor slave cores.
[0026] In an embodiment of the present application, each processor core corresponds to a timer. When the processor core starts running, the timer can be initialized and the timing duration of the timer can be set to a first duration. During the operation of the processor core, the timer is cleared every second duration. The first duration is greater than the second duration. Therefore, when the processor core is working normally, the timer usually does not overflow. When the processor core is in an abnormal working state, the timer cannot usually be cleared in time. At this time, the timer overflows. Therefore, by monitoring whether the timer corresponding to the first processor core overflows, it is possible to accurately determine whether the first processor core is working normally. Without adding a watchdog timer, real-time monitoring of the working status of a single processor core can be achieved. When the timer corresponding to the first processor core overflows, a reset operation is performed on the first processor core. The processor core can be restored to a normal working state through the reset operation.
[0027] In this embodiment, the multi-core processor 100 includes a reset control register. The reset control register includes control bits corresponding to at least two processor cores, respectively. The control bits corresponding to the processor cores are used to control the processor cores to be in a power-on state or a power-off state. By outputting a signal to the control bits corresponding to the processor cores, the processor cores can be switched between the power-on state and the power-off state, thereby implementing a reset operation on the processor cores.
[0028] In some embodiments, the multi-core processor 100 further includes a watchdog, which is used to monitor the status of a processor core (such as a processor main core).
[0029] Please refer to Figure 2 , which shows a flow chart of a method for simulating a watchdog using a universal timer provided by an embodiment of the present application. The method may include the following process.
[0030] S201, when a first processor core among at least two processor cores starts to run, initialize a timer corresponding to the first processor core.
[0031] The first processor core may be any one of the at least two processor cores. The timing duration of the timer corresponding to the first processor core is the first duration. The first duration may be set based on experiments or experience, and the embodiment of the present application does not limit this, for example, 3 seconds.
[0032] Initializing the timer corresponding to the first processor core includes: setting the working mode of the timer corresponding to the first processor core, setting the timing duration corresponding to the first processor core, enabling the timer corresponding to the first processor core, etc. After initializing the timer corresponding to the first processor core, the timer corresponding to the first processor core starts counting, and during the counting process, monitors whether it overflows in real time. Wherein, timer overflow means that the count value of the timer is greater than the first duration.
[0033] S202: Perform a clearing operation on the timer corresponding to the first processor core at second intervals.
[0034] The second duration is less than the first duration. The clearing operation refers to updating the count value of the timer corresponding to the first processor core to the initial value, after which the timer corresponding to the first processor core restarts counting. Since the second duration is less than the first duration, when the first processor core works normally, the timer corresponding to the first processor core will never overflow.
[0035] In some embodiments, the first processor core may perform a clearing operation on a timer corresponding to the first processor core through a monitor thread. In some embodiments, the first processor core may perform a clearing operation on a timer corresponding to the first processor core through an idle thread.
[0036] S203: If the timer corresponding to the first processor core overflows, the monitoring core performs a reset operation on the first processor core.
[0037] If the first processor core fails to perform a clearing operation on the timer in time, the timer corresponding to the first processor core overflows, and the first processor core is likely to be in an abnormal working state, so a reset operation needs to be performed on it so that the first processor core can resume a normal working state. The reset operation refers to an operation of restarting or reinitializing the first processor core.
[0038] After the first processor core is reset, the first processor core reinitializes the timer corresponding to the first processor core, and clears the timer corresponding to the first processor core every second time period.
[0039] If the timer corresponding to the first processor core has not overflowed, the first processor core continues to execute S202.
[0040] To summarize, the technical solution provided by the embodiment of the present application is that when the first processor core in a multi-core processor starts running, the timer corresponding to the first processor core is initialized, the timing duration of the timer corresponding to the first processor core is a first duration, and the first processor core performs a clearing operation on the timer every second duration. Since the first duration is greater than the second duration, the timer corresponding to the first processor core will not overflow when the first processor core is working normally. Therefore, by monitoring whether the timer corresponding to the first processor core overflows, it is possible to detect whether the first processor core is working normally. Without adding a watchdog, a watchdog is simulated by a timer to achieve real-time monitoring of the working status of the first processor core. When the timer corresponding to the first processor core overflows, it is determined that the first processor core is in an abnormal working state. At this time, the monitoring core performs a reset operation on the first processor core, so that the first processor core can resume a normal working state, thereby improving the reliability of the multi-core processor.
[0041] Please refer to Figure 3 , which shows a flow chart of a method for simulating a watchdog using a universal timer provided in another embodiment of the present application. The method includes the following process.
[0042] S301 , when a first processor core among at least two processor cores starts to run, initialize a timer corresponding to the first processor core.
[0043] The timing duration of the timer corresponding to the first processor core is the first duration.
[0044] S302: Register the timer corresponding to the first processor core with the interrupt processing function of the second processor core.
[0045] The interrupt handling function is a predefined function for handling interrupt requests. Registering the interrupt handling function means registering the interrupt event of the timer overflow corresponding to the first processor core into the interrupt handling table. In this way, when the timer corresponding to the first processor core overflows, the second processor core will transfer from the current process to the interrupt handling function and perform the corresponding interrupt handling operation.
[0046] The second processor core and the first processor core may be the same processor core or different processor cores. In the case where the second processor core and the first processor core are different processor cores, the second processor core may be a processor master core or a processor slave core among the at least two processor cores, which is not limited in the embodiments of the present application.
[0047] In some embodiments, S302 may be implemented as: registering the timer corresponding to the first processor core with the interrupt processing function of the processor master core. In this way, each processor core may register its own timer with the interrupt processing function of the processor master core, so that the processor master core can uniformly manage the timers of each processor slave core.
[0048] In some other embodiments, S302 may be implemented as: registering the timer corresponding to the first processor core with the interrupt processing function of the processor slave core.
[0049] The first processor core may randomly select a processor slave core, or select a processor slave core according to a preset screening rule, and then register an interrupt processing function of the selected processor slave core.
[0050] The preset screening rule may be at least one of the following: the utilization of the processor core, the priority of the thread executed by the processor core. For example, the first processor core may select the processor core with the lowest utilization as the second processor core, or the first processor core may select the processor core with a utilization less than the first preset utilization as the second processor core. For another example, the first processor core may select the processor core with the lowest priority of the executed thread as the second processor core, or the first processor core may select the processor core with the priority of the executed thread less than the first preset priority as the second processor core. The first preset utilization and the first preset priority are set according to actual needs, and the embodiments of the present application are not limited thereto.
[0051] When the second processor core is not the main processor core, the first processor core first detects whether the second processor core is in a dormant state; if the second processor core is not in a dormant state, the step of registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core is executed.
[0052] Since when the second processor core is in a sleep state, it is usually necessary to wake up the second processor core first, resulting in a long time required to register the timer corresponding to the first processor core with the interrupt processing function of the processor slave core. Therefore, when the second processor core is not in a sleep state, the first processor core executes subsequent steps of registering the interrupt processing function, and when the second processor core is in a sleep state, the first processor core reselects a new second processor core to reduce the time required to register the interrupt processing function.
[0053] In some embodiments, the first processor core may register the timer corresponding to the first processor core with the interrupt processing function of the processor slave core when the utilization rate of the processor master core is greater than the second preset utilization rate, otherwise, register the timer corresponding to the first processor core with the interrupt processing function of the processor master core. The second preset utilization rate is set based on experiments or experience, and the embodiments of the present application are not limited to this. In this way, it can be avoided that when the processor master core is in a busy running state, it is disturbed by the first processor core in an abnormal working state.
[0054] In other embodiments, the first processor core may register the timer corresponding to the first processor core with the interrupt processing function of the processor slave core when the priority of the thread executed by the processor master core is greater than the second preset priority, otherwise, register the timer corresponding to the first processor core with the interrupt processing function of the processor master core. The preset priority is set based on experiments or experience. In this way, when the processor master core runs a thread with a higher priority, it can be avoided that the first processor core is disturbed when it is in an abnormal working state.
[0055] S303: Perform a clearing operation on the timer corresponding to the first processor core at second intervals.
[0056] The second duration is less than the first duration.
[0057] S304: If the timer corresponding to the first processor core overflows, the interrupt processing function of the second processor core generates an interrupt signal.
[0058] When the timer corresponding to the first processor core overflows, the relevant parameters of this interrupt event are transferred to the interrupt processing function of the second processor core, and the interrupt processing function generates an interrupt signal.
[0059] S305: The monitoring core performs a reset operation on the first processor core based on the interrupt signal.
[0060] The monitoring core is also the second processor core. The second processor core pauses its currently executed thread based on the interrupt signal and performs a reset operation on the first processor core.
[0061] When there are multiple timers corresponding to the first processor core registered with the interrupt handling function of the second processor core, the second processor core may determine the corresponding first processor core based on the interrupt bit in the interrupt signal, and then perform a reset operation on the determined first processor core.
[0062] Optionally, the second processor core first sends a first signal to the control terminal corresponding to the first processor core in the reset control register, and then sends a second signal to the control terminal corresponding to the first processor core in the reset control register. The reset control register controls the first processor core to switch to a power-off state according to the first signal, and controls the first processor core to enter a power-on state according to the second signal, thereby implementing a reset operation on the first processor core. The levels of the first signal and the second signal are different. Exemplarily, the level of the first signal is less than the level of the second signal.
[0063] To summarize, the technical solution provided by the embodiment of the present application registers the timer corresponding to the first processor core with the interrupt handling function of the second processor core. When the timer corresponding to the first processor core overflows, the interrupt handling function of the second processor core can generate an interrupt signal and perform a reset operation on the first processor core according to the interrupt signal, so that the first processor core can resume normal working state and improve the reliability of the multi-core processor.
[0064] Please refer to Figure 4 , which shows a flow chart of a method for simulating a watchdog using a universal timer provided by an embodiment of the present application. The method includes the following process.
[0065] S401: When a first processor core among at least two processor cores starts to run, detecting whether a watchdog corresponding to the first processor core exists in the multi-core processor.
[0066] S402: If the multi-core processor does not have a watchdog corresponding to the first processor core, initialize a timer corresponding to the first processor core.
[0067] The timing duration of the timer corresponding to the first processor core is the first duration.
[0068] If the multi-core processor has a watchdog corresponding to the first processor core, the watchdog is used to monitor the state of the first processor core during operation of the first processor core, and when the first processor core is detected to be in an abnormal working state, the watchdog is used to reset the first processor core. In this way, the multi-core processor can be prevented from starting execution from the step of initializing the timer corresponding to the first processor core when the watchdog corresponding to the first processor core exists, thereby saving processing resources of the multi-core processor.
[0069] S403: Clear the timer corresponding to the first processor core at a second time interval, where the second time interval is shorter than the first time interval.
[0070] S404: If the timer corresponding to the first processor core overflows, the monitoring core performs a reset operation on the first processor core.
[0071] To sum up, the technical solution provided in the embodiment of the present application also detects whether there is a watchdog corresponding to the first processor core in the multi-core processor when the first processor core starts running. If there is a watchdog corresponding to the first processor core, the status of the first processor core is monitored through the watchdog. If there is no watchdog corresponding to the first processor core, the status of the first processor core is monitored by monitoring whether the timer overflows, which can save processing resources of the multi-core processor.
[0072] Please refer to Figure 5 , which shows a structural block diagram of a device for simulating a watchdog using a universal timer according to an embodiment of the present application. The device comprises: a timer initialization module 510 , a clearing module 520 and a reset module 530 .
[0073] The timer initialization module 510 is used to initialize the timer corresponding to the first processor core when the first processor core among the at least two processor cores starts to run, and the timing duration of the timer corresponding to the first processor core is a first duration.
[0074] The clearing module 520 is configured to perform a clearing operation on the timer corresponding to the first processor core every second time period, where the second time period is less than the first time period.
[0075] The reset module 530 is configured to enable the monitoring core to perform a reset operation on the first processor core if the timer corresponding to the first processor core overflows.
[0076] In some embodiments, the device further includes: an interrupt registration module (not shown in the figure). The interrupt registration module is used to register the timer corresponding to the first processor core with the interrupt processing function of the second processor core. A reset module 530 is used to generate an interrupt signal in the interrupt processing function of the second processor core if the timer corresponding to the first processor core overflows; and the monitoring core performs a reset operation on the first processor core based on the interrupt signal.
[0077] In some embodiments, the interrupt registration module is used to detect whether the second processor core is in a sleep state when the second processor core is not the main processor core among at least two processor cores; if the second processor core is not in a sleep state, the step of registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core is executed.
[0078] In some embodiments, the interrupt registration module is used to register the timer corresponding to the first processor core with the interrupt processing function of the processor main core in at least two processor cores.
[0079] In some embodiments, the reset module 530 is used to send a first signal to a control bit in a reset control register corresponding to the first processor core, and then send a second signal to a control bit in the reset control register corresponding to the first processor core to implement a reset operation on the first processor core; the reset control register is used to control the first processor core to switch to a power-off state according to the first signal, and to control the first processor core to switch to a power-on state according to the second signal, and the level of the first signal is different from the level of the second signal.
[0080] In some embodiments, the timer initialization module 510 is used to detect whether there is a watchdog corresponding to the first processor core in the multi-core processor when the first processor core among the at least two processor cores starts running; if there is no watchdog corresponding to the first processor core in the multi-core processor, the timer corresponding to the first processor core is initialized.
[0081] To summarize, the technical solution provided by the embodiment of the present application is that when the first processor core in a multi-core processor starts running, the timer corresponding to the first processor core is initialized, the timing duration of the timer corresponding to the first processor core is a first duration, and the first processor core performs a clearing operation on the timer every second duration. Since the first duration is greater than the second duration, the timer corresponding to the first processor core will not overflow when the first processor core is working normally. Therefore, by monitoring whether the timer corresponding to the first processor core overflows, it is possible to detect whether the first processor core is working normally. Without adding a watchdog, a watchdog is simulated by a timer to achieve real-time monitoring of the working status of the first processor core. When the timer corresponding to the first processor core overflows, it is determined that the first processor core is in an abnormal working state. At this time, the monitoring core performs a reset operation on the first processor core, so that the first processor core can resume a normal working state, thereby improving the reliability of the multi-core processor.
[0082] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0083] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.
[0084] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.
[0085] See also Figure 6 The embodiment of the present application further provides an electronic device 600, which includes: one or more multi-core processors 610, a memory 620, and one or more applications. Among them, the one or more applications are stored in the memory 620 and are configured to be executed by the one or more multi-core processors 610, and the one or more applications are configured to execute the method described in the above embodiment.
[0086] The multi-core processor 610 may include one or more processing cores. The multi-core processor 610 uses various interfaces and lines to connect various parts of the entire battery management system, and executes various functions and processes data of the battery management system by running or executing instructions, programs, code sets or instruction sets stored in the memory 620, and calling data stored in the memory 620. Optionally, the multi-core processor 610 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The multi-core processor 610 can integrate one or more combinations of a central multi-core processor 610 (Central Processing Unit, CPU), an image multi-core processor 610 (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the multi-core processor 610, and may be implemented separately through a communication chip.
[0087] The memory 620 may include a random access memory 620 (Random Access Memory, RAM), and may also include a read-only memory 620 (Read-Only Memory). The memory 620 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 620 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the various method embodiments described below, etc. The data storage area may also store data created by the electronic device during use (such as a phone book, audio and video data, chat record data), etc.
[0088] See also Figure 7The embodiment of the present application also provides a computer-readable storage medium 700, in which computer program instructions 710 are stored. The computer program instructions 710 can be called by a processor to execute the method described in the above embodiment.
[0089] The computer-readable storage medium 700 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium 700 includes a non-transitory computer-readable storage medium. The computer-readable storage medium 700 has storage space for computer program instructions 710 for executing any method steps in the above method. These computer program instructions 710 may be read from or written to one or more computer program products. The computer program instructions 710 may be compressed in an appropriate form.
[0090] The above are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technical personnel in the field can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present application. However, any brief modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.
Claims
1. A method for simulating a watchdog using a general timer, characterized in that: Applied to a multi-core processor, the multi-core processor includes at least two processor cores, the method includes: When a first processor core among the at least two processor cores starts running, initializing a timer corresponding to the first processor core, wherein the timing duration of the timer corresponding to the first processor core is a first duration; performing a clearing operation on a timer corresponding to the first processor core at intervals of a second time period, wherein the second time period is less than the first time period; If the timer corresponding to the first processor core overflows, the monitoring core performs a reset operation on the first processor core.
2. The method according to claim 1, characterized in that After the timer corresponding to the first processor core is initialized, the method further includes: Registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core; If the timer corresponding to the first processor core overflows, the monitoring core performs a reset operation on the first processor core, including: If the timer corresponding to the first processor core overflows, the interrupt processing function of the second processor core generates an interrupt signal; The monitoring core performs a reset operation on the first processor core based on the interrupt signal.
3. The method according to claim 2, characterized in that The registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core includes: In a case where the second processor core is not a processor master core among the at least two processor cores, detecting whether the second processor core is in a dormant state; If the second processor core is not in the sleep state, the step of registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core is performed.
4. The method according to claim 2, characterized in that: The registering the timer corresponding to the first processor core with the interrupt processing function of the second processor core includes: The timer corresponding to the first processor core is registered with an interrupt processing function of a processor main core in at least two of the processor cores.
5. The method according to claim 2, characterized in that: The multi-core processor includes a reset control register, and the monitoring core performs a reset operation on the first processor core based on the interrupt signal, including: The monitoring core sends a first signal to a control bit in the reset control register corresponding to the first processor core, and then sends a second signal to a control bit in the reset control register corresponding to the first processor core, so as to implement a reset operation on the first processor core; The reset control register is used to control the first processor core to switch to a power-off state according to the first signal, and to control the first processor core to switch to a power-on state according to the second signal, and the level of the first signal is different from the level of the second signal.
6. The method according to any one of claims 1 to 5, characterized in that Initializing a timer corresponding to a first processor core among the at least two processor cores when the first processor core starts running includes: When a first processor core among the at least two processor cores starts to run, detecting whether the multi-core processor has a watchdog timer corresponding to the first processor core; If the multi-core processor does not have a watchdog timer corresponding to the first processor core, the timer corresponding to the first processor core is initialized.
7. A device for simulating a watchdog using a general timer, characterized in that: The device comprises: a timer initialization module, configured to initialize a timer corresponding to a first processor core among the at least two processor cores when the first processor core starts running, wherein the timing duration of the timer corresponding to the first processor core is a first duration; a clearing module, configured to perform a clearing operation on the timer corresponding to the first processor core at intervals of a second time period, wherein the second time period is less than the first time period; The reset module is used for, if the timer corresponding to the first processor core overflows, allowing the monitoring core to perform a reset operation on the first processor core.
8. A multi-core processor, characterized in that: The multi-core processor is configured to execute the method for simulating a watchdog using a general timer as claimed in any one of claims 1 to 6.
9. An electronic device, characterized in that: include: The multi-core processor as claimed in claim 8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and the computer program instructions can be called by a processor to execute the method according to any one of claims 1 to 6.