Cache-based memory access tracking

Abstract

There is provided an apparatus for executing a software program, comprising: a processing unit; a plurality of memory components, each memory component connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; and at least one memory tracking circuit connected to the processing unit and the at least one memory component. The memory tracking circuit is configured to: in each of a plurality of iterations, in response to receiving a memory access command from the processing unit, update at least one statistical counter of a plurality of statistical counters; and providing one or more of the plurality of statistical counters to a memory management component in order to map application memory of the software program to the at least one memory component.

Description

[0001] This application is a divisional application. The application number of the original application is 202280092125.4, and the original application date is February 23, 2022. The entire contents of the original application are incorporated into this application by reference. Background Art

[0002] The present invention relates to a computerized device and, more particularly, but not exclusively, to a computerized device having more than one memory component.

[0003] For the sake of brevity, the term "system" is hereinafter used to refer to a computerized system, and the terms are used interchangeably.

[0004] There are numerous metrics used to measure the performance of computerized systems, such as throughput, which is the amount of tasks executed in a determined time interval, and latency, which is the amount of time a task is delayed before being executed. Improving the performance of a system, such as by increasing the throughput of the system and / or reducing the latency of the system, depends on, among other factors, the amount of computer resources available in the system and how well the various components of the system work together. For example, reducing the latency when accessing memory and / or increasing the throughput of memory accesses can improve the performance of a system.

[0005] Memory components with relatively high performance access characteristics, such as low latency memory components or high throughput memory components, such as static RAM (SRAM), are generally more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). It is common practice to design the memory of a system using more than one type of memory component to balance the cost and performance of the system. Some common system designs organize multiple memory components in multiple memory tiers, where small and fast tiers are above larger and slower tiers as caches for the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available to software programs, i.e., addressable using the software program's application memory address, and the other tiers in the hierarchy are used as hierarchical caches.

[0006] Some other system designs make all memory tiers addressable using the software program's application memory address. In such systems, the performance of the system is affected by the distribution of the software program's application memory among multiple memory tiers (i.e., among one or more memory components of the system). When the software program's application memory includes multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high-performance memory components, while lower-performance memory components are used to store infrequently accessed application memory regions.

[0007] The term non-uniform memory access (NUMA) refers to a computerized system with more than one memory component where some characteristics of memory access from a processing unit to the memory component (e.g., latency and / or throughput) depend on the topology of the system, such as the location of the memory component relative to the processing unit. In a manner similar to the above-described systems, in a system with NUMA, the performance of the system may be affected by the distribution of a software program's application memory among one or more memory components. Summary of the invention

[0008] The present invention includes describing an apparatus and method for tracking memory access and managing memory. In some embodiments described herein, one or more memory tracking circuits are used to update at least one of a plurality of statistical counters in response to receiving a memory access command from a processing unit. In addition, in these embodiments, the one or more memory tracking circuits are used to provide one or more of the plurality of statistical counters to a memory management component to map an application memory of a software program to a plurality of memory components connected to the processing unit. Updating at least one statistical counter using the one or more memory tracking circuits reduces the amount of processing overhead required by the processing unit to track memory access and manage the allocation of the application memory of the software program to the plurality of memory components, thereby improving the performance of the apparatus.

[0009] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0010] According to a first aspect, there is provided an apparatus for executing a software program, the apparatus comprising: a processing unit; at least one memory component, each memory component being connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; at least one memory tracking circuit being connected to the processing unit and the at least one memory component, and being used to: update at least one statistical counter of a plurality of statistical counters in response to receiving a memory access command from the processing unit in each of a plurality of iterations; and provide one or more of the plurality of statistical counters to a memory management component so as to map the application memory of the software program to the at least one memory component.

[0011] According to a second aspect, a method for managing memory in a device for executing one or more software programs is provided, the method comprising: in each iteration of multiple iterations, in response to receiving a memory access command from a processing unit, at least one memory tracking circuit connected to the processing unit and at least one memory component updates at least one of a plurality of statistical counters, the at least one memory component being connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; and providing one or more of the plurality of statistical counters to a memory management component so as to map the application memory of the software program to the at least one memory component.

[0012] According to a third aspect, there is provided a software program product for memory management, the software program product comprising: a non-transitory computer-readable storage medium; program instructions for: receiving, in each of one or more management iterations, one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component to map application memory of a software program to the at least one memory component, the at least one memory component being connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit. According to the third aspect, the program instructions are executed by at least one computerized processor from the non-transitory computer-readable storage medium.

[0013] According to a fourth aspect, a method for a memory management component is provided, the method comprising: in each management iteration of one or more management iterations, receiving one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component so as to map an application memory of a software program to at least one of the memory components, the at least one memory component being connected to the processing unit, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit.

[0014] According to a fifth aspect, a memory tracking circuit is provided, comprising a plurality of statistical counters, the plurality of statistical counters comprising: a high access counter; a low access counter; and a plurality of range access counters. According to the fifth aspect, the memory tracking circuit is used, when connected to a processing unit and at least one memory component, each memory component is connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges: in each iteration of a plurality of iterations, in response to receiving a memory access command from the processing unit: identifying a memory address in the memory access command; identifying a memory address range in the plurality of memory address ranges, wherein the memory address range includes the memory address; increasing a corresponding range access counter associated with the memory address range; when the corresponding range access counter exceeds a high access threshold, increasing the high access counter; providing one or more of the plurality of statistical counters to a memory management component so as to map the application memory of the software program to the at least one memory component.

[0015] In an implementation of the first aspect and the second aspect, the plurality of statistical counters include at least one of the following: at least one watermark counter selected from the group consisting of a high access counter and a low access counter; a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges. Using at least one watermark counter in addition to the plurality of range access counters helps to reduce the amount of accesses to the plurality of range access counters, and reduces the amount of computing resources required for memory management compared to a method of accessing all of the plurality of range access counters. Optionally, at least one other statistical counter of the plurality of statistical counters is implemented in the at least one memory tracking circuit. Implementing the statistical counters in the memory tracking circuit reduces the amount of computing resources required to track one or more memory accesses compared to a method of implementing the statistical counters in a page table of an operating system executed by a processing unit executing a software program. Optionally, at least one other statistical counter of the plurality of statistical counters is implemented in a cache memory component connected to one or more of the at least one memory component. Optionally, at least one additional other statistical counter of the plurality of statistical counters is implemented in one of the at least one memory component.

[0016] In another implementation of the first aspect and the second aspect, updating the at least one statistical counter comprises: identifying a memory address in the memory access command; identifying a memory address range in the multiple memory address ranges, wherein the memory address range includes the memory address; increasing a corresponding range access counter; and increasing the high access counter when the corresponding range access counter exceeds a high access threshold. When the corresponding range access counter associated with the memory address range exceeds the high access threshold, increasing the high access counter helps to reduce the amount of access to the multiple range access counters, and reduces the amount of computing resources required for memory management compared to the method of accessing all multiple range access counters. Optionally, providing the one or more statistical counters to the memory management component comprises: providing the at least one watermark counter; and providing at least one range access counter of the multiple range access counters in response to a request from the memory management component. Optionally, the memory management component is used to: perform another analysis including the at least one watermark counter; and send a request to the at least one memory tracking circuit to provide the at least one range access counter based on another result of the another analysis. In one or more steps, while performing another analysis, one or more statistical counters are provided from at least one memory tracking circuit to the memory management component, reducing the amount of access to multiple range access counters, and reducing the amount of computing resources required for memory management compared to a method of accessing all multiple range access counters, including reducing processing time, processing complexity and the amount of access to at least one memory tracking circuit. Optionally, the memory management component is also used to configure at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Optionally, based on another result of another analysis including the one or more statistical counters, the memory management component configures at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Configuring the low access threshold and / or the high access threshold improves the accuracy of the high access counter and the low access counter, and improves the accuracy of the memory map calculated based on the one or more statistical counters.

[0017] In another implementation of the first aspect and the second aspect, the at least one memory tracking circuit is used to update the at least one statistical counter and to provide one or more of the plurality of statistical counters when the processing unit executes the software program. When the processing unit executes the software program, updating the at least one statistical counter and providing one or more statistical counters facilitates runtime modification of a memory map of an application memory of the software program, thereby improving system performance when executing the software program.

[0018] In another implementation of the first and second aspects, the at least one memory tracking circuit includes a plurality of local tracking circuits. Optionally, each of the plurality of local tracking circuits is connected to the processing unit and one or more memory components of the at least one memory component; when at least one of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit includes a local memory address as a memory address in a memory address command, each of the plurality of local tracking circuits updates the at least one statistical counter in response to receiving the memory access command. Using a plurality of local tracking circuits improves the usability of the method described herein in a system in which at least one memory component is topologically far away from each other.

[0019] In another implementation of the first aspect and the second aspect, the application memory of the software program includes a plurality of application memory areas, each of which is stored in one of the at least one memory components; the mapping of the application memory by the memory management component includes: performing an analysis including the one or more statistical counters; and in response to the result of the analysis, moving at least one of the plurality of application memory areas from one of the at least one memory component to another of the at least one memory component. Optionally, when the processing unit executes the software program, the memory mapping component maps the application memory. When the processing unit executes the software program, moving the application memory area from one memory component to another memory component helps to reduce the total delay of multiple memory accesses performed when executing the software program and / or increase the total bandwidth of multiple memory accesses, thereby improving the performance of the device executing the software program. Performing an analysis including one or more statistical counters increases the accuracy of the analysis results, so that compared with other methods of selecting a memory area that does not include one or more statistical counters collected when the processing unit executes the software program, for example, a method using static analysis of the software program, moving at least one application memory area according to the analysis results improves the performance of the device executing the software program.

[0020] In another implementation of the first aspect and the second aspect, the at least one memory tracking circuit is also used to: in each management iteration of one or more management iterations: execute the multiple iterations, including updating the at least one statistical counter; providing the one or more statistical counters to the memory management component; resetting one or more other statistical counters among the multiple statistical counters.

[0021] In another implementation of the first aspect and the second aspect, the memory management component includes a software object executed by the processing unit. Optionally, the memory management component includes a memory management circuit connected to the at least one memory tracking circuit and the at least one memory component. Using the memory management circuit reduces the amount of computing resources of the processing unit required for memory management, reducing the impact of memory management on the performance of the device executing the software program.

[0022] In another implementation of the first and second aspects, the processing unit is used to execute an operating system. Optionally, the operating system uses a plurality of operating system memory pages to address the at least one memory component, each operating system memory page having a page size in an identified set of page sizes; at least one of the plurality of memory address ranges has a range size that is not equal to any page size in the set of page sizes. Tracking memory address ranges whose range size is not equal to any page size in the set of page sizes of the operating system improves the accuracy of analysis of one or more statistical counters, thereby improving the performance of the device executing the software program.

[0023] In an implementation of the fourth aspect, the plurality of statistical counters include a high access counter, a low access counter, and at least one of a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges. Optionally, receiving the one or more statistical counters includes receiving at least one of the high access counter and the low access counter. Optionally, the method further includes: performing an analysis including at least one of the low access counter and the high access counter; and sending a request to the at least one memory tracking circuit to provide the at least one range access counter based on a result of the another analysis.

[0024] Other systems, methods, features and advantages of the present invention will be or become apparent to those skilled in the art after studying the following drawings and detailed description. It is intended that all such other systems, methods, features and advantages be included in this description, within the scope of the present invention, and protected by the accompanying claims.

[0025] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as those known to those of ordinary skill in the art to which the implementation belongs. Although methods and materials similar or equivalent to the methods and materials described herein can be used in the practice or testing of the implementation, exemplary methods and / or materials are described below. In the event of a conflict, this patent specification (including definitions) shall prevail. In addition, these materials, methods and examples are illustrative only and are not necessarily restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Some embodiments are described herein by way of example only in conjunction with the accompanying drawings. The following detailed descriptions with specific reference to the accompanying drawings emphasize that the details shown are only examples and are for illustrative purposes only in discussing the embodiments. Thus, based on the accompanying drawings, those skilled in the art will readily understand how to practice the embodiments.

[0027] In the attached picture:

[0028] Figure 1 is a schematic block diagram of an exemplary apparatus provided by some embodiments;

[0029] Figure 2 is a schematic block diagram of another exemplary apparatus provided by some embodiments;

[0030] Figure 3 is a schematic block diagram of an exemplary address mapping provided by some embodiments;

[0031] Figure 4 is a flowchart schematically showing an optional operation flow for managing memory provided by some embodiments;

[0032] Figure 5 is a flowchart schematically showing an optional operation flow for updating a statistical counter provided by some embodiments;

[0033] Figure 6 is a flowchart schematically showing an optional operation flow for memory management provided by some embodiments;

[0034] Figure 7 is a sequence diagram of optional operation processes provided by some embodiments;

[0035] Figure 8 is a schematic block diagram of an exemplary memory map provided by some embodiments;

[0036] Fig. 9 is a schematic block diagram of another exemplary memory mapping provided by some embodiments. DETAILED DESCRIPTION

[0037] As used herein, the term "processing unit" refers to any type of programmable or non-programmable circuitry for performing the operations described below. A processing unit may include hardware and software. For example, a processing unit may include one or more processors and a transient or non-transient memory that carries a program that, when executed by the one or more processors, causes the processing unit to perform the corresponding operations.

[0038] In addition, the term "physical address" as used herein refers to the address used by the processing unit in a memory access request to access a memory component. In addition, the term "application address" as used herein refers to an address used in an application. An application address may be a virtual address, in which case the application address needs to be converted to a physical address in order to access one or more memory components. The term "memory mapping" as used herein refers to mapping an application memory address of a software program to a physical address in a memory access request sent by a processing unit. This mapping can be used to convert an application address to a physical address that identifies a location in a memory component where application data or instructions are stored.

[0039] Furthermore, as used herein, the terms "memory access request" and "memory access command" are both used to refer to a request to access a memory component in order to read from and / or write to the memory component, and these terms are used interchangeably. A memory access request may be generated when computer instructions of a software program including memory access computer instructions are executed.

[0040] In addition, the terms "range of memory addresses" and "memory address range" used in this article are both used to refer to the range of memory addresses and can be used interchangeably.

[0041] In order to assign each of multiple application memory regions to one or more memory components connected to a processing unit, thereby improving the performance of the system, some systems track accesses to one or more memory components. Some existing tracking methods maintain access counters in a page table used to map application addresses to physical addresses. This method requires updating the counters in the page table each time the memory is accessed. In addition, analyzing multiple counters in the page table requires merging counters of multiple virtual pages mapped to a common physical page. In addition, some methods require sorting multiple counters to classify page table entries, for example, to identify page table entries that describe high-access application memory regions. Such methods reduce the performance of the system because they require computing resources of the processing unit.

[0042] In some other approaches to tracking memory accesses, a processing unit maintains multiple counters stored in one or more memory components. In a system implementing this approach, each memory access request from a processing unit requires the processing unit to access the memory twice: once to update the counter and once to access the data in the memory, thereby reducing the effective throughput of the memory (i.e., access to the application memory area).

[0043] In order to reduce the amount of computer resources of the processing unit used to track multiple memory accesses, in some embodiments described herein, the inventors propose to use one or more memory management circuits connected to the processing unit and one or more memory components to update at least one of the multiple statistical counters in response to receiving a memory access command from the processing unit. Optionally, the statistical counter indicates multiple memory access commands. For example, when the processing unit has multiple memory address ranges and each of the one or more memory components is mapped to one or more of the multiple memory address ranges, the statistical counter can be a range access counter associated with the memory address range, indicating the number of times the memory address range is accessed in multiple memory access commands. Optionally, the statistical counter indicates the amount of range access counters that meet the identified criteria. For example, the statistical counter can be a watermark counter indicating the amount of range access counters that exceed a high access threshold, wherein the high access threshold indicates the amount of access to the memory address range that is considered high. Alternatively, the watermark counter can indicate the amount of range access counters that is less than a low access threshold, wherein the low access threshold indicates another amount of access to the memory address range that is considered low. Optionally, the statistical counter indicates the amount of memory access commands received from the processing unit. Optionally, the one or more processing circuits receive the memory access command in each of the plurality of iterations and update at least one of the plurality of statistics counters in each of the plurality of iterations. Using the one or more processing circuits to update the at least one statistics counter reduces the amount of resources used by the processing unit to track the plurality of memory accesses, such as reducing the amount of memory accesses performed by the processing unit and / or reducing the amount of processor cycles of the processing unit used to calculate the memory map. Reducing the amount of computing resources used by the processing unit improves the performance of the system when executing the software program, such as by increasing throughput and / or reducing latency when executing one or more tasks of the software program.

[0044] Optionally, at least one of the plurality of statistical counters is implemented in one or more memory tracking circuits to further reduce the amount of access to one or more memory components, thereby improving system performance.

[0045] In addition, in some embodiments, the present invention proposes that one or more memory tracking circuits provide one or more of a plurality of statistical counters to a memory management component so as to map the application memory of the software program to one or more memory components. Optionally, the memory management component analyzes the one or more statistical counters so as to map the application memory. Optionally, the memory management component includes a software object executed by the processing unit. Optionally, the memory management component includes other circuits, which are optionally connected to the one or more memory tracking circuits and the one or more memory components. Providing one or more statistical counters to the memory management component helps improve system performance by moving one or more application memory areas of a plurality of application memory areas of the software program from one of the one or more memory components to another of the one or more memory components. For example, a range access counter of a memory address range that exceeds a high access threshold may indicate that the memory address range is frequently accessed, and an application memory area referenced by the memory address range in the plurality of application memory areas should be stored in a memory component with higher performance access characteristics (e.g., low latency and / or high throughput). Similarly, another range access counter of another memory address range below the low access threshold may indicate that the another memory address range is rarely accessed and that another application memory region of the plurality of application memory regions referenced by the another memory address range should be stored in another memory component having relatively lower performance access characteristics (e.g., higher latency and / or lower throughput than a memory component having relatively higher performance access characteristics). Optionally, the memory mapping component maps application memory when the processing unit executes the software program, and optionally moves one or more application memory regions when the processing unit executes the software program.

[0046] In some embodiments described herein, at least one memory component is a plurality of memory components, including at least two memory components. Optionally, the one or more memory tracking circuits include a plurality of local tracking circuits, such that each of the plurality of local tracking circuits is connected to one or more of the plurality of memory components. Optionally, each local tracking circuit is connected to a subset of the plurality of memory components, such that the local tracking circuit is not connected to at least one of the plurality of memory components. Optionally, each local tracking circuit updates at least one statistics counter according to the one or more memory components connected thereto when at least one of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit includes a local memory address in a memory address command. When the processing unit is connected to the at least one memory component via a host memory controller, the local tracking circuit connected to the at least one memory component is optionally additionally connected to the host memory controller.

[0047] Optionally, when the one or more memory tracking circuits provide the one or more statistical counters to the memory management component, the one or more statistical counters include one or more watermark counters. Optionally, the memory management component performs another analysis on the one or more watermark counters, and based on the result of the another analysis, the memory management component optionally sends a request to the one or more memory tracking circuits to provide at least one range access counter. For example, the memory management component can request at least one range access counter only when the result of the another analysis indicates that the high watermark counter exceeds the identified threshold. In this example, as long as the amount of ranges experiencing high access is below the threshold, it may not be necessary to move the memory region. This requires fewer computing resources than some other methods that require reading all multiple range access counters to identify that the memory region does not need to be moved. In another example, the memory management component can request one or more range access counters until an amount of range access counters exceeding a high watermark threshold equal to the high watermark counter is received. In this example, identifying all memory regions experiencing high access rates can be achieved without reading all multiple memory counters, which requires fewer computing resources than some other methods that do not use watermark counters.

[0048] When the processing unit executes the operating system, the operating system can use multiple operating system memory pages to address multiple memory components. It is common practice not to use arbitrary page sizes for multiple operating system memory pages, that is, each of the multiple operating system memory pages has a page size in the identified page size set. When memory access tracking is completed using the page table of the operating system, the granularity of the memory access tracking is based on the corresponding page size of each of the multiple operating system memory pages. In some embodiments described herein, at least one of the multiple memory address ranges has a range size that is not equal to any one of the page size set. Using one or more memory tracking circuits to track multiple memory access commands based on multiple memory address ranges, supporting tracking of multiple memory access commands at a granularity different from the page size of the operating system, compared with the memory map calculated when tracking based on the operating system page size, the accuracy of the memory map calculated based on multiple statistical counters is improved, thereby improving the accuracy of allocating multiple application memory areas to one or more memory components, and improving the performance of the system.

[0049] Before describing at least one embodiment in detail, it should be understood that the embodiments are not necessarily limited to the details of the construction and arrangement of the components and / or methods described in the following description and / or drawings and / or examples. The implementations described herein support other embodiments or support being practiced or executed in various ways.

[0050] The embodiments may be a system, method and / or computer program product. The computer program product may include one or more computer-readable storage media having computer-readable program instructions that cause a processor to perform various aspects of the embodiments.

[0051] The computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. The computer-readable storage medium may be, but is not limited to, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above devices. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the above. The computer-readable storage medium used herein should not be interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0052] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0053] The computer-readable program instructions for performing the operation of the embodiment can be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code, local compilation or real-time compilation (just-in-time, JIT), written in any combination of one or more programming languages, the one or more programming languages ​​include object-oriented programming languages, such as Smalltalk, C++, Java, object-oriented Fortran, etc., interpret programming languages, such as JavaScript, Python, etc., and traditional procedural programming languages, such as "C" programming language, Fortran or similar programming languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer; as an independent software package, partially on the user's computer and partially on the remote computer, or completely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), and can also be connected to an external computer (e.g., by using the Internet of an Internet service provider). In some embodiments, electronic circuits including programmable logic circuits, field-programmable gate arrays (FPGAs) or programmable logic arrays (PLAs), etc., can execute computer-readable program instructions to customize the electronic circuits by using state information of the computer-readable program instructions, thereby performing various aspects of the embodiments.

[0054] The present invention is combined with the flowchart and / or block diagram of the method, device (system) and computer program product provided by the embodiment to describe various aspects of the embodiment. It should be understood that each box in the flowchart illustration and / or block diagram and the combination of boxes in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0055] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device create a module for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can instruct a computer, a programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable storage medium storing the instructions includes an article containing the instructions, which are used to implement various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0056] Computer-readable program instructions can also be loaded into a computer, other programmable data processing apparatus, or other device, so that a series of operating steps are performed on the computer, other programmable apparatus, or other device, thereby producing a computer-implemented process, so that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0057] The flow chart and block diagram in the figure illustrate the architecture, function and operation of the possible implementation of the system, method and computer program product provided by various embodiments. In this regard, each box in the flow chart or block diagram can represent a module, a section or a partial instruction, which includes one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the function described in the box may not be implemented in the order described in the figure. For example, in fact, the two boxes shown in succession can be executed almost simultaneously, or sometimes in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart and the box combination in the block diagram and / or flow chart can be implemented by a system based on special-purpose hardware, which performs specific functions or actions, or performs a combination of special-purpose hardware and computer instructions.

[0058] Reference now Figure 1 , which shows a schematic block diagram of an exemplary apparatus 100 provided in some embodiments. In these embodiments, the processing unit 101 is connected to at least one memory component 120.

[0059] For the sake of brevity, hereinafter, the term "memory component 120" is used to mean "at least one memory component 120", and these terms are used interchangeably. Optionally, the memory component 120 includes one memory component, such as memory component 120C. Optionally, the memory component 120 includes more than one memory component, such as memory component 120A, memory component 120B, and memory component 120C. The memory component can be a random access memory (random access memory, RAM) component, such as an SRAM component or a DRAM component. Other examples of memory components include read-only memory (read-only memory, ROM) components, electrically erasable programmable ROM (electrically erasable programmable ROM, EEPROM) and non-volatile RAM (non-volatile RAM, NVRAM). Optionally, one or more of the memory components 120 are electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 are connected to the processing unit 101 via a host memory controller (not shown).

[0060] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to another cache memory component (not shown) that is additionally connected to the processing unit 101.

[0061] Optionally, one or more memory tracking circuits 130 are connected to the processing unit 101 and the memory component 120 .

[0062] Now also refer to Figure 2 , which shows a schematic block diagram of another exemplary apparatus 200 provided by some embodiments. In these embodiments, one or more memory tracking circuits 130 include multiple local tracking circuits 201, for example, including local tracking circuit 201A and local tracking circuit 201B. Optionally, each of the multiple local tracking circuits 201 is connected to one or more of the memory components 120. Optionally, each of the multiple local tracking circuits is connected to a subset of the memory components 120, so that each of the multiple local tracking circuits 201 is not connected to at least one of the memory components 120. In this example, local tracking circuit 201A is connected to memory component 120A and memory component 120B, but not to memory component 120C. In addition, in this example, local tracking circuit 201B is connected to memory component 120C, and not to memory component 120A and memory component 120B. Optionally, each of the multiple local tracking circuits 201 is connected to one of the memory components 120.

[0063] Now refer to it again Figure 1Optionally, each of the memory components 120 is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit 101 .

[0064] Now also refer to Figure 3 , which shows a schematic block diagram of an exemplary address mapping 300 provided by some embodiments. In this example, the memory component 120A is mapped to the memory address range 301A, the memory address range 301B, and the memory address range 301C in the plurality of memory address ranges 301. Therefore, when the processing unit 101 accesses a memory address in the memory address range 301A, the memory address range 301B, and the memory address range 301C, the processing unit 101 accesses the memory component.

[0065] Similarly, memory component 120B is mapped to memory address range 301D among multiple memory address ranges 301 , and memory component 120C is mapped to memory address range 301E and memory address range 301F among multiple memory address ranges 301 .

[0066] Optionally, processing unit 101 executes an operating system that uses a plurality of operating system memory pages to address memory component 120. Optionally, each of the plurality of operating system memory pages has a page size that is one of the identified set of page sizes. Optionally, a size of at least one of the plurality of memory address ranges 301 is not a member of the identified set of page sizes.

[0067] Now refer to it again Figure 1 Optionally, one or more memory tracking circuits 130 are connected to the memory management component 110. Optionally, the memory management component 110 includes a software object executed by the processing unit 101. Optionally, the memory management component 110 includes memory management circuits additionally connected to the processing unit 101 and the memory component 120.

[0068] According to some embodiments, in order to track memory access commands and manage memory, the following optional methods may be implemented by system 100 or system 200 .

[0069] Now also refer to Figure 4, which shows a flowchart schematically representing an optional operational process 400 for managing memory provided by some embodiments. In these embodiments, in 401, one or more memory tracking circuits 130 receive a memory access command including a memory address from a processing unit 101. Optionally, the memory address is in one of a plurality of memory address ranges 301. For example, when the memory address is in a memory address range 301E, the memory address is a local memory address of a memory component 120C. In this example, the memory address range 301E includes a local memory address of the memory component 120C, which is the memory address in the memory access command. Optionally, the processing unit 101 sends a memory access command when executing a software program, optionally for accessing an application memory of the software program.

[0070] In 410, the one or more memory tracking circuits 130 optionally update at least one of the plurality of statistical counters. Optionally, the plurality of statistical counters include a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges 301. Optionally, the plurality of statistical counters include one or more watermark counters, each watermark counter being associated with a frequency of access to the memory component. The watermark counter may indicate an amount of memory access ranges accessed at a frequency associated with the watermark counter. The watermark counter may be a high access counter indicating an amount of range access counters in the plurality of range access counters that exceed a high access threshold, thereby indicating frequent access to the corresponding memory component associated with the range access counter that exceeds the high access threshold. For example, a range access counter of the memory address range 301F that exceeds the high access threshold may indicate frequent access to the memory component 120C associated with the memory address range 301F. Another example of a watermark counter is a low access counter indicating an amount of range access counters in the plurality of range access counters that exceed a low access threshold. There may be more than two watermark counters, each associated with one of the plurality of access frequencies to the memory component. Each of the two or more watermark counters may be associated with an access threshold indicating an access frequency associated therewith, ie indicating an amount of range access counters of the plurality of range access counters exceeding the threshold associated with the watermark counter.

[0071] Optionally, at least one of the plurality of statistics counters is implemented in one or more memory tracking circuits 130. Optionally, at least one other of the plurality of statistics counters is implemented in one of the memory components 120. Optionally, one of the memory components implementing the at least one other statistics counter is a cache memory component of the processing unit 101. Optionally, at least one other of the plurality of statistics counters is implemented in another cache memory component connected to one or more of the memory components 120.

[0072] Now also refer to Figure 5 , which shows a flowchart schematically representing an optional operation flow 500 for updating statistical counters provided by some embodiments. In these embodiments, in 501, one or more memory tracking circuits 130 identify a memory address in a memory access command received in 401. In 502, one or more memory tracking circuits 130 optionally identify a memory address range in a plurality of memory address ranges 301, wherein the memory address range includes a memory address. For example, a memory command may include a memory address within a memory address range 301F. In this example, the one or more memory tracking circuits 130 identify the memory address range 301F. Optionally, in 510, the one or more memory tracking circuits 130 increase a corresponding range access counter in a plurality of range access counters associated with the memory address range 301F. When the one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, each of the plurality of local tracking circuits 201 updates at least one statistical counter when at least one memory address range in the plurality of memory address ranges 301 associated with one or more memory components connected to the local tracking circuit includes a memory address of a memory access command. For example, when the local tracking circuit 201B identifies that the memory address of the memory access command is within the memory address range 301F associated with the memory component 120C connected to the local tracking circuit 201B, the local tracking circuit 201B may update one or more statistics counters.

[0073] At 520, the one or more memory tracking circuits 130 optionally determine whether the corresponding range access counter associated with the memory address range 301F exceeds a low access threshold, and in the event that the corresponding range access counter associated with the memory address range 301F exceeds the low access threshold, the one or more memory tracking circuits 130 optionally decrement the low access counter at 521. At 530, the one or more memory tracking circuits 130 optionally determine whether the corresponding range access counter associated with the range of memory addresses 301F exceeds a high access threshold, and in the event that the corresponding range access counter associated with the memory address range 301F exceeds the high access threshold, the one or more memory tracking circuits 130 optionally increment the high access counter at 531. When the one or more watermark counters include more than two watermark counters, the one or more tracking circuits 130 optionally determine, for each of the more than two watermark counters, whether the corresponding range access counter associated with the memory address range 301F exceeds a threshold associated with the watermark counter, and upon determining that the corresponding range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, the one or more memory tracking circuits 130 optionally increase the watermark counter.

[0074] Now refer to it again Figure 4 Optionally, the one or more memory tracking circuits 130 perform 401 and 410 when the processing unit 101 executes the software program. Optionally, the one or more memory tracking circuits 130 repeat 401 and 410 in each of a plurality of iterations.

[0075] At 420, the one or more memory tracking circuits 130 optionally provide one or more of the plurality of statistical counters to the memory management component 110, optionally for mapping application memory of the software program to the memory component 120. Optionally, the one or more memory tracking circuits 130 provide the one or more statistical counters when the processing unit 101 executes the software program. Optionally, the memory mapping component 110 maps the application memory to the memory component 120 when the processing unit 101 executes the software program.

[0076] Now refer to it again Figure 6 , which shows an optional operation flow 600 for memory management provided by some embodiments. In these embodiments, in 601, the memory management component 110 performs analysis of one or more statistical counters. The following is an exemplary, non-mandatory method for performing the analysis.

[0077] Now also refer to Figure 7, which shows a sequence diagram of an optional operational flow 700 provided by some embodiments. In these embodiments, in 701, one or more memory tracking circuits 130 provide one or more watermark counters to the memory management component 110. Optionally, the one or more memory tracking circuits 130 provide a subset of the one or more watermark counters in 701, such as only one of the one or more watermark counters. Optionally, the one or more watermark counters include a high access counter. Optionally, the one or more watermark counters include a low access counter. In 702, the one or more memory tracking circuits 130 perform another analysis including the one or more watermark counters. Based on the result of the another analysis, in 710, the memory management component 110 optionally sends a request to the one or more memory tracking circuits 130 in 710 to provide at least one range access counter of a plurality of range access counters. For example, when the result of the another analysis indicates that the watermark counter exceeds a frequency threshold, the memory mapping component can request at least one range access counter to identify which of the plurality of memory address ranges is frequently accessed. On the other hand, when the result of the other analysis indicates that the watermark counter does not exceed the frequency threshold, the memory mapping component 110 can refuse to perform the other analysis and refuse to modify the mapping of the application memory of the software program. The other analysis can use one of the one or more watermark counters, for example when only one watermark counter is implemented. The other analysis can use more than one of the one or more watermark counters. When the one or more watermark counters include at least one of a low access counter and a high access counter, the other analysis optionally includes at least one of the low access counter and the high access counter.

[0078] In response to receiving the request from the memory management component 110, in 711, the one or more memory tracking circuits 130 optionally send at least one range access counter to the memory management component 110. Optionally, 710 and 711 are repeated in multiple read iterations. Optionally, in 711, the one or more memory tracking circuits 130 send one range access counter to the memory management component 110, so that the memory management component 110 accesses one or more range access counters at a time. Optionally, in each execution of 711, the one or more memory tracking circuits 130 send a subset of the plurality of range access counters to the memory management component 110. Optionally, the management component 110 refuses to execute 710 if a stop condition is identified, such as receiving an amount of range access counters that exceeds a threshold value equal to the value of the watermark counter provided in 701.

[0079] Now refer to it again Figure 6 Based on the results of the analysis performed in 601 , the memory management component 110 optionally performs one or more memory management tasks, such as mapping the application memory of the software program. Another example of a memory management task is configuring one or more memory tracking circuits 130 .

[0080] Now also refer to Figure 8 , which shows a schematic block diagram of an example memory map 800 provided by some embodiments. Optionally, the application memory of the software program includes multiple application memory areas 801, for example, including a memory application area 801A, a memory application area 801B, and a memory application area 801C. Optionally, each of the multiple memory application areas is stored in one of the memory components 120. For example, the application memory area 801A can be stored in the memory component 120A, the application memory area 801B can be stored in the memory component 120B, and the application memory area 801C can be stored in the memory component 120C.

[0081] Now refer to it again Figure 6 At 610 , in response to the analysis performed at 601 (eg, using method 700 ), memory management component 110 may move one or more application memory areas of plurality of application memory areas 801 from one of memory components 120 to another of memory components 120 .

[0082] Now also refer to Fig. 9 , which shows a schematic block diagram of another exemplary memory mapping 900 provided by some embodiments. In this example, the result of the analysis may be, for example, when the memory component 120C has a higher performance access characteristic than the memory component 120A and the result of the analysis indicates a high frequency access to the application memory area 801A, the memory management component 110 moves the application memory area 801A from the memory component 120A to the memory component 120C. Optionally, the memory management component 110 updates the mapping between the application memory and one or more of the plurality of memory address ranges 301, for example, in a page table of an operating system executed by the processing unit 101.

[0083] Now refer to it again Figure 7 . In 721, the memory management component 110 optionally configures one or more watermark thresholds, such as a high watermark threshold or a low watermark threshold, in one or more memory tracking circuits 130. Optionally, in 720, the memory management component 110 performs another analysis of the one or more statistical counters and executes 721 based on another result of the further analysis. For example, when the memory component with high-performance access characteristics is not fully utilized, the memory management component 110 can lower the high watermark threshold. Similarly, when the memory component with high-performance access characteristics is overused, the memory management component 110 can increase the high watermark threshold.

[0084] Now refer to it again Figure 4. In 430, the one or more memory tracking circuits 130 optionally reset one or more other counters of the plurality of statistical counters. For example, in 420, the one or more memory tracking circuits 130 may reset the statistical counters after providing the statistical counters to the memory management component 110. Resetting the counters may be setting the counters to zero. Resetting the counters may be setting the counters to an initial value. For example, the low access counter may start at a value equal to the amount of memory components in the memory component 120 and be decremented in 521 for each range access counter that exceeds the low watermark threshold.

[0085] Optionally, the one or more memory tracking circuits 130 repeatedly perform a plurality of iterations including 401 and 410 , provide one or more statistical counters in 420 , and reset one or more other counters in each of the plurality of management iterations.

[0086] The descriptions of various embodiments are for illustrative purposes only, but these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles, practical applications, or technological advances of the embodiments, or to enable other persons skilled in the art to understand the embodiments disclosed herein, as compared to existing technologies on the market.

[0087] It is expected that during the life of the patent expiring on this application, many related memory tracking circuits will be developed, and the scope of the term memory tracking circuit is intended a priori to include all such new technologies.

[0088] As used herein, the term "about" refers to ± 10%.

[0089] The terms "including," "having," and variations thereof mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of.

[0090] The phrase "consisting essentially of" means that the composition or method may include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0091] As used herein, the singular forms "a", "an" and "the" include plural references unless the context clearly indicates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[0092] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features of other embodiments.

[0093] As used herein, the word “optionally” means “provided in some embodiments and not provided in other embodiments.” Any particular embodiment may include multiple “optional” features, unless such features are in conflict.

[0094] In the present application, various embodiments can be presented by range format.It should be understood that the description of range format is only for convenience and brevity, and should not be interpreted as a fixed limitation to the scope of the embodiment.Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and the individual numerical values ​​in the range.For example, the description of the range such as from 1 to 6 should be considered to have specifically disclosed the sub-ranges from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc. and the individual numbers such as 1, 2, 3, 4, 5 and 6 in the range.No matter how wide the scope is, this applies.

[0095] When a numerical range is indicated herein, it is meant to include any listed numerals (fractional or integer) within the indicated range. The phrases "range between a first indicated number and a second indicated number" and "range from a first indicated number to a second indicated number" are used interchangeably herein to include the first indicated number and the second indicated number and all fractions and integers between the two.

[0096] It should be understood that certain features of the embodiments described in the context of separate embodiments for the sake of brevity may also be provided in a single embodiment by combination. Conversely, individual features of the embodiments described in the context of a single embodiment for the sake of brevity may also be provided in any other described embodiment individually or by any suitable sub-combination or as appropriate. Certain features described in the context of individual embodiments are not considered essential features of these embodiments, unless the embodiments are inoperable without these elements.

[0097] Although the embodiments have been described in conjunction with their specific embodiments, it is evident that many alternatives, modifications and variations are apparent to those skilled in the art. Therefore, it is intended to encompass all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

[0098] It is the purpose of the applicant that all publications, patents and patent applications mentioned in this specification are incorporated herein by reference in their entirety, as if each individual publication, patent or patent application was specifically and individually indicated when it was mentioned to be incorporated herein by reference. In addition, the reference or identification of any reference of the present application cannot be regarded as allowing such reference to take precedence over the present invention in the prior art. With respect to the use of section headings, section headings should not be understood as necessary limitations. In addition, the entire contents of any one or more priority documents of the present application are incorporated herein by reference.

Claims

1. A memory data migration method, characterized in that: The method is applied to a memory system, wherein the memory system includes a memory tracking circuit, a memory management component, a first memory component and a second memory component. The memory tracking circuit tracks memory access commands sent from the processing unit and updates at least one statistical counter; The memory tracking circuitry provides the at least first statistics counter to the memory management component; The memory management component accesses the at least first statistical counter and moves an application memory area between a first memory component and a second memory component based on statistical data in the first statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory area is a memory area frequently accessed by software programs.

2. The method according to claim 1, characterized in that The memory management component manages multiple application memory areas, the multiple application memory areas include the application memory area, and the multiple application memory areas correspond to multiple memory address ranges.

3. The method according to claim 1 or 2, characterized in that: The memory tracking circuit tracks the memory access command sent from the processing unit and updates at least one statistical counter, including: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

4. The method according to claim 3, characterized in that The first memory address range corresponds to the first memory component.

5. The method according to claim 2, characterized in that: The moving the application memory area between the first memory component and the second memory component based on the statistical data in the first statistical counter includes: The memory management component performs analysis of the at least one statistical counter; Based on the result of the analysis, at least one of the multiple application memory areas is moved from the first memory component to the second memory component, wherein the multiple application memory areas are memory areas accessible to the software program.

6. The method according to claim 5, characterized in that When the processing unit executes the software program, a memory mapping component maps the multiple application memory areas.

7. The method according to claim 2, characterized in that include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

8. A memory data migration method, characterized in that: The method is performed by a memory tracking circuit, comprising: tracking memory access commands sent from the processing unit and updating at least one statistical counter; The at least one statistical counter is provided to a memory management component so that the memory management component moves an application memory area between a first memory component and a second memory component, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory area is an area frequently accessed by a software program.

9. The method according to claim 8, characterized in that The tracking of the memory access command sent from the processing unit and updating at least one statistical counter includes: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

10. The method according to claim 9, characterized in that The first memory address range corresponds to the first memory component.

11. The method according to claim 9, characterized in that include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

12. A memory management system, characterized in that: The invention comprises a processing unit, a memory tracking circuit, a memory management component and a plurality of memory components, wherein the memory component comprises a first memory component and a second memory component, wherein the memory tracking circuit is connected to the processing unit, the first memory component and the second memory component: The memory tracking circuit is used to track memory access commands sent from the processing unit and update at least one statistical counter; The memory tracking circuit is further configured to provide the at least one statistical counter to the memory management component; The memory management component is used to access the at least first statistical counter and move the application memory area between the first memory component and the second memory component according to the at least one statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory area is a memory area frequently accessed by the software program.

13. The memory management system according to claim 12, characterized in that: include: The first statistics counter is located in the memory tracking circuit.

14. The memory management system according to claim 12, characterized in that: include: The first statistical counter is located in the first memory component or the second memory component.

15. The memory management system according to any one of claims 12 to 14, characterized in that: The memory management component is also used to manage multiple application memory areas, the multiple application memory areas include the application memory area, and the multiple application memory areas correspond to multiple memory address ranges.

16. The memory management system according to any one of claims 12 to 15, characterized in that: The memory tracking circuit tracks the memory access command sent from the processing unit and updates at least one statistical counter, specifically including: The memory access command includes a first address. Based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

17. The memory management system according to claim 16, characterized in that: The first memory address range corresponds to the first memory component.

18. The memory management system according to claim 13, characterized in that: The moving the application memory area between the first memory component and the second memory component based on the statistical data in the first statistical counter specifically includes: The memory management component performs analysis of the at least one statistical counter; Based on the result of the analysis, at least one of the multiple application memory areas is moved from the first memory component to the second memory component, wherein the multiple application memory areas are memory areas accessible to the software program.

19. The memory management system according to claim 18, characterized in that: The memory management system further comprises a memory mapping component, and the memory mapping component is used to map the plurality of application memory areas when the processing unit executes the software program.

20. The memory management system according to claim 13, characterized in that: include: At least one memory address range among the multiple memory address ranges is not equal to the range size of any page size in the page size set.

21. A memory tracking circuit, characterized in that: The memory tracking circuit is used to execute the method of any one of claims 8-11.

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