Cache-based memory access tracking

Abstract

An apparatus for executing a software program is provided, comprising: a processing unit; a plurality of memory components, each memory component connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; and at least one memory tracking circuit connected to the processing unit and the at least one memory component. The memory tracking circuit is configured to: in each iteration of a plurality of iterations, update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit; and provide one or more of the plurality of statistical counters to a memory management component for use in mapping application memory of the software program to the at least one memory component.

Description

[0001] This application is a divisional application of the original application with the application number 202280092125.4 and the original filing date of 23 February 2022, the entire contents of the original application are incorporated herein by reference. BACKGROUND

[0002] The present application relates to a computerized device, and more particularly, but not exclusively, to a computerized device having more than one memory component.

[0003] For brevity, hereafter the term “system” is used to refer to a computerized system, and these terms are used interchangeably.

[0004] There are numerous metrics used to measure the performance of a computerized system, such as throughput, i.e., the amount of tasks performed in a determined time interval, and latency, i.e., the amount of time a task is delayed before being executed. Improving the performance of a system, for example, by increasing the throughput of the system and / or reducing the latency of the system, depends, among other factors, on the amount of computer resources available in the system and on how well the various components of the system work together. For example, reducing the latency of accessing a memory and / or increasing the throughput of memory accesses can improve the performance of a system.

[0005] Memory components with relatively high performance access characteristics, such as low latency memory components or high throughput memory components, such as static RAM (SRAM), are typically more expensive than memory components with lower performance access characteristics, such as dynamic RAM (DRAM). It is a common practice to design the memory of a system using more than one type of memory component to balance the cost and performance of the system. Some common system designs organize multiple memory components in multiple memory tiers, where small and fast tiers are above larger and slower tiers as a cache for the larger tiers. In some designs, there is a hierarchy of tiers, where only the largest tier is available for use by software programs, i.e., application memory addresses of the software programs can address, and the other tiers in the hierarchy are used as hierarchical caches.

[0006] Some other system designs make all the memory tiers available for use by software programs using application memory addresses of the software programs. In such systems, the performance of the system is affected by the distribution of the application memory of the software programs among the multiple memory tiers, i.e., among one or more memory components of the system. When the application memory of the software programs includes multiple application memory regions, performance can be improved when frequently accessed application memory regions are stored in one or more high performance memory components, while lower performance memory components are used to store application memory regions that are not accessed frequently.

[0007] The term non-uniform memory access (NUMA) refers to a computerized system having more than one memory component, where some characteristics (e.g., latency and / or throughput) of memory accesses from processing units to memory components depend on the topology of the system, e.g., the location of the memory components relative to the processing units. In a manner similar to the system described above, in a system having NUMA, the performance of the system can be affected by the distribution of the software program's application memory among one or more memory components. SUMMARY

[0008] The present invention includes describing an apparatus and method for tracking memory accesses and managing memory. In some embodiments described herein, one or more memory tracking circuits are used to update at least one of a plurality of statistical counters in response to receiving a memory access command from a processing unit. Further, in these embodiments, the one or more memory tracking circuits are used to provide one or more of the plurality of statistical counters to a memory management component for mapping the software program's application memory to a plurality of memory components connected to the processing unit. Updating at least one of the statistical counters using the one or more memory tracking circuits reduces the amount of processing overhead required by the processing unit to track memory accesses and manage the allocation of the software program's application memory to the plurality of memory components, thereby improving the performance of the apparatus.

[0009] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the accompanying drawings.

[0010] According to a first aspect, there is provided an apparatus for executing a software program, the apparatus comprising: a processing unit; at least one memory component, each memory component connected to the processing unit and mapped to at least one of a plurality of memory address ranges of the processing unit; at least one memory tracking circuit connected to the processing unit and the at least one memory component, configured to: at each iteration of a plurality of iterations, update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit; provide one or more of the plurality of statistical counters to a memory management component for mapping the software program's application memory to the at least one memory component.

[0011] According to a second aspect, there is provided a method for managing memory in an apparatus for executing one or more software programs, the method comprising: in each iteration of a plurality of iterations, in response to receiving a memory access command from a processing unit, updating, by at least one memory tracking circuit connected to the processing unit and at least one memory component connected to the processing unit, at least one statistical counter of a plurality of statistical counters, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit; providing one or more of the plurality of statistical counters to a memory management component for mapping application memory of a software program to the at least one memory component.

[0012] According to a third aspect, there is provided a software program product for memory management, the software program product comprising: a non-transitory computer readable storage medium; program instructions for: in each management iteration of one or more management iterations, receiving one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component connected to the processing unit, for mapping application memory of a software program to the at least one memory component, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit. According to the third aspect, the program instructions are executed by at least one computerized processor from the non-transitory computer readable storage medium.

[0013] According to a fourth aspect, there is provided a method for a memory management component, the method comprising: in each management iteration of one or more management iterations, receiving one or more of a plurality of statistical counters from at least one memory tracking circuit connected to a processing unit and at least one memory component connected to the processing unit, for mapping application memory of a software program to at least one of the memory components, wherein each of the at least one memory component is mapped to at least one memory address range of a plurality of memory address ranges of the processing unit.

[0014] According to a fifth aspect, there is provided a memory tracking circuit comprising a plurality of statistical counters, the plurality of statistical counters comprising: a high access counter; a low access counter; a plurality of range access counters. According to the fifth aspect, the memory tracking circuit is configured, when connected to a processing unit and at least one memory component, each memory component connected to the processing unit and mapped to at least one memory address range of a plurality of memory address ranges of the processing unit, and when each of the plurality of range access counters is associated with one of the plurality of memory address ranges: at each iteration of a plurality of iterations, in response to receiving a memory access command from the processing unit: identifying a memory address in the memory access command; identifying a memory address range of the plurality of memory address ranges, wherein the memory address range comprises the memory address; increasing a respective range access counter associated with the memory address range; increasing the high access counter when the respective range access counter exceeds a high access threshold; providing one or more of the plurality of statistical counters to a memory management component for mapping an application memory of the software program to the at least one memory component.

[0015] In an implementation form of the first and second aspects, the plurality of statistical counters comprises at least one of: at least one watermark counter selected from a group consisting of the high access counter and the low access counter; a plurality of range access counters, each range access counter associated with one of the plurality of memory address ranges. Using at least one watermark counter in addition to the plurality of range access counters helps to reduce the amount of accesses to the plurality of range access counters, reducing the amount of computational resources required for memory management compared to approaches that access all of the plurality of range access counters. Optionally, at least one further statistical counter of the plurality of statistical counters is implemented in the at least one memory tracking circuit. Implementing the statistical counters in the memory tracking circuit reduces the amount of computational resources required for tracking one or more memory accesses compared to approaches that implement the statistical counters in a page table of an operating system executed by the processing unit executing the software program. Optionally, at least one further statistical counter of the plurality of statistical counters is implemented in a cache memory component connected to one or more of the at least one memory component. Optionally, at least one additional further statistical counter of the plurality of statistical counters is implemented in one of the at least one memory component.

[0016] In an implementation form of the first aspect and the second aspect, updating the at least one statistical counter comprises: identifying a memory address in the memory access command; identifying a memory address range in the plurality of memory address ranges, wherein the memory address range comprises the memory address; increasing a corresponding range access counter; and increasing the high access counter when the corresponding range access counter exceeds a high access threshold. Increasing the high access counter when the corresponding range access counter associated with a memory address range exceeds a high access threshold helps to reduce the amount of accesses to the plurality of range access counters, and reduces the amount of computational resources required for memory management compared to a method of accessing all of the plurality of range access counters. Optionally, providing the one or more statistical counters to the memory management component comprises: providing the at least one watermark counter; and providing at least one range access counter in the plurality of range access counters in response to a request from the memory management component. Optionally, the memory management component is configured to: perform another analysis comprising the at least one watermark counter; and send a request to the at least one memory tracking circuit to provide the at least one range access counter based on another result of the another analysis. Providing the one or more statistical counters from the at least one memory tracking circuit to the memory management component in more than one step in case of performing another analysis helps to reduce the amount of accesses to the plurality of range access counters, and reduces the amount of computational resources required for memory management compared to a method of accessing all of the plurality of range access counters, including reducing processing time, processing complexity and the amount of accesses to the at least one memory tracking circuit. Optionally, the memory management component is further configured to configure at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit. Optionally, the memory management component is configured to configure at least one of the low access threshold and the high access threshold in the at least one memory tracking circuit based on a further result of a further analysis comprising the one or more statistical counters. Configuring the low access threshold and / or the high access threshold improves the accuracy of the high access counter and the low access counter, and improves the accuracy of the memory mapping calculated based on the one or more statistical counters.

[0017] In an implementation form of the first aspect and the second aspect, the at least one memory tracking circuit is configured to update the at least one statistical counter and to provide one or more of the plurality of statistical counters while the processing unit executes the software program. Updating the at least one statistical counter and providing the one or more statistical counters while the processing unit executes the software program helps to enable runtime modification of the memory mapping of the application memory of the software program, and thus improves the system performance while the software program is executed.

[0018] In a further implementation form of the first aspect and the second aspect, the at least one memory tracking circuit comprises a plurality of local tracking circuits. Optionally, each of the plurality of local tracking circuits is connected to the processing unit and one or more of the at least one memory component; each of the plurality of local tracking circuits updates the at least one statistical counter in response to receiving the memory access command when at least one of the plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit comprises a local memory address as a memory address in the memory access command. Using a plurality of local tracking circuits improves the availability of the methods described herein in systems where at least one of the memory components is topologically far away from each other.

[0019] In a further implementation form of the first aspect and the second aspect, the application memory of the software program comprises a plurality of application memory regions, each application memory region being stored in one of the at least one memory component; the mapping of the application memory by the memory management component comprises: performing an analysis comprising the one or more statistical counters; moving at least one of the plurality of application memory regions from one of the at least one memory component to another of the at least one memory component in response to a result of the analysis. Optionally, the memory mapping component maps the application memory while the processing unit executes the software program. Moving an application memory region from one memory component to another memory component while the processing unit executes the software program helps to reduce the total amount of delay of a plurality of memory accesses performed while executing the software program and / or increase the total bandwidth of a plurality of memory accesses, improving the performance of the apparatus executing the software program. Performing an analysis comprising the one or more statistical counters increases the accuracy of the result of the analysis, such that moving at least one application memory region based on the result of the analysis improves the performance of the apparatus executing the software program compared to other methods of selecting memory regions not to be included in the one or more statistical counters collected while the processing unit executes the software program, e.g., methods using static analysis of the software program.

[0020] In a further implementation form of the first aspect and the second aspect, the at least one memory tracking circuit is further configured to, in each of one or more management iterations: perform the plurality of iterations, including updating the at least one statistical counter; provide the one or more statistical counters to the memory management component; reset one or more other statistical counters of the plurality of statistical counters.

[0021] In a further implementation form of the first and second aspects, the memory management component comprises a software object executed by the processing unit. Optionally, the memory management component comprises a memory management circuit connected to the at least one memory tracking circuit and the at least one memory component. Using a memory management circuit reduces the amount of computing resources of the processing unit required for memory management, and reduces the impact of memory management on the performance of the device executing the software program.

[0022] In a further implementation form of the first and second aspects, the processing unit is configured to execute an operating system. Optionally, the operating system addresses the at least one memory component using a plurality of operating system memory pages, each operating system memory page having one of a set of identified page sizes; at least one of the plurality of memory address ranges has a range size not equal to any of the set of page sizes. Tracking memory address ranges having a range size not equal to any of the set of page sizes of the operating system improves the accuracy of the analysis of the one or more statistical counters, and thus improves the performance of the device executing the software program.

[0023] In a further implementation form of the fourth aspect, the plurality of statistical counters comprises at least one of a high access counter, a low access counter, and a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges. Optionally, receiving the one or more statistical counters comprises receiving at least one of the high access counter and the low access counter. Optionally, the method further comprises performing an analysis comprising at least one of the low access counter and the high access counter; and based on a result of the further analysis, sending a request to the at least one memory tracking circuit to provide the at least one range access counter.

[0024] Other systems, methods, features, and advantages of the application will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the application, and be protected by the accompanying claims.

[0025] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the implementation pertains. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present disclosure, exemplary methods and / or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be limiting. BRIEF DESCRIPTION OF DRAWINGS

[0026] Some embodiments are described herein, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments only. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments can be practiced.

[0027] In the drawings:

[0028] Figure 1 is a schematic block diagram of an exemplary apparatus provided by some embodiments;

[0029] Figure 2 is a schematic block diagram of another exemplary apparatus provided by some embodiments;

[0030] Figure 3 is a schematic block diagram of an exemplary address mapping provided by some embodiments;

[0031] Figure 4 is a flowchart diagram schematically representing an optional operational flow for managing memory, provided by some embodiments;

[0032] Figure 5 is a flowchart diagram schematically representing an optional operational flow for updating a statistical counter, provided by some embodiments;

[0033] Figure 6 is a flowchart diagram schematically representing an optional operational flow for memory management, provided by some embodiments;

[0034] Figure 7 is a sequence diagram of an optional operational flow, provided by some embodiments;

[0035] Figure 8 is a schematic block diagram of an exemplary memory mapping provided by some embodiments;

[0036] Figure 9 is a schematic block diagram of another exemplary memory mapping provided by some embodiments. DETAILED DESCRIPTION

[0037] As used herein, the term "processing unit" refers to any type of programmable or non- programmable circuit that is used to perform the operations described below. The processing unit can include hardware and software. For example, the processing unit can include one or more processors and a transitory or non-transitory memory carrying a program that, when executed by the one or more processors, causes the processing unit to perform the corresponding operations.

[0038] Further, as used herein, the term "physical address" refers to an address used by a processing unit in a memory access request to access a memory component. Further, as used herein, the term "application address" refers to an address used in an application. The application address can be a virtual address, in which case the application address needs to be translated to a physical address in order to access one or more memory components. As used herein, the term "memory mapping" refers to mapping of application memory addresses of a software program to physical addresses in memory access requests sent by a processing unit. Such mapping can be used to translate application addresses to physical addresses that identify locations in a memory component where application data or instructions are stored.

[0039] Further, as used herein, the terms "memory access request" and "memory access command" are both used to refer to a request to access a memory component in order to read from and / or write to the memory component, and the terms are used interchangeably. Memory access requests can be generated when computer instructions of a software program that includes memory access computer instructions are executed.

[0040] Further, as used herein, the terms "range of memory addresses" and "memory address range" are both used to refer to a range of memory addresses, and are used interchangeably.

[0041] In order to allocate each of a plurality of application memory regions to one or more memory components connected to a processing unit, thereby improving performance of the system, some systems track accesses to the one or more memory components. Some existing tracking methods maintain access counters in page tables used to map application addresses to physical addresses. Such methods require updating the counters in the page tables each time a memory is accessed. Further, analyzing the plurality of counters in the page tables requires consolidating counters of multiple virtual pages that map to a common physical page. Additionally, some methods require sorting the plurality of counters to categorize the page table entries, for example, to identify page table entries that describe high access application memory regions. Such methods degrade performance of the system as they require computational resources of the processing unit.

[0042] In some other methods of tracking memory accesses, a processing unit maintains a plurality of counters stored in one or more memory components. In systems implementing such methods, each memory access request from the processing unit requires the processing unit to access the memory twice: once to update the counter and once to access data in the memory, thereby degrading effective throughput of the memory (i.e., access to application memory regions).

[0043] To reduce the amount of computer resources used by a processing unit to track a plurality of memory accesses, in some embodiments described herein, the inventors propose using one or more memory management circuits connected to the processing unit and one or more memory components to update at least one of a plurality of statistical counters in response to receiving a memory access command from the processing unit. Optionally, the statistical counter is indicative of a plurality of memory access commands. For example, when the processing unit has a plurality of memory address ranges and each of the one or more memory components is mapped to one or more of the plurality of memory address ranges, the statistical counter can be a range access counter associated with a memory address range, indicative of a number of times the memory address range is accessed in the plurality of memory access commands. Optionally, the statistical counter is indicative of an amount of range access counters that satisfy an identified criterion. For example, the statistical counter can be a watermark counter, indicative of an amount of range access counters that exceed a high access threshold, where the high access threshold is indicative of an amount of accesses to a memory address range deemed high. Or, the watermark counter can be indicative of an amount of range access counters that are less than a low access threshold, where the low access threshold is indicative of another amount of accesses to a memory address range deemed low. Optionally, the statistical counter is indicative of an amount of memory access commands received from the processing unit. Optionally, the one or more processing circuits receive a memory access command in each of a plurality of iterations and update at least one of the plurality of statistical counters in each of the plurality of iterations. Using the one or more processing circuits to update the at least one statistical counter reduces the amount of resources used by the processing unit to track the plurality of memory accesses, for example, reduces an amount of memory accesses performed by the processing unit and / or reduces an amount of processor cycles of the processing unit used to compute memory mappings. Reducing the amount of computer resources used by the processing unit improves performance of the system when executing a software program, for example, by increasing throughput and / or reducing latency when executing one or more tasks of the software program.

[0044] Optionally, at least one of the plurality of statistical counters is implemented in the one or more memory tracking circuits to further reduce an amount of accesses to the one or more memory components, thereby improving performance of the system.

[0045] In addition, in some embodiments, the present application proposes that one or more memory tracking circuits provide one or more of a plurality of statistical counters to a memory management component for mapping application memory of a software program to one or more memory components. Optionally, the memory management component analyzes the one or more statistical counters for mapping the application memory. Optionally, the memory management component comprises a software object executed by the processing unit. Optionally, the memory management component comprises other circuitry that is optionally connected to the one or more memory tracking circuits and the one or more memory components. Providing the one or more statistical counters to the memory management component facilitates improving system performance by moving one or more of a plurality of application memory regions of the software program from one of the one or more memory components to another of the one or more memory components. For example, a range access counter for a range of memory addresses that exceeds a high access threshold can indicate that the range of memory addresses is frequently accessed, and an application memory region of the plurality of application memory regions referenced by the range of memory addresses should be stored in a memory component having relatively high performance access characteristics (e.g., low latency and / or high throughput). Similarly, another range access counter for another range of memory addresses that is below a low access threshold can indicate that the other range of memory addresses is infrequently accessed, and another application memory region of the plurality of application memory regions referenced by the other range of memory addresses should be stored in another memory component having relatively low performance access characteristics (e.g., higher latency and / or lower throughput than the memory component having relatively high performance access characteristics). Optionally, the memory mapping component maps the application memory while the processing unit executes the software program, optionally moves the one or more application memory regions while the processing unit executes the software program.

[0046] In some embodiments described herein, the at least one memory component is a plurality of memory components comprising at least two memory components. Optionally, the one or more memory tracking circuits comprise a plurality of local tracking circuits such that each local tracking circuit of the plurality of local tracking circuits is connected to one or more of the plurality of memory components. Optionally, each local tracking circuit is connected to a subset of the plurality of memory components such that the local tracking circuit is not connected to at least one of the plurality of memory components. Optionally, each local tracking circuit updates the at least one statistical counter in accordance with the one or more memory components connected thereto when at least one memory address range of a plurality of memory address ranges associated with the one or more memory components connected to the local tracking circuit comprises a local memory address in the memory address command. The local tracking circuit connected to the at least one memory component is optionally additionally connected to the host memory controller when the processing unit is connected to the at least one memory component through the host memory controller.

[0047] Optionally, when the one or more memory tracking circuits provide the one or more statistical counters to the memory management component, the one or more statistical counters include one or more watermark counters. Optionally, the memory management component performs another analysis of the one or more watermark counters, and based on a result of the other analysis, the memory management component optionally sends a request to the one or more memory tracking circuits to provide at least one range access counter. For example, the memory management component can request the at least one range access counter only when the result of the other analysis indicates that the high watermark counter exceeds an identified threshold. In this example, as long as the amount of ranges experiencing high access is below the threshold, there can be no need to move the memory region. This requires less computational resources than some other approaches that require reading all of the multiple range access counters to identify that there is no need to move the memory region. In another example, the memory management component can request the one or more range access counters until receiving an amount of range access counters that exceeds a high watermark threshold equal to the high watermark counter. In this example, identifying all of the memory regions experiencing high access rates can be achieved without reading all of the multiple memory counters, which requires less computational resources than some other approaches that do not use watermark counters.

[0048] When the processing unit executes the operating system, the operating system can address the multiple memory components using a plurality of operating system memory pages. It is a common practice to use an arbitrary page size for the plurality of operating system memory pages, i.e., each of the plurality of operating system memory pages has one of a set of identified page sizes. When performing memory access tracking using the page tables of the operating system, the granularity of the memory access tracking is according to the respective page size of each of the plurality of operating system memory pages. In some embodiments described herein, at least one of the plurality of memory address ranges has a range size that is not equal to any of the set of page sizes. Tracking the plurality of memory access commands according to the plurality of memory address ranges using the one or more memory tracking circuits supports tracking the plurality of memory access commands at a granularity that is different from the page size of the operating system, which improves the accuracy of the memory mapping calculated from the plurality of statistical counters compared to the memory mapping calculated when tracking according to the operating system page size, which improves the accuracy of allocating the plurality of application memory regions to the one or more memory components, which improves the performance of the system.

[0049] Before at least one embodiment is described in detail, it is to be understood that the embodiments are not limited in their application to the details of construction and the arrangement of the components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. The implementations described herein support other embodiments or are amenable to different ways of practicing or executing.

[0050] Embodiments can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out operations described herein.

[0051] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the foregoing. Computer readable storage media used in the disclosure can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any suitable combination of the foregoing. The disclosure is not limited to the above examples of computer readable storage media, but can include any computer readable storage media that can be used to store and access computer readable instructions and / or data.

[0052] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0053] Computer readable program instructions for carrying out operations of an embodiment can be in assembly code, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object-oriented programming language such as Smalltalk, C++, Java, or Visual Basic, and conventional procedural programming languages, such as the "C" programming language, Fortran or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), and the connection can be made through external computer or through an Internet service provider. In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to customize the electronic circuitry, in order to perform aspects of an embodiment.

[0054] Aspects of the embodiments are provided herein with reference to the flow diagrams and / or block diagrams of the methods, apparatuses (systems) and computer program products according to this disclosure. It is understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions.

[0055] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions for causing an apparatus to implement various aspects of the functions / acts specified in the flowchart and / or block diagram block or blocks is produced.

[0056] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0057] The flow and block diagrams in the figures illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products

[0058] Reference will now be made to the Figure 1 which shows a schematic block diagram of an exemplary apparatus 100 provided by some embodiments. In these embodiments, a processing unit 101 is connected to at least one memory component 120.

[0059] For brevity, hereafter, the term "memory components 120" is used to mean "at least one memory component 120" and these terms are used interchangeably. Optionally, the memory components 120 include one memory component, such as memory component 120C. Optionally, the memory components 120 include more than one memory component, such as memory component 120A, memory component 120B, and memory component 120C. The memory components can be random access memory (RAM) components, such as SRAM components or DRAM components. Other examples of memory components include read-only memory (ROM) components, electrically erasable programmable ROM (EEPROM), and non-volatile RAM (NVRAM). Optionally, one or more of the memory components 120 are electrically coupled to the processing unit 101. Optionally, one or more of the memory components 120 are connected to the processing unit 101 through a host memory controller (not shown).

[0060] Optionally, one or more of the memory components 120 are cache memory components of the processing unit 101. Optionally, one or more of the memory components 120 are connected to another cache memory component (not shown) that is additionally connected to the processing unit 101.

[0061] Optionally, one or more of the memory tracking circuits 130 are connected to the processing unit 101 and the memory components 120.

[0062] Reference is now also made to Figure 2 which shows a schematic block diagram of another exemplary apparatus 200 provided by some embodiments. In these embodiments, the one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, such as including local tracking circuit 201A and local tracking circuit 201B. Optionally, each of the plurality of local tracking circuits 201 is connected to one or more of the memory components 120. Optionally, each of the plurality of local tracking circuits is connected to a subset of the memory components 120, such that each of the plurality of local tracking circuits 201 is not connected to at least one of the memory components 120. In the present example, local tracking circuit 201A is connected to memory component 120A and memory component 120B, and is not connected to memory component 120C. Further, in the present example, local tracking circuit 201B is connected to memory component 120C, and is not connected to memory component 120A and memory component 120B. Optionally, each of the plurality of local tracking circuits 201 is connected to one of the memory components 120.

[0063] Reference is now again made to Figure 1Optionally, each of the memory components 120 is mapped to at least one of a plurality of memory address ranges of the processing unit 101.

[0064] Now also referring to Figure 3 which shows a schematic block diagram of an exemplary address mapping 300 provided by some embodiments. In this example, the memory component 120A is mapped to the memory address range 301 A, the memory address range 301B, and the memory address range 301C of the plurality of memory address ranges 301. Thus, when the processing unit 101 accesses one of the memory address range 301A, the memory address range 301B, and the memory address range 301C, the processing unit 101 accesses the memory component.

[0065] Similarly, the memory component 120B is mapped to the memory address range 301D of the plurality of memory address ranges 301, and the memory component 120C is mapped to the memory address range 301E and the memory address range 301F of the plurality of memory address ranges 301.

[0066] Optionally, the processing unit 101 executes an operating system that addresses the memory components 120 using a plurality of operating system memory pages. Optionally, each of the plurality of operating system memory pages has a page size that is one of a set of identified page sizes. Optionally, a size of at least one of the plurality of memory address ranges 301 is not a member of the set of identified page sizes.

[0067] Now again referring to Figure 1 Optionally, one or more memory tracking circuits 130 are connected to the memory management component 110. Optionally, the memory management component 110 comprises a software object executed by the processing unit 101. Optionally, the memory management component 110 comprises a memory management circuit additionally connected to the processing unit 101 and the memory components 120.

[0068] According to some embodiments, in order to track memory access commands and manage memory, the following optional methods can be implemented by the system 100 or the system 200.

[0069] Now also referring to Figure 4Fig. 4 shows a flowchart illustrating an exemplary operation flow 400 for managing memory, according to some embodiments. In these embodiments, at 401, one or more memory tracking circuits 130 receive a memory access command including a memory address from a processing unit 101. Optionally, the memory address is in one of a plurality of memory address ranges 301. For example, when the memory address is in memory address range 301E, the memory address is a local memory address of memory component 120C. In this example, memory address range 301E includes the local memory addresses of memory component 120C, which is the memory address in the memory access command. Optionally, the processing unit 101 sends the memory access command while executing a software program, optionally, for accessing application memory of the software program.

[0070] At 410, the one or more memory tracking circuits 130 optionally update at least one of a plurality of statistical counters. Optionally, the plurality of statistical counters includes a plurality of range access counters, each range access counter being associated with one of the plurality of memory address ranges 301. Optionally, the plurality of statistical counters includes one or more watermark counters, each watermark counter being associated with a frequency of access to a memory component. A watermark counter can indicate an amount of memory access ranges accessed at the frequency associated with the watermark counter. A watermark counter can be a high access counter indicating an amount of range access counters in the plurality of range access counters that exceed a high access threshold, thereby indicating frequent access to respective memory components associated with the range access counters that exceed the high access threshold. For example, a range access counter of memory address range 301F that exceeds the high access threshold can indicate frequent access to memory component 120C associated with memory address range 301F. Another example of a watermark counter is a low access counter indicating an amount of range access counters in the plurality of range access counters that exceed a low access threshold. There can be more than two watermark counters, each watermark counter being associated with one of a plurality of frequencies of access to a memory component. Each watermark counter of the more than two watermark counters can be associated with an access threshold indicating the frequency of access associated therewith, i.e., indicating an amount of range access counters in the plurality of range access counters that exceed the threshold associated with the watermark counter.

[0071] Optionally, at least one of the plurality of statistical counters is implemented in the one or more memory tracking circuits 130. Optionally, at least one other statistical counter of the plurality of statistical counters is implemented in one of the memory components 120. Optionally, the one memory component implementing the at least one other statistical counter is a cache memory component of the processing unit 101. Optionally, at least one other statistical counter of the plurality of statistical counters is implemented in another cache memory component connected to one or more of the memory components 120.

[0072] Reference is now also made to Figure 5 FIG. 5 shows a flowchart schematically representing an optional operational flow 500 for updating statistical counters, according to some embodiments. In these embodiments, at 501, the one or more memory tracking circuits 130 identify the memory address in the memory access command received at 401. At 502, the one or more memory tracking circuits 130 optionally identify a memory address range in the plurality of memory address ranges 301, wherein the memory address range includes the memory address. For example, the memory command can include a memory address within the memory address range 301F. In this example, the one or more memory tracking circuits 130 identify the memory address range 301F. Optionally, at 510, the one or more memory tracking circuits 130 increase a respective range access counter in the plurality of range access counters associated with the memory address range 301F. When the one or more memory tracking circuits 130 include a plurality of local tracking circuits 201, each local tracking circuit in the plurality of local tracking circuits 201 updates at least one statistical counter when at least one memory address range in the plurality of memory address ranges 301 associated with one or more memory components connected to the local tracking circuit includes the memory address of the memory access command. For example, when the local tracking circuit 201B identifies that the memory address of the memory access command is within the memory address range 301F associated with the memory component 120C connected to the local tracking circuit 201B, the local tracking circuit 201B can update one or more statistical counters.

[0073] At 520, the one or more memory tracking circuits 130 optionally determine whether the respective range access counter associated with the memory address range 301F exceeds the low access threshold, and in the event that the one or more memory tracking circuits 130 determine that the respective range access counter associated with the memory address range 301F exceeds the low access threshold, at 521, the one or more memory tracking circuits 130 optionally decrease the low access counter. At 530, the one or more memory tracking circuits 130 optionally determine whether the respective range access counter associated with the memory address range 301F exceeds the high access threshold, and in the event that the one or more memory tracking circuits 130 determine that the respective range access counter associated with the memory address range 301F exceeds the high access threshold, at 531, the one or more memory tracking circuits 130 optionally increase the high access counter. When the one or more watermark counters include more than two watermark counters, the one or more tracking circuits 130 optionally determine for each of the more than two watermark counters whether the respective range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, and in the event that the one or more memory tracking circuits 130 determine that the respective range access counter associated with the memory address range 301F exceeds the threshold associated with the watermark counter, the one or more memory tracking circuits 130 optionally increase the watermark counter.

[0074] Now referring again to Figure 4 Optionally, the one or more memory tracking circuits 130 perform 401 and 410 while the processing unit 101 executes the software program. Optionally, the one or more memory tracking circuits 130 repeat 401 and 410 in each of a plurality of iterations.

[0075] In 420, the one or more memory tracking circuits 130 optionally provide one or more of the plurality of statistical counters to the memory management component 110, optionally for mapping application memory of the software program to the memory component 120. Optionally, the one or more memory tracking circuits 130 provide the one or more statistical counters while the processing unit 101 executes the software program. Optionally, the memory mapping component 110 maps the application memory to the memory component 120 while the processing unit 101 executes the software program.

[0076] Now referring again to Figure 6 which shows an optional operational flow 600 for memory management provided by some embodiments. In these embodiments, in 601, the memory management component 110 performs an analysis of the one or more statistical counters. The following are exemplary, non-mandatory methods for performing the analysis.

[0077] Now also referring to Figure 7Fig. 7 illustrates a sequence diagram of an optional operational flow 700 provided by some embodiments. In these embodiments, at 701, one or more memory tracking circuits 130 provide one or more watermark counters to the memory management component 110. Optionally, the one or more memory tracking circuits 130 provide a subset of the one or more watermark counters at 701, such as only one of the one or more watermark counters. Optionally, the one or more watermark counters include a high access counter. Optionally, the one or more watermark counters include a low access counter. At 702, the one or more memory tracking circuits 130 perform another analysis that includes the one or more watermark counters. Based on a result of the other analysis, at 710, the memory management component 110 optionally sends a request to the one or more memory tracking circuits 130 to provide at least one range access counter of a plurality of range access counters. For example, when the result of the other analysis indicates that a watermark counter exceeds a frequency threshold, the memory mapping component can request the at least one range access counter in order to identify which of a plurality of memory address ranges is frequently accessed. On the other hand, when the result of the other analysis indicates that a watermark counter does not exceed a frequency threshold, the memory mapping component 110 can decline to perform the other analysis and decline to modify a mapping of application memory of a software program. The other analysis can use one of the one or more watermark counters, such as when only one watermark counter is implemented. The other analysis can use more than one of the one or more watermark counters. When the one or more watermark counters include at least one of a low access counter and a high access counter, the other analysis optionally includes at least one of the low access counter and the high access counter.

[0078] In response to receiving the request from the memory management component 110, at 711, the one or more memory tracking circuits 130 optionally send the at least one range access counter to the memory management component 110. Optionally, 710 and 711 are repeated in a plurality of read iterations. Optionally, at 711, the one or more memory tracking circuits 130 send one range access counter to the memory management component 110 such that the memory management component 110 accesses one or more range access counters at a time. Optionally, at each performance of 711, the one or more memory tracking circuits 130 send a subset of the plurality of range access counters to the memory management component 110. Optionally, the management component 110 declines to perform 710 in the case of identifying a stopping condition, such as receiving a quantity of range access counters that exceeds a threshold equal to a value of the watermark counter provided at 701.

[0079] Now referring again to Figure 6 Based on a result of the analysis performed at 601, the memory management component 110 optionally performs one or more memory management tasks, such as mapping application memory of a software program. Another example of a memory management task is configuring the one or more memory tracking circuits 130.

[0080] Now also referring to Figure 8 illustrates a schematic block diagram of an example memory mapping 800 provided by some embodiments. Optionally, the application memory of the software program includes a plurality of application memory regions 801, for example including memory application region 801 A, memory application region 801 B, and memory application region 801 C. Optionally, each of the plurality of memory application regions is stored in one of the memory components 120. For example, application memory region 801 A can be stored in memory component 120A, application memory region 801 B can be stored in memory component 120B, and application memory region 801 C can be stored in memory component 120C.

[0081] Now again referring to Figure 6 In 610, in response to the analysis performed in 601 (for example, using method 700), the memory management component 110 can move one or more of the plurality of application memory regions 801 from one of the memory components 120 to another of the memory components 120.

[0082] Now also referring to Figure 9 illustrates a schematic block diagram of another example memory mapping 900 provided by some embodiments. In this example, the result of the analysis can be, for example, that the memory management component 110 moves the application memory region 801 A from the memory component 120A to the memory component 120C when the memory component 120C has higher performance access characteristics than the memory component 120A and the result of the analysis indicates high frequency access to the application memory region 801 A. Optionally, the memory management component 110 updates the mapping between the application memory and one or more of the plurality of memory address ranges 301, for example in the page table of the operating system executed by the processing unit 101.

[0083] Now again referring to Figure 7 In 721, the memory management component 110 optionally configures one or more watermark thresholds, for example a high watermark threshold or a low watermark threshold, in one or more of the memory tracking circuits 130. Optionally, in 720, the memory management component 110 performs a further analysis of the one or more statistical counters and performs 721 in accordance with a further result of the further analysis. For example, the memory management component 110 can lower the high watermark threshold when the memory component having high performance access characteristics is underutilized. Similarly, the memory management component 110 can raise the high watermark threshold when the memory component having high performance access characteristics is overused.

[0084] Now again referring to Figure 4At 430, the one or more memory tracking circuits 130 optionally reset one or more other counters of the plurality of statistical counters. For example, at 420, the one or more memory tracking circuits 130 can reset the statistical counter after providing the statistical counter to the memory management component 110. Resetting the counter can be setting the counter to zero. Resetting the counter can be setting the counter to an initial value. For example, the low access counter can start at a value equal to the amount of memory components 120 in the memory component 120 and decrease at 521 for each range access counter that exceeds the low watermark threshold.

[0085] Optionally, the one or more memory tracking circuits 130 repeatedly perform a plurality of iterations including 401 and 410, provide the one or more statistical counters at 420, and reset one or more other counters in each of the plurality of management iterations.

[0086] The description of the various embodiments is merely intended to be illustrative and not exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0087] It is expected that during the life of a patent maturing from this application many relevant memory tracking circuits will be developed and the scope of the term memory tracking circuit is intended to include all such new technologies a priori.

[0088] The term "about" is used herein to refer to ±10%.

[0089] The terms "comprising," "having," and like terms vary inclusions within the specification, the terms "consisting of and "consisting essentially of limit the scope of the claims accordingly.

[0090] The phrase "consisting essentially of indicates that the composition or method can include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0091] The singular forms "a," "an," and "the" used herein include plural referents unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" can include a plurality of compounds, including mixtures thereof.

[0092] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0093] The word "optionally" is used herein to mean "may or can not be present." Any particular embodiment can include a plurality of "optional" features, unless such features conflict.

[0094] In this application, various embodiments can be presented through a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the embodiments. Accordingly, the description of a range should be considered to have specifically disclosed all possible subranges as well as individual numerical values within that range. For example, a description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.

[0095] When a range of numbers is indicated herein, any number (fractional or integral) within the indicated range is included. The phrases "a range between a first indicated number and a second indicated number" and "a range from a first indicated number to a second indicated number" are used herein interchangeably and are meant to include all fractions and integers within the indicated range.

[0096] It should be understood that certain features of the embodiments described in the context of separate embodiments can also be provided, combined, or divided in a single embodiment. Conversely, various features of the embodiments described in the context of a single embodiment can also be implemented in separate embodiments or in any suitable sub-combination or as appropriate. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiments are inoperative without those elements.

[0097] While embodiments have been described in connection with their specific embodiments, it will be readily apparent to those skilled in the art that numerous substitutions, modifications and changes can be made thereto without departing from the spirit and scope of the application as set forth in the appended claims.

[0098] It is the intent of the Applicant that all publications, patents and patent applications referred to in this specification be incorporated in their entirety by reference into the specification, as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated by reference in its entirety. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to the present application. To the extent that section headings are used, they should not be construed as necessarily limiting. In addition, any priority document(s) of this application is / are hereby incorporated by reference in its / their entirety.

Claims

1. A method for migrating data in a memory, the method comprising: The method is applied to a memory system, the memory system comprising a memory tracking circuit, a memory management component, a first memory component and a second memory component comprising: The memory tracking circuit tracks a memory access command sent from a processing unit, the memory access command accessing an application memory region located in the first memory component or the second memory component, the memory access command being dynamically generated by a software program; The memory tracking circuit updates at least one statistical counter based on the tracked memory access command, the at least one statistical counter indicating an access frequency of the application memory region; The memory tracking circuit provides the at least one statistical counter to the memory management component; The memory management component accesses the at least one statistical counter and moves the application memory region between the first memory component and the second memory component based on statistical data in the at least one statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory region is a memory region frequently accessed by the software program.

2. The method of claim 1, wherein, The memory management component manages a plurality of application memory regions, the plurality of application memory regions comprising the application memory region, the plurality of application memory regions corresponding to a plurality of memory address ranges.

3. The method according to claim 1 or 2, characterized in that, The memory tracking circuit tracks a memory access command sent from a processing unit, updates at least one statistical counter, comprising: The memory access command comprises a first address, based on the first address, a first memory address range corresponding to the first address is determined, and a first statistical counter corresponding to the first memory address range is updated.

4. The method of claim 3, wherein, The first memory address range corresponds to the first memory component.

5. The method of claim 2, wherein, The moving of the application memory region between the first memory component and the second memory component based on statistical data in the at least one statistical counter comprises: The memory management component performs an analysis of the at least one statistical counter; Based on a result of the analysis, at least one application memory region of the plurality of application memory regions is moved from the first memory component to the second memory component, wherein the plurality of application memory regions are memory regions accessible by the software program.

6. The method of claim 5, wherein, A memory mapping component maps the plurality of application memory regions while the processing unit executes the software program.

7. The method of claim 2, wherein, Comprising: At least one memory address range of the plurality of memory address ranges is not equal to a range size of any one page size of a set of page sizes.

8. A method for migrating memory data, the method comprising: The method is performed by a memory tracking circuit, comprising: Tracking a memory access command sent from a processing unit, the memory access command accessing an application memory region located in the first memory component or the second memory component, the memory access command being dynamically generated by a software program Updating at least one statistical counter based on the tracked memory access command, the at least one statistical counter indicating an access frequency of the application memory region; providing the at least one statistical counter to a memory management component, so that the memory management component moves the application memory region between a first memory component and a second memory component, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory region is a region frequently accessed by the software program.

9. The method of claim 8, wherein, The tracking of the memory access command sent from the processing unit, updating at least one statistical counter, includes: The memory access command includes a first address, based on the first address, determining a first memory address range corresponding to the first address, and updating a first statistical counter corresponding to the first memory address range.

10. The method of claim 9, wherein, The first memory address range corresponds to the first memory component.

11. The method of claim 9, wherein, The memory management component manages a plurality of application memory regions, the plurality of application memory regions includes the application memory region, and the plurality of application memory regions corresponds to a plurality of memory address ranges, At least one memory address range in the plurality of memory address ranges is not equal to the range size of any one page size in the set of page sizes.

12. A memory management system, characterized by including, a processing unit, a memory tracking circuit, a memory management component, and a plurality of memory components, the memory components including a first memory component and a second memory component, wherein the memory tracking circuit connects the processing unit, the first memory component, and the second memory component: The memory tracking circuit is used to track the memory access command sent from the processing unit, the memory access command accesses the application memory region located in the first memory component or the second memory component, and the memory access command is dynamically generated by a software program; The memory tracking circuit updates at least one statistical counter based on the tracked memory access command, and the at least one statistical counter indicates the access frequency of the application memory region; The memory tracking circuit is also used to provide the at least one statistical counter to the memory management component; The memory management component is used to access the at least one statistical counter, and move the application memory region between the first memory component and the second memory component according to the at least one statistical counter, wherein the second memory component has higher performance access characteristics than the first memory component, and the application memory region is a frequently accessed memory region of the software program.

13. The memory management system of claim 12, wherein, including: The at least one statistical counter is located in the memory tracking circuit.

14. The memory management system of claim 12, wherein, including: The at least one statistical counter is located in the first memory component or the second memory component.

15. The memory management system according to any one of claims 12-14, wherein, The memory management component is also used to manage a plurality of application memory regions, the plurality of application memory regions includes the application memory region, and the plurality of application memory regions corresponds to a plurality of memory address ranges.

16. The memory management system according to any one of claims 12-15, wherein, The memory tracking circuit tracks the memory access command sent from the processing unit, and updates at least one statistical counter, specifically including: The memory access command includes a first address, based on the first address, determining a first memory address range corresponding to the first address, and updating a first statistical counter corresponding to the first memory address range.

17. The memory management system of claim 16, wherein, The first memory address range corresponds to the first memory component.

18. The memory management system of claim 13, wherein, The moving the application memory region between the first memory component and the second memory component according to the at least one statistical counter specifically includes: The memory management component performs analysis of the at least one statistical counter; Based on a result of the analysis, moving at least one application memory region of a plurality of application memory regions from the first memory component to the second memory component, wherein the plurality of application memory regions are memory regions accessible by the software program.

19. The memory management system of claim 18, wherein, The memory management system further comprises a memory mapping component configured to map the plurality of application memory regions when the processing unit executes the software program.

20. The memory management system of claim 13, wherein, Comprise: At least one memory address range of the plurality of memory address ranges is not equal to a range size of any one page size of a set of page sizes.

21. A memory trace circuit, comprising: The memory tracking circuit is configured to perform the method of any one of claims 8-11.

Images