Channel architecture for memory devices

Abstract

Systems, apparatuses, and methods related to channel architectures for memory devices are described. Various applications may access data from the memory device through multiple channels. The channel may be selectively enabled or disabled based on behavior of the application. For example, a device in the form of a memory system may include an interface coupled to a controller and a plurality of channels. The controller may be configured to: determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller through the plurality of channels; and disabling one or more channels of the plurality of channels based at least in part on the aggregated amount of bandwidth used by the plurality of applications.

Description

[0001] Information about divisional applications

[0002] This case is a divisional application. The parent case of the divisional application is an invention patent application with an application date of June 17, 2020, an invention name of “Channel architecture of memory device”, and an application number of 202010555368.X. Technical Field

[0003] The present disclosure relates generally to semiconductor memories and methods, and more particularly to apparatus, systems, and methods for channel architectures of memory devices. Background Art

[0004] Memory devices are usually provided in a computer or other electronic system in the form of an internal semiconductor integrated circuit. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM) and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining the stored data when power is not supplied, and can include NAND flash memory, NOR flash memory and resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STTRAM), etc.

[0005] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host and / or applications running on the host while the computer or electronic system is operating. For example, during operation of an application running on a host, computing system, or other electronic system, data, commands, and / or instructions may be transferred between the host and one or more memory devices. Summary of the invention

[0006] One aspect of the present application relates to an apparatus comprising: an interface; and a controller coupled to the interface and a plurality of channels, wherein the controller is configured to: determine an aggregate amount of bandwidth used by a plurality of applications accessing data from a memory device, the memory device being coupled to the controller through the plurality of channels; and disable one or more of the plurality of channels based at least in part on the aggregate amount of bandwidth used by the plurality of applications.

[0007] Another aspect of the present application relates to an apparatus comprising: an interface; and a controller coupled to the interface and a plurality of channels, wherein the controller is configured to: determine an aggregate bandwidth usage of a plurality of applications accessing data from a memory device, the memory device being coupled to the controller through the plurality of channels; identify one or more channels of the plurality of channels for accessing the data; and disable a subset of the one or more channels of the plurality of channels based at least in part on the aggregate bandwidth usage of the plurality of applications.

[0008] Another aspect of the present application relates to a method, comprising: determining, by a controller, an aggregate amount of bandwidth used in the execution of multiple applications; determining, by the controller, channels between the controller and one or more memory devices for accessing data as part of the execution of the multiple applications; and disabling one or more of the channels based at least in part on the aggregate amount of bandwidth used in the execution of the multiple applications.

[0009] Yet another aspect of the present application relates to a system, the system comprising: a host; a memory device, the memory device comprising a controller, a multiplexer, and a memory device, wherein the memory device is coupled to the host, and wherein the controller is configured to: determine an amount of bandwidth consumed in execution of a corresponding application executed by the host; and assert, based at least in part on the amount of bandwidth consumed in execution of the corresponding application, signals to a plurality of select pins coupled to the multiplexer to disable one or more channels utilized by the application to access data from the memory device during execution of the application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a functional block diagram of a computing system including a device including a memory system in accordance with several embodiments of the present disclosure.

[0011] Figure 2 is a functional block diagram in the form of a device including front-end bandwidth requirements according to several embodiments of the present disclosure.

[0012] Figure 3 is another functional block diagram in the form of a device incorporating front-end bandwidth requirements in accordance with several embodiments of the present disclosure.

[0013] Figure 4 is another block diagram in the form of a computing system including a memory system in accordance with several embodiments of the present disclosure.

[0014] Figure 5 is a flow chart of a channel architecture for a memory device according to several embodiments of the present disclosure.

[0015] Figure 6 is a flow chart representing an example method for a channel architecture for a memory device according to several embodiments of the present disclosure.

[0016] Figure 7 is another flow chart representing an example method for a channel architecture for a memory device according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] Systems, devices, and methods are described that relate to a channel architecture for a memory device. Various applications may access data from a memory device through multiple channels. The channels may be selectively enabled or disabled based on the behavior of the applications. For example, a device in the form of a memory system may include an interface coupled to a controller and multiple channels. The controller may be configured to: determine an aggregate amount of bandwidth used by multiple applications accessing data from a memory device, the memory device being coupled to the controller through the multiple channels; and disable one or more of the multiple channels based at least in part on the aggregate amount of bandwidth used by the multiple applications.

[0018] Memory devices, such as flash memory devices, can be used to store data in a computing system, and such data can be transferred between hosts associated with the computing system and / or between applications running on the hosts associated with the computing system. The data stored in the memory device may be important or even critical to the operation of the computing system and / or one or more applications running on the host. Flash memory devices are used as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption.

[0019] A memory device that stores data in a memory unit may be included in a memory system. The data may be accessed by an application running on a host through a channel coupled to a controller (e.g., a media controller, a memory device controller, etc.). The channel may include a back-end channel of the controller. The memory device controller may be a media controller tightly coupled to a memory device (e.g., a memory unit, a block, a segment, etc. of a memory device), such as a non-volatile memory express (NVMe) controller.

[0020] The channel can communicatively couple the application to the memory device and facilitate the transfer of data to the storage area device and from the memory device to the application for execution. When the channel is enabled to transfer data from the memory to the application, enabling the application to run on the host can utilize power from the memory system. The amount of power used can depend on the number of channels enabled to facilitate the execution of the application. For example, when the application accesses data from the memory device coupled to the controller, the amount of power used can depend on the characteristics of the application, which can correspond to the number of channels enabled.

[0021] The amount of power consumed in the execution of an application may be determined by the bandwidth requirements of the application and may be referred to herein as bandwidth requirements. In some embodiments, an application may be run on the front end of a memory system, and the amount of bandwidth required to execute the operation of the application may be referred to as the front end bandwidth requirement. However, in some methods, additional channels required to execute the application and meet the bandwidth requirements may be enabled. An application may have the same and / or different bandwidth requirements for executing operations, and may correspond to a single channel to receive data from a memory device, or a single channel that multiple applications may share to receive data. In some methods, each enabled channel may consume a threshold amount of power regardless of the one or more applications that provide data. The power consumption of a memory system may increase the temperature of the memory system, waste resources, and / or reduce efficiency. Thus, disabling redundant channels may save resources and increase efficiency.

[0022] In some approaches, a memory system may be designed to run a limited number of applications to maintain a steady-state temperature and efficiency level. As the number of applications requesting data from the memory device of the memory system increases, the memory system may experience application execution failures, or an increase in temperature that may cause failures in the execution of the application. In some approaches, this temperature increase can be mitigated by using a cooling system that can reduce application execution failures and other adverse thermal effects. However, such a cooling system may require space (e.g., footprint) and / or additional processing resources in the memory system to maintain an appropriate temperature for the application that extracts data from the memory to operate effectively.

[0023] Because the amount of space available on a memory device (and therefore, the amount of space available to provide processing resources and / or cooling systems) may be limited due to various constraints such as form factor, cell density, memory array architecture, power limitations, and / or desired storage capacity, it is difficult to provide sufficient processing resources on the memory device to operate additional channels and / or provide cooling for the memory device while serving data stored by the memory device. Therefore, the performance efficiency of the memory device may be limited in some ways due to form factor and / or power consumption limitations.

[0024] As the storage capacity of the memory devices increases, these effects may become more significant, as more and more data can be stored by the memory and thus becomes accessible to applications running on the host. This may result in an increase in the number of channels required to provide data stored on the application. These effects may be further exacerbated by some methods of limiting power management on the memory system as described above, especially as the amount of data stored in the memory devices increases and the speed at which data is retrieved increases.

[0025] In contrast, embodiments herein relate to a channel architecture for providing data to applications using a modular design based on the amount of bandwidth required by the applications to access the data and / or the amount of bandwidth consumed in the execution of the applications. For example, in some embodiments, a memory system can reduce its power usage by disabling channels that are not needed to provide data to an application. The operations of an application can be consolidated to utilize fewer channels to increase the amount of power used by the memory system.

[0026] As described herein, a controller can determine the bandwidth requirements of applications running on a host and / or that can communicate with the host. The controller can selectively disable one or more channels that are not needed to provide data to the application and meet the bandwidth requirements. In some instances, the disabled channel may not be used to provide data to the application. In other instances, operations previously performed by the selectively disabled channel can be shifted to a different (e.g., enabled) channel. The action of shifting operations from selecting a channel to be disabled to an enabled channel can be referred to as "integration." Enabling a channel reduces the amount of power of the memory system, which can save resources and reduce the temperature of the memory system.

[0027] Additionally, in some embodiments, the controller may be prompted to aggregate the amount of bandwidth consumed by an increase in the temperature of the memory device or an increase / decrease in the number of applications accessing data during the execution of the application. The aggregation of the amount of bandwidth required may include the controller checking the number, activity level, and / or priority level of the applications connected to the host. The controller may enable and / or disable channels that independently provide data to the application, so that any encryption, error correction, or media management logic is saved when the channels are enabled, disabled, and / or consolidated.

[0028] In the following detailed description of the present disclosure, reference is made to the accompanying drawings, which form a part of the detailed description and in which it is shown by way of illustration how one or more embodiments of the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one of ordinary skill in the art to practice the embodiments of the present disclosure, and it is understood that other embodiments may be utilized and that process changes, electrical changes, and structural changes may be made without departing from the scope of the present disclosure.

[0029] As used herein, indicators such as "N", "M", "P", "Q", etc., especially indicators with respect to the reference numerals in the accompanying drawings, indicate that several of the specific features so designated may be included. It should also be understood that the terms used herein are for the purpose of describing specific embodiments only and are not intended to be restrictive. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" may include both singular and plural references. In addition, "several", "at least one", and "one or more" (e.g., several memory devices) may refer to one or more memory devices, however "multiple" is intended to refer to more than one such item. In addition, throughout this application, the words "can" and "may" are used in a permissive sense (i.e., it is possible, able to) rather than a mandatory sense (i.e., must). The term "include" and its derivatives mean "including but not limited to". The terms "coupled" and "coupling" mean a direct or indirect connection, either physically or for accessing and moving (transferring) commands and / or data, as the case may be. The terms "data" and "data values" are used interchangeably herein and may have the same meaning, as the case may be.

[0030] The figures herein follow a numbering convention in which one or more first digits correspond to the figure number of the figure, and the remaining digits identify the element or component in the figure. Similar elements or components between different figures can be identified by using similar numerals. For example, 106 can refer to Figure 1 Component "06" in the figure, and similar components can be found in Figure 2 206. A group or more of similar elements or assemblies may be generally referred to herein by a single element figure number. For example, a plurality of reference elements 112-1, ..., 112-N (e.g., 112-1 to 112-N) may generally be referred to as 112. As will be appreciated, the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated to provide a plurality of other embodiments of the present disclosure. In addition, the proportions and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of the present disclosure and should not be adopted in a restrictive sense.

[0031] Figure 11 is a functional block diagram in the form of a computing system 100 including an apparatus including a memory system 104 according to several embodiments of the present disclosure. As used herein, a "apparatus" may refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuit system, a die or die, one or more modules, one or more devices, or one or more systems. The memory system 104 may be, for example, a solid-state drive (SSD), and may include an interface 108, a controller 110 (e.g., a processor and / or other control circuit system), and a number of memory devices 112-1 to 112-N, such as solid-state memory devices such as NAND flash devices, which provide storage volume for the memory system 104. In several embodiments, the controller 110, the memory devices 112-1 to 112-N, and / or the interface 108 may be physically located on a single die or within a single package, such as a managed NAND application. Likewise, in several embodiments, the memory, such as the memory devices 112-1 to 112-N, may include a single memory device.

[0032] like Figure 1 , the controller 110 may be coupled to the interface 108 and the memory devices 112-1 to 112-N through one or more channels 114-1 to 114-P and may be used to transfer data between the memory system 104 and the host 102. The channels (e.g., 114-1 to 114-P) may be paths for signal transmission or communication between the memory devices (e.g., 112-1 to 112-N) and the controller 110 or the controller 110 and the interface 108. The channel 114 may be a physical connection made with a conductor (e.g., a metal trace, a semiconductor material, etc.). The channel 114 may be enabled or disabled by operating a switch (e.g., one or more transistors) coupled to the channel 114 and the controller 110 or the memory device 112 (or the interface 108), etc. In some embodiments, disabling the channel 114 means opening one or more switches to physically or electrically disconnect (or decouple) the channel 114, thereby removing or disconnecting the signal transmission path between the components or devices.

[0033] The interface 108 may be in the form of a standardized interface. For example, when the memory system 104 is used for data storage in the computing system 100, the interface 108 may be a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, or a Universal Serial Bus (USB) interface, a Double Data Rate (DDR) interface, among other connectors and interfaces. However, in general, the interface 108 may provide an interface for transmitting control signals, address signals, data signals, and other signals between the memory system 104 and the host 102 having a receiver compatible with the interface 108.

[0034] The host 102 may be a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile phone, an Internet of Things (IoT) enabled device or a memory card reader, a graphics processing unit (e.g., a video card), among various other types of hosts. The host 102 may include a system motherboard and / or a backplane, and may include a number of memory access devices, such as a number of processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). It will be appreciated by those of ordinary skill in the art that a "processor" may mean one or more processors, such as a parallel processing system, a number of coprocessors, and the like. The host 102 may be coupled to an interface 108 of a memory storage system 104 via a communication channel 106.

[0035] In some embodiments, host 102 may be responsible for executing an operating system of computing system 100 including memory system 104. Thus, in some embodiments, host 102 may be responsible for controlling the operation of memory system 104. For example, host 102 may execute instructions (e.g., in the form of an operating system) to manage the hardware of computing system 100 (e.g., scheduling tasks), execute one or more applications 116-1 to 116-M, and control peripheral devices.

[0036] The computing system 100 may include separate integrated circuits located on the host 102, the memory system 104, the applications 116-1 to 116-M, the interface 108, the controller 110, and / or the memory devices 112-1 to 112-N may be located on the same integrated circuit. The computing system 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a portion thereof. Although Figure 1 The example shown in shows a system having a Von Neumann architecture, but embodiments of the present disclosure may be implemented on non-Von Neumann architectures, which may not include one or more components (e.g., CPU, ALU, etc.) typically associated with the Von Neumann architecture.

[0037] In some approaches, the memory system 104 (e.g., the controller 110) can use channels 114-1 to 114-P (collectively referred to herein as channels 114) to access data (e.g., memory cells and / or groups of cells, such as data words or sectors) stored in memory devices 112-1 to 112-N (collectively referred to herein as 112) to execute applications 116-1, 116-M (collectively referred to herein as 116). The application 116 can be executed on the host 102 using the data stored in the memory device 112. The term "executed on" may be used interchangeably herein with other terms such as "resident on", "deployed on", or "located on". The channel 114 is enabled by the controller 110 to provide the data stored in the memory device 112 to the application 116. When the channel 116 is enabled, it utilizes the power of the memory system 104. The disabled channel draws less power from the memory system 104 than the enabled channel.

[0038] In some embodiments, the controller 110 may determine the bandwidth demand (e.g., the front-end bandwidth demand) by determining the aggregate amount of bandwidth used by the applications 116 running on the host 102 that access the memory device 112. The controller 110 may monitor the applications 116 running on the host 102 to determine the bandwidth requirements and / or the priority of the applications 116.

[0039] Some applications 116 may have a higher priority than other applications 116. For example, high priority applications may include applications that provide important information and / or operations to users of the applications and / or host 102 and / or system-critical applications that must be executed for the computing system to operate. Low priority applications may include applications 116 that provide entertainment information or less important information to users of the applications and / or host 102. To reduce power consumption and / or reduce the temperature of the memory system 104, the controller 110 may consolidate data requested by the applications 116 over the channels 114 to reduce power to the memory system 104. For example, the controller 110 may selectively disable one or more channels 114 based at least in part on the aggregate amount of bandwidth used by the applications 116 and / or the level of priority associated with the applications 116.

[0040] The controller 110 may selectively disable some channels 114 while avoiding disabling other channels 114. For example, channel 114-1 may provide data from memory device 112-1 to application 116-1. Channel 114-P may provide data from memory device 112-N to application 116-M. The controller 110 may determine an aggregate bandwidth for executing applications 116-1 and 116-M, and based on the determination of the aggregate bandwidth, selectively disable channel 114-P and consolidate operations required to execute application 116-M to channel 114-1. Because the controller 110 may access memory devices 112-1 to 112-N, application 116-M may still access data from memory device 112-N through channel 114-1. The disabled channel 114-P may still draw power from the memory system 104, but the amount of power used by the disabled channel 114-P is less than the amount of power used by the enabled channel 114-1. However, embodiments are not so limited, and in some embodiments, the disabled channel 114-P may draw a vanishing (e.g., zero or near zero) amount of power from the memory system 104. In this manner, the applications 116-1 and 116-M remain operable when the memory system 104 is powered down. In other words, the applications 116-1 and 116-M may access data through the channel 114-1 that remains enabled after the channel 114-P is selectively disabled.

[0041] Further, the controller 110 may be configured to disable the channel 114-P in an independent manner. The controller 110 may be configured to move operations between channels such that any media management logic may be preserved. For example, the application 116-M may contain media management logic, such as data error correction (e.g., ECC) or data encryption, which may be preserved when the operation of the application 116-M is moved (e.g., integrated) from the channel 114-P to the channel 114-1. In this way, the operation of the application 116-1 and the application 116-M may be independent of the channel architecture.

[0042] In some embodiments, as described herein, the controller 110 can determine when an application becomes inactive (e.g., hibernated, disabled, removed, or otherwise less actively performing operations) and adjust the number of channels that are enabled and / or disabled to reduce power usage. When an application 116 is inactive, it may not receive data from the memory device 114 and / or it may receive data less frequently. In such instances, bandwidth requirements (e.g., aggregate bandwidth usage of the application 116) can be reduced, and the controller 110 can selectively disable some channels 114 to reduce power usage of the memory system 104.

[0043] In other embodiments, the controller 110 may determine when an application becomes active (e.g., a new application is connected to the host 102, a previously inactive application has become active, etc.) and adjust the number of channels 114 that are enabled and / or disabled to accommodate bandwidth demand. When an application 116 is active, it may receive data from a memory device, the application 116 may be new to the computing system 100, and / or it may request / receive data frequently and / or at an increased frequency. In such instances, bandwidth demand may increase, and the controller 110 may enable channels 114 (e.g., previously disabled channels) to meet the bandwidth demand of the memory system 104.

[0044] Embodiments are not limited to the method by which channels are enabled to meet bandwidth requirements. In a non-limiting example, applications 116 may have different priority levels and may be ranked by controller 110. Controller 110 may determine that application 116-1 has a higher priority than application 116-M. To save power, memory system 104 may enable channel 114-1 to provide data from memory devices 112-1 to 112-N to applications 116-1 and 116-N, and may selectively disable channel 114-P. For example, controller 110 may prioritize a request for data from application 116-1 through channel 114-1 ahead of a request from application 116-M to receive data through channel 114-1. In this way, memory system 104 may reduce power consumption by avoiding enabling disabled channel 114-P to meet bandwidth requirements.

[0045] The controller 110 may communicate with the memory devices 112-1 to 112-N to control data read, write, and erase operations, among other operations. The controller 110 may include, for example, several components in the form of hardware and / or firmware, for example, one or more integrated circuits, such as one or more application specific integrated circuits (one or more ASICs), one or more field programmable gate arrays (one or more FPGAs), and / or software for controlling access to the number of memory devices 112-1 to 112-N and / or for facilitating data transfer between the host 102 and the memory devices 112-1 to 112-N. The controller 110 may include various components for controlling data read, write, erase, etc. operations that are not shown to avoid obscuring the embodiments of the present disclosure. In some embodiments, such components may not be components of the controller 110, for example, components for controlling data read, write, erase, etc. operations may be independent components located within the memory system 104.

[0046] The memory devices 112-1 to 112-N may include several arrays of memory cells. The arrays may be flash arrays having, for example, a NAND architecture. However, embodiments are not limited to a particular type of memory array or array architecture. The memory cells may, for example, be grouped into several blocks, which may contain several physical pages. Several blocks may be contained in a plane of memory cells and the arrays may contain several planes.

[0047] The memory device 112 may include volatile memory and / or non-volatile memory. In several embodiments, the memory device 112 may include a multi-chip device. The multi-chip device may include a variety of different memory types and / or multiple memory modules. For example, the memory system may include non-volatile or volatile memory on any type of module. In an embodiment where the memory device 112 includes a non-volatile memory, the memory device 112 may be a flash memory device, such as a NAND or NOR flash memory device. However, the embodiment is not limited thereto, and the memory device 112 may include other non-volatile memory devices, such as non-volatile random access memory devices (e.g., NVRAM, ReRAM, FeRAM, MRAM, PCM), "emerging" memory devices, such as 3-D Crosspoint (3DXP) memory devices, etc. or a combination thereof. The 3D XP array of non-volatile memory combined with the stackable cross-grid data access array can perform bit storage based on changes in body resistance. Additionally, in contrast to many flash-based memories, 3DXP non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without the volatile memory having been previously erased.

[0048] The memory devices 112 may provide the main memory of the computing system 100, or may be used as additional memory or storage area for the entire computing system 100. Each memory device 112 may include memory cells, for example, one or more arrays of volatile memory cells and / or non-volatile memory cells. The array may be a flash memory array having, for example, a NAND architecture. Embodiments are not limited to a particular type of memory device. For example, the memory device may include RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, among others.

[0049] Figure 1Embodiments of the present disclosure may include additional circuitry that is not shown to avoid obscuring the embodiments of the present disclosure. For example, the memory system 104 may include address circuitry for latching address signals provided on the I / O connections by the I / O circuitry. The address signals may be received and decoded by a row decoder and a column decoder to access the memory device 112. Those skilled in the art will appreciate that the number of address input connections may depend on the density and architecture of the memory device 112.

[0050] Figure 2 2 is a functional block diagram of a device 201 including a front-end bandwidth demand 218 according to several embodiments of the present disclosure. The device 201 may include applications 216-1, 216-2, 216-3, 216-4, 216-5, and 216-M, which may be collectively referred to as applications 216 and in conjunction with Figure 1 Although not shown to avoid obscuring the examples of the present disclosure, application 216 may be implemented on a host (e.g., Figure 1 During the execution of the application, the application can access data from the memory system 204 according to the command generated by the controller 210. The memory system 204 and the controller 210 can be combined with the memory system 104 and Figure 1 The application 216 may access data from one or more memory devices 212 that are associated with the controller 110. Figure 1 The memory devices 112-1 through 112-N described are similar. The memory device 212 may be included in the Figure 1 The memory device 112 is shown in the memory system 204, or as shown in Figure 2 The memory system 204 is shown external.

[0051] Channels 214-1, 214-2, 214-3, 214-4, 214-5, 214-6, 214-7, and 214-P may be collectively referred to as channels 214 and may be associated with Figure 11 to 114-P. Data may be transferred through each of the channels 214 during execution of a single application (e.g., application 216-1, application 216-2, etc.) and / or multiple applications 216-1 to 216-M. As described in more detail below, execution of one or more applications 216 may consume a threshold amount of bandwidth, which may be referred to herein as a "bandwidth demand" (e.g., front-end bandwidth demand 218, back-end bandwidth demand, etc.). As used herein, the term "back-end" refers to a connection between a controller (e.g., controller 210) and a device (e.g., memory device 212 and / or another computing device). As used herein, the term "front-end" refers to a connection between a controller (e.g., controller 210) and a computing device (e.g., host 102, interface 108, and / or application 116, etc.).

[0052] The front-end bandwidth demand 218 may be an aggregate amount of bandwidth required to execute the application 216. For example, because the channels 214 may draw power from the memory system 204 during execution of the application 216 when the channels 214 are enabled to access data from the memory device 212, the front-end bandwidth demand 218 may correspond to the amount of power drawn from the memory system 204 due to the execution of the application 216. In order to mitigate the amount of power drawn from the memory system 204, the controller 210 may monitor the front-end bandwidth demand 218. The controller 210 may reduce power consumption by selectively disabling a single channel 214 and / or a portion (e.g., a subgroup) of the channels 214 based on the front-end bandwidth demand 218. That is, compared to an approach where each channel is normally active, embodiments herein may allow for a reduction in the amount of power consumed in the execution of an application by selectively disabling one or more of the channels 214 based on the front-end bandwidth demand 218.

[0053] In some embodiments, the amount of bandwidth used by each application 216 may be determined, at least in part, by the controller 210 as an aggregate amount of bandwidth required by all of the applications 216 executed by the host. Each of the applications 216 may include different bandwidth requirements, similar bandwidth requirements, or a combination thereof in order to execute. In a non-limiting example, application 216-1 may require 2 GB / s of bandwidth and application 216-2 may require 10 GB / s of bandwidth while the remaining applications 216-3, 216-4, 216-5, 216-M are inactive. Thus, the front-end bandwidth requirement 218 is the aggregate amount of bandwidth used by the channel 214 to provide data from the memory device 212 to execute the applications 216-1 and 216-2 (e.g., 12 GB / s in this example). Because the remaining applications 216-3, 216-4, 216-5, and 216-M are not active in this example, the controller 210 can selectively disable one or more channels 214 (e.g., channels that would be used by the applications 216-3, 216-4, 216-5, and 216-M if the applications 216-3, 216-4, 216-5, and 216-M were active) to reduce the amount of power used by the memory system 204 while meeting the front-end bandwidth demand 218. This power reduction can save power, reduce temperature, and increase the efficiency of the computing system compared to approaches that do not allow for selective disabling of channels based on the front-end bandwidth demand 218.

[0054] When the front-end bandwidth demand 218 increases, the controller 210 can selectively enable channels (e.g., previously disabled channels 214). For example, the controller 210 can determine the aggregate amount of bandwidth used by applications 216-1 and 216-2 (e.g., active applications) accessing data from the memory device 212 through a single channel 214-1 when channels 214-2, 214-3, 214-4, 214-5, 214-6, 214-7, and 214-P are disabled. Subsequently, the controller 210 can determine different front-end bandwidth demands 218 when new applications are added and / or become active. In a non-limiting example, applications 216-3 and 216-4 can be added and / or become active, and the front-end bandwidth demand 218 can increase. In response to the increased front-end bandwidth demand 218, the controller 210 may select a subset of channels from the disabled channels (e.g., channels 214-2, 214-3, 214-4, 214-5, 214-6, 214-7, and 214-P) to meet the front-end bandwidth demand 218 to execute the newly active applications 216-3 and 216-4. For example, the controller 210 may enable a subset of channels (e.g., channels 214-2 and 214-3) to provide data from the memory device 212 to meet the front-end bandwidth demand 218 including the newly active applications 216-3 and 216-4.

[0055] In some embodiments, the controller 210 may monitor active applications 216-1, 216-2, 216-3, and / or 216-4 and identify when an application 216 has become inactive. When an active application becomes inactive, the front-end bandwidth demand 218 may be reduced, and the controller 210 may disable the channel 214 and / or a subgroup of the channel 214 to reduce power consumption. For example, the controller 210 may determine that applications 216-1 and 216-3 have become inactive. For example, during operation of the memory system 204, the controller 210 may monitor application traffic originating from the host to determine whether an application (e.g., one or more applications 216) is active or inactive. That is, the controller 210 may determine whether applications 216-1 and 216-3 have exhibited reduced bandwidth needs due to no longer being executed. In this instance, the controller 210 may determine which of the channels in the channel 214 correspond to the execution of applications 216-1 and 216-3 and disable the corresponding channel 214. Continuing with this example, if application 216-1 uses channel 214-1 to receive data from memory device 212 and application 216-3 uses channel 214-3 to receive data from memory device 212, controller 210 may disable one (and consolidate operation of the newly disabled channels) or both channels (e.g., channels 214-1 and 214-3) to save power based on a determination that applications 216-1 and 216-3 have exhibited reduced bandwidth requirements due to, for example, being no longer active.

[0056] Figure 3 is another functional block diagram in the form of a device 301 including a front-end bandwidth requirement 318 and a machine learning component 324 according to several embodiments of the present disclosure. Figure 3 301 is not shown in order to avoid obscuring the examples of the present disclosure, but the device 301 may include and combine Figure 1 and 2 The device 301 may facilitate execution of applications 316-1, 316-2, 316-3, 316-4, 316-5, and 316-M, which may be collectively referred to as applications 316 and in conjunction with the memory systems 104 and 204 described above. Figure 1 and 2 The described applications 116 and 216 are similar. Although not shown to avoid obscuring the examples of the present disclosure, application 316 can be on a host (e.g., Figure 1 Although not shown to avoid obscuring examples of the present disclosure, application 316 may be coupled to a memory system (e.g., Figure 1 and 2 memory systems 104 and 204) and a controller 310, the controller being combined with Figure 1 and 2The controllers 110 and 210 described are similar.

[0057] Application 316 may receive data from one or more memory devices 312 that are associated with Figure 1 and 2 The described memory devices 112 to 212 are similar. Application 316 may receive data from memory device 312 via channels 314-1, 314-2, 314-3, 314-4, 314-5, 314-6, 314-7, and 314-P, which may be collectively referred to as channels 314 and may be combined with Figure 1 and 2 The described channels 114 and 214 are similar. Memory device 312 may be included within the memory system or may be external to the memory system.

[0058] The front-end bandwidth demand 318 may be an aggregate amount of bandwidth used by the channels 314 to provide data from the memory devices 312 to the applications 316 during execution of the applications 316. The controller 310 may determine an amount of bandwidth used by each of the applications 316 based at least in part on the aggregate amount of bandwidth used to execute the applications 316. For example, the controller 310 may determine the front-end bandwidth demand 318 and determine which applications 316 require bandwidth and / or have a higher priority based on the number of active applications 316.

[0059] like Figure 3 As shown, the controller 310 may also include a machine learning component 324. The machine learning component 324 may include, for example, a number of components in the form of hardware and / or firmware, such as one or more integrated circuits for monitoring application bandwidth requirements and / or learning application bandwidth behavior over time, such as one or more application specific integrated circuits (one or more ASICs) and / or one or more field programmable gate arrays (one or more FPGAs).

[0060] The controller 310 and / or the machine learning component 324 may be configured to determine the aggregate bandwidth usage of the application 316 accessing data from the memory device 312, which is coupled to the controller 310 via the channels 314. The controller 310 may identify a portion of the channels 314 for accessing data, and selectively disable a subset 322 of the portion of the channels 314 based at least in part on the aggregate bandwidth usage of the application 316. The portion of the channels 314 may include all or some of the channels (e.g., channels 314-1, 314-3, 314-4, 314-5, 314-6, 314-7, and 314-P), but embodiments are not limited to disabling these particular channels. The controller 310 may determine that the front-end bandwidth demand 318, which may represent the aggregate bandwidth usage of the application 316, may be provided by a number of channels 314 that is less than the portion of the channels 314 that supplies data to the application 316. In response to this determination, controller 310 may disable a subset 322 of channels 314 to save power. In a non-limiting example, subset 322 of channels is illustrated as channels 314-6, 314-7, and 314-P indicated by dashed circles.

[0061] In some embodiments, application 316 may access data through channels 314-6, 314-7, and 314-P before controller 310 disables subgroup 322 including channels 314-6, 314-7, 314-P. In this example, application 316 utilizing channels 314-6, 314-7, and 314-P may be transferred to multiple enabled channels (e.g., 314-1, 314-2, 314-3, 314-4, and / or 314-5).

[0062] In some embodiments, one or more channels 314 from subset 322 may be selectively disabled by controller 310 in response to an indication from machine learning component 324. The indication from machine learning component 324 may include information corresponding to application 316 removed from communication with controller 310. For example, application 316 may be running on a host (e.g., Figure 1 host 102) and through the interface ( Figure 1 The interface 108 of the controller is connected to the application 316. When the application 316 is no longer used, has been replaced, expired, malfunctions, etc., the application 316 can be removed from the communication with the controller 310.

[0063] The machine learning component 324 can indicate to the controller 310 information corresponding to the reduction in the amount of power used by the application 316. The reduction in the amount of power can indicate that the application 316 has been removed from communication with the controller 310 and / or that the application 316 has accessed (e.g., requested access to) less data from the memory device 312 than previously through the controller 314 (e.g., the application 316 may be less active). The controller 310 can receive the indication from the machine learning component 324 in the form of signaling.

[0064] For example, the controller 310 may receive signaling (e.g., an alarm) indicating when one or more applications 316-5 and 316-M have ceased receiving data from the memory device 312. The signaling received by the controller 310 may prompt the controller 310 to aggregate the amount of bandwidth used to operate the applications 316 and determine a new front-end bandwidth demand 318. In response to the new front-end bandwidth demand 318, the controller 310 may disable a subset 322 of the channels 314 to reduce power consumption. The machine learning component 324 and / or the controller 310 may determine when the activity of the applications 316 increases and / or when the applications 316 have been added to communicate with the controller 310 and access data through the channels 314.

[0065] The controller 310 may receive an indication and / or an alert generated by the machine learning component 324 in response to a detected increase in the front-end bandwidth demand 318. When the activity of the application increases (e.g., when the application 316 increases the amount of data accessed from the memory device), the application 316 may increase the front-end bandwidth demand 318. The activity of the application 316 may increase when the application 316 is connected to the controller 310 (e.g., a new application is added to communicate with the controller 310) or the application 316 accesses data from the memory device 312 more frequently. The alert received by the controller 310 may prompt the controller 310 to aggregate the amount of bandwidth used to execute the application 316 and determine a new front-end bandwidth demand 318 to reflect the increase in the activity of the application 316. In response to the new front-end bandwidth demand 318, the controller 310 may re-enable the subgroup 322 (or a portion of the subgroup 322) of the channel 314 to accommodate the new front-end bandwidth demand 318. In some embodiments, machine learning component 324 may include circuitry of controller 310 that may monitor applications 316 for changes in power requirements (e.g., addition of new applications, removal of applications, and / or increases and decreases in activity levels of applications 316).

[0066] The machine learning component 324 can predict the front-end bandwidth demand 318 so that the controller 310 can enable and / or disable the channels 314 to meet the front-end bandwidth demand 318 and save power. In a non-limiting example, the machine learning component 324 can monitor the applications 316-1, 316-2, 316-3, 316-4, 316-5, and 316-M and determine that a portion of the applications 320 (including the applications 316-5 and 316-M) are active (e.g., newly connected to the controller 310 and / or accessing data from the memory device 312). The machine learning component 324 can transmit an indication to the controller 310, and the controller 310 can aggregate the bandwidth used by the applications to determine the front-end bandwidth demand 318. The machine learning component 324 can identify a subgroup 322 of the channels 314 to be disabled by the controller 310 based at least in part on the predicted amount of power required in the operation of the channels 314 during the execution of the portion of the applications 320. Based on the determination of the machine learning component 324 , the controller 310 can re-enable the subset 322 of the channels 314 based at least in part on the expected amount of power when a portion of the application 320 is included in the front-end bandwidth demand 318 .

[0067] Figure 4 is another functional block diagram in the form of a computing system 403 including a memory system 404 according to several embodiments of the present disclosure. The computing system 403 may be combined with Figure 1 The computing system 100 described is similar. Figure 4 As shown, the computing system 403 includes a memory system 404 and a controller 410, the memory system and the controller are combined with Figure 1 , 2 The memory systems 104, 204 and controllers 110, 210 and 310 described in 3 are similar. In addition, Figure 4 Memory devices 412-1 through 412-N (which may be collectively referred to as memory devices 412 and may be combined with Figure 1 , 2 Similar to the memory devices 112, 212 and 312 described in 3).

[0068] Although not in Figure 4 , but the memory system 404 may be connected to a host (e.g., in conjunction with Figure 1 The host 102 described above). The memory system 404 may further include an interface, such as a peripheral interconnect express (PCIe) interface. Figure 4 The interface shown in the figure is shown as PCIe 408, but it should be understood that other interfaces, buses and / or communication paths may be used without departing from the spirit of the present disclosure. PCIe 408 may be used to connect the host to the memory system 404. Further, although not shown in the figure, Figure 4 In order not to obscure the examples of the present disclosure, however, application (e.g., in conjunction with Figure 1 , 2 The applications 116, 216, and 316 described in FIG. 3 may be executed (eg, run) on the host. The application may be communicatively connected to the controller 410 via the PCIe 408.

[0069] Controller 410 may include front-end bandwidth requirements (e.g., in conjunction with Figure 2 and 3 The front-end bandwidth requirements 218 and 318 described above may be an aggregate amount of bandwidth used by the channels 414-1 through 414-P to provide data from the memory device 412 to the application during execution of the application by the host. The controller 410 may reduce and / or increase the amount of power used by the memory system 404 by selectively disabling and / or selectively enabling the channels 414-1 through 414-P based at least in part on the front-end bandwidth requirements.

[0070] Scheduler 425 may be provided with computing resources and circuitry for arranging the execution of applications. For example, scheduler 425 may queue requests for data from applications. In some embodiments, controller 410 may determine the priority level of the application to save power, and scheduler 425 may facilitate the priority of the request based on the determination of controller 410. Low priority applications may include applications that request data less frequently than high priority applications and / or may be non-critical applications. High priority applications may include applications that frequently request data compared to low application-level applications and / or may be critical for the operation of host and / or memory system 404. For example, some high priority applications may frequently request data from memory device 412, but the data may be critical for the operation of host and / or memory system 404 when executed.

[0071] The controller 410 may selectively disable a portion of the channels 414-1 to 414-P to save power, and the scheduler 425 may prioritize the retrieval of data from high priority applications over the retrieval of data from low priority applications. In other words, the controller 410 may include latency for low priority applications to save power for the memory system 404. The scheduler 425 may be coupled to the multiplexer 426 and the select pins 428-1 and 428-Q. The multiplexer 426 may be a device that selects between analog-to-digital input signals received by the select pins 428-1 and 428-Q and forwards the input signals to output lines (e.g., connected to the converter 430).

[0072] The converter 430 may receive a selection command from the multiplexer 426 that may cause one or more of the channels 414-1 to 414-P to be selectively enabled or disabled. Channel controllers 432-1 to 432-R may be coupled to the channels 414-1 to 414-P and may switch the corresponding channels 414-1, 414-P to an enabled or disabled state in response to a command or other input from the converter 430.

[0073] As described above, in some embodiments, the controller 410 can determine the amount of bandwidth consumed in the execution of the corresponding application executed on the host. The amount of bandwidth consumed can be aggregated into a front-end bandwidth demand received by the controller 410. The scheduler 425 can determine the queue of data requests based on the front-end bandwidth demand, the priority of the application and / or the signal from the controller 410. The controller 410 can selectively assert the signal to the selection pin 428-1 to 428-Q coupled to the multiplexer 426 so that the corresponding channel controller 432-1 to 432-R switches the corresponding channel 414-1 to 414-P to an enabled or disabled state in response to the asserted (or de-asserted) signal.

[0074] In some embodiments, the one or more signals asserted to the select pins 428-1 and 428-Q may be Boolean logic signals (e.g., signals having a logic value of "0" or a logic value of "1"). Figure 4 As shown, four possible combinations of values ​​can be asserted on the selection pins 428-1 and 428-Q. For example, a logic value of "0" can be asserted on both the selection pins 428-1 and 428-Q, and the logic value corresponds to the disabled channels 414-1 and 414-P. Similarly, if a logic value of "1" is asserted on both the selection pins 428-1 and 428-Q, the channels 414-1 and 414-P can be enabled. A mixed value signal (e.g., a logic value of "0" is asserted on the selection pin 428-1, and a logic value of "1" is asserted on the selection pin 428-Q, or vice versa) can cause one of the channels 414-1 or 414-P to be enabled. The embodiments are not limited to the scenarios enumerated above and more or less than two selection pins 428 can be set on the memory device 404.

[0075] The select pins 428-1 to 428-Q may correspond to different channels 414-1 to 414-P. In some embodiments, the select pin 428-1 may correspond to the channel 414-1 and the second select pin 428-Q may correspond to the channel 414-P. In some embodiments, the controller 410 may de-assert a signal to the select pin 428-1 corresponding to the channel 414-1 that may be utilized by the application (e.g., the controller 410 may assert a logic value of "0" on the select pin 428-1). The converter 430 may receive a signal corresponding to the de-asserted signal corresponding to the channel 414-1 and transmit the signal to the channel controller 432-1 to disable the channel 414-1.

[0076] The channel controller 432-1 may transfer the application's access to data from the memory device 412-1 corresponding to the channel 414-1 to the channel 414-P based on the deassertion signal of the controller 410. In this way, the controller 410 may transfer the application's execution operation corresponding to the channel 414-1 to the channel 414-P in response to the deassertion of the signal to the select pin 428-1.

[0077] The controller 410 may cause independent operation of the select pins 428-1 to 428-Q coupled to the multiplexer 426. In some embodiments, the controller 410 may disable the channel 414-1 by deasserting the signal to the select pin 428-1 and asserting a different signal to the select pin 428-Q, as described above. The assertion of the different signal to the select pin 428-Q is independent of the deasserted signal to the select pin 428-1, so that the select pin 428-Q avoids changing its operation in response to the deasserted signal. For example, the controller 410 may determine to disable one or more channels 414-1 to 414-P and transfer data access to different enabled channels. In some embodiments, when transferring data access to different enabled channels, the media management logic (e.g., encryption, etc.) of the application corresponding to the enabled channels may be saved during the transfer operation. In this manner, controller 410 may cause select pins 428-1 through 428-Q to operate independently of selection to enable and disable channels 414-1 and 414-P. In other words, assertion and de-assertion of select pins 428-1 through 428-Q may not affect the operation of the enabled channels.

[0078] Figure 5 505 is a flow chart of a channel architecture for a memory device according to various embodiments of the present disclosure. Flow chart 505 includes a controller 510, which is combined with Figure 1 , 2 , 3 and 4 are similar to the controllers 110, 210, 310 and 410 described in detail.

[0079] At block 540, the controller 510 may be configured to aggregate bandwidth usage. Bandwidth usage may be aggregated by the controller 510 based on front-end bandwidth requirements (e.g., Figure 2 and 3 The front-end bandwidth requirements 218 and 318) are aggregated and are the channels (e.g., Figure 1 , 2 , 3 and 4 channels 114, 214, 314 and 414) are used to read data from a memory device (e.g., Figure 1 , 2 , 3 and 4 memory devices 112, 212, 312 and 412) to an application (e.g., Figure 1 , 2 and 3 applications 116, 216 and 316) provide an aggregate amount of bandwidth for data.

[0080] The controller 510 may aggregate bandwidth usage periodically or in response to an indication and / or an alert. Bandwidth aggregation at 540 may be used to determine a number of channels to selectively enable (provide increased bandwidth to an application) or selectively disable (save power and / or reduce temperature). The controller 510 may obtain information from a machine learning component (e.g., Figure 3 The machine learning component 324 of the controller 510 receives an indication that an application has been added to the computing system (e.g., coupled to a host) and / or an application has been disabled (e.g., removed, dormant, or no longer being executed). Such indications can prompt the controller 510 to aggregate bandwidth usage to determine whether the controller 510 can selectively disable channels from the computing system.

[0081] In some embodiments, the controller 510 may receive an alert related to the temperature of the computing system, which may prompt the controller 510 to aggregate bandwidth usage in the execution of applications to determine whether power usage of several disabled channels can be reduced. As applications are added to the computing system and / or multiple channels are disabled, the temperature may increase. For example, at box 542, the controller may determine applications that are active (e.g., receiving data from a memory device), and at box 544, it may be determined which application is inactive. Because the increase in temperature may reduce the efficiency of the computing system (e.g., a memory device coupled to the computing system), improved performance of the computing system may be achieved by selectively disabling one or more channels to reduce the amount of power consumed by the computing system compared to an approach that does not selectively disable channels based on aggregate bandwidth usage corresponding to executing applications.

[0082] In some embodiments, inactive applications (e.g., inactive applications 544) may become active (e.g., active applications 542), which may increase power usage and / or increase the temperature of the computing system. To maintain efficiency, the controller 510 may determine whether power consumption (e.g., power consumed by disabled channels) may be reduced. For example, the controller 510 may receive an alert corresponding to an increase in temperature of a memory device coupled to the controller 510 corresponding to executing applications. In response to the alert, the controller 510 may determine a new aggregate bandwidth usage corresponding to executing applications at block 546.

[0083] The controller 510 may use the new aggregate bandwidth usage to determine whether the temperature can be reduced by selectively disabling one or more channels and / or consolidating the execution of applications. As described above, a portion of the determination made by the controller 510 may be based on the priority of the application. For example, at block 548, the controller 510 may determine the priority of the application whose execution includes the new aggregate bandwidth usage determined at block 546.

[0084] In some embodiments, an application may have a high priority, where the controller 510 directs the scheduler (e.g., Figure 4 In other words, data requests for execution of one or more applications can be satisfied as they are received, as opposed to creating delays to allow some applications to execute before other applications. In such embodiments, at block 550, the controller 510 can avoid disabling one or more channels. In this way, multiple channels can remain available to provide data from the memory device to the application.

[0085] In some embodiments, one or more of the applications may have a low priority, where the controller 510 directs the scheduler (e.g., Figure 4 The scheduler 425 of the embodiment of the present invention enables the application to be executed based on the priority of the application. For example, the scheduler can create a queue in which high priority applications are executed first and lower priority applications are executed after the high priority applications. In other words, requests for data for executing applications can be adapted based on priority by generating a delay between the execution of applications, so that some applications are executed before other applications based on the priority of the application. In such embodiments, at box 552, the controller 510 can disable one or more channels, as described above. In this way, power usage and / or temperature can be reduced. In other words, the controller 510 can determine whether reducing power and / or lowering temperature or processing is more important for the execution of all applications with the same priority.

[0086] Figure 66 is a flow chart showing an example method 660 of a channel architecture of a memory device according to several embodiments of the present disclosure. At block 662, the method 660 may include determining, by a controller, an aggregate amount of bandwidth to use when executing one or more applications. The controller and the application may be used in conjunction with the present invention. Figure 1 The controller 110 and application 116 discussed are similar.

[0087] At block 664, method 660 may include determining, by the controller, a channel between the controller and one or more memory devices for accessing data as part of execution of the application. The channel may be associated with Figure 1 The amount of bandwidth determined by the controller may be the front-end bandwidth requirement (e.g., Figure 3 The front-end bandwidth requirement 318) may be an aggregate amount of bandwidth used by the channel to provide data from the memory device to the application during execution of the application.

[0088] At block 666, method 660 may include disabling one or more of the channels based at least in part on the amount of aggregate bandwidth used when executing the plurality of applications. The controller may selectively disable channels that allow data access between the memory device and the applications. The enabled channels may have the ability to provide data to more than one application, and thus, the controller may consolidate providing data from the plurality of applications to a portion of the channels and selectively disable a subset of the channels (e.g., Figure 3 of subgroup 322).

[0089] In some embodiments, method 660 may include a controller determining that a new application has been executed by a host and is requesting data from a memory device coupled via a back-end channel. In such embodiments, method 660 may include determining a new aggregate amount of bandwidth used by applications, including the newly connected application. The controller may selectively re-enable at least one channel in a subset of channels that had been previously disabled to accommodate the new aggregate amount of bandwidth required to execute the application. Method 660 may include the controller managing a channel between the controller and one or more memory devices based at least in part on the new aggregate amount of bandwidth.

[0090] In some embodiments, method 660 may include receiving, by the controller, signaling indicating an increase in temperature of a memory device coupled to the controller corresponding to executing the additional application and / or determining, by the controller, a new aggregate amount of bandwidth for executing the plurality of applications based at least in part on the signaling. In response to the alert, method 660 may further include selectively disabling, by the controller, another portion of the channel.

[0091] Figure 77 is another flow chart showing another example method 770 of a channel architecture of a memory device according to several embodiments of the present disclosure. At block 772, the method 770 may include determining, by a controller, that a channel coupling the controller to the memory device is disabled. The controller may be used in conjunction with the Figure 1 The controller 110 discussed above is similar. A disabled channel may be coupled to the controller and the memory device, but may not be used to transfer data from the memory device to an application (e.g., Figure 1 Application 116). A disabled channel may utilize a small amount of power, while an enabled channel may draw a considerable amount of power.

[0092] At block 774, method 770 may include identifying, by the controller, an application that uses the channel to access data stored by the memory device. The application may be associated with Figure 1 The identified channel may be enabled to transmit data to the application so that it can be transmitted on a host (e.g., Figure 1 As described above, the enabled channel can use data from the memory system (e.g., Figure 1 A certain amount of power of the memory system 104).

[0093] At block 776, method 770 may include determining, by the controller, an aggregate amount of bandwidth to use when executing the applications. The aggregate amount of bandwidth may include an amount of bandwidth used by each application to execute using data provided from the memory device to its respective application via each channel. In some embodiments, there may be more than one application using each channel. The aggregate amount of bandwidth may be determined by the controller and may be referred to as the front-end bandwidth demand (e.g., Figure 3 The aggregate amount of bandwidth may be determined periodically and / or in response to an alarm (e.g., a temperature alarm, etc.), an indication (e.g., an indication that an application is active and / or inactive, added to communications with the controller and / or removed from the communications, etc.). In some embodiments, method 770 may include determining, by the controller, an increase in the aggregate amount of bandwidth used in the execution of the application. The increase in aggregate bandwidth may correspond to at least one application exhibiting increased bandwidth demand. However, embodiments are not limited thereto, and in some embodiments, the controller may also detect a decrease in bandwidth (e.g., a decrease in the aggregate amount of bandwidth used).

[0094] In some embodiments, method 770 may include determining a reduction in the amount of aggregate bandwidth used in the execution of applications and associating each application with a corresponding channel. Further, the controller may disable a portion of the channels based at least in part on the bandwidth requirements of the applications. In other words, the controller may determine to enable more channels than are required to accommodate the bandwidth requirements of the applications (e.g., front-end bandwidth requirements). In this way, the controller may selectively disable a portion (e.g., one or more) of the enabled channels to save power, thereby reducing the temperature of the memory device. The controller may transfer applications that previously accessed data through the newly disabled channels to the enabled channels (e.g., integration). Such channel integration may be accomplished in an independent manner, wherein disabling one or more of the multiple channels may include (e.g., disabling a portion of the channels) to avoid changing the operation of the channels that remain enabled.

[0095] In block 778, method 770 may include comparing, by the controller, the aggregate amount of bandwidth used in the execution of the applications with the amount of channels coupling the controller to the memory device. In some embodiments, the controller may compare the applications accessing the data with the amount of enabled channels to determine whether some channels are disabled to save resources. In some embodiments, the controller may compare the applications accessing the data with the amount of enabled applications to determine whether there are enough enabled channels to efficiently provide data to the applications.

[0096] At block 780, the method 770 may include enabling, by the controller, a disabled channel based at least in part on the comparison. To avoid unnecessary latency in the execution of the application, the controller may enable a channel that had been previously disabled to increase access to data from the memory device. Enabling the previously disabled channel provides an additional connection to the memory device for the application to access data stored by the memory device.

[0097] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that arrangements intended to achieve the same results may replace the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be understood that the above description is provided in an illustrative and non-restrictive manner. After reading the above description, the combination of the above-described embodiments and other embodiments not specifically described herein will be apparent to those of skill in the art. The scope of one or more embodiments of the present disclosure includes other applications in which the above structures and processes are used. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims together with the full scope of equivalents to which such claims are assigned.

[0098] In the foregoing detailed description, some features are grouped together in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. On the contrary, as reflected in the following claims, the inventive subject matter lies in less than all the features of a single disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. An apparatus for operating a memory device, comprising: an interface coupled to the plurality of channels; as well as a controller coupled to the interface, wherein the controller is configured to: determining an aggregate amount of front-end bandwidth used by a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels; determining front-end bandwidth requirements for the plurality of applications based on the aggregate amount of front-end bandwidth used by the plurality of applications; disabling one or more channels of the plurality of channels based at least in part on the aggregate amount of front-end bandwidth used by the plurality of applications in accessing data from the memory device; and A subset of the one or more disabled channels is re-enabled to meet the front-end bandwidth demand.

2. The apparatus of claim 1, wherein the plurality of channels comprises: a plurality of backend channels of the controller; or A plurality of front-end channels of the controller. 3 . The apparatus of claim 1 , wherein the controller is configured to cause the plurality of applications to access data from channels of the plurality of channels that remain enabled after disabling the one or more channels of the plurality of channels.

4. The apparatus of any one of claims 1-3, wherein the controller is configured to: determining that a portion of the plurality of applications is inactive; and A subset of channels used by the portion of the plurality of inactive applications is disabled.

5. An apparatus for operating a memory device, comprising: a plurality of pins coupled to corresponding channels; as well as a controller coupled to the plurality of channels, wherein the controller is configured to: determining an aggregate front-end bandwidth usage of a plurality of applications accessing data from a memory device coupled to the controller via the plurality of channels; determining front-end bandwidth requirements of the plurality of applications based on the aggregate front-end bandwidth usage determined by the plurality of applications; identifying one or more channels of the plurality of channels for accessing the data; asserting the signal on the corresponding pin to disable a subset of the one or more channels of the plurality of channels based at least in part on the determined aggregate front-end bandwidth usage of the plurality of applications and an output of an operation resulting from assertion of the signal on the corresponding pin; as well as At least one channel in the subset of the one or more channels is re-enabled to meet the front-end bandwidth demand.

6. The apparatus of claim 5, wherein the controller comprises a computing component configured to estimate an amount of front-end bandwidth usage when executing at least one of the plurality of applications.

7. The apparatus of claim 5, wherein the controller comprises a computing component configured to identify one or more of the plurality of channels for accessing the data based at least in part on a predicted amount of front-end bandwidth usage involving at least one of the plurality of applications.

8. A method for operating a memory device, comprising: determining an aggregate amount of front-end bandwidth used in execution of the plurality of applications; determining front-end bandwidth requirements for the plurality of applications based on the aggregate amount of front-end bandwidth used in execution of the plurality of applications; determining a channel between a controller and one or more memory devices for accessing data as part of execution of the plurality of applications; disabling one or more of the channels by asserting the respective signals on the respective pins coupled to the channels based at least in part on the aggregate amount of front-end bandwidth used in execution of the plurality of applications and an output of a Boolean operation resulting from asserting the respective signals on the respective pins; as well as A subset of disabled channels is re-enabled to meet the front-end bandwidth demand.

9. The method according to claim 8, comprising: Determine that another application is executed; determining a new aggregate amount of front-end bandwidth used in execution of the plurality of applications, wherein the new aggregate amount of front-end bandwidth used in execution of the plurality of applications includes an amount of front-end bandwidth required to execute the additional application; controlling the channel between the controller and the one or more memory devices based at least in part on the new aggregate amount of front-end bandwidth used in execution of the plurality of applications; as well as At least one of the disabled channels is re-enabled to accommodate the new aggregate amount of front-end bandwidth.

10. The method according to claim 8, comprising: receiving signaling indicating a temperature increase in one or more memory devices due to the execution of the further application; as well as A new aggregate amount of front-end bandwidth to be used in the execution of the plurality of applications is determined based at least in part on the signaling.

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