Hard disk control method and device, electronic equipment, storage medium and product

Abstract

The invention provides a hard disk control method and device, electronic equipment, a storage medium and a product. The method is applied to a control panel complex programmable logic device (CPLD) of the storage controller, the control panel CPLD is connected with a plurality of adapter plates CPLDs through an integrated circuit bus (I2C), and the method comprises the following steps: receiving a control request; according to the control request, determining a target adapter plate CPLD corresponding to the target hard disk identifier and a target channel corresponding to the target adapter plate CPLD in the first I2C; and sending the target register instruction to the target adapter plate CPLD through the target channel, so that the target adapter plate CPLD controls a target hard disk connected with the target adapter line CPLD according to the target register instruction. According to the scheme, the plurality of adapter plates connected with the I2C can be controlled through the register instruction, so that the plurality of hard disks are controlled through one group of I2C, lines of the storage controller are reduced, the heat dissipation area is increased on the premise that the specification of the storage controller is not reduced, and the heat dissipation effect of the storage controller is further improved.

Description

Technical Field

[0001] The present application relates to the technical field of solid-state hard disks, and in particular to a hard disk control method, device, electronic device, storage medium and product. Background Art

[0002] With the development of information technology and the expansion of usage scenarios, users' requirements for storage are gradually increasing. In order to meet users' requirements for storage, high-performance solid-state drives (hereinafter referred to as hard drives) have become an important storage tool for users. For business scenarios with large amounts of data, multiple hard drives are used for data storage at the same time. By connecting multiple hard drives through a storage controller, multiple hard drives can be effectively managed.

[0003] In actual applications, a storage controller connects to multiple hard disks for management, and multiple hard disks working simultaneously may generate heat. In related technologies, the heat dissipation effect is improved by reducing the number of hard disks to increase the heat dissipation area and reduce the overall power consumption of the storage controller.

[0004] However, this approach results in a reduction in the specifications of the storage controller, which in turn results in a reduction in the performance of the storage controller. Summary of the invention

[0005] The present application provides a hard disk control method, device, electronic device, storage medium and product, which are used to improve the heat dissipation effect of a storage controller.

[0006] In a first aspect, the present application provides a hard disk control method, which is applied to a control board complex programmable logic device CPLD of a storage controller, wherein the control board CPLD is connected to multiple adapter board CPLDs via an integrated circuit bus I2C, and the method comprises: receiving a control request, wherein the control request comprises a target hard disk identifier and a target control instruction corresponding to a target hard disk; determining, according to the control request, a target adapter board CPLD corresponding to the target hard disk identifier, and a target channel corresponding to the target adapter board CPLD in a first I2C; determining a target register instruction corresponding to the target control instruction; and sending the target register instruction to the target adapter board CPLD via the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction.

[0007] Optionally, the method as described above determines the target register instruction corresponding to the target control instruction, including: determining the target mapping relationship corresponding to the target adapter board CPLD, the target mapping relationship including a mapping relationship between control instructions and register addresses, and a mapping relationship between control instructions and register values; determining a first register address and a first read instruction based on the target mapping relationship, the first register address and the first read instruction being used to read the in-place status information of the target hard disk; determining a second register address and a first register value based on the target control instruction and the target mapping relationship, the second register address and the first register value being used to instruct the target adapter board CPLD to execute the target register instruction; determining that the target register instruction includes the first register address, the first read instruction, the second register address, and the first register value.

[0008] Optionally, the method as described above, sending the target register instruction to the target adapter board CPLD through the target channel, includes: sending a switching instruction to the I2C switch, the switching instruction including the channel identifier corresponding to the target channel; sending the first register address and the first read instruction to the target adapter board CPLD through the target channel, receiving target in-position status information sent by the target adapter board CPLD, the target in-position status information including in-position or not in-position; if the target in-position status information is in-position, sending the second register address and the first register value to the target adapter board CPLD through the target channel.

[0009] Optionally, the method as described above also includes: determining a second read instruction, the second read instruction is used to read the register value of a register; sending the second register address and the second read instruction to the target adapter board CPLD through the target channel, and receiving the second register value sent by the target adapter board CPLD; if the first register value is different from the second register value, repeatedly sending the second register address and the first register value to the target adapter board CPLD through the target channel until the first register value is the same as the second register value.

[0010] Optionally, the method as described above, after repeatedly sending the second register address and the first register value, further includes: starting a timer; if after the timer times out, the first register value is different from the second register value, determining a third register address and a third register value, the third register address and the third register value being used to instruct the target adapter board CPLD to execute a reset instruction; and sending the third register address and the third register value to the target adapter board CPLD through the target channel.

[0011] Optionally, the method as described above further includes: determining a target duration; obtaining multiple communication addresses corresponding to multiple channels under the first I2C at intervals of the target duration; performing verification processing on the first I2C according to the multiple communication addresses to obtain a verification result, wherein the verification result includes a verification pass or a verification fail; if the verification result is a verification fail, sending a register instruction to multiple adapter board CPLDs connected to the first I2C via a second I2C.

[0012] In a second aspect, the present application provides a hard disk control device, which is applied to a control board complex programmable logic device CPLD of a storage controller, wherein the control board CPLD is connected to multiple adapter board CPLDs via an integrated circuit bus I2C, and the device comprises: a receiving module, which is used to receive a control request, wherein the control request comprises a target hard disk identifier and a target control instruction corresponding to the target hard disk; a determining module, which is used to determine, according to the control request, a target adapter board CPLD corresponding to the target hard disk identifier, and a target channel corresponding to the target adapter board CPLD in the first I2C; a comparing module, which is used to determine a target register instruction corresponding to the target control instruction; and a sending module, which is used to send the target register instruction to the target adapter board CPLD via the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction.

[0013] Optionally, in the device as described above, the comparison module is specifically used to determine the target mapping relationship corresponding to the target adapter board CPLD, and the target mapping relationship includes a mapping relationship between control instructions and register addresses, and a mapping relationship between control instructions and register values; the comparison module is also specifically used to determine a first register address and a first read instruction based on the target mapping relationship, and the first register address and the first read instruction are used to read the in-place status information of the target hard disk; the comparison module is also specifically used to determine a second register address and a first register value based on the target control instruction and the target mapping relationship, and the second register address and the first register value are used to instruct the target adapter board CPLD to execute the target register instruction; the comparison module is also specifically used to determine that the target register instruction includes the first register address, the first read instruction, the second register address, and the first register value.

[0014] Optionally, the device as described above further includes: an execution module, used to send a switching instruction to the I2C switch, the switching instruction including a channel identifier corresponding to the target channel; the execution module, further used to send the first register address and the first read instruction to the target adapter board CPLD through the target channel, and receive target in-place status information sent by the target adapter board CPLD, the target in-place status information including in-place or not in-place; the execution module, further used to send the second register address and the first register value to the target adapter board CPLD through the target channel if the target in-place status information is in-place.

[0015] Optionally, the device as described above further includes: a first verification module, used to determine a second read instruction, wherein the second read instruction is used to read the register value of a register; the first verification module is also used to send the second register address and the second read instruction to the target adapter board CPLD through the target channel, and receive the second register value sent by the target adapter board CPLD; the first verification module is also used to repeatedly send the second register address and the first register value to the target adapter board CPLD through the target channel if the first register value is different from the second register value, until the first register value is the same as the second register value.

[0016] Optionally, the device as described above further includes: a second verification module, used to start a timer; the second verification module is also used to determine a third register address and a third register value if the first register value is different from the second register value after the timer times out, the third register address and the third register value being used to instruct the target adapter board CPLD to execute a reset instruction; the second verification module is also used to send the third register address and the third register value to the target adapter board CPLD through the target channel.

[0017] Optionally, as described above, the device further comprises: a backup module, used to determine a target duration; the backup module is further used to obtain multiple communication addresses corresponding to multiple channels under the first I2C at intervals of the target duration; the backup module is further used to perform verification processing on the first I2C according to the multiple communication addresses to obtain a verification result, wherein the verification result comprises a verification pass or a verification failure; the backup module is further used to send register instructions to multiple adapter board CPLDs connected to the first I2C via a second I2C if the verification result is a verification failure.

[0018] In a third aspect, the present application provides an electronic device comprising: a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement any method described in the first aspect.

[0019] In a fourth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by a processor as described in any one of the methods in the first aspect.

[0020] In a fifth aspect, the present application provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor as in any one of the methods in the first aspect.

[0021] The hard disk control method, device, electronic device, storage medium and product provided in the present application are applied to the control board complex programmable logic device CPLD of the storage controller, the control board CPLD is connected with multiple adapter board CPLDs through the integrated circuit bus I2C, and the method includes: receiving a control request, the control request includes the target hard disk identification and target control instruction corresponding to the target hard disk; according to the control request, determining the target adapter board CPLD corresponding to the target hard disk identification, and the target channel corresponding to the target adapter board CPLD in the first I2C; determining the target register instruction corresponding to the target control instruction; sending the target register instruction to the target adapter board CPLD through the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction. In the above scheme, multiple adapter boards connected to I2C can be controlled through register instructions, so that multiple hard disks can be controlled through one group of I2C, the circuit of the storage controller can be reduced, and the heat dissipation area can be increased without reducing the specifications of the storage controller, thereby improving the heat dissipation effect of the storage controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0023] Figure 1 A schematic diagram of an application scenario of a hard disk control method provided in an embodiment of the present application;

[0024] Figure 2 A flowchart of a hard disk control method provided in an embodiment of the present application;

[0025] Figure 3 A schematic diagram of an I2C circuit provided in an embodiment of the present application;

[0026] Figure 4 A flowchart of a hard disk control method provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of sending a target register instruction provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of a reset instruction provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure of a hard disk control device provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of a hard disk control device provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0032] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0034] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use, processing, transmission, provision, disclosure and application of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions, take necessary confidentiality measures, do not violate public order and good morals, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0035] It should be noted that the control method, device, electronic device, storage medium and product of the hard disk of the present application can be used in the field of solid-state hard disk technology, and can also be used in any field other than solid-state hard disks. The application field of the control method, device, electronic device, storage medium and product of the hard disk of the present application is not limited.

[0036] Figure 1 A schematic diagram of an application scenario of a hard disk control method provided in an embodiment of the present application is given as an example in combination with the illustrated scenario: a storage controller is connected to a hard disk backplane, the hard disk backplane includes slots for hard disks, and multiple hard disks are connected to the hard disk backplane through the slots, and thus indirectly connected to the storage controller, so as to enable the storage controller to manage multiple hard disks.

[0037] In actual applications, in order to meet the needs of large storage, the hard disk backplane is connected to multiple hard disks, resulting in a reduced heat dissipation area. In addition, multiple hard disks working at the same time will cause a large amount of heat to be generated, resulting in a high overall temperature of the storage controller.

[0038] In the related art, the number of hard disks connected to the hard disk backplane is reduced to increase the heat dissipation area, thereby improving the heat dissipation effect. However, this method will reduce the specifications of the storage controller. For example, when all the slots of the hard disk backplane are connected to hard disks, the storage controller supports a storage capacity of 10TB. After reducing the number of connected hard disks, the storage controller can only provide 8TB of storage capacity, resulting in a reduction in the specifications of the storage controller, which affects user use.

[0039] The hard disk control method provided in the present application is intended to solve the above technical problems in the prior art.

[0040] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0041] Figure 2 A flowchart of a hard disk control method provided in an embodiment of the present application, the method comprising the following steps:

[0042] S201, receiving a control request, where the control request includes a target hard disk identifier corresponding to a target hard disk and a target control instruction.

[0043] Among them, the present application is applied to a control board complex programmable logic device CPLD of a storage controller, and the control board CPLD is connected to multiple adapter board CPLDs through an integrated circuit bus I2C.

[0044] The control board CPLD is responsible for the overall management of the storage controller, and the control board CPLD is connected to the host and the adapter board CPLD. The adapter board CPLD executes the instructions sent by the control board CPLD, and the adapter board CPLD is connected to the hard disk.

[0045] Exemplarily, the CPU of the mainboard sends a control request to the CPLD of the control board, and the CPLD of the control board executes the control request to control the multiple hard disks.

[0046] Exemplarily, the target hard disk is a hard disk controlled by the mainboard.

[0047] In the related art, the control board CPLD is connected to multiple adapter board CPLDs through multiple control lines, and the multiple control lines correspond to the multiple adapter board CPLDs one by one. In the present application, the control board CPLD controls multiple adapter board CPLDs through one group of I2C, which can effectively reduce the number of control lines.

[0048] Next, combine Figure 3 The I2C circuit is described.

[0049] Figure 3 Schematic diagram of the I2C circuit provided in the embodiment of the present application. Figure 3 As shown in the figure, the hard disk backplane is connected to multiple hard disks, and each adapter board CPLD controls one hard disk. The control board CPLD is connected to multiple adapter board CPLDs through one group of I2C. Figure 3 , the control board CPLD is connected to hard disk 1 to hard disk 5 through the first I2C. Correspondingly, the control board CPLD controls hard disk 1 to hard disk 5 through the first I2C.

[0050] S202: Determine, according to the control request, a target adapter board CPLD corresponding to the target hard disk identifier and a target channel corresponding to the target adapter board CPLD in the first I2C.

[0051] The first I2C includes multiple channels, and each channel corresponds to a transfer board CPLD.

[0052] Exemplarily, the target adapter board CPLD is an adapter board CPLD that controls the target hard disk. The target channel is a channel corresponding to the target adapter board. The control board CPLD can send instructions or data to the target adapter board CPLD through the target channel.

[0053] S203: Determine the target register instruction corresponding to the target control instruction.

[0054] Among them, register instructions are used to control the behavior of hardware devices. By writing a specific value to a register, the hardware device can be triggered to perform the corresponding operation. Register instructions can also be used to read the status information of a hardware device. By reading a specific register, the status information of the device can be obtained. Register instructions can also be used to configure the parameters of a hardware device. By writing a specific value to a configuration register, the configuration parameters can be implemented.

[0055] Optionally, the register includes but is not limited to a power-on / power-off register, a reset register, or an in-position status register.

[0056] Combined with the scenario example, the power-on and power-off register is used to control the hard disk power on or off, the reset register is used to control the hard disk reset, and the in-position status register is used to display whether the hard disk is correctly installed.

[0057] Exemplarily, the target control instruction is a control target sent by the host, and the target register instruction is an instruction sent by the control board CPLD to the adapter board CPLD, including specific operations to be performed so that the adapter board CPLD executes the target register instruction.

[0058] S204, sending a target register instruction to the target adapter board CPLD through the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter cable CPLD according to the target register instruction.

[0059] Exemplarily, the target adapter board CPLD is connected to the target hard disk, and the register stored in the target adapter board CPLD corresponds to the target hard disk.

[0060] Exemplarily, the target register instruction is only sent to the target adapter board CPLD, and the target adapter board CPLD executes the target register instruction according to the register stored in the target adapter board CPLD, thereby accurately controlling the target hard disk.

[0061] It can be understood that the control of multiple adapter board CPLDs is achieved through register instructions. The operating state of the system can be changed or different operations can be performed easily by modifying the value of the register. This design makes the system more flexible and can quickly adapt to different application scenarios and changes in requirements.

[0062] The control method of the hard disk provided in the embodiment of the present application is applied to the control board complex programmable logic device CPLD of the storage controller, and the control board CPLD is connected to multiple adapter board CPLDs through the integrated circuit bus I2C. The method includes: receiving a control request, the control request includes a target hard disk identifier corresponding to the target hard disk and a target control instruction; according to the control request, determining the target adapter board CPLD corresponding to the target hard disk identifier, and the target channel corresponding to the target adapter board CPLD in the first I2C; determining the target register instruction corresponding to the target control instruction; sending the target register instruction to the target adapter board CPLD through the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction. The above scheme can control multiple adapter boards connected to I2C through register instructions, thereby controlling multiple hard disks through one group of I2C, reducing the lines of the storage controller, and increasing the heat dissipation area without reducing the specifications of the storage controller, thereby improving the heat dissipation effect of the storage controller.

[0063] Based on any of the above embodiments, Figure 4 , the detailed process of hard disk control is explained.

[0064] Figure 4 The following is a flow chart of a method for controlling a hard disk provided in an embodiment of the present application. Figure 4 As shown, the method includes:

[0065] S401, receiving a control request, where the control request includes a target hard disk identifier corresponding to a target hard disk and a target control instruction.

[0066] It should be noted that the execution process of S401 refers to S201 and will not be repeated here.

[0067] S402: Determine, according to the control request, a target adapter board CPLD corresponding to the target hard disk identifier and a target channel corresponding to the target adapter board CPLD in the first I2C.

[0068] It should be noted that the execution process of S402 refers to S202 and will not be repeated here.

[0069] S403: Determine a target mapping relationship corresponding to the target adapter board CPLD.

[0070] The target mapping relationship includes a mapping relationship between a control instruction and a register address, and a mapping relationship between a control instruction and a register value.

[0071] Exemplarily, a register address is a number or code used to uniquely identify a register. Each register has a unique address, through which the target adapter board CPLD can access and operate the corresponding register. A register value is the data stored in the register. It can be a numerical value, status information, or configuration parameter, etc. By writing or reading a register value, the target adapter board CPLD can control the behavior of a hardware device or obtain the status of a hardware device, wherein the hardware device in this application corresponds to a hard disk.

[0072] In combination with the scenario example, for a control instruction and a register address that have a mapping relationship, the register corresponding to the register address is used to implement the control instruction. For a control instruction and a register value that have a mapping relationship, the register value is used to implement the control instruction.

[0073] S404: Determine a first register address and a first read instruction according to the target mapping relationship.

[0074] The first register address and the first read instruction are used to read the in-place status information of the target hard disk.

[0075] Exemplarily, the in-place status information indicates whether the target hard disk is correctly installed in the corresponding hard disk slot.

[0076] Combined with the scenario example, before implementing the target control instruction, first determine whether the target is correctly installed through the in-place status information.

[0077] Optionally, the mapping relationship includes an application scenario corresponding to each register address, an application scenario corresponding to each register value, and an application scenario corresponding to each read instruction.

[0078] Combined with the scenario example, the application scenario includes detecting the in-place status of the hard disk, determining the register address corresponding to the in-place status of the hard disk in the mapping relationship as the first register address, and determining the read instruction corresponding to the in-place status of the hard disk in the mapping relationship as the first read instruction.

[0079] In conjunction with the scenario example, the register corresponding to the first register address stores in-place status information. The first read instruction is used to instruct the target adapter board CPLD to read the in-place status information stored in the register.

[0080] S405: Determine the second register address and the first register value according to the target control instruction and the target mapping relationship.

[0081] The second register address and the first register value are used to instruct the target adapter board CPLD to execute the target register instruction.

[0082] Exemplarily, the register corresponding to the second register address is used to execute the target control instruction, and the target adapter board CPLD writes the first register value into the register corresponding to the second register address to execute the target control instruction.

[0083] S406 , determining that the target register instruction includes a first register address, a first read instruction, a second register address, and a first register value.

[0084] Exemplarily, the target adapter board CPLD first reads the in-place status information of the target hard disk according to the first register address and the first read instruction, and then implements the target control instruction sent by the host according to the second register address and the first register value.

[0085] S407: Send a switching instruction to the I2C switch, where the switching instruction includes a channel identifier corresponding to the target channel.

[0086] Among them, an I2C switch is a device used to expand I2C, allowing an I2C master controller (such as a microcontroller or CPLD) to communicate with multiple I2C slave hardware devices at the same time. Through the I2C switch, an I2C bus can be divided into multiple sub-buses, thereby increasing the number of hardware devices that can be connected to the system. In this application, the hardware device corresponds to a hard disk.

[0087] Exemplarily, the control board CPLD is connected to multiple hard disks through multiple channels of I2C. The target hard disk corresponds to the target channel. The target register instruction is sent by controlling the target channel through the I2C switch.

[0088] S408, sending a first register address and a first read instruction to the target adapter board CPLD through a target channel, and receiving target in-place status information sent by the target adapter board CPLD.

[0089] The target presence status information includes presence or absence.

[0090] Combined with the scenario example, the address corresponding to the in-position status information register is set to 0x55, and 0x55 and the first read instruction are sent to the target adapter board CPLD. The target adapter board CPLD determines the register corresponding to 0x55, and the target adapter board CPLD reads the target in-position status information from the register corresponding to 0x55 according to the first read instruction, and sends the target in-position status information to the control board CPLD.

[0091] Optionally, before the target adapter board CPLD executes the first read instruction, it verifies whether the in-place status information stored in the register corresponding to the first register address is the latest in-place status information.

[0092] Combined with the scenario example, the hard disk in-place status information is obtained in real time to ensure that when the hard disk is pulled out or falls off, the in-place status information can accurately reflect the current hard disk in-place status, thereby improving the accuracy of hard disk control.

[0093] S409: If the target in-place status information is in-place, sending the second register address and the first register value to the target adapter board CPLD through the target channel.

[0094] Next, combine Figure 5 The send destination register instruction is described.

[0095] Figure 5 A schematic diagram of sending a target register instruction provided in an embodiment of the present application. Figure 5 As shown, the control board CPLD switches to the target channel of I2C and sends the first register address and the first read instruction through the target channel. The adapter board CPLD receives the instruction and reads the target in-position information. The adapter board CPLD sends the target in-position status information to the control board CPLD. If the control board CPLD determines that it is in-position, it sends the second register address and the first register value to the adapter board CPLD, so that the adapter board CPLD writes the first register value into the register corresponding to the second register address.

[0096] Combined with the scenario example, setting the target in-place information to 0xAA indicates that the target hard disk is correctly installed. If the control board CPLD receives 0xAA, the second register address and the first register value are sent. If the target in-place information received by the control board CPLD is not 0xAA, it means that the target hard disk is not correctly installed. At this time, the first register value cannot be executed even if it is written, so the second register address and the first register value are stopped.

[0097] Optionally, if the target in-place status information is not in place, feedback information is sent to the host to enable the host to confirm that the target hard disk is not correctly installed.

[0098] Optionally, if the target in-place status information is not in place, an alarm is issued to prompt the user to correctly install the target hard disk.

[0099] A feasible implementation method, the hard disk control method also includes: determining a second read instruction, the second read instruction is used to read the register value of the register; sending the second register address and the second read instruction to the target adapter board CPLD through the target channel, and receiving the second register value sent by the target adapter board CPLD; if the first register value is different from the second register value, repeatedly sending the second register address and the first register value to the target adapter board CPLD through the target channel until the first register value is the same as the second register value.

[0100] Combined with the scenario example, the state of the target hard disk may change, and there may be problems in the process of writing the first register value. The above situations will cause the first register value to be executed incorrectly. For example, the target control instruction sent by the host is to control the power-on of the target hard disk. The corresponding first register value is 0x80. The adapter board CPLD writes 0x80 to the register corresponding to the second register address to power on the target hard disk. The second register value in the register corresponding to the second register address is obtained by sending a second read instruction. If the second register value is 0x80, it means that the power-on is successful. If the second register value is not 0x80, it means that the power-on is unsuccessful.

[0101] Exemplarily, by sending the second register address and the second read instruction, it is verified whether the first register value is executed correctly. If the first register value is executed correctly, the verification is passed. If the first register value is not executed correctly, the verification fails, and the first register value is resent until the verification passes.

[0102] In this feasible implementation, the second read instruction is used to verify whether the first register value is correctly written. If it is not correctly written, it is rewritten, which can effectively deal with write failures and thus improve the reliability of hard disk control.

[0103] A feasible implementation method, after repeatedly sending the second register address and the first register value, also includes: starting a timer; if the first register value is different from the second register value after the timer times out, determining a third register address and a third register value, the third register address and the third register value are used to instruct the target adapter board CPLD to execute a reset instruction; sending the third register address and the third register value to the target adapter board CPLD through a target channel.

[0104] Combined with the scenario example, if a fault occurs and the first register value cannot be written correctly, the adapter board CPLD is instructed to perform a reset operation. Among them, the register corresponding to the third register address stores the reset instruction, the third register value is the reset instruction, and writing the third register value to the third register address executes the reset instruction. By executing the reset instruction, the hard disk can be initialized to restore the state of the hard disk.

[0105] Next, combine Figure 6 The reset instruction is explained.

[0106] Figure 6 A schematic diagram of a reset instruction provided in an embodiment of the present application. Figure 6 As shown, after sending the first register value, the second register value is read by the second read instruction to verify whether the first register value is correctly executed. If the first register value is the same as the second register value, the verification is passed. If the first register value is different from the second register value, it is determined whether the timer has timed out. If not, the first register value is sent repeatedly and the verification is repeated. If it is timed out, the third register value is sent to reset.

[0107] In this feasible implementation, by setting a timer, the number of times the first register value is repeatedly sent can be controlled, thereby avoiding failures caused by unlimited sending of the first register value and improving the reliability of the storage controller.

[0108] In a feasible implementation, the hard disk control method also includes: determining a target duration; obtaining multiple communication addresses corresponding to multiple channels under the first I2C at every target duration; verifying the first I2C according to the multiple communication addresses to obtain a verification result, the verification result including verification passed or verification failed; if the verification result is verification failed, sending a register instruction to multiple adapter board CPLDs connected to the first I2C through the second I2C.

[0109] Optionally, if the multiple communication addresses are the same as the preset values, it means that the first I2C can communicate normally, and the verification passes. Otherwise, the verification fails.

[0110] Exemplarily, the second I2C is used as a redundant control I2C. The connection method of the second I2C is the same as that of the first I2C.

[0111] Combined with the scenario example, by default, the second I2C does not work, and data is sent only through the first I2C. When the first I2C fails, it switches to the second I2C to ensure normal data transmission.

[0112] In this feasible implementation, a redundant control I2C is set, and the redundant control I2C works when the first I2C fails, which can increase the fault tolerance of the storage controller and thus improve the reliability of the storage controller.

[0113] Figure 7 This is a schematic diagram of the structure of a hard disk control device provided in an embodiment of the present application. Figure 7 As shown, the hard disk control device 70 may include: a receiving module 71, a determining module 72, a comparing module 73, and a sending module 74, wherein:

[0114] The receiving module 71 is used to receive a control request, where the control request includes a target hard disk identifier corresponding to the target hard disk and a target control instruction.

[0115] The determination module 72 is used to determine the target adapter board CPLD corresponding to the target hard disk identifier and the target channel corresponding to the target adapter board CPLD in the first I2C according to the control request.

[0116] The comparison module 73 is used to determine the target register instruction corresponding to the target control instruction.

[0117] The sending module 74 is used to send a target register instruction to the target adapter board CPLD through a target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction.

[0118] Optionally, the receiving module 71 may execute Figure 2 S201 in the embodiment.

[0119] Optionally, the determination module 72 may execute Figure 2 S202 in the embodiment.

[0120] Optionally, the comparison module 73 may execute Figure 2 S203 in the embodiment.

[0121] Optionally, the sending module 74 may execute Figure 2 S204 in the embodiment.

[0122] It should be noted that the hard disk control device shown in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0123] In a possible implementation, the comparison module 73 is specifically configured to:

[0124] Determine a target mapping relationship corresponding to the target adapter board CPLD, the target mapping relationship including a mapping relationship between a control instruction and a register address, and a mapping relationship between a control instruction and a register value;

[0125] Determine a first register address and a first read instruction according to the target mapping relationship, wherein the first register address and the first read instruction are used to read the in-place status information of the target hard disk;

[0126] Determine a second register address and a first register value according to the target control instruction and the target mapping relationship, wherein the second register address and the first register value are used to instruct the target adapter board CPLD to execute the target register instruction;

[0127] The target register instruction is determined to include a first register address, a first read instruction, a second register address, and a first register value.

[0128] Figure 8 This is a schematic diagram of the structure of a hard disk control device provided in an embodiment of the present application. Figure 7 Based on the embodiment shown, Figure 8 As shown, the hard disk control device 80 also includes: an execution module 75, a first verification module 76, a second verification module 77, and a backup module 78, wherein:

[0129] The execution module 75 is used to:

[0130] Sending a switching instruction to the I2C switch, the switching instruction including a channel identifier corresponding to the target channel;

[0131] Sending a first register address and a first read instruction to a target adapter board CPLD through a target channel, and receiving target in-position state information sent by the target adapter board CPLD, where the target in-position state information includes in-position or not in-position;

[0132] If the target in-place status information is in-place, the second register address and the first register value are sent to the target adapter board CPLD through the target channel.

[0133] The first verification module 76 is used to:

[0134] Determine a second read instruction, the second read instruction is used to read a register value of the register;

[0135] Sending a second register address and a second read instruction to the target adapter board CPLD through a target channel, and receiving a second register value sent by the target adapter board CPLD;

[0136] If the first register value is different from the second register value, the second register address and the first register value are repeatedly sent to the target adapter board CPLD through the target channel until the first register value is the same as the second register value.

[0137] The second verification module 77 is used to:

[0138] Start the timer;

[0139] If the first register value is different from the second register value after the timer times out, a third register address and a third register value are determined, and the third register address and the third register value are used to instruct the target adapter board CPLD to execute a reset instruction;

[0140] The third register address and the third register value are sent to the target adapter board CPLD through the target channel.

[0141] The spare module 78 is used for:

[0142] Determine the target duration;

[0143] At target time intervals, multiple communication addresses corresponding to multiple channels under the first I2C are obtained;

[0144] Performing verification processing on the first I2C according to the multiple communication addresses to obtain a verification result, where the verification result includes verification passing or verification failing;

[0145] If the verification result is that the verification fails, a register instruction is sent to multiple adapter board CPLDs connected to the first I2C via the second I2C.

[0146] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown in FIG. Fig. 9 As shown, the electronic device includes:

[0147] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, the memory 292, and the communication interface 293 may communicate with each other through the bus 294. The communication interface 293 may be used for information transmission. The processor 291 may call the logic instructions in the memory 292 to execute the method of the above embodiment.

[0148] In addition, the logic instructions in the above-mentioned memory 292 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0149] The memory 292 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, that is, implementing the methods in the above method embodiments.

[0150] The memory 292 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 292 may include a high-speed random access memory and may also include a non-volatile memory.

[0151] An embodiment of the present application provides a non-temporary computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method as described in the above embodiment.

[0152] An embodiment of the present application provides a computer program product, including a computer program, which implements the method of the above embodiment when the computer program is executed by a processor.

[0153] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0154] It should be further noted that, although the various steps in the flowchart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowchart may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0155] It should be understood that the above-mentioned device embodiments are only illustrative, and the device of the present application can also be implemented in other ways. For example, the division of units / modules in the above-mentioned embodiments is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units, modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed.

[0156] In addition, unless otherwise specified, each functional unit / module in each embodiment of the present application may be integrated into one unit / module, each unit / module may exist physically separately, or two or more units / modules may be integrated together. The above-mentioned integrated unit / module may be implemented in the form of hardware or in the form of a software program module.

[0157] If the integrated unit / module is implemented in the form of hardware, the hardware may be a digital circuit, an analog circuit, etc. The physical implementation of the hardware structure includes but is not limited to transistors, memristors, etc. The processor may be any appropriate hardware processor, such as a CPU, a GPU, an FPGA, a DSP, and an ASIC, etc. The storage unit may be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access memory DRAM (Dynamic Random Access Memory), a static random access memory SRAM (Static Random-Access Memory), an enhanced dynamic random access memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc.

[0158] If the integrated unit / module is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0159] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0161] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for controlling a hard disk, characterized in that: A control board complex programmable logic device CPLD applied to a storage controller, wherein the control board CPLD is connected to a plurality of adapter board CPLDs via an integrated circuit bus I2C, and the method comprises: receiving a control request, wherein the control request includes a target hard disk identifier corresponding to the target hard disk and a target control instruction; According to the control request, determining the target adapter board CPLD corresponding to the target hard disk identifier and the target channel corresponding to the target adapter board CPLD in the first I2C; Determine a target register instruction corresponding to the target control instruction; The target register instruction is sent to the target adapter board CPLD through the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction.

2. The method according to claim 1, characterized in that Determining a target register instruction corresponding to the target control instruction includes: Determine a target mapping relationship corresponding to the target adapter board CPLD, wherein the target mapping relationship includes a mapping relationship between a control instruction and a register address, and a mapping relationship between a control instruction and a register value; Determine a first register address and a first read instruction according to the target mapping relationship, wherein the first register address and the first read instruction are used to read the in-place status information of the target hard disk; Determine a second register address and a first register value according to the target control instruction and the target mapping relationship, wherein the second register address and the first register value are used to instruct the target adapter board CPLD to execute the target register instruction; Determine that the target register instruction includes the first register address, the first read instruction, the second register address, and the first register value.

3. The method according to claim 2, characterized in that Sending the target register instruction to the target adapter board CPLD through the target channel includes: Sending a switching instruction to the I2C switch, wherein the switching instruction includes a channel identifier corresponding to the target channel; Sending the first register address and the first read instruction to the target adapter board CPLD through the target channel, and receiving target in-position state information sent by the target adapter board CPLD, wherein the target in-position state information includes in-position or not in-position; If the target in-place status information is in-place, the second register address and the first register value are sent to the target adapter board CPLD through the target channel.

4. The method according to claim 3, characterized in that The method further comprises: Determining a second read instruction, wherein the second read instruction is used to read a register value of a register; Sending the second register address and the second read instruction to the target adapter board CPLD through the target channel, and receiving the second register value sent by the target adapter board CPLD; If the first register value is different from the second register value, the second register address and the first register value are repeatedly sent to the target adapter board CPLD through the target channel until the first register value is the same as the second register value.

5. The method according to claim 4, characterized in that After repeatedly sending the second register address and the first register value, the method further includes: Start the timer; If, after the timer times out, the first register value is different from the second register value, determining a third register address and a third register value, wherein the third register address and the third register value are used to instruct the target adapter board CPLD to execute a reset instruction; The third register address and the third register value are sent to the target adapter board CPLD through the target channel.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Determine the target duration; At each target duration, obtaining multiple communication addresses corresponding to multiple channels under the first I2C; Performing verification processing on the first I2C according to the multiple communication addresses to obtain a verification result, wherein the verification result includes verification passing or verification failing; If the verification result is that the verification fails, a register instruction is sent to multiple adapter board CPLDs connected to the first I2C via a second I2C.

7. A hard disk control device, characterized in that: A control board complex programmable logic device CPLD applied to a storage controller, wherein the control board CPLD is connected to a plurality of adapter board CPLDs via an integrated circuit bus I2C, and the device comprises: A receiving module, used for receiving a control request, wherein the control request includes a target hard disk identifier corresponding to the target hard disk and a target control instruction; A determination module, used for determining, according to the control request, a target adapter board CPLD corresponding to the target hard disk identifier and a target channel corresponding to the target adapter board CPLD in the first I2C; A comparison module, used to determine a target register instruction corresponding to the target control instruction; The sending module is used to send the target register instruction to the target adapter board CPLD through the target channel, so that the target adapter board CPLD controls the target hard disk connected to the target adapter line CPLD according to the target register instruction.

8. An electronic device, characterized in that: include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product, characterized in that The invention comprises a computer program, which implements the method according to any one of claims 1 to 6 when being executed by a processor.

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