Peripheral access function implementation method and device, equipment and readable storage medium

Abstract

The invention discloses a peripheral access function implementation method and device, equipment and a readable storage medium. The method comprises the following steps: configuring a start judgment process, basic information for data transmission and a channel number of a next associated DMA channel for each DMA channel contained in a peripheral access program on the basis of configuration information; and after the configuration is completed, running the peripheral access program so as to realize a peripheral access function. According to the method and the device, peripheral access and CPU calculation are decoupled, each DMA channel runs independently of the CPU according to predefined software logic, the method and the device are applicable to conventional MCUs, do not need to depend on a specific MCU architecture, can greatly reduce CPU load at the same time, and are particularly applicable to high-real-time application scenarios.

Description

Technical Field

[0001] The present application relates to the field of embedded technology, and in particular to a method, device, equipment and computer-readable storage medium for implementing a peripheral access function. Background Art

[0002] In embedded systems, the CPU needs to periodically read and write peripheral registers to control data exchange between peripherals and registers to achieve real-time control requirements. However, frequent CPU read and write operations will take up a lot of processor time and system resources, reducing the overall performance and efficiency of the system. To solve this problem, the current solution is to introduce a specific coprocessor or use a single core in a multi-core MCU to perform peripheral access operations. This method requires the custom development of a coprocessor with special functions, which will increase hardware costs.

[0003] Using DMA function to access peripherals can also reduce CPU load, but DMA is only used for data transmission and cannot assist CPU in implementing functional logic. That is, to implement a certain function, DMA simply performs data or peripheral reading and writing functions, while CPU performs logic operations, which cannot completely free up CPU and limits its applicability and flexibility in certain application scenarios. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides a method, device, equipment and computer-readable storage medium for implementing a peripheral access function.

[0005] In a first aspect, an embodiment of the present application provides a method for implementing a peripheral access function, the method comprising:

[0006] Based on the configuration information, a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel are configured for each DMA channel included in the peripheral access program;

[0007] After the configuration is completed, the peripheral access program is run to implement the peripheral access function.

[0008] In conjunction with the first aspect, in one implementation, starting the determination process includes:

[0009] Check whether the state value of the target register is a preset value;

[0010] If it is the preset value, it is determined that the start condition is met.

[0011] In conjunction with the first aspect, in one implementation, starting the determination process includes:

[0012] Detect whether the target peripheral generates a preset event;

[0013] If a preset event occurs, it is determined that the start condition is met.

[0014] In conjunction with the first aspect, in one implementation, starting the determination process includes:

[0015] Check whether the startup instruction sent by the CPU is received;

[0016] If a start instruction is received from the CPU, it is determined that the start condition is met.

[0017] In combination with the first aspect, in one implementation, running the peripheral access program includes:

[0018] When the start condition of the i-th DMA channel is met, the i-th DMA channel operation is triggered. i is used to identify the start order of the DMA channel. The smaller i is, the earlier the start order is. The initial value of i is 1.

[0019] When the i-th DMA channel operation is completed, check whether the channel number of the next associated DMA channel is empty;

[0020] If it is not empty, set i=i+1, and return to when the start condition of the i-th DMA channel is met, trigger the i-th DMA channel operation until the channel number of the next associated DMA channel is empty.

[0021] In a second aspect, an embodiment of the present application provides a device for implementing a peripheral access function, the device for implementing a peripheral access function comprising:

[0022] A configuration module, configured to configure a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel for each DMA channel included in the peripheral access program based on the configuration information;

[0023] The running module is used to run the peripheral access program after the configuration is completed to realize the peripheral access function.

[0024] In conjunction with the second aspect, in one implementation, starting the determination process includes:

[0025] Check whether the state value of the target register is a preset value;

[0026] If it is the preset value, it is determined that the start condition is met.

[0027] In conjunction with the second aspect, in one implementation, starting the determination process includes:

[0028] Detect whether the target peripheral generates a preset event;

[0029] If a preset event occurs, it is determined that the start condition is met.

[0030] In a third aspect, an embodiment of the present application provides a peripheral access function implementation device, which includes a processor, a memory, and a peripheral access function implementation program stored in the memory and executable by the processor, wherein when the peripheral access function implementation program is executed by the processor, the steps of the peripheral access function implementation method described in the first aspect are implemented.

[0031] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a peripheral access function implementation program is stored, wherein when the peripheral access function implementation program is executed by a processor, the steps of the peripheral access function implementation method described in the first aspect are implemented.

[0032] The beneficial effects brought by the technical solution provided in the embodiments of the present application include:

[0033] In the embodiment of the present application, a startup determination process, basic information for data transmission, and the channel number of the next associated DMA channel are configured for each DMA channel included in the peripheral access program based on the configuration information; after the configuration is completed, the peripheral access program is run to implement the peripheral access function. Through the embodiment of the present application, the peripheral access is decoupled from the CPU calculation, and each DMA channel runs independently of the CPU according to the predefined software logic. It is applicable to conventional MCUs without relying on a specific MCU architecture. At the same time, it can greatly reduce the CPU load, which is particularly suitable for high real-time application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a flow chart of an embodiment of a method for implementing a peripheral access function of the present application;

[0035] Figure 2 A schematic diagram of functional modules of an embodiment of a device for implementing a peripheral access function of the present application;

[0036] Figure 3 A schematic diagram of the hardware structure of a device for implementing the peripheral access function involved in the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0039] In a first aspect, an embodiment of the present application provides a method for implementing a peripheral access function.

[0040] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of an embodiment of a method for implementing a peripheral access function of the present application. Figure 1 As shown, the method for implementing the peripheral access function includes:

[0041] Step S10, configuring a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel for each DMA channel included in the peripheral access program based on the configuration information;

[0042] In this embodiment, the peripheral access program includes one or more DMA channels. For ease of explanation, the peripheral access program includes three DMA channels as an example, which are recorded as DMA channel 1, DMA channel 2, and DMA channel 3 in the order of execution. During configuration, the three DMA channels can be configured in the order of execution, or in other orders, or simultaneously configured in parallel.

[0043] Among them, configuring the start determination process is to set the start condition of the DMA channel. The start determination process corresponding to each DMA channel is set based on actual needs. The start determination processes corresponding to different DMA channels can be the same or different.

[0044] Furthermore, in one embodiment, the startup determination process includes:

[0045] Check whether the state value of the target register is a preset value; if it is a preset value, determine that the start condition is met.

[0046] In this embodiment, the status value of the target register is first read through a read instruction and saved in a shared memory, wherein the status value is a specific bit in a byte or multiple bytes. Then, the status value is written into a trigger control register through a write instruction. If the trigger control register detects that the specific bit is a preset value, it is determined that the start condition is met.

[0047] The read instruction is used to write the data in the register into the shared memory, where the value of the register can represent the external input status, such as the input level of the PIN pin, the duty cycle of the frequency signal, the ADC sampling value, the data received by SPI and other peripheral resources. The write instruction is used to write the data in the shared memory into the register, including the output level of the PIN pin, the duty cycle of the frequency signal, the ADC sampling trigger signal, the data to be sent by SPI, etc.

[0048] Furthermore, in one embodiment, the startup determination process includes:

[0049] Detect whether the target peripheral generates a preset event; if the preset event is generated, determine whether the start condition is met.

[0050] In this embodiment, the preset event is, for example, a timer overflow event, a PIN pin level flip event, an ADC data acquisition completion event, etc. The preset event can be generated by writing data in the shared memory into the target register through a write instruction.

[0051] The following is an explanation of the timer overflow event:

[0052] The predefined timer overflow value and control word in the shared memory are written into the timer register corresponding to the DMA channel through a write instruction and the timer register is activated. The timer overflow determines that the start condition is met.

[0053] Furthermore, in one embodiment, the startup determination process includes:

[0054] Check whether a startup instruction sent by the CPU is received; if the startup instruction sent by the CPU is received, it is determined that the startup condition is met.

[0055] In this embodiment, the DMA channel triggering is implemented by the CPU sending a start instruction. The specific DMA channels that are triggered by the CPU sending a start instruction are selected according to actual needs.

[0056] The basic information used for data transmission includes the source address, the destination address, and the read / write flag. For example, if DMA channel 1 is used for a read operation, the source address s1, the destination address o1, and the read / write flag r of DMA channel 1 are set according to the configuration information, and the data in the destination address o1 is cleared; if DMA channel 2 is used for a write operation, the source address s2, the destination address o2, and the read / write flag w of DMA channel 2 are set according to the configuration information, and the preset data is written to the source address s2. It should be noted that this is only a schematic description of the basic information used for data transmission, and the specific content contained therein can be increased or decreased based on actual needs.

[0057] It is easy to understand that the channel number of the next associated DMA channel is related to the execution order, and the last executed DMA channel does not have an associated next DMA channel, that is, the channel number of the next associated DMA channel is empty.

[0058] Step S20, after the configuration is completed, running the peripheral access program to implement the peripheral access function.

[0059] In this embodiment, after the configuration is completed, it can be determined whether the corresponding startup conditions are met based on the startup order of the DMA channels and according to the startup determination process of each DMA channel configuration. If the startup conditions are met, the DMA channel operation is started to realize the peripheral access function.

[0060] Furthermore, in one embodiment, running the peripheral access program includes:

[0061] When the start condition of the i-th DMA channel is met, the i-th DMA channel operation is triggered. i is used to identify the start order of the DMA channel. The smaller i is, the earlier the start order is. The initial value of i is 1.

[0062] When the i-th DMA channel operation is completed, check whether the channel number of the next associated DMA channel is empty;

[0063] If it is not empty, set i=i+1, and return to when the start condition of the i-th DMA channel is met, trigger the i-th DMA channel operation until the channel number of the next associated DMA channel is empty.

[0064] In this embodiment, it is assumed that the DMA channels included in the peripheral access program are DMA channel 1, DMA channel 2 and DMA channel 3, wherein DMA channel 1 is started first, then DMA channel 2 is started, and finally DMA channel 3 is started.

[0065] First, based on the start-up determination process of DMA channel 1, it is determined whether the start-up conditions of DMA channel 1 are met. The start-up determination process is as described above and will not be repeated here. It should be noted that if it is started based on a timer overflow event, the timer overflow event can be generated only once or cyclically. When the start-up conditions of DMA channel 1 are met, the DMA channel 1 operation is triggered, and the DMA channel 1 operation can be the above-mentioned read instruction or write instruction.

[0066] After the DMA channel 1 operation is completed, the channel number of the next associated DMA channel is the channel number of DMA channel 2. It is necessary to determine whether the start condition of DMA channel 2 is met based on the start determination process of DMA channel 2. When the start condition of DMA channel 2 is met, DMA channel operation 2 is triggered. The DMA channel 1 operation can be the above-mentioned read instruction or write instruction. And so on, until the channel number of the next associated DMA channel is empty, the peripheral access program ends.

[0067] In the embodiment of the present application, a startup determination process, basic information for data transmission, and the channel number of the next associated DMA channel are configured for each DMA channel included in the peripheral access program based on the configuration information; after the configuration is completed, the peripheral access program is run to implement the peripheral access function. Through the embodiment of the present application, the peripheral access is decoupled from the CPU calculation, and each DMA channel runs independently of the CPU according to the predefined software logic. It is applicable to conventional MCUs without relying on a specific MCU architecture. At the same time, it can greatly reduce the CPU load, which is particularly suitable for high real-time application scenarios.

[0068] In a second aspect, an embodiment of the present application also provides a device for implementing a peripheral access function.

[0069] In one embodiment, referring to Figure 2 , Figure 2 This is a functional module diagram of an embodiment of a device for implementing a peripheral access function of the present application. Figure 2 As shown, the peripheral access function implementation device includes:

[0070] A configuration module 10, configured to configure a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel for each DMA channel included in the peripheral access program based on the configuration information;

[0071] The running module 20 is used to run the peripheral access program after the configuration is completed to realize the peripheral access function.

[0072] Furthermore, in one embodiment, the startup determination process includes:

[0073] Check whether the state value of the target register is a preset value;

[0074] If it is the preset value, it is determined that the start condition is met.

[0075] Furthermore, in one embodiment, the startup determination process includes:

[0076] Detect whether the target peripheral generates a preset event;

[0077] If a preset event occurs, it is determined that the start condition is met.

[0078] Furthermore, in one embodiment, the startup determination process includes:

[0079] Check whether the startup instruction sent by the CPU is received;

[0080] If a start instruction is received from the CPU, it is determined that the start condition is met.

[0081] Furthermore, in one embodiment, running the peripheral access program includes:

[0082] When the start condition of the i-th DMA channel is met, the i-th DMA channel operation is triggered. i is used to identify the start order of the DMA channel. The smaller i is, the earlier the start order is. The initial value of i is 1.

[0083] When the i-th DMA channel operation is completed, check whether the channel number of the next associated DMA channel is empty;

[0084] If it is not empty, set i=i+1, and return to when the start condition of the i-th DMA channel is met, trigger the i-th DMA channel operation until the channel number of the next associated DMA channel is empty.

[0085] Among them, the function implementation of each module in the above-mentioned peripheral access function implementation device corresponds to each step in the above-mentioned peripheral access function implementation method embodiment, and its functions and implementation processes are no longer repeated here one by one.

[0086] In a third aspect, an embodiment of the present application provides a device for implementing a peripheral access function, which may be a device having a data processing function such as a microcontroller unit MCU or a computer.

[0087] Reference Figure 3 , Figure 3 The hardware structure diagram of the peripheral access function implementation device involved in the embodiment of the present application is shown in FIG. In the embodiment of the present application, the peripheral access function implementation device may include a processor, a memory, a communication interface, and a communication bus.

[0088] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.

[0089] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces, which are used to implement peripheral access functions to interconnect devices within the device, and interfaces used to implement peripheral access functions to interconnect the device with other devices (such as other computing devices or user devices). Physical interfaces can be Ethernet interfaces, optical fiber interfaces, ATM interfaces, etc.; user devices can be display screens (Display), keyboards (Keyboard), etc.

[0090] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0091] The processor may be a general-purpose processor, and the general-purpose processor may call the peripheral access function implementation program stored in the memory and execute the peripheral access function implementation method provided by the embodiment of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the peripheral access function implementation program is called may refer to the various embodiments of the peripheral access function implementation method of the present application, which will not be repeated here.

[0092] Those skilled in the art will understand that Figure 3 The hardware structure shown in the figure does not constitute a limitation on the present application, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0093] In a fourth aspect, an embodiment of the present application also provides a computer-readable storage medium.

[0094] The computer-readable storage medium of the present application stores a peripheral access function implementation program, wherein when the peripheral access function implementation program is executed by a processor, the steps of the peripheral access function implementation method as described above are implemented.

[0095] Among them, the method implemented when the peripheral access function implementation program is executed can refer to the various embodiments of the peripheral access function implementation method of the present application, and will not be repeated here.

[0096] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0097] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0098] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0099] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0100] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0102] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A method for implementing a peripheral access function, characterized in that: The method for implementing the peripheral access function comprises: Based on the configuration information, a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel are configured for each DMA channel included in the peripheral access program; After the configuration is completed, the peripheral access program is run to implement the peripheral access function.

2. The method for implementing the peripheral access function according to claim 1, characterized in that: The startup determination process includes: Check whether the state value of the target register is a preset value; If it is the preset value, it is determined that the start condition is met.

3. The method for implementing the peripheral access function according to claim 1, characterized in that: The startup determination process includes: Detect whether the target peripheral generates a preset event; If a preset event occurs, it is determined that the start condition is met.

4. The method for implementing the peripheral access function according to claim 1, characterized in that: The startup determination process includes: Check whether the startup instruction sent by the CPU is received; If a start instruction is received from the CPU, it is determined that the start condition is met.

5. The method for implementing the peripheral access function according to any one of claims 1 to 4, characterized in that: The running of the peripheral access program comprises: When the start condition of the i-th DMA channel is met, the i-th DMA channel operation is triggered. i is used to identify the start order of the DMA channel. The smaller i is, the earlier the start order is. The initial value of i is 1. When the i-th DMA channel operation is completed, check whether the channel number of the next associated DMA channel is empty; If it is not empty, set i=i+1, and return to when the start condition of the i-th DMA channel is met, trigger the i-th DMA channel operation until the channel number of the next associated DMA channel is empty.

6. A device for implementing a peripheral access function, characterized in that: The peripheral access function implementation device comprises: A configuration module, configured to configure a start determination process, basic information for data transmission, and a channel number of an associated next DMA channel for each DMA channel included in the peripheral access program based on the configuration information; The running module is used to run the peripheral access program after the configuration is completed to realize the peripheral access function.

7. The device for realizing the peripheral access function according to claim 6, characterized in that: The startup determination process includes: Check whether the state value of the target register is a preset value; If it is the preset value, it is determined that the start condition is met.

8. The device for realizing the peripheral access function according to claim 6, characterized in that: The startup determination process includes: Detect whether the target peripheral generates a preset event; If a preset event occurs, it is determined that the start condition is met.

9. A device for implementing a peripheral access function, characterized in that: The peripheral access function implementation device includes a processor, a memory, and a peripheral access function implementation program stored in the memory and executable by the processor, wherein when the peripheral access function implementation program is executed by the processor, the steps of the peripheral access function implementation method as described in any one of claims 1 to 5 are implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a peripheral access function implementation program, wherein when the peripheral access function implementation program is executed by a processor, the steps of the peripheral access function implementation method according to any one of claims 1 to 5 are implemented.

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