Serial communication control method and device, electronic equipment and storage medium

Abstract

The application provides a serial communication control method and device, electronic equipment and a storage medium. The serial communication control method is applied to a digital signal processor (DSP), the DSP comprises a configurable logic block, and the method comprises the following steps: determining a period duration count value according to a negotiated baud rate of serial communication and a clock signal of the DSP; the configurable logic block controls a first counter to perform accumulated counting based on the clock signal of the DSP, outputs a first signal in response to the accumulated counting of the first counter reaching a preset second value, outputs a second signal in response to the accumulated counting reaching a preset first value, and resets the first counter; generating a first clock signal according to the first signal and the second signal, the frequency of the first clock signal being a frequency corresponding to the negotiated baud rate; and controlling the timing of the first clock signal to be aligned with the timing of a data frame of a bus. The application has the advantages of being simpler, more flexible and having better effects.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a serial communication control method and device, electronic equipment and storage medium. BACKGROUND

[0002] Serial communication is widely used because of simple control circuit and strong anti-interference. In actual application scenarios, since there is no transmission synchronization clock, the terminal device of serial communication must communicate at the agreed baud rate. The existence of overlong serial communication lines and the deviation of working clocks of different devices relative to the bus clock will cause positive and negative errors of baud rate to accumulate during communication, resulting in deviation of terminal devices when analyzing the timing of each byte bit, and further communication frame analysis error. In the traditional technology, a separate dedicated integrated circuit is generally used to realize serial communication anti-interference, but there are problems of complexity and high cost. SUMMARY

[0003] The present application provides a serial communication control method and device, electronic equipment and storage medium to solve the problem of complexity of serial communication anti-interference realized by a separate dedicated integrated circuit in the traditional technology. The various aspects involved in the present application are introduced below.

[0004] In a first aspect, the present application provides a serial communication control method applied to a digital signal processor (DSP), wherein the DSP includes a configurable logic block, and the configurable logic block is configured with a first counter; the method includes: determining a preset first value according to an agreed baud rate of serial communication and a clock signal of the DSP; the preset first value is a period length count value; controlling the first counter to perform cumulative counting based on the clock signal of the DSP, and in response to the cumulative counting of the first counter reaching a preset second value, outputting a first signal; in response to the cumulative counting of the first counter reaching the preset first value, outputting a second signal, and resetting the first counter; generating a first clock signal according to the first signal and the second signal, and the frequency of the first clock signal is the frequency corresponding to the agreed baud rate; and controlling the timing of the first clock signal to align with the timing of a data frame of a bus.

[0005] In a second aspect, the present application provides a serial communication control device applied to a DSP; the DSP comprises a configurable logic block; the configurable logic block is configured with a first counter; the serial communication control device comprises: a determination unit configured to determine a preset first value according to a convention baud rate of serial communication and a clock signal of the DSP; the preset first value is a period length count value; a counting unit configured to control the first counter to count based on the clock signal of the DSP, output a first signal in response to the first counter counting reaching a preset second value, output a second signal in response to the first counter counting reaching the preset first value, and reset the first counter; a generation unit configured to generate a first clock signal according to the first signal and the second signal, the frequency of the first clock signal being a frequency corresponding to the convention baud rate; and a corresponding unit configured to control the timing of the first clock signal to align with the timing of a data frame of a bus.

[0006] In a third aspect, the present application provides an electronic device comprising a memory and a DSP, the memory storing a computer program, and the DSP implementing the steps of the method of the first aspect when executing the computer program.

[0007] In a fourth aspect, the present application provides a non-volatile computer readable storage medium storing a computer program, the computer program being executable by a processor to implement the method of the first aspect.

[0008] In a fifth aspect, the present application provides a computer program product, when the computer program product is run on an electronic device, the electronic device is caused to implement the method of the first aspect.

[0009] The present application maps the hardware description language logic of the field programmable gate array to the configurable logic block (CLB) of the DSP. Since the CLB is a built-in module and the CLB has hardware resources such as counters, these hardware resources can be interconnected through programming, and the logic circuit required by the user can be constructed. The CLB generates a system clock signal of the convention baud rate in cooperation with the DSP clock signal, aligns the generated system clock signal with the timing of the data frame, can directly process the data of the serial communication, and avoids the problem of serial communication data frame parsing error caused by baud rate deviation. The present application uses the configurable logic block inside the DSP to implement the anti-interference function of the serial communication, without using a separate application specific integrated circuit, which is more simple and flexible, low in cost, and better in effect. BRIEF DESCRIPTION OF DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced.

[0011] Figure 1 is a flowchart of a serial communication control method provided by the embodiments of the present application.

[0012] Figure 2 is a working schematic diagram of a counter.

[0013] Figure 3 is Figure 1 is a flowchart of a possible implementation of the method.

[0014] Figure 4 is a working schematic diagram of a finite element state machine.

[0015] Figure 5 is Figure 1 is a circuit schematic diagram of a possible implementation of the method.

[0016] Figure 6 is Figure 1 is a circuit schematic diagram of another possible implementation of the method.

[0017] Figure 7 is a composition schematic diagram of a serial communication control device provided by the embodiments of the present application.

[0018] Figure 8 is a composition unit / part composition unit schematic diagram of an electronic device provided by the embodiments of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The same or similar reference signs are used to represent the same or similar modules in the drawings. It should be understood that the drawings are only schematic, and the protection scope of the present application is not limited thereto.

[0020] A serial interface (SI) refers to data being transmitted sequentially one bit at a time, and is a very common low-speed communication interface. Its feature is that the communication line is simple, and only a pair of transmission lines can realize bidirectional communication. Baud rate is a parameter for measuring communication speed, which represents the number of bits transmitted per second, and the unit of baud rate is baud (Baud). The device connected to the serial port communicates at the agreed baud rate, that is, the devices at both ends of the serial port can only realize normal communication under the condition of maintaining the same rate, otherwise debugging instructions will be invalid and display will be garbled.

[0021] In inverter control systems, serial communication is widely used due to its simple control circuitry and strong anti-interference capabilities. In practical applications, since there is no synchronous clock for transmission, the terminal devices in serial communication must communicate at a pre-agreed baud rate. The receiving device samples the received communication byte level on the rising edge of its own clock according to its own operating clock timing, ultimately correctly parsing each individual communication byte.

[0022] In practical applications, excessively long serial communication lines and deviations in the operating clocks of different devices relative to the bus clock can accumulate positive and negative baud rate errors during communication. This leads to deviations in the timing of each byte bit parsing by the terminal device, resulting in communication frame parsing errors. Electromagnetic compatibility (EMC) interference present on the bus can also affect the waveform of serial communication, causing communication frame parsing errors. All of these factors reduce the anti-interference performance of serial communication.

[0023] To improve the anti-interference performance of communication, serial communication terminal equipment needs to consider baud rate adaptive methods. Related technologies employ dedicated application-specific integrated circuits (ASICs) to achieve anti-interference. However, implementing anti-interference for serial communication using ASICs is complex and costly.

[0024] Therefore, it is necessary to design a relatively simple anti-interference technology for serial communication.

[0025] Based on this, this application proposes a serial communication control method. The method of this application is applied to a digital signal processor (DSP), wherein the DSP includes a configurable logic block (CLB), and the configurable logic block is configured with a first counter. This application directly processes the waveform of serial communication through the CLB module built into the DSP, thereby achieving anti-interference control of serial communication. The following is in conjunction with… Figure 1 The serial communication control method of the embodiments of this application will be described in detail. For example... Figure 1 As shown, the serial communication control method of this application embodiment mainly includes steps S110 to S140, which are described in detail below.

[0026] It should be noted that the sequence number of each step in the embodiments of this application does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0027] In step S110, a preset first value is determined based on the agreed baud rate of serial communication and the clock signal of the DSP. The preset first value is the period duration count value.

[0028] The period length count value is determined by the baud rate agreed upon by the serial communication, and is configured before the communication starts. The receiving device must be synchronized to the agreed baud rate of the transmission, so as to correctly sample the received data. Ideally, the sampling clock in the receiving device can be an even multiple of the agreed baud rate, for example, 16 times the baud rate frequency. The sampling clock counts the bits in an even number, so as to have an equal number of high and low pulses. For example, when the agreed baud rate is 2MBps, and the clock frequency of the high-frequency DSP for sampling is 48MHz, then every 24 sampling clock periods is equal to the time for transmitting one bit, and thus the period length count value can be set to 24.

[0029] In step S120, the first counter is controlled to count up based on the clock signal of the DSP. In response to the count up of the first counter reaching a preset second value, a first signal is output. In response to the count up of the first counter reaching a preset first value, a second signal is output, and the first counter is reset. The first counter is controlled to be cleared and start counting again, so as to automatically cycle, which can ensure the accuracy of the data saved by the first counter, and thus improve the stability of the communication clock. The preset second value is less than the period length count value. Preferably, the preset second value is 1 / 2 of the preset first value.

[0030] The counter is a widely used logic element in digital circuits, which is used to count the number of input pulses, and can also be used for frequency division, timing, generating beat pulses, etc. The first counter can be any type of counter, as long as it meets the function in step S120. The first counter can refer to one counter, or a counter module composed of multiple counters.

[0031] Figure 2 is a schematic diagram of a counter. As shown in Figure 2 The counter 200 can have 4 input ports and 3 output ports (pins). The 4 input ports are mode 1 (mode1), mode 2 (mode2), event (event), and reset (reset) ports, and the 3 output ports are match 1 (match1), match 2 (match2), and zero (zero) ports. The counter 200 can be a type of the first counter. The counter 200 can count up with the DSP clock signal, and when the count matches the preset second value, the match1 port outputs a high-level pulse signal; when the count reaches the preset first value, i.e., reaches the period length of the baud rate, the zero port outputs a high-level trigger signal, and the reset port is reset to start counting again.

[0032] The period length count value is an even number, the DSP clock signal is counted by an even number of bits, and the same number of high pulses and low pulses can be generated, which helps to reduce baud rate error and improve communication stability.

[0033] In step S130, a first clock signal is generated according to the first signal and the second signal, and a frequency of the first clock signal is a frequency corresponding to the agreed baud rate.

[0034] It can be understood that the first signal and the second signal are alternating signals. One first signal and one second signal are a cycle period, and then enter the next cycle period.

[0035] In some implementations, the configurable logic block is configured with a first finite element state machine. The method in step S130 can include: controlling the first finite element state machine to output a first level according to the input first signal, the first level being a high level; controlling the first finite element state machine to output a second level according to the input second signal, the second level being a low level; and generating a first clock signal according to the first level and the second level, thereby generating a clock signal of the agreed baud rate of the communication. It can be understood that the first level and the second level are alternating signals of the first finite element state machine.

[0036] In step S140, the timing of the first clock signal is aligned with the timing of the data frame of the bus.

[0037] According to the serial port protocol, when no data is transmitted or data transmission is completed, the communication data line must be kept at a high level, and when the sending end starts to send data, a low level must be sent as a start bit first. Specifically, when a falling edge of the received serial port data is detected in the start bit waiting state, it indicates that the start bit data has been obtained, and then the first counter starts counting.

[0038] Typically, a single frame of data has 10 bits of data, including 1 start bit, 8 data bits, and 1 stop bit, so there can be multiple falling edges. In some implementations, the method of step S140 can specifically include: resetting the first counter according to at least one falling edge pulse signal of the multiple falling edge pulse signals of the received data frame, so that the first counter re-counts, so that the timing of the first clock signal is aligned with the timing of the data frame of the bus. Thus, the timing of the generated first clock signal can be aligned with the timing of the data frame.

[0039] To prevent the noise of the data line from being misjudged as the start data, the serial port data can be collected multiple times to improve the accuracy of the start bit data acquisition. In some implementations, the configurable logic block is configured with a first lookup table. A first input terminal of the first lookup table is configured to receive a signal of a data frame of the bus, and an output terminal of the first lookup table is connected to a reset port of a first counter. The method of step S140 can include: in response to the first lookup table receiving a first falling edge pulse signal of the data frame, outputting a high-level pulse signal, and the high-level pulse signal is used to reset the first counter. Generally, a data frame has multiple falling edge pulse signals, and the first falling edge pulse signal is any falling edge pulse signal in the multiple falling edge pulse signals of the data frame. Multiple correction timings are performed by using the multiple falling edge pulse signals, which helps to avoid timing deviations caused by interference and baud rate deviation, and further enhances the anti-interference ability of serial communication.

[0040] The serial communication bus usually has some spike pulse interference, and it is necessary to filter the pulse signal of the bus. A multiple frequency clock signal can be used to filter the pulse signal of the bus.

[0041] In some implementations, the configurable logic block is configured with a second counter. The method of the embodiment of the application can further include: controlling the second counter to count based on the clock signal of the DSP, and in response to the accumulated count of the second counter reaching 1 / 2n of the preset first value, outputting a third signal. In response to the accumulated count reaching 1 / n of the preset first value, a fourth signal is outputted, and the second counter is reset, where n is an even number, for example, n can be 4, 8, 16, etc. According to the third signal and the fourth signal, a second clock signal is generated. It can be seen that the frequency of the second clock signal is n times the frequency of the first clock signal. That is, the second clock signal is an n times frequency signal of the first clock signal, and the received pulse signal of the bus can be filtered according to the second clock signal.

[0042] In some implementations, the configurable logic block is configured with a second finite element state machine. The above-mentioned generating a second clock signal according to the third signal and the fourth signal can include: controlling the second finite element state machine to output a high level and a low level respectively according to the input third signal and fourth signal; and generating a second clock signal according to the alternately generated high level and low level.

[0043] In some specific implementations, the configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter. The received bus pulse signal is connected to a reset port of the third counter. The filtering of the received bus pulse signal according to the second clock signal can include: inverting the received bus pulse signal by using the second lookup table, and connecting the inverted bus pulse signal to a reset port of the fourth counter; counting the high-level pulse in the bus pulse signal by using the third counter based on the second clock signal, and counting the low-level pulse in the bus pulse signal by using the fourth counter. In response to the accumulated count of the third counter reaching a preset sampling length, a fifth signal is output, and in response to the accumulated count of the fourth counter reaching the preset sampling length, a sixth signal is output. The third finite element state machine outputs high level and low level respectively according to the input fifth signal and sixth signal; and outputs the filtered bus pulse signal according to the high level and low level periodically output by the third finite element state machine. The multiple n of the multiple frequency can be 4, for example, and the received bus pulse signal can be filtered according to the 4 multiple frequency clock signal.

[0044] Since the second clock signal is a multiple frequency signal of the first clock signal, in some implementations, the first counter can count based on the second clock signal generated by the second counter to obtain the first clock signal, which helps to further simplify the circuit.

[0045] The hardware description language (very-high-speed integrated circuit hardware description language, VHDL) logic of the field programmable gate array (FPGA) is mapped to the CLB of the DSP itself in the embodiments of the application. Since the CLB is a built-in module and the CLB has hardware resources such as counters, these hardware resources can be interconnected through programming, and the logic circuit required by the user can be constructed. The CLB cooperates with the DSP signal to generate a system clock signal with a specified baud rate, and aligns the generated system clock signal with the timing of the data frame, so that the serial communication data can be directly processed, and the problem of serial communication data frame analysis error caused by baud rate deviation can be avoided. The embodiments of the application do not need to use a separate application-specific integrated circuit, and the CLB module inside the DSP is used to realize the anti-interference of serial communication, which is more simple and flexible, low in cost, and better in effect.

[0046] The method of the embodiments of the application will be further described below in combination with some possible implementation manners of the embodiments of the application.

[0047] Figure 3 is Figure 1Flowchart of one possible implementation of the method. As Figure 3 The counting flow of the first counter of the embodiment of the application can mainly include steps S310 to S380, which are described in detail below.

[0048] In step S310, start.

[0049] In step S320, the counter accumulates counting.

[0050] The first counter accumulates counting based on the DSP clock signal, and the structure of the counter can be as shown in Figure 2

[0051] In step S330, it is judged whether the counting value reaches a preset second value (i.e. 1 / 2 of the period length counting value).

[0052] If the accumulated counting value reaches the preset second value, step S350 is entered; otherwise, counting continues.

[0053] In step S340, it is judged whether the counting value reaches a preset first value (i.e. the period length counting value).

[0054] That is, it is judged whether the period length counting value is reached, and if the accumulated counting value reaches the preset first value, step S360 is entered; otherwise, counting continues.

[0055] In step S350, the match1 port of the counter outputs a high-level pulse signal, i.e. outputs the first signal.

[0056] In step S360, the match2 port of the counter outputs a high-level pulse signal, i.e. outputs the second signal.

[0057] In step S370, it is judged whether the reset port receives a reset signal.

[0058] In step S380, the first counter is reset, and the zero port outputs a high-level pulse signal.

[0059] After the period length counting value of the agreed baud rate is reached, the reset port is reset, the counting is restarted, and the counting of the next cycle period is started, so as to cyclically generate the first signal and the second signal.

[0060] The period length counting value is an even number, the DSP clock signal counts with even bits, and can have equal numbers of high pulses and low pulses, which helps to improve the stability of the baud rate and reduce the cumulative error of the system.

[0061] Figure 4 ​is a state diagram of a finite state machine. The finite state machine (FSM) is composed of a state register and a combinational logic circuit, and can perform state transition according to a control signal according to a pre-set state, and is a control element for coordinating the actions of related signals and completing a specific operation.

[0062] As shown in Figure 4 , when the match1 port of the first counter outputs a high level trigger signal to the finite state machine (FSM), the finite state machine outputs a high level "1". When the first counter reaches the baud rate period length count value, it will be reset, and the zero port outputs a high level trigger signal to the FSM, and the finite state machine outputs a low level "0". The alternately generated high level "1" and low level "0" generate the first clock signal, that is, the baud rate clock signal agreed upon in communication.

[0063] Figure 5 is Figure 1 The circuit diagram of a possible implementation manner of the method. As shown in Figure 5 , the configurable logic block 500 can include: a second counter 510, a second finite state machine 520, a first lookup table 530, a first counter 540, a first finite state machine 550, a third lookup table 560, and a fourth lookup table 570.

[0064] Among them, the third lookup table 560 and the fourth lookup table 570 are LUT3, which are lookup tables (LUT) with three inputs. The first lookup table 530 is LUT4, which is a lookup table with four inputs. The lookup table is usually used to realize the combinational logic of a specific output corresponding to any given input combination.

[0065] Figure 5 In the embodiment of the application, two parts of generating a system clock and clock alignment are included. Among them, the system clock generates two groups of clock signals, one group is a four times frequency clock signal (i.e. the second clock signal) used for pulse filtering; the other group is a normal baud rate clock signal (i.e. the first clock signal) used for clock alignment processing. The configurable logic block 500 uses a counter (COUNT) and a finite state machine (FSM) to generate a clock signal that meets the baud rate of serial communication. Among them, the second counter 510, the second finite state machine 520 and the fourth lookup table 570 are used to generate the second clock signal (i.e. the four times frequency clock signal).

[0066] 1) Generate a system clock signal.

[0067] Firstly, the period length count value is calculated according to the agreed baud rate of serial communication and the DSP clock signal. According to the period length count value, a preset first value and a preset second value are determined. The preset first value is the period length count value of the system baud rate, and the preset second value is half of the period length count value.

[0068] According to the period length count value, a preset third value and a preset fourth value of the four times frequency clock signal are determined. The preset third value is 1 / 4 of the period length count value, and the preset fourth value is 1 / 8 of the period length count value.

[0069] Based on the DSP clock signal, the second counter 510 performs cumulative counting. When the count value reaches the preset value, the corresponding port outputs a high level pulse signal for driving the subsequent logic unit for logic processing. For example, when the count value reaches the preset fourth value, the match1 port of the second counter 510 outputs a high level trigger signal to the second finite element state machine 520, and the second finite element state machine 520 outputs a high level “1”. When the count value reaches the preset third value (1 / 4 of the period length count value), it is reset, and the zero port of the second counter 510 outputs a high level trigger signal to the second finite element state machine 520, and the second finite element state machine 520 outputs a low level “0”. According to the high and low levels alternately generated by the second finite element state machine 520, the fourth lookup table 570 generates a four times frequency baud rate clock signal. The four times frequency clock signal can be used for pulse signal filtering of the bus. The serial communication bus may, for example, be an RS-422 bus or an RS-485 bus.

[0070] Based on the DSP clock signal, the first counter 540 performs cumulative counting. When the count value matches the preset second value, the match1 port of the first counter 540 outputs a high level trigger signal to the first finite element state machine 550, and the first finite element state machine 550 outputs a high level “1”. When the count value reaches the preset first value (the period length count value of the agreed baud rate), the first counter 540 is reset, and the zero port of the first counter 540 outputs a high level trigger signal to the first finite element state machine 550, and the first finite element state machine 550 outputs a low level “0”. According to the high and low levels cyclically output by the first finite element state machine 550, the second lookup table 560 generates a clock signal of the agreed baud rate, i.e. the first clock signal.

[0071] 2) Clock alignment processing.

[0072] The configurable logic block 500 uses a LUT4, i.e. the first lookup table 530, to realize the timing alignment of the first clock signal and the data frame.

[0073] The single frame data contains 10 bits of data, including 1 start bit, 8 data bits and 1 stop bit, and there can be multiple falling edges. The falling edge pulse signal of the data is connected to the input port i0 of the first lookup table 530, and when the falling edge pulse signal (i.e. the first falling edge pulse signal) arrives, the pulse signal drives the output port of the third lookup table 570 to output a high-level pulse signal. The output high-level pulse signal is connected to the reset port of the first counter 540 and the reset port of the second counter 510, so that the first counter 540 and the second counter 510 are re-counted, i.e. the system clock is re-counted, which can ensure that the generated system clock is aligned with the timing of the data frame. In other words, the timing of the first clock signal is aligned with the timing of the data frame, and the timing of the second clock signal is aligned with the timing of the data frame. Multiple correction timings can be performed using multiple falling edge pulse signals in each data frame, which helps to avoid timing deviations caused by interference and baud rate deviations, and enhances the anti-interference ability of serial communication.

[0074] Figure 6 is Figure 1 Circuit schematic diagram of another possible implementation of the method. As Figure 6 shown, the configurable logic block 500 can further include a second lookup table 610, a third counter 620, a fourth counter 630, a third finite state machine 640, and a fifth lookup table 650. The second lookup table 610 is a LUT4, i.e. a lookup table with four inputs. The fifth lookup table 650 is a LUT3, i.e. a lookup table with three inputs.

[0075] Specifically, the configurable logic block 500 uses the second lookup table 610 to invert the serial communication data input signal, and uses two counters to count the number of pulses on the bus. The third counter 620 and the fourth counter 630 are respectively used for high-level pulse and low-level pulse counting. When any one of the counters reaches a preset sampling length, its match1 port outputs a pulse. The preset sampling length of the filter can be set to 2, and the preset sampling length can be half of the frequency multiplication number (n = 4). For example, when the count value of the high-level pulse of the third counter 620 reaches 2, its match1 port outputs a pulse to the third finite state machine 640. When the count value of the low-level pulse of the fourth counter 630 reaches 2, its match1 port outputs a pulse to the third finite state machine 640. The third finite state machine 640 latches the pulse and inverts the level signal to determine the level required for the S0 port state output. Then the fifth lookup table 650 is used to transmit the filtered signal output to the peripheral device for parsing the serial data frame.

[0076] The embodiment of the application maps the hardware description language logic into the CLB of the DSP itself. Since the CLB is a built-in module, and the CLB has hardware resources such as a counter, a lookup table, a state machine and the like, these hardware resources can be interconnected through programming, and the logic circuit required by the user can be constructed. The CLB generates a system clock signal with a negotiated baud rate in cooperation with the DSP signal, and aligns the generated system clock signal with the timing of the data frame, so that the serial communication data can be directly processed. The different levels of the serial communication data are sampled through a four-fold clock signal, and the signal filtering function is realized through the counter, which helps to enhance the anti-interference ability to the peak pulse and avoid the problem of serial communication data frame analysis error caused by baud rate deviation. The embodiment of the application does not need to use a separate application specific integrated circuit, and uses the CLB module in the DSP to realize the anti-interference of serial communication, which is more simple and flexible and has better effect.

[0077] The above Figures 1-6 The method embodiment of the application is described in detail, and the following Figures 7 to 8 The device embodiment of the application is described in detail. It should be understood that the description of the device embodiment corresponds to the description of the method embodiment, and therefore, the parts not described in detail can be referred to the foregoing method embodiment.

[0078] The embodiment of the application provides a serial communication control device applied to a DSP; the DSP comprises a configurable logic block; the configurable logic block is configured with a first counter. Figure 7 is a schematic diagram of the serial communication control device provided by the embodiment of the application. As Figure 7 shown, the serial communication control device 700 can comprise a determination unit 710, a counting unit 720, a generation unit 730 and an alignment unit 740.

[0079] The determination unit 710 is configured to determine a preset first value according to a negotiated baud rate of serial communication and a clock signal of the DSP; the preset first value is a period length count value.

[0080] The counting unit 720 is configured to control the first counter to perform cumulative counting based on the clock signal of the DSP, output a first signal in response to the cumulative counting of the first counter reaching a preset second value, output a second signal in response to the cumulative counting of the first counter reaching the preset first value, and reset the first counter.

[0081] The generation unit 730 is configured to generate a first clock signal according to the first signal and the second signal, and the frequency of the first clock signal is a frequency corresponding to the negotiated baud rate.

[0082] The alignment unit 740 is configured to align the timing of the first clock signal with the timing of the data frame of the bus.

[0083] Optionally, the aligning unit 740 is configured to reset the first counter according to at least one falling edge pulse signal of the plurality of falling edge pulse signals of the received data frame, so as to align the timing of the first clock signal with the timing of the data frame of the bus.

[0084] Optionally, the configurable logic block is configured with a first lookup table, a first input terminal of the first lookup table being configured to receive a signal of the data frame of the bus, and an output terminal of the first lookup table being connected to a reset port of the first counter. The aligning unit 740 is configured to output a high level pulse signal in response to the first lookup table receiving a first falling edge pulse signal of the data frame, the high level pulse signal being configured to reset the first counter, and the first falling edge pulse signal being any one of the plurality of falling edge pulse signals.

[0085] Optionally, the configurable logic block is configured with a first finite element state machine. The generating unit 730 is configured to control the first finite element state machine to output a first level according to an input first signal, the first level being a high level; control the first finite element state machine to output a second level according to an input second signal, the second level being a low level; and generate the first clock signal according to the first level and the second level.

[0086] Optionally, the configurable logic block is configured with a second counter, and the serial communication control device 700 further comprises a filtering unit. The generating unit 730 is configured to control the second counter to count based on a clock signal of the DSP, output a third signal in response to the count of the second counter reaching 1 / 2n of a preset first value, output a fourth signal in response to the count reaching 1 / n of the preset first value, and reset the second counter, n being an even number; generate the second clock signal according to the third signal and the fourth signal; and the frequency of the second clock signal is n times the frequency of the first clock signal. The filtering unit is configured to filter the received pulse signal of the bus according to the second clock signal.

[0087] Optionally, the configurable logic block is configured with a second finite element state machine. The generating unit 730 is configured to control the second finite element state machine to output a high level and a low level according to an input third signal and an input fourth signal, respectively; and generate the second clock signal according to the alternately generated high level and low level.

[0088] Optionally, the configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter, and the pulse signal of the bus is connected to a reset port of the third counter. The filtering unit is configured to perform inverse processing on the received pulse signal of the bus by using the second lookup table, and the inverse processed pulse signal of the bus is connected to a reset port of the fourth counter; based on the second clock signal, the third counter is configured to count the high-level pulse in the pulse signal of the bus, and the fourth counter is configured to count the low-level pulse in the pulse signal of the bus; in response to the accumulated count of the third counter reaching a preset sampling length, a fifth signal is output; the preset sampling length is n / 2; in response to the accumulated count of the fourth counter reaching the preset sampling length, a sixth signal is output; the third finite element state machine is controlled to output high level and low level respectively according to the input fifth signal and sixth signal; and the third finite element state machine is controlled to output high level and low level alternately according to the high level and low level alternately generated by the third finite element state machine, and the filtered pulse signal of the bus is output.

[0089] The embodiment of the present application also provides an electronic device. Figure 8 is a schematic diagram of a component unit / part component unit of the electronic device provided by the embodiment of the present application. As shown in the figure, the electronic device 800 is configured with a digital signal processor 810, and the digital signal processor 810 includes a configurable logic block 500. The electronic device 800 may, for example, be a frequency converter or an encoder. The digital signal processor 810 is configured to perform the following operations: Figure 8

[0090] According to the convention baud rate of serial communication and the clock signal of the DSP, a preset first value is determined, and the preset first value is a period length count value. The first counter is controlled to perform accumulated counting based on the clock signal of the DSP, a first signal is output in response to the accumulated count of the first counter reaching a preset second value, a second signal is output and the first counter is reset in response to the accumulated count of the first counter reaching the preset first value. The first clock signal is generated according to the first signal and the second signal, and the frequency of the first clock signal is the frequency corresponding to the convention baud rate; and the timing of the first clock signal is controlled to be aligned with the timing of the data frame of the bus. The preset second value may be 1 / 2 of the preset first value.

[0091] Those skilled in the art can understand that, Figure 8 The above merely is an example of the electronic device 800, and does not constitute a limitation on the electronic device. More or fewer components than those shown may be included, or certain components may be combined or different components may be included. The electronic device provided by the embodiment may perform the method embodiments described above, and the implementation principles and technical effects are similar, which will not be described here again.

[0092] ​The embodiment of the present application further provides a nonvolatile computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in each of the method embodiments.

[0093] The embodiment of the present application provides a computer program product. When the computer program product is run on an electronic device, the electronic device is caused to perform the steps in each of the method embodiments.

[0094] The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above method embodiments by a computer program to instruct related hardware to complete. The computer program can be stored in a computer readable storage medium. The computer program is executed by a processor to implement the steps in each of the method embodiments. The computer program includes computer program code. The computer program code can be in the form of source code, object code, executable files or some intermediate forms. The computer readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / electronic device, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk and optical data storage device, etc. The computer readable storage medium mentioned in the present application can be a nonvolatile storage medium, in other words, a non-transitory storage medium.

[0095] In the above embodiments, the description of each embodiment has its own focus. The parts not described or recorded in detail in a certain embodiment can be referred to the relevant description of other embodiments.

[0096] Those skilled in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0097] In the embodiments provided in the present application, it should be understood that the disclosed apparatuses / devices and methods can be implemented in other manners. For example, the embodiments of the apparatus / device described above are merely schematic. For example, the division of the modules or units is merely logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0098] It should be understood that the term "comprising" as used in the specification and the appended claims indicates the presence of the recited features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0099] It should also be understood that the term "and / or" as used in the specification and the appended claims indicates any combination of one or more of the associated listed items and all possible combinations of those items.

[0100] As used in the specification and the appended claims, the term "if" can be interpreted as meaning "when" or "once" or "in response to a determination" or "in response to detecting" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to the determination" or "once [the described condition or event] is detected" or "in response to detecting [the described condition or event]" depending on the context.

[0101] In addition, in the description of the specification and the appended claims, the terms "first", "second", and the like are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0102] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A serial communication control method characterized by comprising: The application is applied to a DSP; the DSP comprises a configurable logic block; The configurable logic block is configured with a first counter; the method comprises: According to a convention baud rate of serial communication and a clock signal of the DSP, a preset first value is determined; the preset first value is a period time count value; The first counter is controlled to count based on the clock signal of the DSP; a first signal is output in response to that the count of the first counter reaches a preset second value; a second signal is output in response to that the count of the first counter reaches the preset first value, and the first counter is reset; According to the first signal and the second signal, a first clock signal is generated; the frequency of the first clock signal is the frequency corresponding to the convention baud rate; The timing of the first clock signal is controlled to be aligned with the timing of a data frame of a bus.

2. The serial communication control method according to claim 1, characterized by, The control of the timing of the first clock signal to be aligned with the timing of the data frame of the bus comprises: According to at least one falling edge pulse signal of a plurality of falling edge pulse signals of a received data frame, the first counter is reset to make the timing of the first clock signal aligned with the timing of the data frame of the bus.

3. The serial communication control method according to claim 2, characterized by, The configurable logic block is configured with a first lookup table; a first input end of the first lookup table is used to receive a signal of a data frame of a bus; an output end of the first lookup table is connected to a reset port of the first counter; The reset of the first counter according to at least one falling edge pulse signal of a plurality of falling edge pulse signals of a received data frame comprises: In response to that the first lookup table receives a first falling edge pulse signal of the data frame, a high level pulse signal is output; the high level pulse signal is used to reset the first counter; the first falling edge pulse signal is any falling edge pulse signal of the plurality of falling edge pulse signals.

4. The serial communication control method according to claim 1, characterized by, The configurable logic block is configured with a first finite element state machine; the generation of the first clock signal according to the first signal and the second signal comprises: The first finite element state machine is controlled to output a first level according to the input first signal; the first level is a high level; The first finite element state machine is controlled to output a second level according to the input second signal; the second level is a low level; The first clock signal is generated according to the first level and the second level.

5. The serial communication control method according to claim 1, characterized by, The configurable logic block is configured with a second counter; the method further comprises: The second counter is controlled to count based on the clock signal of the DSP; a third signal is output in response to that the count of the second counter reaches 1 / 2n of the preset first value; a fourth signal is output in response to that the count reaches 1 / n of the preset first value, and the second counter is reset, n is an even number; According to the third signal and the fourth signal, a second clock signal is generated; the frequency of the second clock signal is n times of the frequency of the first clock signal; The received pulse signal of the bus is filtered according to the second clock signal.

6. The serial communication control method according to claim 5, characterized by, The configurable logic block is configured with a second finite element state machine, and the generating of the second clock signal according to the third signal and the fourth signal comprises: controlling the second finite element state machine to output high level and low level respectively according to the input third signal and fourth signal; generating the second clock signal according to the alternately generated high level and low level.

7. The serial communication control method according to claim 5, characterized by, The configurable logic block is configured with a second lookup table, a third finite element state machine, a third counter and a fourth counter, and the pulse signal of the bus is connected to the reset port of the third counter; the filtering of the received pulse signal of the bus according to the second clock signal comprises: inverting the received pulse signal of the bus by using the second lookup table, and connecting the inverted pulse signal of the bus to the reset port of the fourth counter; counting the high level pulse in the pulse signal of the bus by using the third counter based on the second clock signal, and counting the low level pulse in the pulse signal of the bus by using the fourth counter; outputting a fifth signal in response to the accumulated count of the third counter reaching a preset sampling length; the preset sampling length is n / 2; outputting a sixth signal in response to the accumulated count of the fourth counter reaching the preset sampling length; controlling the third finite element state machine to output high level and low level respectively according to the input fifth signal and sixth signal; outputting the filtered pulse signal of the bus according to the alternately generated high level and low level of the third finite element state machine.

8. A serial communication control device characterized by comprising: The application is applied to a DSP; the DSP comprises a configurable logic block; The configurable logic block is configured with a first counter; and the serial communication control device comprises: a determination unit configured to determine a preset first value according to a convention baud rate of serial communication and a clock signal of the DSP; the preset first value is a period length count value; a counting unit configured to control the first counter to accumulate count based on the clock signal of the DSP, output a first signal in response to the accumulated count of the first counter reaching a preset second value, and output a second signal in response to the accumulated count of the first counter reaching the preset first value and reset the first counter; a generation unit configured to generate a first clock signal according to the first signal and the second signal; the frequency of the first clock signal is the frequency corresponding to the convention baud rate; a corresponding unit configured to control the timing of the first clock signal to align with the timing of a data frame of a bus.

9. An electronic device comprising a memory and a DSP, said memory storing a computer program, characterized in that, The DSP implements the steps of the method of any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored thereon, and the computer program is used to implement the method of any one of claims 1 to 7 when executed.

Images