A PCIe clock gating circuit and a PCIe clock control method

Abstract

The application provides a PCIe clock gating circuit and a PCIe clock control method. The circuit comprises a link width control circuit, a link rate control circuit and a link state control circuit. The link width control circuit is configured to output a control signal for closing the clock of a non-current width related module when the current link width is less than the maximum width. The link rate control circuit is configured to output a control signal for closing the clock of a non-current rate related module. The link state control circuit is configured to output a control signal for closing the clock of a non-normal working state related module when the current link state is a non-normal working state. The non-normal working state related module comprises a related module corresponding to other link states except the current link state. The link state control circuit is further configured to output a control signal for closing the clock of a training code stream sending module, a training code stream receiving module and a link training related module when in a normal working state.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a PCIe clock gating circuit and a PCIe clock control method. BACKGROUND

[0002] With the iterative upgrade of the PCIe protocol, the PCIe protocol has been updated to version 6.0, and the power consumption of the PCIe system gradually increases with the increase of functions and the improvement of complexity. Although the PCIe system has a low-power management (L1 state) by itself, it needs to be negotiated by both ends when entering the low-power state, and the data transmission stops when the entire system enters the low-power mode, so the L1 low-power state of the PCIe can only solve the power consumption problem when the link is idle. SUMMARY

[0003] The application aims to provide a PCIe clock gating circuit and a PCIe clock control method, and aims to solve the problem of power consumption when the PCIe system link is idle.

[0004] According to a first aspect of the application, a PCIe clock gating circuit is provided, comprising a link width control circuit, a link rate control circuit and a link state control circuit; wherein,

[0005] The link width control circuit is configured to output a control signal for closing the clock of a non-current width related module when the current link width is less than the maximum width; the non-current width related module includes a module related to other channels other than the channel corresponding to the current link width, and a module related to other link widths other than the current link width;

[0006] The link rate control circuit is configured to output a control signal for closing the clock of a non-current rate related module, and the non-current rate related module includes a module corresponding to other link rates other than the current link rate;

[0007] The link state control circuit is configured to output a control signal for closing the clock of a non-normal working state related module when the current link state is a non-normal working state, and the non-normal working state related module includes a module corresponding to other link states other than the current link state;

[0008] The link state control circuit is further configured to output a control signal for closing the clock of a training code stream sending module, a training code stream receiving module and a link training related module when in a normal working state.

[0009] In an optional embodiment, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link width.

[0010] In an optional embodiment, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the 128b / 130b conversion module, message reception processing module, message transmission processing module, and Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of the PAM4 encoding and decoding module, message reception processing module, and message transmission processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include the 8b / 10b conversion module corresponding to Gen1 or Gen2 , at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate-related modules include at least one of an 8b / 10b conversion module, a message receiving processing module, and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0011] In an optional embodiment, the abnormal operating state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal operating state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal operating state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module; the abnormal operating state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0012] In an optional embodiment, the PCIe clock gating circuit further includes: a logic OR gate;

[0013] The logic OR gate is used to perform a logic OR operation on the multiple control signals to be output to the same clock.

[0014] In an optional embodiment, the PCIe clock gating circuit further includes: a register enable signal output circuit;

[0015] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

[0016] According to a second aspect of the present application, a PCIe clock control method is provided, comprising:

[0017] When the current link width is less than the maximum width, the link width control circuit outputs a control signal to shut down the clocks of modules not related to the current width; the modules not related to the current width include modules related to channels other than the channel corresponding to the current link width, and modules related to link widths other than the current link width;

[0018] The link rate control circuit outputs a control signal for shutting down clocks of modules not related to the current rate, wherein the modules not related to the current rate include modules corresponding to link rates other than the current link rate;

[0019] When the current link state is an abnormal working state, the link state control circuit outputs a control signal to shut down the clock of a module related to the abnormal working state, wherein the module related to the abnormal working state includes a module corresponding to a link state other than the current link state;

[0020] When the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

[0021] In an optional embodiment, the non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link width.

[0022] In an optional embodiment, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of the 128b / 130b conversion module, message reception processing module, message transmission processing module, and Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of the PAM4 encoding and decoding module, message reception processing module, and message transmission processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include the 8b / 10b conversion module corresponding to Gen1 or Gen2 , at least one of a message receiving processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate-related modules include at least one of an 8b / 10b conversion module, a message receiving processing module, and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

[0023] In an optional embodiment, the abnormal operating state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal operating state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal operating state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module; the abnormal operating state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0024] In an optional embodiment, the method further comprises:

[0025] The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0026] In an optional embodiment, the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate, including:

[0027] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0028] The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0029] Compared with related technologies, the technical solution of this application has the following advantages:

[0030] The PCIe clock gating circuit proposed in this application can effectively reduce the dynamic power consumption of the entire PCIe system. It distinguishes active modules by PCIe link width, link rate, and link operating scenario. Disabling the clocks of inactive modules significantly reduces clock and logic flips. Compared to the related art of clock gating that inserts registers, module-level clock modules require fewer hardware resources and are simpler in design.

[0031] In addition, the module-level clock gating circuit controls the clock on and off without software intervention, and all control is automatically completed by hardware; at the same time, the software can control the opening and closing of the clock gating, which increases the flexibility of the entire solution.

[0032] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purpose and other advantages of the present application can be achieved and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 4 is a structural block diagram of a PCIe clock gating circuit according to an exemplary embodiment of the present application.

[0035] Figure 2 2 is a schematic diagram of a module clock controlled by a link width control circuit according to an exemplary embodiment of the present application.

[0036] Figure 3 2 is a schematic diagram of a module clock controlled by a link rate control circuit according to an exemplary embodiment of the present application.

[0037] Figure 4 2 is a schematic diagram of a module clock controlled by a link state control circuit according to an exemplary embodiment of the present application.

[0038] Figure 5 It is a schematic diagram of the working principle and effect of the PCIe clock control circuit according to an exemplary embodiment of the present application.

[0039] Figure 6is a flow chart of a PCIe clock control method according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solutions and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0041] Because PCIe has numerous features and functions, and cannot enter a low-power state when the link is loaded, dynamic power consumption accounts for a high proportion of the total power consumption in PCIe systems, and clock flip power consumption also accounts for a significant proportion of dynamic power consumption. Generally, register gating is added during PCIe system design to reduce register D-side flips and clock flips. Adding register gating can reduce dynamic power consumption.

[0042] PCIe links can support a maximum width of x16. When system traffic is low, such a large link width is unnecessary. The PCIe system supports negotiation between both ends to reduce the link width. When an unused link enters electrical idle mode, the clock to the corresponding link can be turned off, reducing the dynamic power consumption of the PCIe system.

[0043] As the functionality increases with the iteration of the PCIe protocol, the size of the PCIe system also increases. The PCIe system needs to be backward compatible with previous versions, resulting in the system needing to support many features and functions. Even if the functions of the old version are not used, its clock flips and logic flips will still cause dynamic power consumption. However, in reality, most of the time PCIe will only work stably in one of the link configurations, which causes most modules responsible for different link widths and link speeds to be idle, so the dynamic power consumption caused by the clock flips of these modules can be avoided. In addition, a large part of the logic modules in the PCIe system are used for link training, but when the PCIe system is working (the state machine is in the L0 state), the modules responsible for link training do not need to work, and the clock flips and logic flips of these modules will cause dynamic power consumption expenditure.

[0044] Furthermore, PCIe systems in related art reduce dynamic power consumption by adding register gating. Register gating has the following issues: 1. It consumes a large amount of control resources; 2. It negatively impacts timing; 3. It has little effect on improving dynamic gating efficiency; and 4. Register gating logic cannot be reused. The module-level clock gating used in related art mostly uses customized logic. This design cannot be reused when the PCIe system is iteratively upgraded or the application scenario changes.

[0045] Based on the above analysis, this application proposes a PCIe clock gating circuit, which has the following characteristics:

[0046] 1. Design clock gating by taking advantage of the PCIe system's characteristics of operating at one link width (one of x1, x2, x4, x8, and x16) and one link rate (8b / 10b encoding for Gen1 or Gen2, 128b130b encoding for Gen3, Gen4, or Gen5, and PAM4 encoding for Gen6). Use module-level clock gating to shut down the clocks of modules related to other link widths and link rates that are not working. This approach can reduce clock and logic flips in related modules, thereby reducing dynamic power consumption.

[0047] 2. Design clock gating by taking advantage of the fact that the PCIe system link training-related modules do not work in the L0 state, and use module-level clock gating to shut down the clocks of all modules related to link training.

[0048] 3. Use dedicated clock gating circuits and encapsulate them into a common clock gating component module (CBB). Using circuits optimized for clock gating that provide better performance and lower leakage current, encapsulating them into modules and instantiating them at the top level can increase the reuse of module-level clock gating.

[0049] 4. Add register enable for module-level clock gating. The host can control the clock gating switch by configuring the register. When the enable switch is on, the hardware controls whether the clock gating turns off the clock. When the enable switch is off, the clock gating keeps the clock on. This approach can increase system stability and flexibility.

[0050] See also Figure 1 As shown, the present application exemplarily proposes a PCIe clock gating circuit, including: a link width control circuit 101, a link rate control circuit 102 and a link state control circuit 103. Among them:

[0051] The link width control circuit 101 is configured to output a control signal to shut down clocks of modules not related to the current width when the current link width is less than the maximum width; the modules not related to the current width include modules related to channels other than the channel corresponding to the current link width, and modules related to link widths other than the current link width;

[0052] The link rate control circuit 102 is used to output a control signal to shut down the clock of the non-current rate related modules, and the non-current rate related modules include related modules corresponding to other link rates other than the current link rate;

[0053] The link state control circuit 103 is configured to output a control signal to shut down the clocks of modules related to the abnormal working state when the current link state is an abnormal working state, wherein the modules related to the abnormal working state include modules corresponding to other link states other than the current link state;

[0054] The link state control circuit 103 is further configured to output a control signal to shut down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules in a normal working state.

[0055] In some embodiments, when the current link width is less than the maximum width supported by the PCIe system, unused channels, i.e., channels other than the current channel, enter an electrical idle state. At this time, the logic of the other channels is not used, and the clocks of the corresponding modules, i.e., modules not related to the current width, can be turned off. It is understandable that when the current link width is the maximum width, since all channels will be used, there is no need to turn off the clocks of the corresponding modules. For example, if the current link width is 4 and the maximum width is 16, then the modules corresponding to the other link widths can be modules that are used only when the other channels, except for the 4 channels corresponding to the current link width, are turned on.

[0056] In some optional implementations, the non-current width-related module includes a channel-related module and a path-related module; the channel-related module includes at least one of a de-skew module, an scrambling module, and a message bus module corresponding to each other channel; the path-related module includes a rate conversion module, a message sending module, and a message receiving module corresponding to the other link widths.

[0057] See also Figure 2 As shown, in some embodiments, the training code stream (TS) related modules, the Deskew module (deskewing module), the scrambling and descrambling modules, and the message bus module are all instantiated based on the number of channels in the PCIe system, that is, each channel corresponds to the above modules. When the current link width is less than the maximum width, the link width control circuit can generate a control signal to shut down the clock of the corresponding module, thereby shutting down the above modules corresponding to other unused channels (that is, the training code stream (TS) related modules, the Deskew module (deskewing module), the scrambling and descrambling modules, and the message bus module, wherein the training code stream (TS) related modules are link training related modules, which are always shut down under normal working conditions). The above modules can be referred to as channel related modules.

[0058] Exemplarily, the non-current width related module further comprises a lane related module. The conversion between 8b / 10b and 128b / 130b in the data lane is also instantiated in the number of lanes, and when the current link width is less than the maximum width, the clock corresponding to the rate conversion module related to the conversion between 8b / 10b and 128b / 130b corresponding to other lanes can be turned off. The rate conversion module corresponding to other lanes belongs to the lane related module.

[0059] Exemplarily, the sending and receiving of the message in the data lane are related to the current PCIe link width. The current PCIe link width determines the position of the symbol code (identification code) and the token code (token code) of the message, and different link widths have different decoding logics. Therefore, the PCIe system only needs to turn on the clock of the message sending module and the message receiving module related to the current link width, and the clock of the message sending module and the message receiving module of other link widths can be turned off. The message sending module or the message receiving module corresponding to other link widths belongs to the lane related module.

[0060] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate related module comprises at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module and the Gen5 pre-encoding module corresponding to Gen3, Gen4 or Gen5, and at least one of the PAM4 encoding and decoding module, the message receiving processing module and the message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related module comprises at least one of the 8b / 10b conversion module, the message receiving processing module and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the PAM4 encoding and decoding module, the message receiving processing module and the message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related module comprises at least one of the 8b / 10b conversion module, the message receiving processing module and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module and the Gen5 pre-encoding module corresponding to Gen3, Gen4 or Gen5.

[0061] Referring to Figure 3As shown, illustratively, when the current link rate is Gen1 or Gen2, the clocks of the training stream (TS) transmission / reception module, 8b / 10b conversion module, and data transmission / reception module corresponding to Gen1 or Gen2 are all turned on, while at other link rates, the clocks of these modules are turned off. In other words, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include the relevant modules corresponding to Gen3, Gen4, Gen5, and Gen6, and the link rate control circuit outputs a control signal to turn on the clock to the relevant modules corresponding to Gen1 or Gen2, while outputting a control signal to turn off the clock to the relevant modules corresponding to Gen3, Gen4, Gen5, and Gen6.

[0062] When the current link rate is Gen3, Gen4, or Gen5, the clocks of the training stream (TS) transmit / receive module, 128b / 130b conversion module, message receive processing module, message transmit processing module, and precoding module (operating only at Gen5) corresponding to Gen3, Gen4, or Gen5 are enabled. At other link rates, the clocks of these modules are disabled. That is, when the current link rate is Gen3, Gen4, or Gen5, the modules not related to the current rate include the modules corresponding to Gen1, Gen2, and Gen6. The link rate control circuit outputs a clock-enabling control signal to the modules corresponding to Gen3, Gen4, or Gen5, while outputs a clock-disabling control signal to the modules corresponding to Gen1, Gen2, and Gen6.

[0063] When the current link rate is Gen6, the clocks of the PAM4 codec module, message reception processing module, and message transmission processing module corresponding to Gen6 are enabled, while at other link rates, the clocks of these modules are disabled. That is, when the current link rate is Gen6, the link rate control circuit outputs a clock-enabling control signal to the modules corresponding to Gen6, and a clock-disabling control signal to the modules corresponding to Gen1 or Gen2 and Gen3, Gen4, or Gen5, respectively.

[0064] In some optional implementations, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0065] See also Figure 4 As shown, exemplarily, currently in the link establishment (configuration) phase, the clocks of the training code stream (TS) sending module, the training code stream (TS) receiving module, the link peer detection module, the link polling module and the link equalization module can be turned on, while the clocks of other modules can be turned off.

[0066] Currently in the link recovery phase, the clocks of the training stream (TS) sending module, the training stream (TS) receiving module, the link rate switching and link width switching related modules can be turned on, while the clocks of other modules can be turned off.

[0067] When in a low power state, the clocks of the modules related to the corresponding low power sub-state can be turned on according to the current LTSSM state. For example, when in L1ss, the clocks of the L1-related modules are turned on, while the clocks of all other modules can be turned off. Exemplarily, the modules related to the low power sub-state include the L0s management module, the L0p management module, the L1ss management module, and the L2 management module.

[0068] The link establishment phase, link recovery phase and low power consumption state are all abnormal working states, and other states are normal working states. Under normal working state, the clocks of modules related to link training can be turned off, such as the training code stream (TS) sending module, the training code stream (TS) receiving module and the link training related modules. It should be noted that Figure 4 The clocks of the three modules described above can be disabled during normal operation. The shutdown of other modules is controlled by the link width control circuit and the link rate control circuit. In other words, the control signals output by the link width control circuit and the link rate control circuit are valid during normal operation and invalid during abnormal operation. During abnormal operation, the control signals output by the link state control circuit control the clocks of each module.

[0069] In some optional implementations, the PCIe clock gating circuit further includes: a logic OR gate;

[0070] The logic OR gate is used to perform a logic OR operation on the multiple control signals to be output to the same clock.

[0071] For example, under normal operating conditions, the link width control circuit, the link rate control circuit, and the link status control circuit output control signals to the clocks of each module according to their respective logics. There may be multiple control signals output to the clock of the same module. Therefore, a logic OR gate can be set before the clock of the same module so that multiple control signals are output to the clock after the logic OR operation of the logic OR gate. In this way, as long as there is a control signal to turn on the clock, the clock will be turned on. If all control signals output to the same clock are off signals, the clock will be turned off. It should also be noted that under normal operating conditions, the clocks of modules related to link training are all turned off.

[0072] In some optional implementations, the PCIe clock gating circuit further includes: a register enable signal output circuit;

[0073] The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

[0074] See also Figure 5 As shown, illustratively, the enable signal output by the register enable signal output circuit is also output to a logic OR gate to perform a logic OR operation with the control signals output by the link width control circuit, the link rate control circuit, and the link state control circuit. The enable signal output by the register enable signal output circuit depends on the configuration information of the register. If the configuration information enables the control signals output by the link width control circuit, the link rate control circuit, and the link state control circuit, the register enable signal output circuit outputs a low level, so that the control signal ultimately output to the clock is based on the control signals output by the link width control circuit, the link rate control circuit, and the link state control circuit. If the configuration information disables the control signals output by the link width control circuit, the link rate control circuit, and the link state control circuit, the register enable signal output circuit outputs a high level, so that the control signal ultimately output to the clock is always a high level and is not affected by the control signals output by the link width control circuit, the link rate control circuit, and the link state control circuit.

[0075] Refer to the following Figure 5The design of the PCIe clock gating circuit is described as follows, where control circuit A represents the circuit including the link width control circuit, link rate control circuit, and link status control circuit. CLK Gate represents the clock, and modules A and B represent the modules that need to be turned off or on.

[0076] ① Design clock enable control signals for different scenarios based on PCIe link width, link rate, and link working scenarios;

[0077] ② The configuration register generates an enable signal. When the enable signal is low, the hardware controls whether the clock gating turns off the clock; when the enable signal is high, the clock gating is always on.

[0078] ③ Generate dedicated clock gating circuits and encapsulate them into universal clock gating component modules (CLK Gate CBB). These circuits are specially optimized for clock gating and can provide better performance and lower leakage current.

[0079] ④ Use the control signal to connect the universal clock gating component module. When the control signal is valid, the clock is turned on. When the control signal is invalid, the clock is turned off and the controlled gated clock is output. Finally, the gated output clock is input to the controlled module.

[0080] The above is the PCIe clock gating circuit proposed in this application, which can effectively reduce the dynamic power consumption of the entire PCIe system. By distinguishing the active modules based on PCIe link width, link rate, and link operating scenario, and disabling the clocks of inactive modules, clock and logic flips can be significantly reduced. Compared to the clock gating that inserts registers in related technologies, module-level clock modules require fewer hardware resources and are simpler in design.

[0081] In addition, the module-level clock gating circuit controls the clock on and off without software intervention, and all control is automatically completed by hardware; at the same time, the software can control the opening and closing of the clock gating, which increases the flexibility of the entire solution.

[0082] This application supports different versions of the PCIe protocol and can reduce the dynamic power consumption of the PCIe controller in various business scenarios. Simulations have shown that in the PCIe controller's idle mode (L1ss), system power consumption can be reduced by 70%; in a single-channel (x1) normal business scenario (L0), system power consumption can be reduced by 30%; and in a full-channel (x16) normal business scenario (L0), system power consumption can be reduced by 10%.

[0083] Accordingly, see Figure 6 As shown, the present application exemplarily provides a PCIe clock control method, including:

[0084] In step S601, when the current link width is less than the maximum width, the link width control circuit outputs a control signal for shutting down the clocks of modules not related to the current width; the modules not related to the current width include modules related to channels other than the channel corresponding to the current link width, and modules related to link widths other than the current link width.

[0085] In step S602, the link rate control circuit outputs a control signal for shutting down clocks of modules not related to the current rate, wherein the modules not related to the current rate include modules corresponding to link rates other than the current link rate.

[0086] In step S603, when the current link state is an abnormal working state, the link state control circuit outputs a control signal to shut down the clocks of modules related to the abnormal working state, where the modules related to the abnormal working state include modules corresponding to link states other than the current link state.

[0087] In step S604, when the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

[0088] In some optional implementations, the non-current width-related module includes a channel-related module and a path-related module; the channel-related module includes at least one of a de-skew module, an scrambling module, and a message bus module corresponding to each other channel; the path-related module includes a rate conversion module, a message sending module, and a message receiving module corresponding to the other link widths.

[0089] In some optional implementations, when the current link rate is Gen1 or Gen2, the non-current rate-related modules include at least one of a 128b / 130b conversion module, a message receiving processing module, a message sending processing module, and a Gen5 precoding module corresponding to Gen3, Gen4, or Gen5, and at least one of a PAM4 encoding and decoding module, a message receiving processing module, and a message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4, or Gen5, the non-current rate-related modules include an 8b / 10b conversion module corresponding to Gen1 or Gen2. block, at least one of a message receiving and processing module and a message sending processing module, and at least one of a PAM4 encoding and decoding module, a message receiving and processing module and a message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate related modules include at least one of an 8b / 10b conversion module, a message receiving and processing module and a message sending processing module corresponding to Gen1 or Gen2, and at least one of a 128b / 130b conversion module, a message receiving and processing module, a message sending processing module and a Gen5 precoding module corresponding to Gen3, Gen4 or Gen5.

[0090] In some optional implementations, the abnormal working state includes: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

[0091] In some optional implementations, the method further includes:

[0092] The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0093] In some optional implementations, the multiple control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate, including:

[0094] The register enable signal output circuit outputs an enable signal to the logic OR gate;

[0095] The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

[0096] The above PCIe clock control method can be implemented by the PCIe clock gating circuit provided in the above embodiment. For specific implementation methods, please refer to the description of the PCIe clock gating circuit in the above embodiment, which will not be repeated here.

[0097] It is understood that the circuit structures, names, and parameters described in the above embodiments are merely examples. Those skilled in the art may also readily conceive of combinations and adjustments to the structural features of the above embodiments as needed, and should not limit the concept of this application to the specific details of the above examples.

[0098] Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A PCIe clock gating circuit, characterized in that: include: Link width control circuit, link rate control circuit and link status control circuit; wherein, The link width control circuit is configured to output a control signal to shut down clocks of modules not related to the current width when the current link width is less than the maximum width; the modules not related to the current width include modules related to channels other than the channel corresponding to the current link width, and modules related to link widths other than the current link width; The link rate control circuit is used to output a control signal for shutting down the clock of a module not related to the current rate, wherein the module not related to the current rate includes a module corresponding to a link rate other than the current link rate; The link state control circuit is used to output a control signal to shut down the clock of the abnormal working state related module when the current link state is an abnormal working state, and the abnormal working state related module includes the related modules corresponding to other link states other than the current link state; The link state control circuit is further configured to output a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules in a normal working state.

2. The PCIe clock gating circuit according to claim 1, wherein: The non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link width.

3. The PCIe clock gating circuit according to claim 1, wherein: When the current link rate is Gen1 or Gen2, the non-current rate related modules include at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5, and at least one of the PAM4 encoding and decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related modules include the 8b / 10b conversion module, message receiving processing module and Gen6 precoding module corresponding to Gen1 or Gen2. At least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding and decoding module, the message receiving processing module, and the message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate-related modules include at least one of the 8b / 10b conversion module, the message receiving processing module, and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module, and the Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

4. The PCIe clock gating circuit according to claim 1, wherein: Abnormal working states include: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

5. The PCIe clock gating circuit according to any one of claims 1 to 4, wherein: Also includes: logical OR gate; The logic OR gate is used to perform a logic OR operation on the multiple control signals to be output to the same clock.

6. The PCIe clock gating circuit according to claim 5, wherein: Also includes: Register enable signal output circuit; The register enable signal output circuit is used to output an enable signal to the logic OR gate according to the configuration information in the setting register, so as to enable the control signal output to the clock.

7. A PCIe clock control method, characterized in that: include: When the current link width is less than the maximum width, the link width control circuit outputs a control signal to shut down the clocks of modules not related to the current width; the modules not related to the current width include modules related to channels other than the channel corresponding to the current link width, and modules related to link widths other than the current link width; The link rate control circuit outputs a control signal for shutting down clocks of modules not related to the current rate, wherein the modules not related to the current rate include modules corresponding to link rates other than the current link rate; When the current link state is an abnormal working state, the link state control circuit outputs a control signal to shut down the clock of a module related to the abnormal working state, wherein the module related to the abnormal working state includes a module corresponding to a link state other than the current link state; When the current link state is a normal working state, the link state control circuit outputs a control signal for shutting down the clocks of the training code stream sending module, the training code stream receiving module and the link training related modules.

8. The PCIe clock control method according to claim 7, wherein: The non-current width related module includes a channel related module and a path related module; the channel related module includes at least one of a de-skew module, an scrambling module and a message bus module corresponding to each other channel; the path related module includes a rate conversion module, a message sending module and a message receiving module corresponding to the other link width.

9. The PCIe clock control method according to claim 7, wherein: When the current link rate is Gen1 or Gen2, the non-current rate related modules include at least one of the 128b / 130b conversion module, message receiving processing module, message sending processing module and Gen5 precoding module corresponding to Gen3, Gen4 or Gen5, and at least one of the PAM4 encoding and decoding module, message receiving processing module and message sending processing module corresponding to Gen6; when the current link rate is Gen3, Gen4 or Gen5, the non-current rate related modules include the 8b / 10b conversion module, message receiving processing module and Gen6 precoding module corresponding to Gen1 or Gen2. At least one of the processing module and the message sending processing module, and at least one of the PAM4 encoding and decoding module, the message receiving processing module, and the message sending processing module corresponding to Gen6; when the current link rate is Gen6, the non-current rate-related modules include at least one of the 8b / 10b conversion module, the message receiving processing module, and the message sending processing module corresponding to Gen1 or Gen2, and at least one of the 128b / 130b conversion module, the message receiving processing module, the message sending processing module, and the Gen5 precoding module corresponding to Gen3, Gen4, or Gen5.

10. The PCIe clock control method according to claim 7, wherein: Abnormal working states include: the state of the link establishment phase, the state of the link recovery phase and the low power consumption state; the abnormal working state-related modules corresponding to the state of the link establishment phase include the training code stream sending module, the training code stream receiving module, the link peer detection module, the link polling module and other modules other than the link balancing module; the abnormal working state-related modules corresponding to the state of the link recovery phase include the training code stream sending module, the training code stream receiving module, the link rate switching-related module and the link width switching-related module other than the modules; the abnormal working state-related modules corresponding to the low power consumption state include other modules other than the management module corresponding to the current low power consumption sub-state.

11. The PCIe clock control method according to any one of claims 7 to 10, wherein: Also includes: The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

12. The PCIe clock control method according to claim 11, wherein: The plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate, comprising: The register enable signal output circuit outputs an enable signal to the logic OR gate; The enable signal and the plurality of control signals to be output to the same clock pass through a logic OR gate and are then output to the clock by the logic OR gate.

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