Method and apparatus to facilitate immutable configuration of memory devices

Abstract

The invention relates to a method and apparatus for facilitating immutable configuration of a memory device. Methods, apparatus, systems, and articles of manufacture corresponding to an immutable configuration of a memory device are described. An example memory (102) includes: a memory bank (106) including a first portion (111) and a second portion (107), the second portion (107) configured to store configuration information specifying whether the first portion (111) is immutable; and a controller (104) coupled to the memory bank (106), the controller (104) configured to determine whether to block writing of data to the first portion (111) based on the configuration information.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 532,099, filed on August 11, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present description relates generally to circuits and, more particularly, to methods and apparatus that facilitate immutable configuration of memory devices. Background Art

[0004] Devices containing electronic components are produced by manufacturers and may be integrated into intermediate and / or final products by one or more suppliers. Such devices may include processing circuitry, memory, etc. Memory may include both volatile memory and non-volatile memory. Non-volatile memory, such as flash memory, is memory that retains stored values ​​even after power is removed from the device. Such non-volatile memory may store user-writable data and data that should not be written by the user, such as encryption key data or manufacturer / supplier / user proprietary code. Summary of the invention

[0005] An example of the present specification includes a method comprising a memory, the memory comprising: a memory group, which includes a first part and a second part, the second part is configured to store configuration information that identifies the first part as immutable; and a controller, which is coupled to the memory group, and the controller prevents data from being written to the first part based on the configuration information after initialization.

[0006] An example device includes: a memory circuit system comprising a first portion of memory and a second portion, the second portion being configured to store configuration information identifying the first portion as immutable; a processing circuit system that is used to: obtain the configuration information from the memory circuit; store the configuration information in a register; and after obtaining an identification of an operation on the first portion of memory, send a message that prevents the operation on the first portion of memory.

[0007] An example device includes: a memory circuit system comprising a first portion and a second portion of a memory, the second portion being configured to store configuration information identifying the first portion as immutable; a memory controller for instantiating and / or executing computer-readable instructions to: after obtaining an instruction corresponding to a write operation to write data to a location of the memory circuit, output a warning including the location of the memory circuit; and after obtaining a response to the warning, prevent the write operation to the location of the memory circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1is a block diagram of an example of a device that includes flash memory.

[0009] Figure 2 Draw Figure 1 An instance structure of an immutable section of flash memory that defines an instance of the flash memory.

[0010] Figure 3 The illustrated representations may be performed, instantiated, or performed by an example programmable circuit system to implement Figure 1 A flow chart of example machine-readable instructions or example operations for a memory controller to facilitate manufacturer / vendor / user-defined immutable configuration of a non-volatile rewritable memory device.

[0011] Figure 4 The illustrated representations may be performed, instantiated, or performed by an example programmable circuit system to implement Figure 1 A flowchart of example machine-readable instructions or example operations for a processing circuit system to facilitate manufacturer / supplier / user-defined immutable configuration of a non-volatile rewritable memory device.

[0012] Figure 5 A method comprising machine-readable instructions configured to execute, instantiate and / or perform an example or to perform Figures 3 to 4 Example operation to implement Figure 1 A block diagram of an example processing platform of a processing circuit system or programmable circuit system of a memory controller.

[0013] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar (either functionally or structurally) features. DETAILED DESCRIPTION

[0014] The drawings are not necessarily drawn to scale. In general, the same reference numerals in one or more of the drawings and the specification refer to the same or similar parts. Although the drawings show areas with clear lines and boundaries, some or all of these lines or boundaries may be idealized. In practice, boundaries or lines may be unobservable, mixed or irregular.

[0015] A computing device is any device that includes a processing circuit system to perform one or more operations. Most computing devices include non-volatile memory. Non-volatile memory is a memory that retains stored values ​​even after power is removed from the device. Non-volatile memory includes flash memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase change memory (PCM), resistive random access memory (RRAM), etc. During the boot process of the computing device, the computing device may execute code stored on the BootROM, which may include copying the code from the BootRom to a non-volatile rewritable memory (e.g., flash memory). However, by default, the code in the non-volatile rewritable memory may be overwritten or changed.

[0016] Some manufacturers, suppliers, or users may want to define areas (e.g., sectors, portions, etc.) of non-volatile rewritable memory as immutable (e.g., areas of memory that cannot be changed, erased, updated, or written to after initialization). For example, immutable code (e.g., code stored in an immutable area of ​​memory) may be used to recover from a firmware upgrade failure. A failure during a firmware upgrade may cause the device to enter an unrecoverable stage. However, the immutable code in the non-volatile memory may be used to recover by instantiating the computing device to perform a complete erase of the non-immutable sectors of the memory. Additionally, or alternatively, portions of the non-volatile rewritable memory reserved for immutable code may be used for key (e.g., encryption key) storage.

[0017] The examples described herein allow manufacturers / suppliers / users to define a segment of a non-volatile rewritable memory as immutable, and facilitate the operation of the memory to preserve the immutable segment of the memory. The non-volatile rewritable memory may include various areas, such as a key area and a data area. Its key area may be designed to be written once (e.g., it may include a support circuit system to write data by changing 1 to 0, without having a circuit system to erase data by changing 0 to 1), and the data area may be rewritable (e.g., it may include a support circuit system to write data and erase data). In some examples, the key area may be used to store key data (e.g., encryption keys, manufacturer / supplier / user-specific keys, etc.), and the data area may be used to store manufacturer / supplier / user codes. The examples described herein utilize a manufacturer, supplier, or user that can control to define a segment of a data area as a segment of a key area (e.g., an immutable configuration area) that is immutable (e.g., neither writable nor erasable). For example, if the data area is a 64 kilobyte (Kb) memory, the immutable configuration area may include 32 bit cells, where each bit cell of the immutable configuration area corresponds to a unique 2Kb area of ​​the 64Kb data area of ​​the memory. In this example, a bit cell storing a first value (e.g., '0') configures the corresponding 2Kb area as immutable, while a bit cell storing a second value (e.g., '1') configures the corresponding 2Kb area as non-immutable. Therefore, the memory location of any write, erase, or change operation to the data area of ​​the nonvolatile memory is first checked relative to the bit cell value corresponding to the immutable area of ​​the nonvolatile memory. In this way, writing, erasing, or changing an area marked as immutable based on the value stored in the bit cell is not permitted.

[0018] Thus, a manufacturer, supplier, or user may store code to a portion of the data area, and then store a value in the key area, which makes the portion of the data area immutable. After defining the immutable area of ​​the non-volatile memory, the examples disclosed herein enable or allow read operations to the immutable area, but disable or prevent write operations and erase operations to the immutable area. For example, after the manufacturer / supplier / user defines a segment of the non-volatile rewritable memory as immutable by setting a bit of the immutable configuration area, a direct memory access (DMA) controller of the computing device may perform direct memory access to access a value of the immutable configuration area from the key area of ​​the non-volatile rewritable memory.

[0019] The DMA controller stores the accessed value in a set of triggers, registers, or any other storage devices. The set of triggers, registers, or any other devices stores the accessed value, thereby allowing the processing circuit system of the computing device to identify the immutable section of the non-volatile rewritable memory. In this way, after the memory controller of the non-volatile rewritable memory obtains an instruction to write or erase to a portion of the data area, the memory controller outputs a warning to the processing circuit system. The warning identifies the write or erase operation of the corresponding location.

[0020] In response to the processing circuit system obtaining the warning, the processing circuit system compares the location of the operation identified in the warning with the value stored in the register, flip-flop, etc. that identifies the immutable area of ​​the non-volatile rewritable memory. If the processing circuit system determines that the write or erase operation corresponds to the immutable section, the processing circuit system outputs a signal to the memory controller to prevent the operation. Therefore, the examples described herein provide a structure and operation for facilitating manufacturer / supplier / user-defined invariance of non-volatile rewritable memory.

[0021] Figure 1 A block diagram of an example device 100 that facilitates immutable configuration of a memory device. Figure 1 The example described in the embodiment includes flash memory 102, memory controller 104, memory bank 106, direct memory access (DMA) controller 108, register / flip-flop 110, processing circuitry 112, comparator 114, and interface 116. Device 100 may include Figure 1 Additional components not shown.

[0022] Figure 1 The device 100 may be any device that includes a non-volatile memory and a processing circuit system. For example, the device 100 may be one or more of the following: a computer, a mobile phone, a tablet computer, a server, a cloud-based or edge-based device, a television, a video game device, an automotive computing device, or any other device that includes or is otherwise connected to a non-volatile memory and a processing circuit system.

[0023] Figure 1The flash memory 102 is a memory that can store data and maintain the stored data even after power is removed. Although the device 100 includes the flash memory 102, the examples described herein may be implemented in conjunction with any type of non-volatile rewritable memory. The flash memory 102 includes a memory controller 104 and an example memory group 106, which includes memory cells for storing data. The memory group 106 includes a key area 105 that can be used to store keys and a data area 109 that can be used to store code. During boot or initialization, a manufacturer, supplier, or user may store key information, code, etc. in the memory group 106 of the flash memory 102, and define one or more sub-areas 111 in the data area 109 of the memory group 106 that are immutable. For example, the manufacturer / supplier / user may instruct the memory controller 104 to write a value to the immutable configuration area 107 of the key area 105 of the memory group 106, and the immutable configuration area 107 defines which parts of the data area are immutable. The following description is combined with Figure 2 An example of memory bank 106 is further described.

[0024] Figure 1The memory controller 104 reads (e.g., obtains, accesses, etc.) data, writes (e.g., stores, programs, etc.) data to the memory group 106, or erases data based on instructions from the DMA controller 108, the processing circuit system 112, or any other device. For example, a bit cell of the memory group 106 may be initialized to a first value (e.g., '1'), and the memory controller 104 may program a specific bit (e.g., change the bit cell from '1' to '0'), erase the bit cell (e.g., change from '0' to '1'), or read the content stored in the bit cell. The memory controller 104 may store or write values ​​to the immutable configuration area of ​​the memory group 106 based on manufacturer / vendor / user instructions. After defining the immutable area, the memory controller 104 cannot reverse the instructions (e.g., change the immutable area to a non-immutable area). However, the memory controller 104 may extend the immutable area after booting or initialization so that the non-immutable area becomes the immutable area. In addition, after booting or initialization, the memory controller 104 may obtain instructions to write or erase to a segment of the memory bank 106. These instructions may be received from the processing circuit system 112, the DMA controller 108, or other suitable elements of the device 100. In response to these instructions, the memory controller 104 outputs a warning or indication of the operation and the corresponding location to the processing circuit system 112. If the memory controller 104 obtains an indication from the processing circuit system 112 to prohibit the operation of the location, the memory controller 104 ignores the operation. If the memory controller 104 does not obtain an indication to prohibit the operation of the location, the memory controller 104 continues the operation. In some examples, the processing circuit system 112 or the memory controller 104 may output an indication of the prohibited operation to the device that sent the instruction or to the user.

[0025] Figure 1 The DMA controller 108 of the flash memory 102 can buffer the values ​​in the configuration area 107 in the set of registers / flip-flops 110 by performing direct memory access to access the values ​​stored in the configuration area of ​​the memory bank 106 and storing the accessed values ​​in the registers / flip-flops 110. As described above, the values ​​stored in the immutable configuration area correspond to one or more manufacturer / vendor / user defined immutable areas of the memory bank 106. In some examples, the DMA controller 108 functions together with the memory controller 104 of the flash memory 102 to access data from the memory bank 106. For example, in response to a direct memory access instruction from the DMA controller 108, the memory controller 104 can output data corresponding to the direct memory access instruction.

[0026] Figure 1The register / flip-flop 110 stores the accessed information from the DMA operation. As described above, the DMA operation accesses data related to the segment of the memory group 106 defined by the manufacturer / supplier / user as immutable. Although the register / flip-flop 110 is included in the device 100, the register / flip-flop can be replaced by other storage devices.

[0027] Figure 1 Processing circuit system 112 of the memory controller 104 monitors the warning from the memory controller 104 to determine whether the memory controller 104 has output a warning that the memory controller 104 is to write to or erase to a location in the memory bank 106. Processing circuit system 112 includes a comparator 114 and an interface 116. Processing circuit system 112 uses comparator 114 to compare a location corresponding to an operation included in the warning from the memory controller 104 with a buffered copy of a value stored in register / flip-flop 110 and / or a copy of a value stored in configuration area 107. If comparator 114 determines that the location corresponding to the operation corresponds to an immutable area based on the value of register / flip-flop 110 and / or configuration area 107, then processing circuit system 112 determines that the operation should be prohibited. For example, if the first value stored in the register / flip-flop 110 and / or the configuration area 107 corresponds to the first 2Kb area of ​​the memory bank 106 and the warning corresponds to the first 2KB area, the comparator 114 determines whether the first value stored in the register / flip-flop 110 and / or the configuration area 107 corresponds to the first value indicating an immutable area or the second value indicating a non-immutable area. If the comparator 114 determines that the location corresponding to the operation is an immutable location, the processing circuit system 112 outputs an indication (e.g., via the interface 116) to the memory controller 104 to prevent the operation from proceeding. If the comparator 114 determines that the location corresponding to the operation is not an immutable location, the processing circuit system 112 outputs an indication to the memory controller 104 to allow the operation, or does not output any indication.

[0028] Figure 1 The interface 116 of the memory controller 104 accesses the values ​​stored in the register / flip-flop 110 and / or the configuration area 107. As described above, because the value identifies the immutable area of ​​the memory bank 106, the comparator 114 can use the value to determine whether the operation corresponds to the immutable location. In addition, if the operation corresponds to the immutable location of the memory bank 106, the interface 116 outputs an indication that the operation should be prohibited to the memory controller 104. In some examples, if the operation corresponds to a non-immutable location of the memory bank 106, the interface 116 outputs an indication that the operation should be permitted to the memory controller 104.

[0029] Figure 2 for Figure 11. Memory group 106 of flash memory 102 of FIG. 106 includes keystore region 200 and data region 202. Keystore region 200 includes immutable configuration region 204. Data region 202 (also referred to as code region or code / data region) includes immutable code region 206 and non-immutable code region. In some examples, keystore region 200 and data region 202 are connected to each other. Figure 1 The key area 105 corresponds to the immutable configuration area 204 and Figure 1 The immutable configuration area 107 corresponds to the data area 202. Figure 1 The data area 109 corresponds to the immutable code area 206. Figure 1 One or more of the sub-regions 111 designated as immutable correspond.

[0030] Figure 2 The keystore area 200 of the device 100 stores key information (e.g., a manufacturer / vendor / user-specific encryption key). During startup or initialization of the device 100 or the flash memory 102, the manufacturer, vendor, or user may store the key information in the keystore area 200. The keystore area 200 includes an immutable configuration area 204. As described above, the immutable configuration area 204 stores information that defines one or more portions of the immutable segment of the data area 202 that the manufacturer / vendor / user of the data area 202 wants to retain for the data area 202. In some instances, the memory controller 104 may only change the bit value of the immutable configuration area 204 from '1' to '0', but not from '0' to '1'. In these instances, after the manufacturer / vendor / user defines the immutable segment in the code by programming the value into the immutable configuration area 204, the user cannot unmark the immutable segment to return to the non-immutable segment. In these instances, the user may only expand (e.g., increase) the number of immutable areas of the memory group 106 (e.g., not reduce the immutable area). In the example, each bit cell of the immutable configuration region corresponds to a sub-region of the data region 202. Thus, the value of the bit cell defines whether the corresponding sub-region is immutable or non-immutable.

[0031] exist Figure 2 In the example of , the first portion of the data area 202 (eg, the immutable area 206) has been selected by the manufacturer, supplier, or user to be immutable. For example, the first bit cell corresponding to the immutable area 206 stores a first value corresponding to immutable (eg, '0'). Figure 2 In the example of , the rest of the data area 202 is non-immutable, so the value in the immutable configuration area 204 stores a second value (eg, '1') corresponding to non-immutable.

[0032] Figure 3 The drawing indicates that Figure 1 Flowchart of a method or example operations 300 performed or instantiated by the memory controller 104 to facilitate manufacturer / vendor / user defined immutable configuration of the flash memory 102 . Figure 3 The machine readable instructions or operations 300 of begin at block 301 where the memory controller 104 writes data to a portion of the memory. For example, the memory controller 104 may write data to a portion of the code area 202 of the memory 106.

[0033] At block 302, the memory controller 104 determines whether an immutable section directive has been obtained to make portions of the memory immutable. For example, during boot, start, or initialization, a manufacturer, supplier, and / or user may provide an immutable section directive that defines which areas of the data region 202 in the memory bank 106 of the flash memory 102 should be immutable.

[0034] If the memory controller 104 determines that the immutable section instruction has not been obtained (block 302: No), control returns to block 302 until the instruction has been obtained. If the memory controller 104 determines that the immutable section instruction has been obtained (block 302: Yes), the memory controller 104 writes or programs the immutable configuration into the immutable configuration portion 204 of the key store area 200 of the memory bank 106 of the flash memory 102 based on the instruction (block 304). At block 306, the memory controller 104 determines whether an instruction to write or erase data at a location in the data area 202 of the memory bank 106 in the flash memory 102 has been obtained. If the memory controller 104 determines that the instruction to write or erase data at a location in the memory bank 106 in the flash memory 102 has not been obtained (block 306: No), control continues to block 316, as further described below.

[0035] If the memory controller 104 determines that an instruction to write or erase data at a location of the memory bank 106 in the flash memory 102 has been obtained (block 306: yes), the memory controller 104 outputs a warning corresponding to the write / erase operation at the location in the flash memory 102 to the processing circuit system 112 (block 308). As described above, the processing circuit system 112 receives the warning and determines whether the location is immutable. Therefore, if the location of the write / erase operation is immutable, the processing circuit system 112 will output an indication to prevent the operation. Therefore, at block 310, the memory controller 104 determines whether a response to prevent writing or erasing at the location has been obtained. If the memory controller 104 determines that a response to prevent writing / erase operations at the location has been obtained (block 310: yes), the memory controller 104 prevents the write / erase operation at the location of the flash memory 102 (block 312). If the memory controller 104 determines that a response has not been obtained that prevents the write / erase operation at the location (block 310: NO), the memory controller 104 performs the write or erase operation at the location of the flash memory 102 (block 314).

[0036] At block 316, the memory controller 104 determines whether an instruction to expand the immutable section of the data area 202 in the memory bank 106 of the flash memory 102 has been obtained (e.g., from a user). If the memory controller 104 determines that an instruction to expand the immutable section has not been obtained (block 316: No), control returns to block 306. If the memory controller 104 determines that an instruction to expand the immutable section has been obtained (block 316: Yes), the memory controller 104 writes the expansion configuration information in the immutable configuration area 204 of the keystore area 200 of the memory bank 106 based on the expansion instruction (block 318) and control returns to block 306.

[0037] Figure 4 The drawing indicates that Figure 1 Flowchart of a method or example operations 300 performed or instantiated by the processing circuitry 112 to facilitate manufacturer / vendor / user defined immutable configuration of the flash memory 102 . Figure 4 The machine readable instructions or operations 400 of the embodiment begin at block 402 where the DMA controller 108 accesses immutable configuration information from the immutable configuration area 204 of the key store 200 in the flash memory 102. As described above, the immutable configuration information is a value in a bit cell of the immutable configuration area 204 that identifies a sub-area of ​​the data area 202 of the memory bank 106 that is immutable.

[0038] At block 404, the DMA controller 108 stores the immutable configuration information in Figure 110. At block 406, processing circuitry 112 determines whether a warning has been obtained from memory controller 104 (via interface 116) regarding a write or erase operation at a location of memory bank 106 of flash memory 102. If processing circuitry 112 determines that a warning has not been obtained (block 406: No), control continues to block 416. If processing circuitry 112 determines that a warning has been obtained (block 406: Yes), comparator 114 compares the location of the write / erase operation from the warning with the immutable configuration information stored in one or more registers / one or more flip-flops 110 (block 408). Additionally or alternatively, comparator 114 may compare the location of the write / erase operation from the warning with the immutable configuration information stored in the immutable configuration area 204 of key store 200 in flash memory 102.

[0039] At block 410, the example comparator 114 determines whether the location from the warning corresponds to one of the immutable locations defined by the one or more registers / one or more flip-flops 110 and / or the values ​​in the immutable configuration region 204. If the comparator 114 determines that the location from the warning corresponds to one of the immutable locations (block 410: yes), then the processing circuitry 112 transmits a response to the memory controller 104 that prevents a write or erase operation at the location identified in the warning (block 412). If the comparator 114 determines that the location from the warning does not correspond to one of the immutable locations (block 410: no), then the processing circuitry 112 transmits a response to the memory controller 104 that allows a write or erase operation at the location identified in the warning (block 414). In some examples, in response to the location from the warning not corresponding to one of the immutable locations, the processing circuitry 112 may not perform any operation.

[0040] At block 416, processing circuitry 112 determines whether the immutable section has been extended. For example, memory controller 104 may output a warning that the immutable portion of memory bank 106 has been extended. If processing circuitry 112 determines that the immutable section has not been extended (block 416: No), control returns to block 406. If processing circuitry 112 determines that the immutable section has been extended (block 416: Yes), processing circuitry 112 causes DMA controller 108 to access the extended immutable configuration information from immutable configuration area 204 of key store 200 and store the extended immutable configuration information in one or more registers / one or more flip-flops 110, and control returns to block 406.

[0041] Figure 5 To be constructed to execute and / or instantiate Figure 3 and / or 4 example machine readable instructions and / or example operations to implement Figure 1The programmable circuit system platform 500 is a block diagram of an example of a device 100. The programmable circuit system platform 500 can be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, such as an iPad TM tablet computer), Internet appliance, DVD player, CD player, digital video recorder, game console, personal video recorder, set-top box, head-mounted device (e.g., augmented reality (AR) headset, virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing and / or electronic device.

[0042] The programmable circuit system platform 500 of the illustrated example includes a programmable circuit system 512. The programmable circuit system 512 of the illustrated example is hardware. For example, the programmable circuit system 512 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, and / or microcontrollers from any desired family or manufacturer. The programmable circuit system 512 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 512 implements Figure 1 The memory controller 104, DMA controller 108 and processing circuit system 112 are provided.

[0043] The programmable circuit system 512 of the illustrated example includes a local memory 513 (e.g., cache, registers, etc.). The programmable circuit system 512 of the illustrated example communicates with main memory 514, 516 (including volatile memory 514 and non-volatile memory 516) via a bus 518. The volatile memory 514 may be composed of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory and / or any other type of RAM device. The non-volatile memory 516 may be implemented by flash memory and / or any other desired type of memory device. In some examples, the non-volatile memory 516 may be implemented by Figure 1 102 of the flash memory 102. Access to the main memory 514, 516 of the illustrated example is controlled by a memory controller 517. In some examples, the memory controller 517 may be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data to and from the main memory 514, 516.

[0044] The programmable circuit system platform 500 of the illustrated example also includes an interface circuit system 520. The interface circuit system 520 can be implemented by hardware replacing any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface.

[0045] In the example shown, one or more input devices 522 are connected to the interface circuitry 520. The one or more input devices 522 permit a user (e.g., a human user, a machine user, etc.) to enter data and / or commands into the programmable circuitry 512. The one or more input devices 522 may be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, buttons, a mouse, a touch screen, and / or a voice recognition system.

[0046] One or more output devices 524 are also connected to the interface circuit system 520 of the illustrated example. One or more output devices 524 may be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switch (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit system 520 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics processor circuit system such as a GPU.

[0047] The interface circuitry 520 of the illustrated example also includes communication devices, such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces, to facilitate the exchange of data with external machines (e.g., any type of computing device) via the network 526. Communications may occur via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

[0048] The programmable circuit system platform 500 of the illustrated example also includes one or more mass storage disks or devices 528 to store firmware, software and / or data. Examples of such mass storage disks or devices 528 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, and / or solid-state storage disks or devices, such as flash memory devices and / or SSDs.

[0049] can be Figure 3The machine-readable instructions 532 implemented by the machine-readable instructions of and / or 4 may be stored in the mass storage device 528, in the volatile memory 514, in the non-volatile memory 516, and / or on at least one removable non-transitory computer-readable storage medium such as a CD or DVD.

[0050] exist Figure 1 An example method of implementing the device 100 is shown in FIG. Figure 1 One or more of the elements, processes, and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0051] In addition, the memory controller 104, the DMA controller 108, the processing circuit system 112 and / or the comparator 114 may be implemented by hardware, software, firmware and / or any combination of hardware, software and / or firmware. Thus, for example, any of the memory controller 104, the DMA controller 108, the processing circuit system 112 and / or the comparator 114 may be implemented by one or more of the following: one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application specific integrated circuits (ASICs), one or more programmable logic devices (PLDs) and / or one or more field programmable logic devices (FPLDs).

[0052] When any of the apparatus or system claims of this patent are read to cover only software and / or firmware implementations, at least one of the memory controller 104, DMA controller 108, processing circuit system 112, and / or comparator 114 is expressly defined herein as comprising a non-transitory computer-readable storage device or storage disk, such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc., comprising the software and / or firmware. In addition, the memory controller 104, the DMA controller 108, the processing circuit system 112, and / or the comparator 114 may include other than Figure 2 In addition to or in place of the components, processes and / or devices shown in Figure 2 The present invention may include one or more of the elements, processes and / or devices shown in the embodiment of the present invention, and / or may include more than one of any or all of the elements, processes and devices shown. As used herein, the phrase "communication" includes variations thereof covering direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but also includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals and / or one-time events.

[0053] Figure 3 and 4 The diagram shows a method for implementing Figure 1 The present invention provides a flowchart of an example hardware logic, machine readable instructions, hardware implemented state machine, and / or any combination thereof of the device 100. The machine readable instructions may be one or more executable programs or one or more portions of an executable program for execution by a computer processor. The program may be implemented in software stored on a non-transitory computer readable storage medium such as a CD-ROM, floppy disk, hard drive, DVD, Blu-ray disk, or memory associated with a processor, but the entire program and / or portions thereof may alternatively be executed by a device other than a processor and / or implemented in firmware or dedicated hardware.

[0054] In addition, although the reference Figure 3 and 4 The flowchart shown in describes an example procedure, but many other methods of implementing the device 100 may be used alternatively. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform corresponding operations without executing software or firmware.

[0055] The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, and the like. The machine-readable instructions described herein may be stored as data (e.g., a portion of an instruction, code, a code representation, and the like) that may be used to create, manufacture, and / or generate machine-executable instructions. For example, the machine-readable instructions may be segmented and stored on one or more storage devices and / or computing devices (e.g., a server). The machine-readable instructions may require one or more of installation, modification, adaptation, update, combination, supplementation, configuration, decryption, decompression, decapsulation, allocation, reassignment, compilation, and the like to make them directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions may be stored in multiple portions that are individually compressed, encrypted, and stored on separate computing devices, where the portions, when decrypted, decompressed, and combined, form a set of executable instructions that implement a program such as the program described herein.

[0056] In another example, the machine-readable instructions may be stored in a state in which they can be read by a computer, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the instructions on a particular computing device or other device. In another example, the machine-readable instructions and / or one or more corresponding programs may be configured (e.g., stored settings, data inputs, recorded network addresses, etc.) before the machine-readable instructions and / or one or more corresponding programs can be executed in whole or in part. Thus, the machine-readable instructions and / or one or more corresponding programs described encompass such machine-readable instructions and / or one or more programs regardless of the particular format or state of the machine-readable instructions and / or one or more programs while stored or otherwise at rest or in transit.

[0057] The machine-readable instructions described herein may be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0058] As mentioned above, Figure 3 The example processes of may be implemented using executable instructions (e.g., computer and / or machine readable instructions) stored on a non-transitory computer and / or machine readable medium, such as a hard drive, flash memory, read-only memory, compact disk, digital versatile disk, cache, random access memory, and / or any other storage device or storage disk in which information is stored for any duration (e.g., for an extended period of time, permanently, for a short period of time, temporary buffering and / or caching of information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and / or storage disk, and to exclude propagating signals and to exclude transmission media.

[0059] Although certain example methods, apparatus, and articles of manufacture have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus, and articles of manufacture falling within the scope of the claims of this patent.

[0060] When identifying multiple elements or components that can be mentioned separately, the descriptors "first", "second", "third", etc. are used in this article. Unless otherwise specified or based on the context of the use of the descriptors, these descriptors do not imply any meaning of priority, physical order, or arrangement or chronological order in a list for ease of understanding the described examples, but are only used as labels to refer to multiple elements or components respectively. In some instances, the descriptor "first" can be used to refer to an element in a specific embodiment, while the same element can be referred to in the claims by different descriptors such as "second" or "third". In these cases, these descriptors are used only for the convenience of referring to multiple elements or components.

[0061] In this specification and claims, unless otherwise stated, the terms "including" and "having" and variations thereof are included in a manner similar to the term "comprising". Unless otherwise stated, "about", "roughly" or "substantially" in front of a value means + / -10% of the stated value. In another example, "about", "roughly" or "substantially" in front of a value means + / -5% of the stated value. In another example, "about", "roughly" or "substantially" in front of a value means + / -1% of the stated value.

[0062] As used herein, the terms "couple", "coupled", "couples" and variations thereof may cover connections, communications or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal for controlling device B to perform an action, then: in a first instance, device A is coupled to device B; or in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A. In addition, the terms "couple", "coupled", "couples" or variations thereof include indirect or direct electrical or mechanical connections.

[0063] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be by firmware and / or software programming of the device, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0064] Although not in Figure 2Although all are individually labeled in the , the components or elements of the systems and circuits shown therein have one or more conductors or terminals that allow signals to enter and exit the components or elements. The conductors or terminals (or portions thereof) may be referred to herein as pins, pads, terminals (e.g., including input terminals, output terminals, reference terminals, and ground terminals), input terminals, output terminals, nodes, and interconnects.

[0065] As used herein, a "terminal" of a component, device, system, circuit, integrated circuit, or other electronic or semiconductor component generally refers to a conductor, such as a wire, trace, pin, pad, or other connector or interconnect, which enables a component, device, system, etc. to be electrically and / or mechanically connected to another component, device, system, etc. For example, a terminal can be used to receive or provide an analog or digital electrical signal (or only a signal), or electrically connected to a common or ground reference. Therefore, an input terminal or input end is used to receive a signal from another component, device, system, etc. An output terminal or output end is used to provide a signal to another component, device, system, etc. Other terminals can be used to connect to a common, ground, or voltage reference, such as a reference terminal or a ground terminal. The terminal of an IC or PCB may also be referred to as a pin (vertical conductor) or a pad (planar conductor). A node refers to a connection point or interconnection point of two or more terminals. An example number of terminals and nodes may be shown. However, depending on a specific circuit or system topology, there may be more or fewer terminals and nodes. However, in some cases, "terminals," "nodes," "interconnects," "pads," and "pins" may be used interchangeably.

[0066] The term "or" or "and / or" when used in the form of, for example, A, B and / or C, refers to any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A and B, (5) A and C, (6) B and C, or (7) A, B and C.

[0067] Example methods, apparatus, systems, and articles of manufacture that facilitate user-defined immutable configuration of a nonvolatile rewritable memory device are described herein. Other examples and combinations thereof include the following: Example 1 includes a memory, the memory comprising: a memory bank, which includes a first portion and a second portion, the second portion configured to store configuration information specifying whether the first portion is immutable; and a controller, which is coupled to the memory bank, the controller configured to determine whether to prevent data from being written to the first portion based on the configuration information.

[0068] Example 2 includes the memory of Example 1, wherein the memory bank is a flash memory.

[0069] Example 3 includes the memory of Example 1, wherein the second portion is within a keystore area of ​​the memory group.

[0070] Example 4 includes the memory of Example 1, wherein the first portion is within a data area of ​​the memory bank.

[0071] Example 5 includes the memory of Example 1, wherein the controller is configured to prevent data from being written to the first portion by: outputting configuration information to a processor; based on receiving a write operation to a location of a memory group, outputting a warning including the location to the processor; and based on receiving an indication that the location is immutable, preventing write operations to the location of the memory group.

[0072] Example 6 includes the memory of Example 1, wherein the second portion includes a plurality of memory cells, wherein each of the memory cells corresponds to a respective position of the memory bank.

[0073] Example 7 includes the memory of Example 6, wherein each of the memory cells is configured to store a respective value indicating whether a respective position of the memory group is immutable.

[0074] Example 8 includes a device comprising: a memory comprising a first portion and a second portion of the memory, the second portion being configured to store configuration information specifying whether the first portion is immutable; and a processing circuit system configured to: obtain the configuration information from the memory; store the configuration information in a register; and based on an operation directed to the first portion of the memory, send a response specifying whether to prevent an operation on the first portion of the memory based on the configuration information.

[0075] Example 9 includes the apparatus of example 8, wherein the memory is a non-volatile rewritable memory.

[0076] Example 10 includes the device of example 8, wherein the second portion is in a keystore area of ​​the memory.

[0077] Example 11 includes the apparatus of Example 8, wherein the first portion is within a data area of ​​the memory.

[0078] Example 12 includes the apparatus of Example 8, wherein an identification of an operation on a first portion of a memory is included in a warning from the memory, and the processing circuit system is configured to perform the following operations based on the warning: compare location information included in the warning with configuration information in a register; and send a response specifying whether the operation is to be prevented based on the comparison.

[0079] Example 13 includes the apparatus of Example 8, wherein the identifier is a first identifier, the response is a first response, and the operation is a first operation, and the processing circuit system is configured to send a second response allowing operation on a third portion of the memory based on a second identifier of a second operation on a third portion of the memory different from the first portion.

[0080] Example 14 includes the apparatus of Example 8, wherein the processing circuitry is to update the configuration information in the register based on the alert that the first portion of the memory has been expanded.

[0081] Example 15 includes a device comprising: a memory comprising a first portion and a second portion of the memory, the second portion being configured to store configuration information specifying whether the first portion is immutable; and a memory controller for instantiating and / or executing computer-readable instructions to perform the following operations: based on an instruction corresponding to a write operation to write data to a location in the memory, outputting a warning containing a location in the memory; and based on a response to the warning, determining whether to block the write operation to the location in the memory.

[0082] Example 16 includes the device of example 15, wherein the response to the alert specifies blocking write operations.

[0083] Example 17 includes the apparatus of Example 15, wherein the memory controller is configured to write the extended configuration information into the second portion of the memory based on the indication of the extended first portion of the memory.

[0084] Example 18 includes the apparatus of example 15, wherein the memory is a non-volatile rewritable memory.

[0085] Example 19 includes the apparatus of example 15, wherein the second portion is in a keystore area of ​​the memory.

[0086] Example 20 includes the apparatus of example 15, wherein the first portion is within a data area of ​​the memory.

[0087] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A memory comprising: a memory group comprising a first portion and a second portion, the second portion configured to store configuration information specifying whether the first portion is immutable; and A controller is coupled to the memory bank, the controller being configured to determine whether to prevent data from being written to the first portion based on the configuration information.

2. The memory according to claim 1, wherein the memory bank is a flash memory.

3. The memory of claim 1, wherein the second portion is within a keystore area of ​​the memory bank.

4. The memory of claim 1, wherein the first portion is within a data area of ​​the memory bank.

5. The memory of claim 1 , wherein the controller is configured to prevent the data from being written to the first portion by: Outputting the configuration information to a processor; outputting a warning including the location to the processor based on receiving a write operation to the location of the memory bank; as well as Based on receiving an indication that the location is immutable, the write operation to the location of the memory bank is prevented.

6. The memory of claim 1, wherein the second portion comprises a plurality of memory cells, wherein each of the memory cells corresponds to a respective position of the memory bank.

7. The memory of claim 6, wherein each of the memory cells is configured to store a respective value indicating whether the respective position of the memory group is immutable.

8. A device comprising: a memory comprising a first portion of memory and a second portion, the second portion configured to store configuration information specifying whether the first portion is immutable; and A processing circuit system configured to: Obtaining the configuration information from the memory; Storing the configuration information in a register; as well as Based on the operation directed to the first portion of the memory, a response is sent specifying whether the operation on the first portion of the memory is to be prevented based on the configuration information.

9. The apparatus according to claim 8, wherein the memory is a non-volatile rewritable memory.

10. The apparatus of claim 8, wherein the second portion is within a keystore area of ​​the memory.

11. The apparatus of claim 8, wherein the first portion is within a data area of ​​the memory.

12. The apparatus of claim 8, wherein the identification of the operation on the first portion of the memory is included in an alert from the memory, the processing circuitry being configured to, based on the alert: comparing the location information contained in the warning with the configuration information in the register; and The response is sent specifying whether the operation is to be prevented based on the comparison.

13. The apparatus of claim 8, wherein the identifier is a first identifier, the response is a first response, and the operation is a first operation, and the processing circuit system is configured to send a second response allowing the operation on the third portion of the memory based on a second identifier of a second operation on the third portion of the memory that is different from the first portion.

14. The apparatus of claim 8, wherein the processing circuitry is to update the configuration information in the register based on a warning that the first portion of the memory has been expanded.

15. An apparatus comprising: a memory comprising a first portion of memory and a second portion, the second portion configured to store configuration information specifying whether the first portion is immutable; and A memory controller configured to instantiate and / or execute computer readable instructions to: outputting a warning including the location of the memory based on an instruction corresponding to a write operation to write data to the location of the memory; as well as Based on a response to the alert, a determination is made whether to block the write operation to the location in the memory.

16. The apparatus of claim 15, wherein the response to the alert specifies blocking the write operation.

17. The apparatus of claim 15, wherein the memory controller is configured to write extended configuration information into the second portion of the memory based on an indication to expand the first portion of the memory.

18. The apparatus according to claim 15, wherein the memory is a non-volatile rewritable memory.

19. The apparatus of claim 15, wherein the second portion is within a keystore area of ​​the memory.

20. The apparatus of claim 15, wherein the first portion is within a data area of ​​the memory.

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