Chip packaging finite element model analysis method, device and equipment

Abstract

The present invention relates to the field of finite element analysis technology, and discloses a chip packaging finite element model analysis method, device and equipment. The method includes reading a chip packaging finite element model, and dividing the chip packaging finite element model into multiple subtasks based on the characteristics of the chip packaging structure; initializing a parallel computing environment and creating multiple threads; allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks; and processing the subtasks in parallel based on threads according to the resource allocation results to obtain model analysis results. In the present invention, the finite element model is analyzed by parallel computing, which shortens the simulation calculation time, especially when processing large-scale chip packaging models. The performance improvement is particularly significant. Through optimized task division and load balancing strategies, computing resources are fully utilized, the situation of thread idle waiting is reduced, and tasks are evenly distributed among computing units to improve the overall parallel computing efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of finite element analysis, and in particular to a chip packaging finite element model analysis method, device and equipment. Background Art

[0002] With the development of miniaturization and high performance of modern electronic devices, chip packaging technology plays a key role in semiconductor manufacturing. Chip packaging not only affects the electrical performance of the chip, but also involves multi-physics issues such as thermal management and stress distribution. Therefore, accurate chip packaging simulation is crucial to ensure product quality and performance.

[0003] In chip packaging simulation, finite element analysis (FEA) is often used to simulate the stress, deformation, thermal conduction and electromagnetic effects of packaging materials under different process conditions. However, with the increasing complexity of chip structures and model size, the amount of calculation of finite element models has increased dramatically. Traditional single-threaded or serialized analytical methods face performance bottlenecks when processing large-scale complex finite element models, and it is difficult to meet the needs of fast and efficient simulation.

[0004] To meet this challenge, existing technologies have gradually introduced parallel computing and high-performance computing (HPC) methods to accelerate the analysis process of finite element analysis models. However, most of the current parallel computing methods still have problems such as uneven load balancing, data transmission bottlenecks, and non-optimized multi-threaded task scheduling when processing large finite element models, resulting in insufficient improvement in analysis performance. Therefore, there is an urgent need for a finite element analysis model analysis method based on parallel computing that can effectively cope with the analysis tasks of large-scale models in chip packaging simulation, improve simulation speed, and ensure high-precision simulation results. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip packaging finite element model analysis method, device and equipment, aiming to solve at least one of the above-mentioned technical problems.

[0006] To achieve the above object, the present invention provides a chip packaging finite element model analysis method, comprising:

[0007] Reading a chip package finite element model, and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics;

[0008] Initialize the parallel computing environment and create multiple threads;

[0009] Allocating resources based on the geometric dimensions, material property differences, and loading conditions of the subtasks;

[0010] The subtasks are processed in parallel based on the threads according to the resource allocation result to obtain a model parsing result.

[0011] In some embodiments, the reading of the chip package finite element model and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics include:

[0012] Read the chip package finite element model according to the chip package simulation input file;

[0013] Acquiring chip packaging data based on the chip packaging finite element model; wherein the chip packaging data includes geometric information, material properties, boundary conditions, a hierarchy of packaging materials, a connection method between the chip and the substrate, a packaging solder ball array, and thermal expansion coefficients of different materials;

[0014] The chip package finite element model is divided into a plurality of subtasks based on the geometric regions, material properties and load conditions of the chip package data.

[0015] In some embodiments, dividing the chip package finite element model into a plurality of subtasks based on the geometric regions, material properties and load conditions of the chip package data includes:

[0016] Identify and separate the chip package finite element model based on the geometric regions and key nodes of stress concentration of the chip package data to obtain multiple sub-regions;

[0017] Identify and separate the chip package finite element model based on the material properties of the chip package data and the material differences of adjacent regions to obtain a plurality of sub-regions;

[0018] The sub-areas are adjusted based on the load conditions and load distribution characteristics of the chip packaging data to obtain a plurality of sub-tasks.

[0019] In some embodiments, the processing the subtasks in parallel based on the threads according to the resource allocation result to obtain the model parsing result includes:

[0020] Processing the subtasks in parallel based on the threads according to the resource allocation result;

[0021] Generating a mesh according to the geometric characteristics and the area division scheme of the chip package finite element model;

[0022] Applying boundary conditions to the subtasks according to the load conditions and constraint requirements of the chip package finite element model;

[0023] Start the solver;

[0024] The solver independently calculates each of the subtasks according to the boundary conditions and the grid to obtain a model analysis result.

[0025] In some embodiments, the step of independently calculating each of the subtasks based on the boundary conditions and the grid by the solver to obtain a model analysis result includes:

[0026] When processing the subtask, performing regional parsing based on the grid;

[0027] Determine the basic equation for strain based on the amount of stress, the material elastic modulus stress, and the amount of strain;

[0028] Based on the basic equation of the strain combined with the boundary conditions, the local stress and deformation distribution of each subtask is solved;

[0029] Aggregating the local stress and deformation distributions of each of the subtasks to generate an overall stress distribution result;

[0030] The overall stress distribution result is used as the model analysis result.

[0031] In some embodiments, the aggregating the local stress and deformation distribution of each of the subtasks to generate an overall stress distribution result includes:

[0032] When each of the threads completes a subtask, result data of local stress and deformation distribution are obtained;

[0033] Compressing or formatting the result data into unified structure data;

[0034] Receiving the unified structure data of each subtask through a distributed message queue or a shared memory area;

[0035] Gathering the unified structure data into the main thread based on an asynchronous result collection mechanism;

[0036] The batch processing merges the unified structural data to generate an overall stress distribution result.

[0037] In some embodiments, the method further comprises:

[0038] Monitor the CPU utilization, memory usage and task completion percentage of each thread in real time to obtain the task progress status and load status of the thread;

[0039] A dynamic adjustment strategy is executed according to the task progress status and load conditions; wherein the dynamic adjustment strategy includes task splitting and transfer, resource reallocation and delayed task reallocation.

[0040] In some embodiments, the method further comprises:

[0041] Performing data visualization on the model analysis result based on a graphics processing unit to obtain an initial visualization image;

[0042] Performing layered rendering and detail control on the initial visual image to obtain an updated visual image;

[0043] Analyzing the model analysis results according to stress analysis and deformation trend detection algorithms to identify stress concentration points in key areas of the chip;

[0044] Automatically marking stress concentration points in the key area of ​​the chip in the updated visualization image to obtain a target visualization image;

[0045] Performing error propagation analysis on the model analysis results according to the benchmark model and the real test data to obtain error values ​​of key nodes, and generating an error distribution diagram according to the error values ​​of the key nodes;

[0046] Perform stress history change analysis on the model analysis results to obtain stress change trend prediction results;

[0047] The target visualization image and the error distribution diagram are displayed, and an early warning is issued according to the stress change trend prediction result.

[0048] In addition, to achieve the above-mentioned purpose, the present invention also proposes a chip packaging finite element model analysis device, comprising:

[0049] A task division module, used for reading a chip package finite element model and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics;

[0050] A thread creation module is used to initialize the parallel computing environment and create multiple threads;

[0051] A resource allocation module, used for allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks;

[0052] The task analysis module is used to process the subtasks in parallel based on the threads according to the resource allocation result to obtain a model analysis result.

[0053] In addition, to achieve the above-mentioned purpose, the present invention also proposes an electronic device, which includes: a memory, a processor, and a chip packaging finite element model analysis program stored in the memory and runnable on the processor, and the chip packaging finite element model analysis program is configured to implement the chip packaging finite element model analysis method as described above.

[0054] The present invention provides a chip package finite element model analysis method, including: reading the chip package finite element model, and dividing the chip package finite element model into multiple subtasks based on the chip package structure characteristics; initializing a parallel computing environment and creating multiple threads; allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks; and processing the subtasks in parallel based on the threads according to the resource allocation results to obtain model analysis results. In the present invention, the finite element model is analyzed by parallel computing, which greatly shortens the simulation calculation time, especially when processing large-scale chip package models, the performance improvement is particularly significant. Through optimized task division and load balancing strategies, computing resources are fully utilized, the situation of thread idle waiting is reduced, and tasks are evenly distributed among computing units to improve the overall parallel computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of the structure of an electronic device in a hardware operating environment involved in an embodiment of the present invention;

[0056] Figure 2 It is a schematic diagram of a flow chart of an embodiment of a chip packaging finite element model analysis method of the present invention;

[0057] Figure 3 A flowchart of a fast analysis of a finite element model for parallel computing involved in an embodiment of the present invention;

[0058] Figure 4 It is a structural block diagram of an embodiment of a chip package finite element model analysis device of the present invention.

[0059] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0062] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the ability of ordinary technicians in the field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0063] Reference Figure 1 , Figure 1 The figure is a schematic diagram of the structure of an electronic device of the hardware operating environment involved in the embodiment of the present invention.

[0064] like Figure 1 As shown, the electronic device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (Wireless-Fidelity, Wi-Fi) interface). The memory 1005 may be a high-speed random access memory (Random Access Memory, RAM memory) or a stable non-volatile memory (Non-Volatile Memory, NVM), such as a disk memory. The memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0065] Those skilled in the art will understand that Figure 1 The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0066] like Figure 1 As shown, the memory 1005 as a storage medium may include an operating system, a network communication module, a user interface module, and a chip package finite element model analysis program.

[0067] exist Figure 1In the electronic device shown, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the electronic device of the present invention can be set in the electronic device, and the electronic device calls the chip package finite element model analysis program stored in the memory 1005 through the processor 1001, and executes the chip package finite element model analysis method provided in an embodiment of the present invention.

[0068] The present invention provides a chip packaging finite element model analysis method, device and equipment.

[0069] The embodiment of the present invention provides a chip packaging finite element model analysis method, referring to Figure 2 , Figure 2 It is a schematic diagram of a flow chart of an embodiment of a chip package finite element model analysis method of the present invention.

[0070] like Figure 2 As shown, the chip package finite element model analysis method includes:

[0071] Step S100: reading a chip package finite element model, and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics;

[0072] Step S200: Initialize a parallel computing environment and create multiple threads;

[0073] Step S300: Allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks;

[0074] Step S400: Processing the subtasks in parallel based on the threads according to the resource allocation result to obtain a model analysis result.

[0075] It should be noted that the execution subject in this embodiment may be an electronic device, which may be a computer device with data processing functions, or other devices that can achieve the same or similar functions. This embodiment does not limit this. In this embodiment, a computer device is used as an example for explanation.

[0076] It is understandable that the method described in this embodiment adopts a finite element analysis model analysis method based on parallel computing, which can effectively cope with the analysis requirements of large-scale and complex finite element models in chip packaging simulation, and by dividing the analysis task of the finite element model into multiple parallel subtasks, reasonably allocating computing resources, and optimizing the load balancing and data transmission mechanism, the analysis speed is significantly improved, the analysis time is reduced, and the simulation accuracy is maintained. The following is an explanation in conjunction with specific steps.

[0077] In one embodiment, a chip packaging finite element model is read, and the chip packaging finite element model is divided into multiple subtasks based on the chip packaging structure characteristics, including: reading the chip packaging finite element model according to a chip packaging simulation input file; acquiring chip packaging data based on the chip packaging finite element model; wherein the chip packaging data includes geometric information, material properties, boundary conditions, a hierarchical structure of packaging materials, a connection method between the chip and the substrate, a packaging solder ball array, and thermal expansion coefficients of different materials; and dividing the chip packaging finite element model into multiple subtasks based on the geometric area, material properties, and load conditions of the chip packaging data.

[0078] In this embodiment, Figure 3 As shown, task division and preprocessing include model reading and task division.

[0079] Specifically, model reading: First, the data of the chip package finite element model (chip package data) is read from the chip package simulation input file, including but not limited to geometric information, material properties, boundary conditions, and data specific to chip package, etc. For example, the hierarchical structure of the package material, the connection method between the chip and the substrate, the solder ball array in the package, and the thermal expansion coefficient of different materials, etc. The accurate reading and analysis of these specific chip package data is the basis for ensuring the accuracy of the simulation results.

[0080] Exemplarily, data specific to chip packaging may also include the following aspects: package type (e.g., quad flat no-lead package QFN, small outline integrated circuit SOIC, dual in-line package DIP, pin grid array PGA, ball grid array BGA, round pin grid array PGA, wafer level package WLP, thin quad flat package TQFP and various other package types, etc.); package dimensions, such as the chip package's outer dimensions (length, width, height, etc.), pin pitch and number of pins; pin configuration, such as the arrangement and function of the pins (power pins, ground pins, input pins, output pins, etc.); packaging materials, such as the type of material used for packaging (plastic, ceramic, metal, etc.); ); packaging process such as the process used for chip packaging (wire bonding, flip chip, solder ball, etc.); thermal characteristics such as thermal conductivity, thermal expansion coefficient and other thermal characteristics data of chip packaging; electrical characteristics such as capacitance, inductance, resistance and other electrical characteristics of chip packaging; mechanical characteristics such as mechanical strength, impact resistance, vibration stability, etc. of the packaging; environmental characteristics such as moisture resistance, corrosion resistance, operating temperature range and other environmental characteristics of the packaging; reliability data such as reliability indicators of chip packaging (mean time between failures MTBF, service life, etc.); standards and certifications such as international or domestic standards followed by the packaging, specific quality certifications, etc.; manufacturing information such as the name of the packaging manufacturer, manufacturing location, manufacturing batch number, etc.

[0081] Specifically, task division: after reading the data, the chip packaging finite element model is divided into multiple sub-models or sub-tasks based on the geometric area, material properties and load conditions of the model according to the structural characteristics of the large-scale chip packaging model. For example, the task division process first identifies and separates key areas that are highly sensitive to temperature and stress (such as the chip and substrate connection area) and areas with significant differences in material properties (such as the solder ball and substrate connection area). In this embodiment, this method can ensure that the computational load of each sub-task is relatively balanced, thereby improving the efficiency of parallel computing.

[0082] Exemplarily, the geometric area includes but is not limited to the following information: chip: including silicon chip and any dielectric layers, metal interconnect layers, etc. that may exist on the chip; packaging materials: such as substrate, lead frame, plastic packaging material, etc.; leads: metal leads or solder balls connecting the chip and the substrate; solder joints: solder joints connecting the chip and the packaging material or lead frame; interface area: contact area between the chip and the packaging material or lead frame; heat dissipation device (if a heat dissipation device is provided): such as heat sinks, heat sinks, heat pipes and other heat dissipation devices; environmental area: simulates the impact of the external environment on the package, such as temperature field distribution, etc.

[0083] Exemplarily, material properties include but are not limited to the following information: chip material: elastic modulus, Poisson's ratio, thermal expansion coefficient and thermal conductivity of silicon; packaging material: elastic modulus, Poisson's ratio, thermal expansion coefficient, thermal conductivity and electrical conductivity of materials such as plastic, ceramic and metal; lead material: elastic modulus, Poisson's ratio, thermal expansion coefficient and melting point of lead material; solder material: melting point, thermal conductivity and viscoelastic properties of solder material; heat dissipation material: elastic modulus, Poisson's ratio, thermal expansion coefficient and thermal conductivity of heat dissipation material.

[0084] Exemplarily, load conditions include but are not limited to the following information: thermal load: thermal stress distribution of packaging materials at different temperatures, including thermal cycling, thermal shock, etc.; mechanical load: response of packaging structure under loads such as mechanical pressure, vibration and shock; electrical load: thermal effects and electromagnetic field influences of chips and packaging structures under electrical loads; chemical load: chemical stability of packaging materials under specific environments, such as humidity, corrosion, etc.; thermomechanical load: combined effect of thermal load and mechanical load, such as stress changes caused by temperature changes.

[0085] In one example, the chip packaging finite element model is divided into multiple subtasks based on the geometric area, material properties and load conditions of the chip packaging data, including: identifying and separating the chip packaging finite element model based on the geometric area and key nodes of stress concentration of the chip packaging data to obtain multiple sub-areas; identifying and separating the chip packaging finite element model based on the material properties of the chip packaging data and the material differences of adjacent areas to obtain multiple sub-areas; adjusting the sub-areas based on the load conditions and load distribution characteristics of the chip packaging data to obtain multiple sub-tasks.

[0086] It should be noted that task division optimization: In this embodiment, after the initial division, in order to further improve the computing efficiency and simulation accuracy, the tasks are optimized in combination with the characteristics of chip packaging simulation. Optimization of geometric area division: Refine the key nodes of stress concentration so that these areas can more accurately reflect the load response. Optimization of material properties: Make finer divisions in parts where the materials of adjacent areas are relatively different to reduce the impact of material properties on computational stability at the partition boundaries. In addition, in the optimization of load conditions, sub-areas are adjusted according to the characteristics of uneven load distribution so that each subtask can bear the actual computing load more reasonably.

[0087] In one embodiment, a parallel computing environment is initialized and multiple threads are created; and resources are allocated according to the geometric dimensions, material property differences, and load conditions of the subtasks.

[0088] In this embodiment, Figure 3 As shown, the parallel computing environment setting includes multi-thread / multi-process creation and resource allocation.

[0089] Specifically, multi-thread / multi-process creation: initialize the parallel computing environment and create multiple threads or processes to process the divided subtasks. Based on the load characteristics of the task, a parallel computing framework (such as MPI, OpenMP) can be used to efficiently manage the allocation and scheduling of threads or processes to ensure that each subtask runs independently and in parallel in a multi-thread or multi-process environment. Among them, MPI (Message Passing Interface) is suitable for distributed memory systems, and nodes communicate through message passing; OpenMP (Open Multi-Processing) is suitable for shared memory systems and uses multi-threading technology to achieve parallelism.

[0090] In practical applications, parallel computing libraries such as MPI, OpenMP, or parallel finite element analysis software such as ANSYS, ABAQUS, and COMSOL Multiphysics can be used.

[0091] Specifically, resource allocation: when allocating resources, the large-scale characteristics of the chip packaging model are comprehensively considered and optimized according to the complexity and load characteristics of the subtasks. For example, computing resources (such as CPU cores and memory) are preferentially allocated to task units involving key areas (such as solder ball areas and chip-substrate connection areas) to ensure the simulation accuracy of these high computing demand areas. In terms of allocation conditions, resource allocation can be dynamically adjusted according to priority based on the geometric dimensions, material property differences and load conditions of each subtask to ensure that more CPU and memory resources are allocated to complex tasks when resources are sufficient, while smaller or low-priority tasks use appropriate resources. This allocation strategy ensures the parsing efficiency of key areas in large-scale chip packaging models while maintaining the balance and efficiency of the overall calculation.

[0092] It is understandable that in the resource allocation process, the resource allocation can be dynamically adjusted according to the priority based on the geometric size, material property differences and load conditions. The following strategies can be adopted: First, analyze the resource requirements, such as analyzing the characteristics of the finite element model, including geometric complexity, material type and quantity, load conditions, etc., and evaluate the consumption of different resources (CPU, memory, computing power, etc.) in different parts of the model. Determine the priority rules based on the geometric size, material property differences and load conditions, where large or complex geometric model parts may require more computing resources, different material properties (such as elastic modulus, thermal conductivity, etc.) may require different calculation methods or parameters, and high-load areas may require more precise analysis, so more resources may be required. Set up priority queues: allocate resources to high-priority tasks, such as high-load areas or parts with complex material properties. Establish a feedback mechanism to monitor resource usage in real time, including CPU utilization, memory utilization, and network bandwidth, and provide feedback based on task completion progress and resource usage to optimize future resource allocation, ensure that all computing nodes have similar workloads, avoid resource waste, and improve resource utilization.

[0093] In one embodiment, the subtasks are processed in parallel based on the threads according to the resource allocation result to obtain a model analysis result, including: processing the subtasks in parallel based on the threads according to the resource allocation result; generating a mesh according to the geometric characteristics and area division scheme of the chip package finite element model; applying boundary conditions to the subtasks according to the load conditions and constraint requirements of the chip package finite element model; starting a solver; and independently calculating each of the subtasks according to the boundary conditions and the mesh based on the solver to obtain a model analysis result.

[0094] In one embodiment, the solver independently calculates each of the subtasks according to the boundary conditions and the grid to obtain a model analysis result, including: performing regional analysis based on the grid when processing the subtasks; determining a basic equation of strain based on the stress amount, material elastic modulus stress, and strain amount; solving the local stress and deformation distribution of each subtask based on the basic equation of strain combined with the boundary conditions; summarizing the local stress and deformation distribution of each subtask to generate an overall stress distribution result; and using the overall stress distribution result as the model analysis result.

[0095] In this embodiment, Figure 3 As shown, parallel parsing includes subtask execution and data local optimization.

[0096] Specifically, subtask execution: the finite element model is decomposed into multiple subtasks, each of which is assigned to a processor or node to ensure load balancing. Each thread or process independently executes its assigned subtask to parse the finite element data of a large-scale chip packaging model, including the following main steps:

[0097] 1. Grid generation: Generate a grid that adapts to the complex packaging structure based on the geometric characteristics of the chip packaging model and the area division scheme. In this embodiment, a refined grid strategy is used for thermally sensitive areas and stress concentration areas to improve the analytical accuracy of these areas.

[0098] 2. Apply boundary conditions: In each subtask, apply corresponding boundary conditions according to the specific load conditions and constraint requirements of the chip packaging model. For example, boundary conditions include thermal load, mechanical load, etc., and these conditions are converted into force or displacement on nodes or units through formulas. Here, boundary conditions include but are not limited to: fixed boundary: fixed or restricted conditions of the packaging structure in a certain direction; loading area: specific area where mechanical load or thermal load is applied; environmental conditions: ambient temperature, humidity and other conditions of the packaging structure.

[0099] 3. Solver operation: Each subtask starts the corresponding solver for independent calculation. During the solving process, the basic equation based on stress and strain ;in, is stress, is the elastic modulus of the material, is strain. Combined with the boundary conditions unique to chip packaging models such as thermal expansion and heat flow, the local stress and deformation distribution of each subtask is solved. The calculation results will be summarized after the parallel solution is completed to generate the overall stress distribution results.

[0100] In practical applications, appropriate material properties and load conditions are selected according to the specific analysis purpose and model complexity, and appropriate meshing is performed on the chip package finite element model to ensure calculation accuracy and efficiency. These data usually come from material testing, experimental data, supplier data sheets or industry standards.

[0101] Specifically, data locality optimization: In order to improve the efficiency of the parallel parsing process, this embodiment ensures that each thread or process performs data processing locally and minimizes data transmission across threads or processes. The specific implementation process is as follows: Data allocation during task initialization: The data to be processed (such as mesh information, material properties, and boundary conditions, etc.) is allocated to the memory space of the same thread or process as much as possible during the task division stage to reduce the subsequent data sharing requirements.

[0102] Exemplarily, a cache mechanism is used: an independent cache space is configured for each thread or process to store the data required for local calculations. During the calculation process, frequently accessed data will be stored in the cache first to avoid repeated reading of main memory data. Reduce cross-process communication: When subtasks are executed, the data dependency between different processes or threads is reduced through optimization algorithms. For example, boundary node data with shared boundary conditions is used, and internal data in different areas is isolated to reduce data interaction between different tasks. Data synchronization: After the subtasks are executed, the calculation results of each subtask are synchronized to the main thread by summarizing local results to avoid frequent synchronization during the execution of subtasks. This process reduces the communication overhead of parallel computing while maintaining data locality.

[0103] It is understandable that when data processing is performed in parallel threads or processes, data transmission across threads or processes is one of the performance bottlenecks. In order to reduce this transmission, the following strategies can also be adopted: In terms of data segmentation, task division: divide the data into blocks as large as possible so that each thread or process can process it independently, reducing the need for data sharing; locality principle: try to maintain the locality of data so that the data processed by each thread or process has good continuity in memory. In terms of prefetching and caching, data prefetching: predict the data that the thread or process may need next, and load it into the cache in advance when the processor is idle; cache consistency: use cache consistency protocol to ensure that the data in the cache is consistent with the data in the main memory. In terms of minimizing data replication, read-only data: try to use read-only data, which can avoid data replication and synchronization; shared memory: use shared memory instead of message passing to reduce the overhead of data transmission. In terms of data aggregation, data aggregation: before sending data, try to aggregate data at the sending end to reduce the amount of data transmitted; batch processing: merge multiple small data transmissions into one large data transmission. In terms of communication optimization, communication overlap: perform other computing tasks while sending or receiving data to hide communication delays; communication mode: select an appropriate communication mode, such as asynchronous communication, to reduce the waiting time of threads or processes. In terms of data localization, data rearrangement: rearrange data so that the data processed by each thread or process is stored continuously in memory as much as possible; space filling: fill empty spaces in the data structure to reduce cache misses. The above strategies can significantly reduce data transmission across threads or processes when performing data processing in parallel threads or processes, thereby improving overall performance.

[0104] In one embodiment, the local stress and deformation distribution of each of the subtasks are summarized to generate an overall stress distribution result, including: obtaining result data of the local stress and deformation distribution when each of the threads completes a subtask; compressing or formatting the result data into unified structure data; receiving the unified structure data of each subtask through a distributed message queue or a shared memory area; aggregating the unified structure data into a main thread based on an asynchronous result collection mechanism; and batch processing and merging the unified structure data to generate an overall stress distribution result.

[0105] In this embodiment, Figure 3 As shown, result summary and post-processing include result collection and post-processing.

[0106] Specifically, result collection: after each thread or process completes the subtask, an efficient asynchronous result collection mechanism is used to collect the analysis results (such as stress, deformation and other data) into the main process or main thread. Exemplarily, when each subtask is completed, the result data is compressed or formatted into a unified data structure to reduce the amount of data transmission and memory usage. The main process receives the results of each subtask through a distributed message queue or a shared memory area, merges these results using a batch processing method, and reconstructs the analysis state of the entire finite element model. In this embodiment, the use of asynchronous collection and batch merging not only improves the aggregation efficiency, but also avoids performance bottlenecks caused by excessive data transmission.

[0107] In one embodiment, the method further includes: real-time monitoring of the CPU utilization, memory occupancy and task completion percentage parameters of each of the threads to obtain the task progress status and load conditions of the threads; executing a dynamic adjustment strategy based on the task progress status and load conditions; wherein the dynamic adjustment strategy includes task splitting and transfer, resource reallocation and delayed task reallocation.

[0108] In this embodiment, Figure 3 As shown, load balancing and dynamic scheduling include load monitoring and dynamic adjustment.

[0109] Specifically, load monitoring: by real-time monitoring of the computing load and task progress of each thread or process, the progress status and resource consumption are obtained. For example, progress monitoring is based on parameters such as the CPU utilization, memory usage, and task completion percentage of the thread or process. By collecting this information, the real-time execution status of each subtask can be determined. For example, when the CPU usage of a thread increases significantly or the task completion percentage is lower than expected, it can be identified that the thread has a high load.

[0110] Specifically, dynamic adjustment: Based on the results of load monitoring, dynamic adjustment strategies are adopted to ensure balanced load and optimize computing resource utilization. Dynamic adjustment strategies include but are not limited to task splitting and transfer, resource reallocation, delayed task reallocation, and adaptive strategy optimization.

[0111] For example, task splitting and transfer: when it is detected that a thread or process is overloaded and the progress is lagging behind, some subtasks are split again, and the smaller task fragments are transferred to threads or processes with lighter loads for execution. The specific operation includes storing the current progress and locking the task data to be transferred, and then restarting the task fragment in the low-load thread to achieve load redistribution.

[0112] For example, resource reallocation: In a multi-threaded environment, the computing power of each task can be balanced by adjusting thread priorities or increasing the CPU resources available to threads. For a multi-process environment, more memory or GPU resources can be dynamically allocated according to task progress to speed up the execution of heavy-load tasks.

[0113] For example, delayed task reallocation: For threads that are significantly behind schedule, a dynamic scheduling mechanism is used to divide their remaining tasks into multiple small subtasks and assign them to currently idle or lightly loaded threads to improve overall processing efficiency. This adjustment method can prevent a single task from affecting the overall progress and ensure the real-time and computational balance of large-scale model analysis.

[0114] Exemplarily, adaptive strategy optimization: adjust the scheduling strategy through machine learning or preset rules, adaptively optimize task allocation based on historical monitoring data and real-time feedback, and ensure that scheduling decisions can continuously improve the computing load balance of each thread and reduce the risk of delays in overweight tasks.

[0115] It should be noted that during performance monitoring and optimization, resource monitoring can monitor the CPU usage, memory usage, and network bandwidth of computing nodes. Adjust task allocation according to computing progress and resource usage to maintain load balance. Reduce communication overhead and improve computing efficiency by optimizing parallel algorithms. In addition, a fault-tolerant mechanism can be established to ensure that a single node failure will not affect the entire computing process. Regularly back up computing data to prevent data loss. Through the above steps, computing resources can be effectively allocated and utilized to improve the parallel computing efficiency of chip packaging finite element model analysis.

[0116] In one embodiment, the method further includes: performing data visualization on the model analysis results based on a graphics processing unit to obtain an initial visualization image; performing layered rendering and detail control on the initial visualization image to obtain an updated visualization image; analyzing the model analysis results according to a stress analysis and deformation trend detection algorithm to identify stress concentration points in key areas of the chip; automatically marking the stress concentration points in key areas of the chip in the updated visualization image to obtain a target visualization image; performing error propagation analysis on the model analysis results according to a benchmark model and real test data to obtain error values ​​of key nodes, and generating an error distribution map based on the error values ​​of the key nodes; performing stress history change analysis on the model analysis results to obtain a stress change trend prediction result; displaying the target visualization image and the error distribution map, and issuing an early warning based on the stress change trend prediction result.

[0117] Specifically, Figure 3 As shown, post-processing: After the summary is completed, the analysis results are post-processed, including the following steps:

[0118] 1. Data visualization: Real-time visualization technology based on graphics processing unit (GPU) acceleration is used to display key results such as stress and deformation. By using graphic elements such as contour maps and vector fields, simulation data is presented to users in an intuitive way. In this embodiment, in order to meet the needs of large-scale chip packaging models, the visualization operation introduces layered rendering and detail control functions, so that users can choose to observe the global or local area as needed, and the rendering speed is not affected when zooming in on local details. In addition, an adaptive graphics compression algorithm is used to display high-resolution images under limited hardware resources.

[0119] 2. Result analysis: In response to the needs of chip packaging simulation, a variety of stress analysis and deformation trend detection algorithms are built in. For example, the abnormal stress point detection algorithm based on neighborhood stress difference can effectively identify stress concentration points in key areas of the chip and automatically mark them in 3D visualization. In addition, stress history change analysis is introduced to predict stress change trends in multi-step simulations and provide users with early warnings of potential failure risks.

[0120] 3. Error evaluation: The error propagation analysis method is used to evaluate the reliability of the analytical results. By introducing the comparison between the benchmark model and the real test data, the error value of each key node is calculated, and an error distribution diagram is generated so that users can intuitively understand the accuracy of the simulation results. At the same time, a set of adaptive error control algorithms is designed to dynamically adjust the calculation accuracy according to the error evaluation results, such as re-refining the grid or increasing the calculation accuracy in the high error area, thereby improving the overall accuracy of the simulation.

[0121] Among them, an abnormal stress point detection algorithm based on neighborhood stress difference is used to detect potential weaknesses or high-risk areas in the structure. Specifically, finite element analysis is performed on the result data to obtain stress distribution data; FEA software (such as ANSYS, ABAQUS, etc.) is used to simulate the stress state of the chip under various working conditions; define the neighborhood: define a neighborhood for each node or element, which can be based on geometric distance or connectivity (such as nodes directly connected to the node); calculate the average stress of the neighborhood: for each node or element, calculate the average stress of all nodes in its neighborhood or the average stress component; calculate stress difference: for each node or element, calculate the difference between its stress value and the average stress value of its neighborhood; define an abnormal threshold: define a threshold to distinguish between normal stress levels and abnormal stress levels, and this threshold can be determined based on statistical methods (such as standard deviation, confidence interval, etc.) or based on engineering experience; identify abnormal stress points: for each node or element, if its stress difference exceeds the defined threshold, the point is considered to be an abnormal stress point; visualize: visualize the abnormal stress points on the chip model to intuitively display the area of ​​stress concentration. Through the above steps, stress concentration points in critical areas of the chip can be effectively identified, which is crucial to ensuring the structural integrity of the chip under various working conditions.

[0122] It should be noted that the method described in this embodiment can also be adaptively expanded to support distributed computing: it supports running in a distributed computing environment and can be expanded to multiple computers as needed to perform large-scale model analysis; flexible task division strategy: it provides a flexible task division strategy to adapt to chip packaging simulation tasks of different scales and complexities.

[0123] Exemplarily, the method described in this embodiment is described by taking Embodiment 1 as an example.

[0124] Embodiment 1: Decompose the finite element model file into geometric information data, mesh information data, material property boundary condition load and other information. Create multiple reading tasks, including 4 tasks of reading geometric data information, reading mesh data information, reading material property information, reading boundary condition load and other setting information. Initialize the parallel computing environment, use the existing parallel computing framework (MPI, OpenMP) to manage threads and processes, allocate computer resources (CPU core, memory, etc.) according to the current resource environment of the computer, and independently execute the assigned subtasks in each thread or process to parse the finite element model. When executing subtasks, try to keep the data in local memory and reduce data transmission across threads or processes to improve access speed. By monitoring the load of each thread or process in real time, evaluate the progress of task completion, and perform load balancing and dynamic scheduling. Report the task parsing results by checking the execution of all tasks, whether all tasks are parsed successfully, summarize the correct parsing results into the specified data structure, and display the parsing failure module and return the possible error reasons for the parsing failure.

[0125] In this embodiment, the method has the following beneficial effects:

[0126] Significantly improve analysis speed: The finite element model is analyzed through parallel computing, which greatly shortens the simulation calculation time. The performance improvement is particularly significant when processing large-scale chip packaging models.

[0127] Improve parallel resource utilization: Through optimized task division and load balancing strategies, computing resources are fully utilized, reducing the situation where threads or processes are idle and waiting, ensuring that tasks are evenly distributed among computing units, and improving the overall parallel computing efficiency.

[0128] Reduce data transmission bottlenecks: Through data locality optimization and intelligent task scheduling, the amount of data transmission between subtasks is reduced, excessive data communication overhead is avoided, and the overall parsing efficiency is improved.

[0129] Strong adaptability: It is not only suitable for a single high-performance computing device, but can also be extended to a distributed computing environment and executed in parallel on multiple computers. It can flexibly adapt to finite element models of different sizes and dynamically adjust the task division strategy according to the complexity of the model.

[0130] Guaranteed simulation accuracy: Despite the accelerated analysis process, the high accuracy of finite element simulation can still be maintained, especially in complex problems such as stress, heat conduction, and multi-physics fields in the chip packaging field, ensuring the accuracy and reliability of simulation results.

[0131] Improve the R&D efficiency of chip packaging simulation: By accelerating analysis and improving computing efficiency, the product development cycle can be shortened and R&D costs can be reduced during the simulation process in the chip packaging field, thus bringing significant economic benefits to the company.

[0132] This embodiment provides a chip package finite element model analysis method, including: reading the chip package finite element model, and dividing the chip package finite element model into multiple subtasks based on the characteristics of the chip package structure; initializing a parallel computing environment and creating multiple threads; allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks; and processing the subtasks in parallel based on the threads according to the resource allocation results to obtain model analysis results. In this embodiment, the finite element model is analyzed through parallel computing, which greatly shortens the simulation calculation time, especially when processing large-scale chip package models, the performance improvement is particularly significant. Through optimized task division and load balancing strategies, computing resources are fully utilized, reducing the situation of idle waiting of threads, ensuring that each computing unit is evenly distributed with tasks, and improving the overall parallel computing efficiency.

[0133] In addition, an embodiment of the present invention further proposes a storage medium, on which a chip package finite element model analysis program is stored. When the chip package finite element model analysis program is executed by a processor, the steps of the chip package finite element model analysis method described above are implemented.

[0134] Reference Figure 4 , Figure 4 It is a structural block diagram of an embodiment of a chip package finite element model analysis device of the present invention.

[0135] like Figure 4 As shown, the chip packaging finite element model analysis device includes:

[0136] A task division module 10 is used to read the chip package finite element model and divide the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics;

[0137] A thread creation module 20, used to initialize a parallel computing environment and create multiple threads;

[0138] A resource allocation module 30, configured to allocate resources according to the geometric dimensions, material property differences and load conditions of the subtasks;

[0139] The task analysis module 40 is used to process the subtasks in parallel based on the threads according to the resource allocation result to obtain a model analysis result.

[0140] The present embodiment provides a chip packaging finite element model analysis device, including: a task division module 10, a thread creation module 20, a resource allocation module 30 and a task analysis module 40. The chip packaging finite element model analysis device significantly improves the analysis speed: the finite element model is analyzed by parallel computing, which greatly shortens the simulation calculation time, especially when processing large-scale chip packaging models, the performance improvement is particularly significant. Improve the utilization of parallel resources: through optimized task division and load balancing strategies, the computing resources are fully utilized, the situation of idle waiting of threads or processes is reduced, and tasks are evenly distributed among computing units, which improves the overall parallel computing efficiency. Reduce the bottleneck of data transmission: through data locality optimization and intelligent task scheduling, the amount of data transmission between subtasks is reduced, excessive data communication overhead is avoided, and the overall analysis efficiency is improved. Strong adaptability: not only suitable for a single high-performance computing device, but also can be extended to a distributed computing environment, executed in parallel on multiple computers, can flexibly adapt to finite element models of different sizes, and can dynamically adjust the task division strategy according to the complexity of the model. Simulation accuracy is guaranteed: Despite the accelerated analysis process, the high accuracy of finite element simulation can still be maintained, especially in complex problems such as stress, heat conduction, and multi-physics fields in the chip packaging field, ensuring the accuracy and reliability of simulation results. Improve the R&D efficiency of chip packaging simulation: By accelerating analysis and improving computing efficiency, the product development cycle can be shortened and R&D costs can be reduced in the simulation process in the chip packaging field, thereby bringing significant economic benefits to enterprises.

[0141] It should be noted that the technical details that are not fully described in the embodiment of the chip package finite element model analysis device can be found in the chip package finite element model analysis method provided in any embodiment of the present invention as described above, and will not be repeated here.

[0142] It should be understood that the above is only an example and does not constitute any limitation on the technical solution of the present invention. In specific applications, technicians in this field can make settings as needed, and the present invention does not limit this.

[0143] It should be noted that the workflow described above is merely illustrative and does not limit the scope of protection of the present invention. In practical applications, technicians in this field can select part or all of them according to actual needs to achieve the purpose of the present embodiment, and no limitation is made here.

[0144] In addition, it should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0145] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0146] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory (ROM) / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0147] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A chip packaging finite element model analysis method, characterized in that: include: Reading a chip package finite element model, and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics; Initialize the parallel computing environment and create multiple threads; Allocating resources based on the geometric dimensions, material property differences, and loading conditions of the subtasks; Process the subtasks in parallel based on the threads according to the resource allocation result to obtain a model analysis result; Among them, the preliminary division into multiple subtasks includes: identifying and separating the chip packaging finite element model based on the geometric area of ​​the chip packaging data and the key nodes of stress concentration of the chip packaging finite element model, and obtaining multiple sub-areas; identifying and separating the chip packaging finite element model based on the material properties of the chip packaging data and the material differences of adjacent areas, and obtaining multiple sub-areas; adjusting the sub-areas based on the load conditions and load distribution characteristics of the chip packaging data, and obtaining multiple sub-tasks; After the preliminary division, the key nodes of stress concentration are refined in the division optimization of the geometric area; in the division optimization of the load conditions, the sub-areas are adjusted according to the characteristics of uneven load distribution.

2. The method according to claim 1, characterized in that The step of reading the chip package finite element model and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics includes: Read the chip package finite element model according to the chip package simulation input file; Acquiring chip packaging data based on the chip packaging finite element model; wherein the chip packaging data includes geometric information, material properties, boundary conditions, a hierarchy of packaging materials, a connection method between the chip and the substrate, a packaging solder ball array, and thermal expansion coefficients of different materials; The chip package finite element model is divided into a plurality of subtasks based on the geometric regions, material properties and load conditions of the chip package data.

3. The method according to claim 1, characterized in that The step of processing the subtasks in parallel based on the threads according to the resource allocation result to obtain the model parsing result includes: Processing the subtasks in parallel based on the threads according to the resource allocation result; Generating a mesh according to the geometric characteristics and the area division scheme of the chip package finite element model; Applying boundary conditions to the subtasks according to the load conditions and constraint requirements of the chip package finite element model; Start the solver; The solver independently calculates each of the subtasks according to the boundary conditions and the grid to obtain a model analysis result.

4. The method according to claim 3, characterized in that The step of independently calculating each of the subtasks based on the solver according to the boundary conditions and the grid to obtain a model analysis result includes: When processing the subtask, performing regional parsing based on the grid; Determine the basic equation for strain based on the amount of stress, the material elastic modulus stress, and the amount of strain; Based on the basic equation of the strain combined with the boundary conditions, the local stress and deformation distribution of each subtask is solved; Aggregating the local stress and deformation distributions of each of the subtasks to generate an overall stress distribution result; The overall stress distribution result is used as the model analysis result.

5. The method according to claim 4, characterized in that The summarizing of the local stress and deformation distribution of each of the subtasks to generate an overall stress distribution result includes: When each of the threads completes a subtask, result data of local stress and deformation distribution are obtained; Compressing or formatting the result data into unified structure data; Receiving the unified structure data of each subtask through a distributed message queue or a shared memory area; Gathering the unified structure data into the main thread based on an asynchronous result collection mechanism; The batch processing merges the unified structural data to generate an overall stress distribution result.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Monitor the CPU utilization, memory usage and task completion percentage of each thread in real time to obtain the task progress status and load status of the thread; A dynamic adjustment strategy is executed according to the task progress status and load conditions; wherein the dynamic adjustment strategy includes task splitting and transfer, resource reallocation and delayed task reallocation.

7. The method according to claim 6, characterized in that The method further comprises: Performing data visualization on the model analysis result based on a graphics processing unit to obtain an initial visualization image; Performing layered rendering and detail control on the initial visual image to obtain an updated visual image; Analyzing the model analysis results according to stress analysis and deformation trend detection algorithms to identify stress concentration points in key areas of the chip; Automatically marking stress concentration points in the key area of ​​the chip in the updated visualization image to obtain a target visualization image; Performing error propagation analysis on the model analysis results according to the benchmark model and the real test data to obtain error values ​​of key nodes, and generating an error distribution diagram according to the error values ​​of the key nodes; Perform stress history change analysis on the model analysis results to obtain stress change trend prediction results; The target visualization image and the error distribution diagram are displayed, and an early warning is issued according to the stress change trend prediction result.

8. A chip packaging finite element model analysis device, characterized in that: include: A task division module, used for reading a chip package finite element model and dividing the chip package finite element model into a plurality of subtasks based on the chip package structure characteristics; A thread creation module is used to initialize the parallel computing environment and create multiple threads; A resource allocation module, used for allocating resources according to the geometric dimensions, material property differences and load conditions of the subtasks; A task parsing module, used for processing the subtasks in parallel based on the threads according to the resource allocation result to obtain a model parsing result; Among them, the preliminary division into multiple subtasks includes: identifying and separating the chip packaging finite element model based on the geometric area of ​​the chip packaging data and the key nodes of stress concentration of the chip packaging finite element model, and obtaining multiple sub-areas; identifying and separating the chip packaging finite element model based on the material properties of the chip packaging data and the material differences of adjacent areas, and obtaining multiple sub-areas; adjusting the sub-areas based on the load conditions and load distribution characteristics of the chip packaging data, and obtaining multiple sub-tasks; After the preliminary division, the key nodes of stress concentration are refined in the division optimization of the geometric area; in the division optimization of the load conditions, the sub-areas are adjusted according to the characteristics of uneven load distribution.

9. An electronic device, characterized in that: The electronic device comprises: a memory, a processor, and a chip packaging finite element model analysis program stored in the memory and executable on the processor, wherein the chip packaging finite element model analysis program is configured to implement the chip packaging finite element model analysis method according to any one of claims 1 to 7.

Images