A global routing method for integrated circuits based on multi-level queues

Abstract

The present invention discloses a global routing method for integrated circuits based on multi-level queues, including: S10, line edge capacity reduction stage: using rectangular uniform wire density, estimating routing congestion, and reducing line edge capacity based on the number of pins; S20, multi-level queue routing stage, for networks that cannot be routed in the current routing mode, directly adding them to the next level queue to wait for routing; when there is no overflow or the last level queue completes routing, the multi-level queue routing ends; S30, based on the rewiring of the congested area, a maze routing strategy is adopted; S40, based on the rewiring result, a global routing result is output. The present invention reduces the capacity of the pin congestion area, uses multi-level queue routing to obtain the initial routing result, and then uses the maze routing based on the overflow distance to reduce the overflow.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an integrated circuit global wiring method based on multi-level queues. Background Art

[0002] Routing is a critical stage in the integrated circuit manufacturing process and is usually divided into global routing and detailed routing stages. This division is necessary due to the complexity of VLSI routing problems. Global routing is performed on a coarse three-dimensional grid graph, where each edge represents multiple wires or vias, and its capacity represents the resources available to the global router. Compared with global routing, detailed routing involves more complex design rules, larger design scale, and is more time-consuming. The two steps complement each other to complete the routing task in integrated circuit design. However, a good global routing result does not necessarily lead to a good detailed routing result.

[0003] Global routing can be divided into sequential global routing and concurrent global routing. In sequential global routing, the nets are routed in a specific order, such as sorting by half-perimeter wire length or number of pins. A major disadvantage of this sorting method is that it may not find the best routing solution because it cannot consider future routing requirements during the routing process. They rely on good net sorting and continuous tearing and rerouting of congested nets, which can be time-consuming and may cause some nets to miss the best routing strategy. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes an integrated circuit global routing method based on multi-level queues, which reduces the capacity of the pin congestion area, uses multi-level queue routing to obtain the initial routing results, and then uses maze routing based on overflow distance to reduce overflow.

[0005] To achieve the above object, the technical solution adopted by the present invention is: a global wiring method for integrated circuits based on multi-level queues, comprising the steps of:

[0006] S10, line edge capacity reduction phase: using rectangular uniform wire density, estimating routing congestion, and reducing line edge capacity based on the number of pins;

[0007] S20, multi-level queue routing stage, for networks that cannot be routed in the current routing mode, they are directly added to the next level queue to wait for routing; when there is no overflow or the last level queue completes routing, the multi-level queue routing ends;

[0008] S30, based on the rewiring of congested areas, a maze wiring strategy is adopted;

[0009] S40, outputting the global wiring result based on the rewiring result.

[0010] Furthermore, the rectangular uniform wire density is:

[0011] ;

[0012] Where, Wirelength(n) refers to the length of the half-perimeter of the network, bbox(n) refers to the bounding box of the network; x is the horizontal coordinate, y is the vertical coordinate, n is the network, and bboxarea(n) refers to the bounding box area of ​​network n;

[0013] For each coordinate (x, y), the RUDY accumulation method is used to calculate:

[0014] ;

[0015] N is the total number of networks; RUDY N (x,y) is the cumulative value of rectangular uniform wire density;

[0016] Based on the number of pins and the rectangular uniform wire density value, the capacity multiplier is calculated using the characteristic equation:

[0017] ;

[0018] Where Track(x,y) is the number of tracks at the coordinate, α(x,y) is the capacity multiplier; β and θ are parameters, set to 0.9 and 2 respectively;

[0019] However, since pins physically exist, the capacity is reduced based on the number of pins. The following equation is used to reduce the capacity:

[0020] ;

[0021] Where Cap(x,y) is the calculated capacity, PinNum(x,y) is the number of pins at the coordinate (x,y), and ω is a parameter set to 1.

[0022] Furthermore, multi-level queue routing solves the routing problem step by step, with each level trying to route the network using a different routing mode; if a level fails to successfully route a network, the network is pushed to the next level for further processing; eventually, all networks are routed.

[0023] Furthermore, in the multi-stage queue routing stage, the steps are included:

[0024] First stage queue routing: Process nets {A, B, C, D} in order. Use L-type routing in the first stage queue. Net A is successfully routed, but net B cannot be routed and is moved to the next stage queue for Z-type routing. Then, net C is routed and net D is moved to the next stage queue.

[0025] Second stage queue routing: Processing net {B, D} using Z-type routing, net B is successfully routed, but net D is moved to the last level queue for maze routing;

[0026] The third stage queue routing, consisting of network D, completes the maze routing of network D.

[0027] Furthermore, based on the rewiring of the congested area, a maze wiring strategy is adopted, including the steps of: performing maze wiring based on the multi-level queue wiring results; when there is no overflow or the final iteration is completed, the rewiring ends and the result is output.

[0028] Furthermore, based on the rewiring of the congested area, a maze wiring strategy is adopted, including the steps of:

[0029] In one iteration, the netlist is first enumerated, and the nets with overflow are retained. The pin positions and overflow areas of the overflowed nets are known, and adjacent overflowed G units are regarded as a single overflow area; each overflowed net has a pin set P={P1,P2,…}, where each element represents the G unit coordinates of the net connected to the pin, and an overflow area set O={O1,O2,…}, where each element represents an overflow area; each overflow area contains multiple consecutive overflow G units; the calculation of the overflow area and its pins is the following function:

[0030] ;

[0031] in, represents the Manhattan distance between two coordinates, is an element of the set O; the smallest value among them is retained, and if any pin is in the overflow region, the function will return 0;

[0032] Use the following sum function to evaluate the overall rewiring value of the overflow network:

[0033] ;

[0034] Sort the overflowed nets in descending order according to the required routing values ​​and process them in sequence;

[0035] Overflow check is performed for each net, and if overflow exists, tearing the net and rewiring is performed; this process continues until all nets in the current iteration are processed, with a total of 5 iterations.

[0036] The beneficial effects of adopting this technical solution are:

[0037] The present invention can generate higher quality global routing and detailed routing results. Routing congestion is reflected by rectangular uniform wire density, and then detailed routability is improved by capacity reduction. Better global routing results can be obtained by routing with multi-level queues. Maze routing based on overflow distance can directly alleviate congestion. This design makes global routing and detailed routing more efficient and coordinated.

[0038] The present invention adopts a unique network sorting method to increase routing quality, uses rectangular uniform wire density to reduce capacity to improve detailed routability, can effectively reduce detailed routing violations, and effectively reserve routable space for detailed routing in congested areas.

[0039] The present invention adopts a queue-based multi-level network sequential routing method to generate an initial routing solution. The algorithm can route more networks and obtain higher quality.

[0040] The present invention uses a sorting algorithm based on the proximity between the overflow area and the network pins in the tear rewiring stage to reduce global overflow; using the sorting algorithm of the overflow area, the global congestion is significantly reduced in the global routing stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic flow chart of a multi-level queue-based integrated circuit global routing method of the present invention;

[0042] Figure 2 This is a multi-level queue wiring diagram in an embodiment of the present invention, wherein: Figure 2 (a) is the queue wiring diagram of the first stage. Figure 2 (b) is the queue wiring diagram of the second stage. Figure 2 (c) in the figure is the queue wiring of the third stage. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described below with reference to the accompanying drawings.

[0044] In this embodiment, see Figure 1 As shown, the present invention proposes a global routing method for integrated circuits based on a multi-level queue, comprising the steps of:

[0045] S10, line edge capacity reduction phase: using rectangular uniform wire density, estimating routing congestion, and reducing line edge capacity based on the number of pins;

[0046] S20, multi-level queue routing stage, for networks that cannot be routed in the current routing mode, they are directly added to the next level queue to wait for routing; when there is no overflow or the last level queue completes routing, the multi-level queue routing ends;

[0047] S30, based on the rewiring of congested areas, a maze wiring strategy is adopted;

[0048] S40, outputting the global wiring result based on the rewiring result.

[0049] As an optimization scheme of the above embodiment, in the pre-routing stage, the rectangular uniform wire density can be used to predict the congested area. By calculating the rectangular uniform wire density, the routing congestion can be estimated. The congested area is more likely to cause design rule violations in the detailed routing. Reducing the capacity of the congested area reserves routing space for the detailed routing, thereby reducing the design rule violations.

[0050] The rectangular uniform wire density:

[0051] ;

[0052] Among them, Wirelength(n) refers to the half-circumference of the network, bbox(n) refers to the bounding box of the network; x is the horizontal coordinate and y is the vertical coordinate, which are used to describe the specific location of each endpoint in the network, n is a specific network, and bboxarea(n) refers to the bounding box area of ​​network n;

[0053] For each coordinate (x, y), the RUDY accumulation method is used to calculate:

[0054] ;

[0055] N is the total number of networks; RUDY N (x,y) is the cumulative value of rectangular uniform wire density;

[0056] Based on the number of pins and the rectangular uniform wire density value, the capacity multiplier is calculated using the characteristic equation:

[0057] ;

[0058] Where Track(x,y) is the number of tracks at the coordinate, α(x,y) is the capacity multiplier; β and θ are parameters, set to 0.9 and 2 respectively;

[0059] However, since pins physically exist, the capacity is reduced based on the number of pins. The following equation is used to reduce the capacity:

[0060] ;

[0061] Where Cap(x,y) is the calculated capacity, PinNum(x,y) is the number of pins at the coordinate (x,y), and ω is a parameter set to 1.

[0062] The present invention uses rectangular uniform wire density to predict congestion locations, and reduces line edge capacity through characteristic functions to enhance the routability of detailed wiring.

[0063] As an optimization solution of the above embodiment, unlike the traditional pattern wiring, the multi-level queue wiring process is not limited to a single wiring pattern (L-shaped or maze), and will not destroy any network during the wiring process. For the net that cannot be wired in the current wiring pattern, it is directly added to the next level queue to wait for wiring. When the last level queue completes the wiring, the multi-level queue wiring ends.

[0064] Multi-level queue routing solves the routing problem step by step, with each level attempting to route the net using a different routing pattern; if a level fails to route a net, the net is pushed to the next level for further processing; eventually, all nets are routed. Multi-level queue routing algorithms effectively handle complex circuit routing problems by balancing routing efficiency and effectiveness through step-by-step processing and different routing patterns.

[0065] Specifically, Figure 2 A multi-level queue routing method is presented, including the following steps:

[0066] First stage queue routing: Process nets {A, B, C, D} in order. L-type routing is used in the first stage queue. Net A is successfully routed, but net B cannot be routed and is moved to the next stage queue for Z-type routing. Then, net C is routed and net D is moved to the next stage queue. After completing the first stage queue routing, Figure 2 As shown in (a);

[0067] Second stage queue routing: Use Z-type routing to process network {B, D}. Network B is successfully routed, but network D is moved to the last level queue for maze routing. After completing the first stage queue routing, Figure 2 As shown in (b);

[0068] The third stage queue routing consists of network D and completes the maze routing of network D. Figure 2 As shown in (c), the routing is finalized without overflow, completing the netlist routing process.

[0069] The present invention balances the efficiency and effectiveness of routing through step-by-step processing and different routing modes based on a routing algorithm of a multi-stage queue.

[0070] The present invention gradually uses L-type wiring, Z-type wiring and maze wiring to complete the initial wiring task based on the multi-level queue wiring algorithm, thereby enhancing the quality of wiring.

[0071] As an optimization scheme of the above embodiment, after completing the multi-level queue routing, the congested areas and pin locations of the net with overflow can be known. Assuming that all pin locations are far away from the congested areas, there will be enough routing space to avoid these congested areas during rerouting. On the contrary, if the congested area is close to the pin, the rerouting may still encounter congestion because it must be connected to the pin, thereby passing through the congested area.

[0072] Based on the rewiring of the congested area, a maze wiring strategy is adopted, including the steps of: performing maze wiring based on the multi-level queue wiring results; when there is no overflow or the final iteration is completed, the rewiring ends and the result is output.

[0073] The specific steps include:

[0074] In one iteration, the netlist is first enumerated, and the nets with overflow are retained. The pin positions and overflow areas of the overflowed nets are known, and adjacent overflowed G units are regarded as a single overflow area; each overflowed net has a pin set P={P1,P2,…}, where each element represents the G unit coordinates of the net connected to the pin, and an overflow area set O={O1,O2,…}, where each element represents an overflow area; each overflow area contains multiple consecutive overflow G units; the calculation of the overflow area and its pins is the following function:

[0075] ;

[0076] in, represents the Manhattan distance between two coordinates, is an element of the set O; the smallest value among them is retained, and if any pin is in the overflow region, the function will return 0;

[0077] Use the following sum function to evaluate the overall rewiring value of the overflow network:

[0078] ;

[0079] Sort the overflowed nets in descending order according to the required routing values ​​and process them in sequence;

[0080] Overflow check is performed for each net, and if overflow exists, tearing the net and rewiring is performed; this process continues until all nets in the current iteration are processed, with a total of 5 iterations.

[0081] The present invention uses an algorithm based on overflow distance sorting network to make the wiring sequence closer to the actual congestion situation;

[0082] The invention aims to reduce congestion, reduce line length vias and increase global routing and detailed routing quality, and designs a global routing algorithm based on multi-level queue routing.

[0083] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention to be protected. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for global routing of integrated circuits based on multi-level queues, characterized in that: Includes steps: S10, line edge capacity reduction phase: using rectangular uniform wire density, estimating routing congestion, and reducing line edge capacity based on the number of pins; However, since pins physically exist, the capacity is reduced based on the number of pins. The following equation is used to reduce the capacity: ； Among them, Cap(x,y) is the calculated capacity, PinNum(x,y) is the number of pins at the coordinate (x,y); ω is a parameter, set to 1; Track(x,y) is the number of tracks at the coordinate; Based on the number of pins and the rectangular uniform wire density value, the capacity multiplier is calculated using the characteristic equation: ； Among them, α(x,y) is the capacity multiplier; β and θ are parameters, which are set to 0.9 and 2 respectively; RUDY N (x,y) is the cumulative value of rectangular uniform wire density; S20, multi-level queue routing stage, for networks that cannot be routed in the current routing mode, they are directly added to the next level queue to wait for routing; when there is no overflow or the last level queue completes routing, the multi-level queue routing ends; S30, based on the rewiring of the congested area, adopts a maze wiring strategy, including the steps of: In one iteration, the netlist is first enumerated, and the nets with overflow are retained. The pin positions and overflow areas of the overflowed nets are known, and adjacent overflow G units are regarded as a single overflow area; each overflowed net has a pin set P={P1,P2,…}, where each element represents the G unit coordinates of the net connected to the pin, and an overflow area set O={O1,O2,…}, where each element represents an overflow area; each overflow area contains multiple consecutive overflow G units; the calculation of the overflow area and its pins is the following function: ； in, represents the Manhattan distance between two coordinates, is an element of the set O; the smallest value among them is retained, and if any pin is in the overflow region, the function will return 0; Use the following sum function to evaluate the overall rewiring value of the overflow network: ； Sort the overflowed nets in descending order according to the required routing values ​​and process them in sequence; Overflow check is performed on each network, and if overflow exists, network tearing and rewiring are performed; this process continues until all networks in the current iteration are processed, with a total of 5 iterations; S40, outputting the global wiring result based on the rewiring result.

2. The integrated circuit global routing method based on multi-level queues according to claim 1, characterized in that: The rectangular uniform wire density: ； Among them, Wirelength(n) refers to the half-circumference of the network, bbox(n) refers to the bounding box of the network; x is the horizontal coordinate, y is the vertical coordinate, n refers to the network, and bboxarea(n) refers to the bounding box area of ​​network n; For each coordinate (x, y), the RUDY accumulation method is used to calculate: ； N is the total number of networks; RUDY N (x,y) is the cumulative value of the rectangular uniform wire density.

3. The integrated circuit global routing method based on multi-level queues according to claim 1, characterized in that: Multi-level queue routing solves the routing problem step by step, with each level attempting to route the net using a different routing pattern; if a level fails to successfully route a net, the net is pushed to the next level for further processing; eventually, all nets are routed.

4. The integrated circuit global routing method based on multi-level queues according to claim 3, characterized in that: In the multi-level queue routing stage, the steps are included: First stage queue routing: Process nets {A, B, C, D} in order using L-type routing in the first stage queue; net A is successfully routed, but net B cannot be routed and is moved to the next stage queue for Z-type routing; Then, network C is routed and network D is moved to the next stage queue; Second stage queue routing: Processing network {B, D} using Z-type routing, network B is successfully routed, but network D is moved to the last level queue for maze routing; The third stage queue routing, consisting of network D, completes the maze routing of network D.

5. The integrated circuit global routing method based on multi-level queues according to claim 1, characterized in that: Based on the rewiring of the congested area, a maze routing strategy is adopted, including the steps of: performing maze routing based on the multi-level queue routing results; When there is no overflow or the final iteration is completed, the rewiring ends and the result is output.

Images