Method for realizing chaotic state by using metastable state characteristic of hardware
By utilizing the metastable characteristics and counters in the hardware timing circuit, the trigger circuit of chaotic state is realized, solving the problem of the inability to reduce the hardware cost and power consumption of the artificial intelligence terminal, and achieving more flexible state jumps and smarter AI action.
Patent Information
- Application Number
- CN202411292281.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-02-18
AI Technical Summary
When the prior art supports artificial intelligence terminals to respond to environmental changes in a timely manner, it requires flexible state jumps based on random numbers, resulting in the inability to further reduce hardware costs and power consumption, limiting the expansion of artificial intelligence terminals.
By leveraging the metastable characteristics in the hardware timing circuit, a simple output of a single uncertain 0/1 state output is generated, and combined with a counter with adjustable total calculations, it is combined into a chaotic trigger circuit to replace the complex Random number generation circuit.
It realizes more flexible state machine state jumps on more intense hardware resources, and closes some features of infinite state machines, reducing hardware costs and power consumption, and supporting smarter AI actions.
Smart Images
Figure CN119476512A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electrical engineering technology, in particular to subfields related to integrated circuit design, microelectronics, embedded systems or computer hardware, and specifically to a method for realizing a chaotic state by utilizing the metastable characteristics of hardware. Background Art
[0002] With the implementation of artificial intelligence in user terminals, the contradiction between limited hardware resources and the flexible state jump required by artificial intelligence has become increasingly acute. At present, in order to support algorithms that can respond to changes in the user's environment in a timely manner, it is necessary to support flexible state jumps. At present, to achieve this function, it is necessary to generate random numbers, which means that more costs are required in hardware. Since the minimum demand for hardware resources cannot be lowered, the hardware cost and power consumption of the user end cannot be further reduced, which makes it difficult to roll out artificial intelligence terminals on a larger scale.
[0003] To this end, we provide a method for realizing a chaotic state by utilizing the metastable characteristics of hardware. The present invention utilizes the metastable characteristics that may occur in hardware sequential circuits to generate a simple output of a single uncertain 0 / 1 state. Counting is performed through a counter with an adjustable total calculation number, and the next state jump is determined based on the counting result. A metastable circuit and a counter are combined into a chaotic state trigger circuit to replace the complex random number generation circuit. Summary of the invention
[0004] The purpose of the present invention is to provide a method for realizing a chaotic state by utilizing the metastable characteristics of hardware, so as to solve the problems raised in the above background technology.
[0005] To achieve the above object, the present invention provides the following technical solution: a method for realizing a chaotic state by utilizing the metastable characteristics of hardware, comprising counting by a counter with an adjustable total calculation number, a metastable circuit and a counter, which are combined into a chaotic state trigger circuit, comprising the following steps: Step 1: Use the metastable characteristics that may occur in hardware sequential circuits to generate a simple single-shot uncertain 0 / 1 state output; Step 2: After entering the metastable state, the signal flipping from "logic 0" to "logic 1" will converge to "logic 1" with probability, and the signal flipping from "logic 1" to "logic 0" will converge to "logic 0" with probability, so that it will eventually realize a chaotic state trigger circuit; Step 3: Adjust the standard value and statistical variance of the normal distribution, wherein the standard value is achieved by fine-tuning the alignment of DATA and CLK, and the statistical variance is adjusted by adjusting the total calculation number of the counter in the chaotic state trigger circuit; Step 4: The chaotic state triggers each sub-state of the next jump, and each sub-state includes the entire set of actions that should be performed in the chaotic state; Step 5: All next jump states triggered by the same chaotic state should eventually jump back to a single collection state; Step 6: A counter connected to the output of the metastable circuit has an adjustable total calculation number. External sensor data enters the sensor data analysis module in the peripheral finite state machine, and sends a model validity judgment mark to the collection state in the chaotic state.
[0006] Preferably, in step 2, the specific method of realizing the trigger circuit of the chaotic state is to count the number of times the metastable circuit enters "logic 0" or obtains "logic 1" according to the time window. Since the number of times entering the metastable state is uncertain as the environment changes, it is mathematically chaotic, and thus a chaotic state trigger circuit is realized with extremely low hardware cost.
[0007] Preferably, the number of times the metastable circuit enters "logic 0" or "logic 1" is counted according to a time window, and the number of statistics obtained in the time window can be controlled with the collection state. Statistically, it is known that when the statistical samples decrease, low-probability samples are more likely to appear, and vice versa, low-probability samples are more difficult to appear. By utilizing this feature, the state machine can achieve autonomous switching based on model parameter correction and model architecture correction without the need for "man in the loop" model intervention correction.
[0008] Preferably, in step 4, when the chaotic state triggers the next jump to each diversity state, the weights in the state machine are consistent, and an infinite loop will not be caused because the input of the diversity A state must wait for the output of the diversity B state.
[0009] Preferably, in step 4, the initial model identifier and model parameters required for the diversity state are acquired from a peripheral finite state machine.
[0010] Preferably, in step five, the aggregated state serves as the only interface for the chaotic state to output to the state machine, and unifies the interaction model and parameter information to the peripheral finite state machine.
[0011] Preferably, in step six, when the aggregated state output is determined that the current result is not the optimal solution, the total number of calculations decreases, the statistical variance increases as the total number of calculations decreases, the counts corresponding to lower probabilities in the chaotic state are easier to achieve, and the corresponding algorithm model adjustment mechanism is easier to be activated, and the state machine tends to adjust the model architecture rather than the model parameters at this time; when the aggregated state output is determined that the current result is the optimal solution but the convergence is too slow, the total number of calculations increases, the statistical variance decreases as the total number of calculations increases, the counts corresponding to higher probabilities in the chaotic state are easier to achieve, and the corresponding algorithm parameter adjustment mechanism is easier to be activated, and the state machine tends to adjust the model parameters rather than the model architecture at this time.
[0012] Preferably, in step six, the peripheral finite state machine is responsible for the only external input and output interface, and the chaotic state is not directly connected to the external input and output.
[0013] The present invention provides a method for realizing a chaotic state by utilizing the metastable characteristics of hardware. It has the following beneficial effects: (1) The present invention refers to a state in which the output introduces a chaotic result rather than a single clear result as a chaotic state, and a state machine containing a chaotic state as a chaotic state machine. A chaotic state machine may contain more than one chaotic state. Compared with a conventional finite state machine, the state jump of a chaotic state machine is more flexible, can rely on more scarce hardware resources, and to a certain extent is closer to some characteristics of an infinite state machine.
[0014] (2) The present invention uses the metastable characteristics of hardware to form a trigger mechanism for a chaotic state; a counter whose count is adjustable according to the output result of the aggregated state, whose adjustment will reshape the tendency of the diversity state selection in the chaotic state; the chaotic state thus formed can be embedded in a conventional finite state machine, and the design of other modules of the state machine is still designed according to the requirements of the conventional finite state machine. Based on the above, a more flexible state machine state jump can be achieved on more scarce hardware resources to achieve a more intelligent AI action on the terminal side. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] Figure 1 A schematic diagram of the establishment time / maintenance time of the present invention; Figure 2 This is a schematic diagram of the metastable state of the present invention - a probability flip view of "logic 0" to "logic 1"; Figure 3 This is a schematic diagram of the chaotic state machine of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0017] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0018] A preferred embodiment of the method for realizing a chaotic state by utilizing the metastable characteristics of hardware provided by the present invention is as follows: Figure 1-3 As shown: A method for realizing a chaotic state by utilizing the metastable characteristics of hardware, including counting through a counter with an adjustable total calculation number, a metastable circuit and a counter, which are combined into a chaotic state trigger circuit, including the following steps: Step 1: Use the metastable characteristics that may appear in the hardware timing circuit to generate a simple output that can output a single uncertain 0 / 1 state; the data arrives after the clock of the hardware timing circuit arrives, and the time difference is called the setup time; the time difference between the data being maintained until the clock flips is called the hold time. Since both the clock and the data have phase jitter, even if the initial design makes the setup time just enough to ensure that the clock has made the hardware circuit state a normal receiving state before the data arrives, and the hold time just enough to ensure that the data level is maintained just long enough for the register to collect, there will still be a normal distribution with the phase jitter without any margin, so that there is a situation where the data does not meet the setup time or hold time requirements and leads to a metastable state.
[0019] Step 2: After entering the metastable state, the signal that flips from "logic 0" to "logic 1" will converge to "logic 1" with probability, and the signal that flips from "logic 1" to "logic 0" will converge to "logic 0" with probability, so that it finally realizes a chaotic state trigger circuit; the specific method of realizing the chaotic state trigger circuit is to count the number of times the metastable circuit enters "logic 0" and obtains "logic 1" according to the time window. Since the number of times it enters the metastable state is uncertain as the environment changes, it is mathematically chaotic. Therefore, a chaotic state trigger circuit is realized with extremely low hardware cost. The number of times the metastable circuit enters "logic 0" and obtains "logic 1" is counted according to the time window. The number of statistics obtained in the time window can be controlled with the aggregation state. It is statistically known that when the statistical samples decrease, low-probability samples are more likely to appear, and vice versa, low-probability samples are more difficult to appear. Using this feature, the state machine can realize autonomous switching based on model parameter correction and model architecture correction without the need for "man in the loop" model intervention correction.
[0020] Step 3: Adjust the standard value and statistical variance of the normal distribution. The standard value is achieved by fine-tuning the alignment of DATA and CLK, and the statistical variance is adjusted by adjusting the total number of calculations of the counter in the chaotic state trigger circuit. The working environment of the control system can adjust the standard value and statistical variance of the normal distribution, but it cannot change the chaotic characteristics of the number of times this circuit enters the metastable state.
[0021] Step 4: The chaotic state triggers each diversity state for the next jump. Each diversity state contains the entire set of actions that should be performed in the chaotic state. The weights in the state machine are consistent, and there will be no infinite loop because the input of the diversity state A must wait for the output of the diversity state B. The initial model identifier and model parameters required for the diversity state are obtained from the peripheral finite state machine.
[0022] Step 5: All next jump states triggered by the same chaotic state should eventually jump back to a single collection state; the collection state serves as the only interface for the chaotic state to output to the state machine, unifying the interaction model and parameter information to the peripheral finite state machine.
[0023] It is further obtained that the chaotic state trigger circuit, the complete action combination composed of each diversity state, and the single output aggregation state constitute a complete chaotic state. This chaotic state can be embedded into a conventional finite state machine as a component.
[0024] Step 6: A counter connected to the output of the metastable circuit has an adjustable total calculation number. External sensor data enters the sensor data analysis module in the peripheral finite state machine, and sends a model validity judgment mark to the collection state in the chaotic state. It is further obtained that: when the current result of the aggregated state output is determined to be not the optimal solution, the total number of calculations decreases, the corresponding counts with lower probability in the chaotic state are easier to achieve, and the corresponding algorithm model adjustment mechanism is easier to be activated. At this time, the state machine tends to adjust the model architecture rather than the model parameters; it is further obtained that: when the current result of the aggregated state output is determined to be not the optimal solution, the total number of calculations decreases, the statistical variance increases with the decrease in the total number of calculations, the corresponding counts with lower probability in the chaotic state are easier to achieve, and the corresponding algorithm model adjustment mechanism is easier to be activated. At this time, the state machine tends to adjust the model architecture rather than the model parameters; when the current result of the aggregated state output is determined to be the optimal solution but the convergence is too slow, the total number of calculations increases, the statistical variance decreases with the increase in the total number of calculations, the corresponding counts with higher probability in the chaotic state are easier to achieve, and the corresponding algorithm parameter adjustment mechanism is easier to be activated. At this time, the state machine tends to adjust the model parameters rather than the model architecture. It is further obtained that the peripheral finite state machine is responsible for the only external input and output interface, and the chaotic state is not directly connected to the external input and output to avoid the appearance of metastable states that are not required by the design, which affects the normal operation of the state machine.
[0025] In summary, when a system introduces chaotic results rather than a single clear result in output, this state is called a chaotic state. Correspondingly, a state machine that contains a chaotic state is called a chaotic state machine. It is worth noting that a chaotic state machine can contain more than one chaotic state. Compared with traditional finite state machines, chaotic state machines are more flexible in state jumps and can rely on tighter hardware resources to achieve this flexibility. To some extent, the state jump mode of chaotic state machines is closer to some characteristics of infinite state machines, and thus to some extent, it is closer to some characteristics of infinite state machines.
[0026] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for realizing a chaotic state by utilizing the metastable characteristics of hardware, comprising counting by a counter with an adjustable total number of calculations, a metastable circuit and a counter, which are combined into a chaotic state trigger circuit, characterized in that: The following steps are involved: Step 1: Use the metastable characteristics that may occur in hardware sequential circuits to generate a simple single-shot uncertain 0 / 1 state output; Step 2: After entering the metastable state, the signal that flips from "logic 0" to "logic 1" will converge to "logic 1" with probability, and the signal that flips from "logic 1" to "logic 0" will converge to "logic 0" with probability, so that it finally realizes a chaotic state trigger circuit; Step 3: Adjust the standard value and statistical variance of the normal distribution, wherein the standard value is achieved by fine-tuning the alignment of DATA and CLK, and the statistical variance is adjusted by adjusting the total calculation number of the counter in the chaotic state trigger circuit; Step 4: The chaotic state triggers each sub-state of the next jump, and each sub-state includes the entire set of actions that should be performed in the chaotic state; Step 5: All next jump states triggered by the same chaotic state should eventually jump back to a single collection state; Step 6: After declaring the statistical variance adjustment method, the counter output by the metastable circuit is connected, and its total calculation number is adjustable. The external sensor data enters the sensor data analysis module in the peripheral finite state machine, and sends the model validity judgment mark to the collection state in the chaotic state.
2. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In the step 2, the specific method of realizing the chaotic state trigger circuit is to count the number of times the metastable circuit enters "logic 0" or obtains "logic 1" according to the time window. Since the number of times entering the metastable state is uncertain with environmental changes, it is mathematically chaotic, and there is no need to use a complex circuit to generate random numbers. Therefore, a chaotic state trigger circuit is realized with extremely low hardware cost.
3. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 2, characterized in that: The number of times the metastable circuit enters "logic 0" and obtains "logic 1" is counted according to the time window. The number of statistics obtained in the time window can be controlled with the collection state. Statistically, when the statistical samples decrease, low-probability samples are more likely to appear, and vice versa. By using this feature, the state machine can achieve autonomous switching based on model parameter correction and model architecture correction without the need for "man in the loop" model intervention correction.
4. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In step 4, when the chaotic state triggers the next jump to each diversity state, the weights in the state machine are consistent, and an infinite loop will not be caused because the input of the diversity A state must wait for the output of the diversity B state.
5. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In the step 4, the initial model identifier and model parameters required for the diversity state are obtained from the peripheral finite state machine.
6. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In the step 5, the aggregated state serves as the only interface of the chaotic state to the state machine output, and unifies the interaction model and parameter information to the peripheral finite state machine.
7. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In the step six, when the aggregated state output is determined that the current result is not the optimal solution, the total number of calculations decreases, the statistical variance increases as the total number of calculations decreases, the counts corresponding to lower probabilities in the chaotic state are easier to achieve, and the corresponding algorithm model adjustment mechanism is easier to be activated, and the state machine is more inclined to adjust the model architecture rather than the model parameters at this time; when the aggregated state output is determined that the current result is the optimal solution but the convergence is too slow, the total number of calculations increases, the statistical variance decreases as the total number of calculations increases, the counts corresponding to higher probabilities in the chaotic state are easier to achieve, and the corresponding algorithm parameter adjustment mechanism is easier to be activated, and the state machine is more inclined to adjust the model parameters rather than the model architecture at this time.
8. The method for realizing a chaotic state by utilizing the hardware metastable characteristic according to claim 1, characterized in that: In step six, the peripheral finite state machine is responsible for the only external input and output interface, and the chaotic state is not directly connected to the external input and output.