Directed acyclic graph-based power source traceability graph generation method and system

Abstract

The invention discloses a directed acyclic graph-based power source traceability graph generation method and system, and the method comprises the steps: constructing a directed acyclic graph, taking a load node and power grid equipment as vertexes, taking a power supply line as an edge, and taking a power supply direction as a direction; hierarchies are divided according to the voltage levels of the vertexes and the connection relation between the vertexes, and the vertical coordinates of the vertexes of the same hierarchy are the same Segmenting the edge spanning the plurality of hierarchies into a plurality of edges spanning only adjacent hierarchies by inserting pseudo nodes; sequencing the vertexes of the same level, and reducing the crossing number of edges in the graph; determining abscissas of the vertexes after sorting; and according to the abscissa and the ordinate of the vertex, determining coordinates of the power grid equipment and the load node and a path of the power supply line, and completing generation of the power supply traceability diagram. The power source tracing result of the load node is abstracted into the directed acyclic graph, the situation that multiple power supply paths exist between the power source and the load node can be processed, the mapping effect is more accurate and visual, and the power supply logic relation between power grid equipment can be clearly reflected.

Description

Technical Field

[0001] The present invention relates to the generation of thematic power grid maps in an electric power system, and in particular to a method and system for generating a power supply tracing map based on a directed acyclic graph. Background Art

[0002] The power supply traceability diagram is a commonly used basic diagram in power grid operation and maintenance management. It has a wide range of application scenarios in businesses such as visualization of power outage information, auxiliary formulation of business expansion and registration plans, fault repair, and full life cycle management of power assets.

[0003] At present, there are very limited studies on the automatic generation of power supply traceability diagrams. There are two ways to draw power supply traceability diagrams in the prior art. One is to directly use the geographical coordinates of the device for drawing. This method can show the geographical location of the device, but it cannot intuitively show the logical relationship between the power supply between the devices. The other is to lay out the devices in layers according to the power supply relationship between the devices. However, the current layout method can only handle the situation where there is at most one path from any power source to the load node. In the actual operating power grid, especially between the power source above 500kV and the load node, there will be multiple power supply paths. The current layout method cannot correctly handle this situation. Summary of the invention

[0004] Purpose of the invention: In view of the above shortcomings, the present invention provides a method and system for generating a power traceability diagram based on a directed acyclic graph, which accurately, intuitively and clearly reflects the power supply logic relationship between devices.

[0005] Technical solution: To solve the above problems, the present invention adopts a method for generating a power traceability diagram based on a directed acyclic graph, comprising the following steps:

[0006] Constructing a directed acyclic graph, with load nodes and power grid equipment as vertices of the directed acyclic graph, with power supply lines as edges of the directed acyclic graph, with the edges of the directed acyclic graph connecting the vertices of the directed acyclic graph, and with the power supply direction of the power supply line as the direction of the directed acyclic graph; each of the vertices has a voltage level attribute;

[0007] According to the voltage level of the vertex and the connection relationship between the vertices, the vertices are divided into different levels, and the vertices of the same level have the same vertical coordinate;

[0008] Inserting a pseudo node in an edge that spans multiple levels to split it into a number of edges that span only adjacent levels; sorting the vertices of the same level after the pseudo node is inserted to reduce the number of intersections between edges in the directed acyclic graph, wherein the vertices of the same level after the pseudo node is inserted include the pseudo node; and determining the horizontal coordinates of the vertices after sorting;

[0009] According to the horizontal and vertical coordinates of the vertices, the coordinates of the power grid equipment and load nodes and the path of the power supply line are determined to complete the generation of the power supply traceability diagram.

[0010] Furthermore, the specific steps of dividing the vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices are as follows:

[0011] Delete the edges with different voltage levels at both ends of the directed acyclic graph to obtain independent subgraphs of each voltage level;

[0012] The vertices in the subgraph of each voltage level are divided into levels: the vertex with in-degree 0 is taken as the source vertex, and the level of the source vertex is set to 1. Starting from the source vertex, the graph is traversed in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex is increased by one. If the vertex levels obtained through different paths are different, the vertex level obtained through the longest path is taken; the level of any vertex v obtained is L′(v);

[0013] Update the hierarchy of vertices according to voltage levels: Arrange all voltage levels in order from low to high as V1, V2, ..., V n ; Voltage level V i The highest level of vertices in is C(V i ), 1≤i≤n; update the level of vertex v to Where V(v) is the order of the voltage level where vertex v is located;

[0014] Add the deleted edges back to the directed acyclic graph to obtain a hierarchically divided directed acyclic graph.

[0015] Furthermore, the specific steps of sorting the vertices of the same level after the pseudo nodes are inserted to reduce the number of intersections between edges in the directed acyclic graph include:

[0016] Forward traversal: start traversing from the second level of the directed acyclic graph and traverse to the last level of the directed acyclic graph, that is, the nth level; when traversing the i-th level, sort the vertices according to the centroid of the vertices. The centroid of the vertex of the i-th level is the average value of the order of several vertices of the i-1th level connected to it by edges in the i-1th level. After the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph;

[0017] Reverse traversal: start traversing from the n-1th level of the directed acyclic graph and traverse to the 1st level of the directed acyclic graph; when traversing the jth level, sort the vertices according to the centroid of the vertices, the centroid of the vertex of the jth level is the average value of the order of several vertices of the j+1th level connected to it by edges in the j+1th level, and after the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph;

[0018] After the forward traversal is completed, the reverse traversal is performed; the forward traversal and the reverse traversal are repeated until the number of intersections between the edges in the directed acyclic graph no longer decreases, and the sorting of the vertices of the directed acyclic graph is completed.

[0019] Furthermore, the specific steps of determining the horizontal coordinates of the vertices after sorting include:

[0020] When the inner edge and the outer edge intersect or have a common point in a directed acyclic graph, mark the outer edge; when the inner edge and the inner edge intersect or have a common point, or the outer edge and the outer edge intersect or have a common point in a directed acyclic graph, mark any one of the edges; the edge whose two end vertices are both pseudo nodes is the inner edge, and the other edges are the outer edges;

[0021] After ignoring the marked edges, the directed acyclic graph is subjected to the operations of top alignment-left compression, top alignment-right compression, bottom alignment-left compression, and bottom alignment-right compression, respectively, to obtain the four horizontal coordinates of the vertex, and the four horizontal coordinates of the vertex are sorted in order: the first horizontal coordinate, the second horizontal coordinate, the third horizontal coordinate, and the fourth horizontal coordinate, and the average of the second horizontal coordinate and the third horizontal coordinate is taken as the final horizontal coordinate of the vertex;

[0022] The specific steps of the top alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its upper neighbor. If there are multiple upper neighbors, the middle upper neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates.

[0023] The specific steps of the lower alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its lower neighbor. If there are multiple lower neighbors, the middle lower neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates.

[0024] The specific steps of the left compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, then add an edge from B(v) to B(u) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks B(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be -δ×L block(B), δ is the minimum distance between vertices in the same layer;

[0025] The specific steps of right compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, add an edge from B(u) to B(v) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks B(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be δ×L block (B), δ is the minimum distance between vertices in the same layer.

[0026] The present invention also adopts a power supply traceability diagram generation system based on a directed acyclic graph, comprising:

[0027] An initial graph construction module is used to construct a directed acyclic graph, with load nodes and power grid equipment as vertices of the directed acyclic graph, power supply lines as edges of the directed acyclic graph, the edges of the directed acyclic graph connecting the vertices of the directed acyclic graph, and the power supply direction of the power supply line as the direction of the directed acyclic graph; each of the vertices has a voltage level attribute;

[0028] A vertical coordinate determination module is used to divide vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices. Vertices at the same level have the same vertical coordinates.

[0029] The horizontal coordinate determination module is used to insert a pseudo node in the edge spanning multiple levels, and divide it into a number of edges spanning only adjacent levels; sort the vertices of the same level after the pseudo node is inserted, and reduce the number of intersections between edges in the directed acyclic graph, wherein the vertices of the same level after the pseudo node is inserted include the pseudo node; and determine the horizontal coordinate of the vertex after sorting;

[0030] The power supply tracing diagram generation module is used to determine the coordinates of the power grid equipment and load nodes and the path of the power supply line according to the horizontal and vertical coordinates of the vertices, and complete the generation of the power supply tracing diagram.

[0031] Furthermore, the specific steps of dividing the vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices are as follows:

[0032] Delete the edges with different voltage levels at both ends of the directed acyclic graph to obtain independent subgraphs of each voltage level;

[0033] The vertices in the subgraph of each voltage level are divided into levels: the vertex with in-degree 0 is taken as the source vertex, and the level of the source vertex is set to 1. Starting from the source vertex, the graph is traversed in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex is increased by one. If the vertex levels obtained through different paths are different, the vertex level obtained through the longest path is taken; the level of any vertex v obtained is L′(v);

[0034] Update the hierarchy of vertices according to voltage levels: Arrange all voltage levels in order from low to high as V1, V2, ..., V n ; Voltage level V i The highest level of vertices in is C(V i ), 1≤i≤n; update the level of vertex v to Where V(v) is the order of the voltage level where vertex v is located;

[0035] Add the deleted edges back to the directed acyclic graph to obtain a hierarchically divided directed acyclic graph.

[0036] Furthermore, the specific steps of sorting the vertices of the same level after the pseudo nodes are inserted to reduce the number of intersections between edges in the directed acyclic graph include:

[0037] Forward traversal: start traversing from the second level of the directed acyclic graph and traverse to the last level of the directed acyclic graph, that is, the nth level; when traversing the i-th level, sort the vertices according to the centroid of the vertices. The centroid of the vertex of the i-th level is the average value of the order of several vertices of the i-1th level connected to it by edges in the i-1th level. After the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph;

[0038] Reverse traversal: start traversing from the n-1th level of the directed acyclic graph and traverse to the 1st level of the directed acyclic graph; when traversing the jth level, sort the vertices according to the centroid of the vertices, the centroid of the vertex of the jth level is the average value of the order of several vertices of the j+1th level connected to it by edges in the j+1th level, and after the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph;

[0039] After the forward traversal is completed, the reverse traversal is performed; the forward traversal and the reverse traversal are repeated until the number of intersections between the edges in the directed acyclic graph no longer decreases, and the sorting of the vertices of the directed acyclic graph is completed.

[0040] Furthermore, the specific steps of determining the horizontal coordinates of the vertices after sorting include:

[0041] When the inner edge and the outer edge intersect or have a common point in a directed acyclic graph, mark the outer edge; when the inner edge and the inner edge intersect or have a common point, or the outer edge and the outer edge intersect or have a common point in a directed acyclic graph, mark any one of the edges; the edge whose two end vertices are both pseudo nodes is the inner edge, and the other edges are the outer edges;

[0042] After ignoring the marked edges, the directed acyclic graph is subjected to the operations of top alignment-left compression, top alignment-right compression, bottom alignment-left compression, and bottom alignment-right compression, respectively, to obtain the four horizontal coordinates of the vertex, and the four horizontal coordinates of the vertex are sorted in order: the first horizontal coordinate, the second horizontal coordinate, the third horizontal coordinate, and the fourth horizontal coordinate, and the average of the second horizontal coordinate and the third horizontal coordinate is taken as the final horizontal coordinate of the vertex;

[0043] The specific steps of the top alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its upper neighbor. If there are multiple upper neighbors, the middle upper neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates.

[0044] The specific steps of the lower alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its lower neighbor. If there are multiple lower neighbors, the middle lower neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates.

[0045] The specific steps of the left compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, then add an edge from B(v) to B(u) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above B(u) and B(v) are the blocks to which u and v belong, O(u) and O(v) are the order of u and v in the hierarchy; Use the longest path algorithm to calculate the length of graph G block Layering: Take the vertex with in-degree 0 as the source vertex, set the level of the source vertex to 1, and start from the source vertex. Traverse the graph in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex increases by one. If the levels of the vertices obtained through different paths are different, take the level of the vertex obtained through the longest path. The level of any block B obtained is L block (B); Let the horizontal coordinates of all vertices in block B be -δ×L block (B), δ is the minimum distance between vertices in the same layer;

[0046] The specific steps of right compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, then add an edge from B(u) to B(v) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above B(u) and B(v) are the blocks to which u and v belong, O(u) and O(v) are the order of u and v in the hierarchy; Use the longest path algorithm to calculate the length of graph G block Layering: Take the vertex with in-degree 0 as the source vertex, set the level of the source vertex to 1, and start from the source vertex. Traverse the graph in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex increases by one. If the levels of the vertices obtained through different paths are different, take the level of the vertex obtained through the longest path. The level of any block B obtained is L block (B); Let the horizontal coordinates of all vertices in block B be δ×L block (B), δ is the minimum distance between vertices in the same layer.

[0047] The present invention also adopts a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above method when executing the computer program.

[0048] The present invention also adopts a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the above method are implemented.

[0049] Beneficial effect: Compared with the prior art, the significant advantage of the present invention is that it abstracts the power tracing results of the load node into a directed acyclic graph. Compared with the method of abstracting the power tracing results into a tree, it can handle the situation where there are multiple power supply paths from the power source to the load node, and the power grid equipment is layered based on the power supply relationship and voltage level of the power grid equipment. The number of intersections is reduced by sorting the vertices, and the horizontal coordinates of the vertices are calculated by vertical alignment and horizontal compression, so that the drawing effect is more accurate and intuitive, and can clearly reflect the logical power supply relationship between the power grid equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a schematic diagram of the flow of the method for generating a power supply traceability diagram in the present invention.

[0051] Figure 2 It is a schematic diagram of the process of vertex level division in the present invention.

[0052] Figure 3 It is a schematic diagram of the principle of reducing the number of crossovers in the present invention.

[0053] Figure 4 It is a schematic diagram of the vertical alignment step in the present invention.

[0054] Figure 5 It is a schematic diagram of the horizontal left compression step in the present invention.

[0055] Figure 6 A schematic diagram of the effect of generating a power supply tracing diagram according to an embodiment of the present invention. DETAILED DESCRIPTION

[0056] Example 1

[0057] like Figure 1 As shown, in this embodiment, a power supply tracing diagram generation method based on a directed acyclic graph is provided. The power supply tracing result of the load node is input, and it is abstracted into a directed acyclic graph. The directed acyclic graph is laid out using a layout algorithm to generate a power supply tracing diagram for the power grid equipment. The following steps are included:

[0058] Step 1: Construct a directed acyclic graph:

[0059] The power supply traceability results of power grid equipment include load nodes, power grid equipment and power supply lines. The load nodes and power grid equipment are abstracted as vertices of a directed acyclic graph. The vertex objects contain information such as ID, name, and voltage level. The power supply line connects two different power grid equipment or load nodes. The power supply line has a power supply direction, which points from the source end to the end end. The source end device is said to be located upstream of its end device, and the end device is located downstream of its source end device. The power supply line is abstracted as an edge of a directed acyclic graph. The starting point of the edge is the vertex corresponding to the source end device of the power supply line, and the end point of the edge is the vertex corresponding to the end device of the power supply line. The power supply direction of the power supply line is abstracted as the direction of the directed acyclic graph. Starting from any power grid device, recursively traverse its downstream devices, and cannot traverse to itself. Load nodes and power grid equipment are accompanied by voltage level information. Devices with high voltage levels can supply power to devices with low voltage levels, but not vice versa.

[0060] Step 2: Divide into levels:

[0061] According to the connection relationship and voltage level between vertices in the directed acyclic graph, the vertices are divided into different levels, and the vertices at the same level are assigned the same vertical coordinate.

[0062] Delete the edges whose starting and ending voltage levels are different from the graph. If there is no edge with a vertex as the end point, that is, the in-degree of the vertex is 0, then this vertex is called the source vertex. Let the level of the source vertex be 1, starting from the source vertex, and traverse the graph in the direction of the edge. Each time a vertex is traversed, the level of the vertex increases by one. If the vertex levels obtained through different paths are different, take the vertex level obtained through the longest path. The level of any vertex v obtained here is recorded as L′(v). Arrange all the voltage levels of the vertices in the graph in order from low to high as V1, V2, ..., V n . In each voltage level, the highest level of the vertex is C (Vi ), 1≤i≤n. Update the level of vertex v to The vertex division is completed. Finally, the edges with different voltage levels between the starting and ending points that were deleted at the beginning are added back to the graph.

[0063] like Figure 2 As shown in the figure, the specific process of dividing the levels is as follows:

[0064] 1) Traverse the edges in the directed acyclic graph. If the voltage levels of the starting point and the end point are different, remove these edges from the directed acyclic graph;

[0065] 2) Create a vertex-to-initial-level mapping L′, a vertex-to-level mapping L, and initialize them to 1. Create a queue of vertices to be traversed Q;

[0066] 3) If there is no edge ending at a vertex, the level of the vertex is recorded as 1 and it is added to the queue Q;

[0067] 4) If the vertex queue Q is not empty, take the first vertex u from Q, otherwise end the traversal;

[0068] 5) Traverse all edges starting from u and obtain the end point set V of the edge;

[0069] 6) Traverse the set V, record the current traversal vertex as v, if the traversal is complete, return to step 4);

[0070] 7) If L′[v]≥L′[u]+1, return to step 6);

[0071] 8) Let L′[v]=L′[u]+1, add v to the queue Q, and return to step 6;

[0072] 9) After the traversal is completed, all the voltage levels of the vertices in the graph are arranged in order from low to high as V1, V2, ..., V n , in each voltage level, the highest level of the vertex is C (V i ), 1≤i≤n. Set the level of vertex v to

[0073] 10) Add the edges removed in step 1) back to the graph.

[0074] Step 3: Insert pseudo node:

[0075] Insert a pseudo node in the edge that spans multiple levels to split it into several edges that only span adjacent levels. Traverse all edges, for any edge (u, v), record L(v)-L(u)=n, if n>1, insert a pseudo node Split the edge (u, v) into several edges that only span one level

[0076] Step 4: Lower the crossover:

[0077] Sort vertices at the same level to reduce the number of crossovers in the graph.

[0078] Forward traversal: Let the number of layers of the graph be n, start traversing from the 2nd layer of the graph, and traverse to the nth layer of the graph. When traversing any level i, define the centroid of the vertices of the i-th layer as the average of the order of the vertices of the i-1th layer adjacent to it in the i-1th layer, and sort the vertices in the i-th layer according to the centroid. After completing the traversal, traverse in the reverse direction, starting from the n-1th layer of the graph and traversing to the 1st layer of the graph. When traversing any level j, define the centroid of the vertices of the j-th layer as the average of the order of the vertices of the j+1th layer adjacent to it in the j+1th layer, and sort the vertices in the j-th layer according to the centroid. Traverse back and forth in this way until the number of intersections between edges in the graph no longer decreases.

[0079] like Figure 3 As shown, subgraph (1) is a graph composed of layer A and layer B, and the number of intersections between the two layers is 10. Fix layer A, calculate the centroid of the nodes in layer B, and sort the nodes in layer B to obtain the result as subgraph (2), with a crossover number of 3. Conversely, fix layer B, calculate the centroid of the nodes in layer A, and sort the nodes in layer A to obtain the result as subgraph (3), with a crossover number of 1. Fix layer A again, calculate the centroid of the nodes in layer B, and sort the nodes in layer B to obtain the result as subgraph (4), with a crossover number of 0. At this time, the crossover number cannot be reduced, and the algorithm ends.

[0080] Step 5: Determine the horizontal axis:

[0081] Adjust the horizontal coordinate position of the vertices while ensuring the sorting, so that the layout effect is as balanced as possible.

[0082] Define the edges whose start and end points are both pseudo nodes as inner edges, and the rest as outer edges. If there are inner edges and outer edges crossing each other in the graph, mark the outer edge. If there are inner edges and inner edges crossing each other, or outer edges and outer edges crossing each other in the graph, mark any one of them. Ignore the marked edges in the subsequent alignment operations.

[0083] Then, the vertical alignment and horizontal compression steps are performed. There are four vertical alignment and horizontal compression methods, one of which is described below, and the other methods can be obtained by vertical symmetry and left-right symmetry.

[0084] In the vertical alignment step, determine the alignment relationship of vertices in the vertical direction. For any edge (u, v), u is called the lower neighbor of v, and v is called the upper neighbor of u. Align a vertex with its upper neighbor. If there are multiple upper neighbors, select the middle one. If two vertices are aligned, they are said to be in the same block. If a vertex is not aligned with any other vertex, it is in a separate block by itself. In this way, the graph is divided into several blocks, and all vertices in each block have the same abscissa. For each block, define its root node as the vertex with the lowest level in the block.

[0085] The specific implementation process is as follows:

[0086] 1) Create a root node mapping Root of vertices and an aligned vertex mapping Align of vertices. For each vertex v, initialize Root[v] = v and Align[v] = v;

[0087] 2) Denote the maximum level number as h. Traverse from the second level to the h-th level, and denote the traversed level number as i. In each traversal, execute step 3);

[0088] 3) Let r = 0. Traverse all vertices in the i-th level in the order obtained in the vertex sorting stage. Denote the traversed vertex as v. In each traversal, execute step 4;

[0089] 4) If v has several upper neighbors arranged in order as u1, u2,..., u n , and Align[v] = v, execute step 5;

[0090] 5) Let Denote the order of um in the vertex sorting stage as p. If r < p, execute step 6;

[0091] 6) Let Align[u m = v, Root[v] = Root[u m , Align[v] = Root[v], and r = p;

[0092] After completing the above process, the mapping Align forms several circular linked lists. All vertices in each circular linked list are vertically aligned and have the same abscissa. All vertices in each circular linked list are said to form a block. The vertex with the lowest level in each block is called the root node of the block, which is represented by the mapping Root.

[0093] For example Figure 4As shown, the solid points in the figure represent the initial vertices of the layout, and the hollow points represent pseudo nodes. In subgraph (1), the inner edge (b, c) and the outer edge (b, e) have common points, so the outer edge is marked and (b, e) is ignored in the following operations to ensure that the start and end points of the inner edge (b, c) are aligned. Set the alignment node of a to b, the alignment node of b to c, and the alignment node of c to d. If node e has several upper neighbors f, g, h, i, then set its alignment node to h, and obtain subgraph (2), where the solid lines represent edges in the linked list and the dotted lines represent edges not in the linked list. Then point the tail of the linked list back to the head, and set the alignment node of the node not in any linked list to itself. Obtain subgraph (3), each rectangle represents a block, the nodes are divided into 5 blocks, a, f, g, e, i are the root nodes of each block respectively, the nodes in the block have the same horizontal coordinates, and there is a fixed horizontal order between blocks.

[0094] In the horizontal compression step, determine the horizontal coordinates of the block, and make the interval between adjacent vertices as small as possible while maintaining the order between vertices and the minimum interval δ. The specific process is that for any two vertices u and v at the same level of the graph G, if O(v)-O(u)=1, then add an edge from B(v) to B(u) between blocks B(u) and B(v). If there is already an edge from B(v) to B(u), do not add it again, and get a directed acyclic graph G with blocks as vertices. block ; The above B(u) and B(v) are the blocks to which u and v belong, O(u) and O(v) are the order of u and v in the hierarchy; Use the longest path algorithm to calculate the length of graph G block Layering: Take the vertex with in-degree 0 as the source vertex, set the level of the source vertex to 1, and start from the source vertex. Traverse the graph in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex increases by one. If the levels of the vertices obtained through different paths are different, take the level of the vertex obtained through the longest path. The level of any block B obtained is L block (B); Let the horizontal coordinates of all vertices in block B be -δ×L block (B).

[0095] The specific implementation process is:

[0096] 1) Create graph G block The mapping End of the start point to the end point set of the middle edge; create a vertex-level mapping L block And initialize it to 1; create a vertex set Q to be traversed;

[0097] 2) Traverse all vertices of all levels in graph G in order. For adjacent vertices u and v at the same level, O(v)-O(u)=1, and add B(v) to the set End(B(u));

[0098] 3) If Figure Gblock If there is no edge ending at a certain vertex, the level of the vertex is recorded as 1 and it is added to the queue Q;

[0099] 4) If the queue Q is not empty, take the first vertex B(u) from Q, otherwise end the traversal;

[0100] 5) Traverse all edges starting from B(u) and obtain the end point set V of the edge;

[0101] 6) Traverse the set V, record the current traversal vertex as B(v), if the traversal is complete, return to step 4);

[0102] 7) If L block [B(v)]≥L block [B(u)]+1, return to step 6);

[0103] 8) Let L block [B(v)]=L block [B(u)]+1, and add B(v) to the queue Q, and return to step 6);

[0104] 9) Let the horizontal coordinate of any vertex v in graph G be -δ×L block (B(v))

[0105] like Figure 5 As shown in subgraph (1), there are 8 blocks in the graph, namely B1, B2, ... B8. By adding edges from right to left between adjacent vertices at the same level in the graph, we get a directed acyclic graph G consisting of blocks and newly added edges. block , use the longest path algorithm to block The layers are layered, and the vertices at the same level have the same horizontal coordinates. The result is shown in subgraph (2).

[0106] The above-mentioned vertical symmetry means that in the vertical alignment step, the vertices are aligned with their upper neighbors instead of their lower neighbors. The above-mentioned left-right symmetry means that in the horizontal compression step, the graph G is aligned with its lower neighbors instead of its upper neighbors. block The edge in the middle is changed from right to left to left to right. Through the vertical symmetry and left-right symmetry, four vertical alignment and horizontal compression methods can be obtained.

[0107] After executing the above four vertical alignment and horizontal compression methods respectively, each method will give the x coordinates of all vertices. For each vertex, sort the x coordinates given by the four layout methods, and record the sorted x coordinates as x1, x2, x3, and x4. Let the x coordinate of the vertex be Get the final layout result.

[0108] Step 6: Generate a power traceability diagram:

[0109] After completing the layout of the directed acyclic graph, the coordinates of the grid equipment and load nodes and the path of the line are determined according to the coordinates of the vertices in the graph and the corresponding relationship between the equipment and the vertices, and the power traceability diagram is automatically generated. Figure 6 An example of the effect generated for a power traceability diagram.

[0110] Example 2

[0111] In this embodiment, a power supply traceability diagram generation system based on a directed acyclic graph includes:

[0112] An initial graph construction module is used to construct a directed acyclic graph, with load nodes and power grid equipment as vertices of the directed acyclic graph, power supply lines as edges of the directed acyclic graph, the edges of the directed acyclic graph connecting the vertices of the directed acyclic graph, and the power supply direction of the power supply line as the direction of the directed acyclic graph; each of the vertices has a voltage level attribute;

[0113] A vertical coordinate determination module is used to divide vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices. Vertices at the same level have the same vertical coordinates.

[0114] The horizontal coordinate determination module is used to insert a pseudo node in the edge spanning multiple levels, and divide it into a number of edges spanning only adjacent levels; sort the vertices of the same level after the pseudo node is inserted, and reduce the number of intersections between edges in the directed acyclic graph, wherein the vertices of the same level after the pseudo node is inserted include the pseudo node; and determine the horizontal coordinate of the vertex after sorting;

[0115] The power supply tracing diagram generation module is used to determine the coordinates of the power grid equipment and load nodes and the path of the power supply line according to the horizontal and vertical coordinates of the vertices, and complete the generation of the power supply tracing diagram.

[0116] Example 3

[0117] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0118] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0119] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0120] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0121] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which all fall within the protection of the present invention.

Claims

1. A method for generating a power supply traceability diagram based on a directed acyclic graph, characterized in that: The following steps are involved: Constructing a directed acyclic graph, with load nodes and power grid equipment as vertices of the directed acyclic graph, with power supply lines as edges of the directed acyclic graph, with the edges of the directed acyclic graph connecting the vertices of the directed acyclic graph, and with the power supply direction of the power supply line as the direction of the directed acyclic graph; each of the vertices has a voltage level attribute; According to the voltage level of the vertex and the connection relationship between the vertices, the vertices are divided into different levels, and the vertices of the same level have the same vertical coordinate; Inserting a pseudo node in an edge that spans multiple levels to split it into a number of edges that span only adjacent levels; sorting the vertices of the same level after the pseudo node is inserted to reduce the number of intersections between edges in the directed acyclic graph, wherein the vertices of the same level after the pseudo node is inserted include the pseudo node; and determining the horizontal coordinates of the vertices after sorting; According to the horizontal and vertical coordinates of the vertices, the coordinates of the power grid equipment and load nodes and the path of the power supply line are determined to complete the generation of the power supply traceability diagram.

2. The method for generating a power supply traceability diagram according to claim 1, characterized in that: The specific steps of dividing the vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices are as follows: Delete the edges with different voltage levels at both ends of the directed acyclic graph to obtain independent subgraphs of each voltage level; Use the longest path algorithm to hierarchically divide the vertices in each voltage level subgraph: take the vertex with in-degree 0 as the source vertex, set the source vertex's level to 1, and start from the source vertex to traverse the graph in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the vertex's level increases by one. If the vertex levels obtained through different paths are different, take the vertex level obtained through the longest path. The level of any vertex v obtained is L′(v); Update the hierarchy of vertices according to voltage levels: Arrange all voltage levels in order from low to high as V1, V2, ..., V n ; Voltage level V i The highest level of vertices in is C(V i ),1≤i≤n; Update the level of vertex v to Where V(v) is the order of the voltage level where vertex v is located; Add the deleted edges back to the directed acyclic graph to obtain a hierarchically divided directed acyclic graph.

3. The method for generating a power supply traceability diagram according to claim 2, characterized in that: The specific steps of sorting the vertices of the same level after the pseudo nodes are inserted to reduce the number of intersections between edges in the directed acyclic graph include: Forward traversal: start traversing from the second level of the directed acyclic graph and traverse to the last level of the directed acyclic graph, that is, the nth level; when traversing the i-th level, sort the vertices according to the centroid of the vertices. The centroid of the vertex of the i-th level is the average value of the order of several vertices of the i-1th level connected to it by edges in the i-1th level. After the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph; Reverse traversal: start traversing from the n-1th level of the directed acyclic graph and traverse to the 1st level of the directed acyclic graph; when traversing the jth level, sort the vertices according to the centroid of the vertices, the centroid of the vertex of the jth level is the average value of the order of several vertices of the j+1th level connected to it by edges in the j+1th level, and after the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph; After the forward traversal is completed, the reverse traversal is performed; the forward traversal and the reverse traversal are repeated until the number of intersections between the edges in the directed acyclic graph no longer decreases, and the sorting of the vertices of the directed acyclic graph is completed.

4. The method for generating a power supply traceability diagram according to claim 1, characterized in that: The specific steps of determining the horizontal coordinates of the vertices after sorting include: When the inner edge and the outer edge intersect or have a common point in a directed acyclic graph, mark the outer edge; when the inner edge and the inner edge intersect or have a common point, or the outer edge and the outer edge intersect or have a common point in a directed acyclic graph, mark any one of the edges; the edge whose two end vertices are both pseudo nodes is the inner edge, and the other edges are the outer edges; After ignoring the marked edges, the directed acyclic graph is subjected to the operations of top alignment-left compression, top alignment-right compression, bottom alignment-left compression, and bottom alignment-right compression, respectively, to obtain the four horizontal coordinates of the vertex, and the four horizontal coordinates of the vertex are sorted in order: the first horizontal coordinate, the second horizontal coordinate, the third horizontal coordinate, and the fourth horizontal coordinate, and the average of the second horizontal coordinate and the third horizontal coordinate is taken as the final horizontal coordinate of the vertex; The specific steps of the top alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its upper neighbor. If there are multiple upper neighbors, the middle upper neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates. The specific steps of the lower alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its lower neighbor. If there are multiple lower neighbors, the middle lower neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates. The specific steps of the left compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, then add an edge from B(v) to B(u) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks V(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be -δ×L block (B), δ is the minimum distance between vertices in the same layer; The specific steps of right compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, add an edge from B(u) to B(v) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks B(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be δ×L block (B), δ is the minimum distance between vertices in the same layer.

5. A power traceability diagram generation system based on directed acyclic graph, characterized in that: include: An initial graph construction module is used to construct a directed acyclic graph, with load nodes and power grid equipment as vertices of the directed acyclic graph, power supply lines as edges of the directed acyclic graph, the edges of the directed acyclic graph connecting the vertices of the directed acyclic graph, and the power supply direction of the power supply line as the direction of the directed acyclic graph; each of the vertices has a voltage level attribute; A vertical coordinate determination module is used to divide vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices. Vertices at the same level have the same vertical coordinates. The horizontal coordinate determination module is used to insert a pseudo node in the edge spanning multiple levels, and divide it into a number of edges spanning only adjacent levels; sort the vertices of the same level after the pseudo node is inserted, and reduce the number of intersections between edges in the directed acyclic graph, wherein the vertices of the same level after the pseudo node is inserted include the pseudo node; and determine the horizontal coordinate of the vertex after sorting; The power supply tracing diagram generation module is used to determine the coordinates of the power grid equipment and load nodes and the path of the power supply line according to the horizontal and vertical coordinates of the vertices, and complete the generation of the power supply tracing diagram.

6. The power supply traceability diagram generation system according to claim 5, characterized in that: The specific steps of dividing the vertices into different levels according to the voltage levels of the vertices and the connection relationships between the vertices are as follows: Delete the edges with different voltage levels at both ends of the directed acyclic graph to obtain independent subgraphs of each voltage level; The vertices in the subgraph of each voltage level are divided into levels: the vertex with in-degree 0 is taken as the source vertex, and the level of the source vertex is set to 1. Starting from the source vertex, the graph is traversed in the direction of the edge in the directed acyclic graph. Each time a vertex is traversed, the level of the vertex is increased by one. If the vertex levels obtained through different paths are different, the vertex level obtained through the longest path is taken. The level of any vertex v obtained is L′(v); Update the hierarchy of vertices according to voltage levels: Arrange all voltage levels in order from low to high as V1, V2, ..., V n ; Voltage level V i The highest level of vertices in is C(V i ),1≤i≤n; Update the level of vertex v to Where V(v) is the sequence number of the voltage level where the vertex v is located; Add the deleted edges back to the directed acyclic graph to obtain a hierarchically divided directed acyclic graph.

7. The power supply traceability diagram generation system according to claim 5, characterized in that: The specific steps of sorting the vertices of the same level after the pseudo nodes are inserted to reduce the number of intersections between edges in the directed acyclic graph include: Forward traversal: start traversing from the second level of the directed acyclic graph and traverse to the last level of the directed acyclic graph, that is, the nth level; when traversing the i-th level, sort the vertices according to the centroid of the vertices. The centroid of the vertex of the i-th level is the average value of the order of several vertices of the i-1th level connected to it by edges in the i-1th level. After the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph; Reverse traversal: start traversing from the n-1th level of the directed acyclic graph and traverse to the 1st level of the directed acyclic graph; when traversing the jth level, sort the vertices according to the centroid of the vertices, the centroid of the vertex of the jth level is the average value of the order of several vertices of the j+1th level connected to it by edges in the j+1th level, and after the traversal is completed, calculate the number of intersections between the edges in the directed acyclic graph; After the forward traversal is completed, the reverse traversal is performed; the forward traversal and the reverse traversal are repeated until the number of intersections between the edges in the directed acyclic graph no longer decreases, and the sorting of the vertices of the directed acyclic graph is completed.

8. The power supply traceability diagram generation system according to claim 5, characterized in that: The specific steps of determining the horizontal coordinates of the vertices after sorting include: When the inner edge and the outer edge intersect or have a common point in a directed acyclic graph, mark the outer edge; when the inner edge and the inner edge intersect or have a common point, or the outer edge and the outer edge intersect or have a common point in a directed acyclic graph, mark any one of the edges; the edge whose two end vertices are both pseudo nodes is the inner edge, and the other edges are the outer edges; After ignoring the marked edges, the directed acyclic graph is subjected to the operations of top alignment-left compression, top alignment-right compression, bottom alignment-left compression, and bottom alignment-right compression, respectively, to obtain the four horizontal coordinates of the vertex, and the four horizontal coordinates of the vertex are sorted in order: the first horizontal coordinate, the second horizontal coordinate, the third horizontal coordinate, and the fourth horizontal coordinate, and the average of the second horizontal coordinate and the third horizontal coordinate is taken as the final horizontal coordinate of the vertex; The specific steps of the top alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its upper neighbor. If there are multiple upper neighbors, the middle upper neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates. The specific steps of the lower alignment operation are as follows: for any edge (u, v), vertex u is called the lower neighbor of vertex v, and vertex v is the upper neighbor of vertex u. The vertex is aligned with its lower neighbor. If there are multiple lower neighbors, the middle lower neighbor is selected. The aligned vertices are in the same block. If the vertex is not aligned with any other vertices, it is located in a separate block, and the vertices in each block have the same horizontal coordinates. The specific steps of the left compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, then add an edge from B(v) to B(u) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks B(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be -δ×L block (B), δ is the minimum distance between vertices in the same layer; The specific steps of right compression are: for any two vertices u and v at the same level, if O(v)-O(u)=1, add an edge from B(u) to B(v) between blocks B(u) and B(v), and obtain a directed acyclic graph G with blocks as vertices block ; The above blocks B(u) and B(v) are the blocks to which vertices u and v belong respectively, O(u) and O(v) are the order of vertices u and v in the hierarchy respectively; Use the longest path algorithm to calculate the directed acyclic graph G block The level of any block B is L. block (B); Let the horizontal coordinates of all vertices in block B be δ×L block (B), δ is the minimum distance between vertices in the same layer.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 4 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 4 are implemented.

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