Memory and operating method thereof

Abstract

The present disclosure discloses a memory and an operating method thereof. The memory includes: a plurality of memory cells and a delay circuit coupled to the plurality of memory cells; the plurality of memory cells includes a first memory cell in a first storage state and a second memory cell in a second storage state, wherein the threshold voltage corresponding to the second storage state is greater than the threshold voltage corresponding to the first storage state; the delay circuit is configured to: delay a read voltage pulse applied to the first memory cell so that the threshold voltage corresponding to the first storage state increases; and delay a read voltage pulse applied to the second memory cell so that the threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of memory technology, and relate to, but are not limited to, a memory and an operating method thereof. Background Art

[0002] Memories are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, and digital displays. This information is typically stored by programming different states of the memory. The rapid development of artificial intelligence (AI) is placing higher demands on the computing performance, read and write performance, reliability, and data retention capabilities of electronic devices, such as dynamic random access memory (DRAM) and non-volatile memory.

[0003] Compared with three-dimensional phase-change memory (3D XPoint), selector-only memory (SOM) has the advantages of simple structure, high scalability, fast data read and write speed, good cycle life, vertical stacking, and low risk of write crosstalk caused by thermal effects. It is a very promising non-volatile memory with obvious advantages and good application prospects in fields such as high-speed interconnect technology (Compute Express Link, CXL) and high-bandwidth memory (HBM). Summary of the Invention

[0004] According to a first aspect of an embodiment of the present disclosure, a memory is provided, comprising: a plurality of memory cells and a delay circuit coupling the plurality of memory cells; the plurality of memory cells comprise a first memory cell in a first storage state and a second memory cell in a second storage state, a threshold voltage corresponding to the second storage state being greater than a threshold voltage corresponding to the first storage state; the delay circuit is configured to: delay a read voltage pulse applied to the first memory cell so that the threshold voltage corresponding to the first storage state increases; and delay a read voltage pulse applied to the second memory cell so that the threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

[0005] In some embodiments, the memory cell includes a first electrode, a memory layer, and a second electrode stacked in sequence; the memory further includes:

[0006] a first conductive line, the first conductive line being located on a side of the first electrode relatively far from the storage layer and extending along a first direction, the first direction being perpendicular to the stacking direction;

[0007] a second conductive line, the second conductive line being located on a side of the second electrode relatively far from the storage layer and extending along a second direction, the second direction being perpendicular to the stacking direction and intersecting the first direction;

[0008] The delay circuit is coupled to the first conductive line or the second conductive line.

[0009] In some embodiments, the memory further includes a write driver; the write driver is configured to apply a write current pulse to the first conductive line or a write voltage pulse to the second conductive line when the delay circuit is coupled to the first conductive line.

[0010] In some embodiments, the memory further includes a write driver; the write driver is configured to apply a write current pulse to the second conductive line or a write voltage pulse to the first conductive line when the delay circuit is coupled to the second conductive line.

[0011] In some embodiments, the duration of the write current pulse or the write voltage pulse is 1 nanosecond to 1000 nanoseconds.

[0012] In some embodiments, the delay circuit includes at least one of a resistor and a capacitor.

[0013] In some embodiments, the resistance of the resistor ranges from 0.1 kilo-ohms to 20 kilo-ohms.

[0014] In some embodiments, the duration of the read voltage pulse is 1 nanosecond to 1000 nanoseconds.

[0015] According to a second aspect of an embodiment of the present disclosure, a method for operating a memory is provided, wherein the method is used to read the voltage of the memory according to any embodiment of the first aspect; the method comprising:

[0016] delaying a read voltage pulse applied to the first memory cell by a delay circuit of the memory so that a threshold voltage corresponding to the first storage state increases;

[0017] The read voltage pulse applied to the second storage unit is delayed by the delay circuit of the memory so that the threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

[0018] In some embodiments, the operating method further comprises: applying a write current pulse and the read voltage pulse to one of the first conductive line and the second conductive line; or,

[0019] A write voltage pulse is applied to one of the first conductive line and the second conductive line, and the read voltage pulse is applied to the other of the first conductive line and the second conductive line; wherein the first conductive line and the second conductive line are respectively located on opposite sides of the memory cell.

[0020] In the memory provided by the embodiment of the present disclosure, by providing a delay circuit coupled to multiple memory cells, the delay circuit can delay the read voltage pulse applied to the first memory cell and the read voltage pulse applied to the second memory cell, respectively, so that the threshold voltage corresponding to the first storage state and the threshold voltage corresponding to the second storage state are both increased, and the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state. In this way, on the one hand, the difference between the threshold voltages of the second memory cell in the second storage state and the first memory cell in the first storage state can be increased, thereby increasing the read and write window; on the other hand, since the read and write window between memory cells in different storage states is increased, the impact of threshold voltage drift and temperature on the read and write window can be reduced; on the other hand, the differences between different devices can also cause the read and write window to be reduced, and increasing the read and write window can reduce the impact of differences between devices on the read and write window. Here, the above three aspects can all improve the accuracy of reading and writing and the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0022] Figure 1 Schematic diagram of a memory provided by the first embodiment of the present disclosure.

[0023] Figure 2 FIG. 1 is a schematic diagram of applying a voltage pulse to a memory according to the first embodiment of the present disclosure.

[0024] Figure 3 Schematic diagram of the threshold voltages of memory cells in two storage states provided by the first embodiment of the present disclosure.

[0025] Figure 4 Schematic diagram of current for reading memory cells in two storage states according to the first embodiment of the present disclosure.

[0026] Figure 5 This is a schematic diagram of changes in threshold voltage and read / write window provided by the first embodiment of the present disclosure.

[0027] Figure 6 2 is a schematic diagram of a memory provided by the second embodiment of the present disclosure.

[0028] Figure 7 2 is a schematic diagram of performing write and read operations according to the first embodiment of the present disclosure.

[0029] Figure 8 2 is a schematic diagram of performing write and read operations according to the second embodiment of the present disclosure.

[0030] Figure 9 3 is a schematic diagram of performing write and read operations according to the third embodiment of the present disclosure.

[0031] Figure 10 2 is a schematic diagram of performing write and read operations according to the fourth embodiment of the present disclosure.

[0032] Figure 11 1 is a schematic diagram of changes in the threshold voltage and threshold voltage difference of memory cells in two storage states when no series resistor is connected, according to an embodiment of the present disclosure.

[0033] Figure 12 1 is a schematic diagram of changes in the threshold voltage and threshold voltage difference of memory cells in two storage states when a series resistor is connected according to an embodiment of the present disclosure.

[0034] Figure 13 This is a flowchart of a memory operation method provided by an embodiment of the present disclosure.

[0035] Figure 14 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] To facilitate understanding of the present disclosure, exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0037] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of an actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0038] Generally, terms can be understood, at least in part, from their use in context. For example, depending, at least in part, on the context, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "the" can likewise be understood to convey singular usage or to convey plural usage, depending, at least in part, on the context. Additionally, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending, at least in part, on the context.

[0039] Unless otherwise defined, the purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0040] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0041] Figure 1 1 is a schematic diagram of a memory provided in the first embodiment of the present disclosure. The memory includes but is not limited to SOM. For ease of understanding, the memory is described below as SOM.

[0042] Reference Figure 1 As shown, the memory 100 includes a first conductive line 110, a memory cell 120, and a second conductive line 130. The memory cell 120 includes a first electrode 121, a memory layer 122, and a second electrode 123. The first conductive line 110 is located on a side of the first electrode 121 relatively far from the memory layer 122, and the second conductive line 130 is located on a side of the second electrode 123 relatively far from the memory layer 122. The first conductive line 110 can be one of a word line and a bit line, and the second conductive line 130 can be the other of the word line and the bit line. It will be understood that the SOM memory can adopt a three-dimensional stacked structure similar to a three-dimensional phase change memory.

[0043] The storage layer 122 has both storage and switching functions, that is, the material of the storage layer 122 is a dual-function material (DFM). Exemplarily, the material of the storage layer 122 may include any appropriate ovonic threshold switch (OTS) material. The OTS material may include a chalcogenide alloy such as germanium (Ge), arsenic (As), selenium (Se), tellurium (Te), and their compounds. The materials of the first electrode 121 and the second electrode 123 include conductive materials such as copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C), their compounds, and doped semiconductors. The materials of the first electrode 121 and the second electrode 123 may be the same or different.

[0044] The memory may include a plurality of memory cells, each of which may be written to a first memory state (eg, a SET state storing a bit “1”) or a second memory state (eg, a RESET state storing a bit “0”). Figure 2 Schematic diagram of applying voltage pulses to a memory according to the first embodiment of the present disclosure. Figure 2 As shown in the figure, a forward voltage pulse P1 is applied to the selected memory cell to make the elements in the OTS material achieve forward migration or positive polarization, thereby storing a bit "1". This process is a SET operation; a reverse voltage pulse P2 (also called a negative pulse) is applied to the selected memory cell to make the elements in the OTS material achieve reverse migration or reverse polarization, thereby storing a bit "0". This process is a RESET operation.

[0045] Figure 3 is a schematic diagram of the threshold voltages of memory cells in two storage states provided by the first embodiment of the present disclosure, Figure 3 State1 and State2 represent the SET state and RESET state respectively. Figure 3 As shown, the memory cell in the SET state has a first threshold voltage V th1 , the memory cell in the RESET state has a second threshold voltage V th2 By applying a voltage pulse between the SET state and RESET state threshold transition voltage to the memory cell (i.e., a read voltage pulse V read ), the resistance value of the OTS material in the memory cell in two states can be measured to obtain data. Here, V read Can be between V th1 and V th2 It is used to distinguish the two storage states of the storage unit.

[0046] Figure 4 is a schematic diagram of currents for reading memory cells in two storage states provided by the first embodiment of the present disclosure, Figure 4 State1 and State2 represent the SET state and RESET state respectively. The SET state is a low impedance state and the RESET state is a high impedance state. Figure 4 As shown, the current of the sensing device is read. If the current is low, the memory cell is in the RESET state; if the current is high, the memory cell is in the SET state. Figure 4 The read voltage pulse V read It is 3.5V. However, in practical applications, the read voltage pulse is not limited to this and can be reasonably selected according to the threshold voltage of different storage states.

[0047] It should be noted that the OTS material is used as the storage medium of the SOM device, so that the threshold voltage difference between the two storage states is about 1V. Figure 3 As shown, the first threshold voltage V th1 and the second threshold voltage V th2 The voltage difference between the two storage states (i.e., the memory window, MW) is about 1.2V. In other words, the voltage difference between the two storage states determines the size of the read-write window (Read-Write Margin, RWM) of the SOM device. If the threshold voltage difference between the two storage states is small, it will affect the read-write window of the SOM device. In addition, the read-write window of the SOM device is also affected by factors such as time, temperature, and differences between different devices. Figure 5 An exemplary description is given.

[0048] Figure 5 : is a schematic diagram of a change in threshold voltage and read / write window provided by the first embodiment of the present disclosure, wherein: Figure 5 Figure (a) is a schematic diagram of the threshold voltage drift of the memory cell in two storage states. Figure 5 Figure (b) is a schematic diagram of the threshold voltage drift of the memory cell in two storage states at 25°C. Figure 5 Figure (c) is a schematic diagram of the threshold voltage difference of the memory cell in two storage states at 25°C. Figure 5 Figure (d) is a schematic diagram of the threshold voltage drift of the memory cell in two storage states at 125°C. Figure 5 Figure (e) is a schematic diagram of the threshold voltage difference of a memory cell in two storage states at 125°C.

[0049] OTS materials have drift phenomena, which causes the threshold voltage of the memory cell to change over time. Figure 5As shown in Figures (a), (b), and (d), the threshold voltage of the memory cell increases with the relaxation time, causing the read and write window of the SOM device to further decrease. In severe cases, it may be impossible to distinguish between the RESET state and the SET state, resulting in an inability to read correctly.

[0050] In addition, the temperature increase of the SOM device will further aggravate the drift, resulting in a further reduction in the read and write window of the SOM device, such as Figure 5 As shown in Figures (b) to (e) of the , the threshold voltage difference between the two storage states of the memory cell decreases as the temperature increases. Furthermore, considering the possible differences between different SOM devices, it is necessary to further restrict the read and write window to meet the read and write operations of different SOM devices.

[0051] Based on one or more of the above-mentioned technical problems, embodiments of the present disclosure provide a memory. The memory includes a plurality of memory cells and a delay circuit coupled to the plurality of memory cells. The plurality of memory cells include a first memory cell in a first storage state and a second memory cell in a second storage state, wherein the threshold voltage corresponding to the second storage state is greater than the threshold voltage corresponding to the first storage state. The delay circuit is configured to: delay a read voltage pulse applied to the first memory cell so as to increase the threshold voltage corresponding to the first storage state; and delay a read voltage pulse applied to the second memory cell so as to increase the threshold voltage corresponding to the second storage state; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state. Thus, firstly, the difference between the threshold voltages of the second memory cell in the second storage state and the first memory cell in the first storage state can be increased, thereby increasing the read / write window. Secondly, due to the increased read / write window between memory cells in different storage states, the effects of threshold voltage drift and temperature on the read / write window can be reduced. Thirdly, the effects of device-to-device variations on the read / write window can be reduced. All three of these aspects can improve read / write accuracy and device reliability.

[0052] It should be noted that the first storage unit and the second storage unit in the embodiments of the present disclosure and below are merely for the purpose of distinguishing between storage units in two different storage states and do not constitute a limitation of the present disclosure. It should be understood that in other embodiments, a storage unit in the first storage state can be erased and written to the second storage state, in which case the storage unit is recorded as the second storage unit; and a storage unit in the second storage state can be erased and written to the first storage state, in which case the storage unit is recorded as the first storage unit. In other words, any one of the multiple storage units can be written to either the first storage state or the second storage state.

[0053] Figure 6This is a schematic diagram of a memory provided in the second embodiment of the present disclosure. The memory includes but is not limited to an SOM memory. For ease of understanding, the present disclosure will use the SOM memory as an example for illustrative description.

[0054] Reference Figure 6 As shown, the memory 200 includes a plurality of memory cells 220, each memory cell 220 includes a first electrode 221, a memory layer 222, and a second electrode 223 stacked in sequence, the first electrode 221 is coupled to the first conductive line 210, and the second electrode 223 is coupled to the second conductive line 230. For ease of understanding, Figure 6 Two storage units 220 are shown in FIG. , and in actual applications, the number of storage units 220 may be more than two.

[0055] The material of the storage layer 222 may include any appropriate OTS material. The OTS material may include a chalcogenide alloy, for example, germanium (Ge), arsenic (As), selenium (Se), tellurium (Te), and compounds thereof.

[0056] The materials of the first electrode 221 and the second electrode 223 include conductive materials, such as copper (Cu), aluminum (Al), gold (Au), tungsten (W), carbon (C) and their compounds, doped semiconductors, etc. The materials of the first electrode 221 and the second electrode 223 can be the same or different.

[0057] In some embodiments, the memory cell 220 further includes a first adhesion layer 224 located between the first electrode 221 and the memory layer 222, and / or a second adhesion layer 225 located between the second electrode 223 and the memory layer 222. The first adhesion layer 224 is used to increase the adhesion between the first electrode 221 and the memory layer 222, and the second adhesion layer 225 is used to increase the adhesion between the second electrode 223 and the memory layer 222. This can reduce or prevent film shedding in the memory cell, improve the yield and reliability of the memory, and control the internal resistance to regulate overshoot current within the device.

[0058] The materials of the first adhesion layer 224 and the second adhesion layer 225 include metal nitrides, for example, at least one of tungsten nitride, tantalum nitride, and titanium nitride. The materials of the first adhesion layer 224 and the second adhesion layer 225 can be the same or different. Figure 6 The first adhesive layer and the second adhesive layer are shown in FIG. 3 , but in other embodiments, the first adhesive layer or the second adhesive layer may be omitted.

[0059] It should be noted that multiple memory cells 220 can form a memory cell array, and each memory cell 220 can be located at the intersection of a first conductive line 210 extending along a first direction and a second conductive line 230 extending along a second direction. Therefore, the memory cell array is also called a cross-point array. By activating (or selecting) a first conductive line and activating (or selecting) a second conductive line, a corresponding logical operation can be performed on the selected memory cell located at the intersection of the selected first conductive line and the selected second conductive line. The logical operation includes a read operation, a write operation, an erase operation, etc.

[0060] The memory 200 may include a plurality of first conductive lines 210 arranged along the second direction and a plurality of second conductive lines 230 arranged along the first direction. Each first conductive line 210 extends along the first direction and is coupled to a plurality of memory cells 220 arranged along the first direction. Each second conductive line 230 extends along the second direction and is coupled to a plurality of memory cells 220 arranged along the second direction. The first conductive lines 210 and the second conductive lines 230 may be located on opposite sides of the memory cells 220, such as Figure 6 As shown, the first conductive line 210 is located on a side of the first electrode 221 relatively far away from the storage layer 222 , and the second conductive line 230 is located on a side of the second electrode 223 relatively far away from the storage layer 222 .

[0061] It should be noted that the first direction, the second direction, and the stacking direction used in the present disclosure are represented as the x direction, the y direction, and the z direction, respectively, in the drawings, and the x direction and the y direction are parallel to the substrate ( Figure 6 The z direction is perpendicular to the surface of the substrate. The angle between the x direction and the y direction can be an acute angle, a right angle, or an obtuse angle. In this example, the angle between the x direction and the y direction is a right angle, that is, the x direction, the y direction, and the z direction are perpendicular to each other. Figure 6 The structure shown may be formed on one side of a substrate. For example, a first conductive line 210 , a memory cell 220 , and a second conductive line 230 may be formed on the substrate.

[0062] Each memory cell 220 can be written to a first storage state or a second storage state. For example, a first memory cell among the plurality of memory cells 220 can be written to the first storage state, and a second memory cell among the plurality of memory cells 220 can be written to the second storage state. As described above, the first storage state and the second storage state correspond to the SET state for storing a bit "1" and the RESET state for storing a bit "0," respectively. Therefore, the threshold voltage corresponding to the second storage state is greater than the threshold voltage corresponding to the first storage state.

[0063] The memory 200 further includes a delay circuit 240 coupled to the plurality of memory cells 220. The delay circuit 240 is configured to: read Delay is performed so that the threshold voltage corresponding to the first storage state increases; a read voltage pulse V applied to the second storage cell is read A delay is performed so that a threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

[0064] In the embodiment of the present disclosure, when a read operation is performed, the delay circuit 240 can delay the read voltage pulse V applied to the memory cell 220. read A delay is performed so that the threshold voltage of the memory cell 220 increases, and the threshold voltage increase of the memory cell in the RESET state is more significant than the threshold voltage increase of the memory cell in the SET state, that is, the threshold voltage increment corresponding to the second memory state is greater than the threshold voltage increment corresponding to the first memory state. In this way, even if the threshold voltages of memory cells in different memory states drift due to factors such as time and temperature, the difference between the threshold voltages of the second memory state and the first memory state can be increased, thereby widening the read and write window.

[0065] In some embodiments, the delay circuit 240 includes at least one of a resistor R and a capacitor C. In the case where the delay circuit 240 includes the resistor R and the capacitor C, the resistor R and the capacitor C may form an RC delay circuit. Of course, the delay circuit 240 may also include any other circuit capable of realizing the read voltage pulse V read For ease of description, the delay circuit 240 will be described below as a resistor R.

[0066] In some embodiments, the resistance value of the resistor R ranges from 0.1 kilo-ohm (KΩ) to 20 kilo-ohm. For example, the resistance value of the resistor R is 0.1 KΩ, 1 KΩ, 5 KΩ, 10 KΩ, 15 KΩ, or 20 KΩ.

[0067] In some embodiments, the delay circuit 240 is coupled to the first conductive line 210 or the second conductive line 230. The first conductive line 210 can be one of a word line and a bit line, and the second conductive line 230 can be the other of the word line and the bit line. That is, the delay circuit 240 can be coupled to the word line or the bit line. read The read voltage pulse V read For the convenience of description, the following description will be given by taking the first conductive line 210 as a bit line and the second conductive line 230 as a word line as an example.

[0068] In some embodiments, the memory 200 further includes a write driver 250 coupled to the plurality of memory cells 220. During a write operation, the write driver 250 may apply a write current pulse or a write voltage pulse to the memory cells 220, thereby writing the memory cells 220 to the first storage state or the second storage state. Here, the write driver 250 may be coupled to a word line or a bit line.

[0069] In some embodiments, the write driver 250 is configured to apply a write current pulse to the first conductive line 210 when the delay circuit 240 is coupled to the first conductive line 210. Figure 7 The delay circuit 240 is coupled to the first conductive line 210 and applies a write current pulse.

[0070] Figure 7 is a schematic diagram of performing write and read operations provided by the first embodiment of the present disclosure, wherein: Figure 7 Figure (a) shows the write operation. Figure 7 Figure (b) shows the read operation. Figure 7 In Figures (a) and (b), the resistor R and the bit line BL are connected in series.

[0071] Reference Figure 7 As shown in FIG. (a), when performing a write operation, a write current pulse I can be applied to the bit line BL. write , and couples the word line WL to the ground terminal GND, thereby writing the memory cell 220 to the SET state or the RESET state. Figure 7 As shown in FIG. 1(b), when performing a read operation, a read voltage pulse V may be applied to the bit line BL. read The word line WL is coupled to the ground terminal GND to sense the current flowing through the memory cell 220. If the current is low, it is determined that the resistance of the memory cell 220 is high and the memory cell 220 is in the RESET state; if the current is high, it is determined that the resistance of the memory cell 220 is low and the memory cell 220 is in the SET state.

[0072] It is understandable that Figure 7 In the embodiment shown, the SOM device is written by current drive, and then a read voltage pulse V is applied. read , the storage state of the device is judged by the device current value. Write current pulse I write and read voltage pulse V read Both are applied to the side with series resistance R, that is, the write current pulse I write and read voltage pulse V read Both are applied to the bit line BL.

[0073] In other embodiments, combined Figure 7 As shown, the delay circuit 240 may include a resistor R and a capacitor (not shown in the figure), the resistor R and the bit line BL are connected in series, the first electrode plate of the capacitor is coupled to the node between the resistor R and the bit line BL, and the second electrode plate of the capacitor is coupled to the ground terminal.

[0074] In some embodiments, the write driver 250 is configured to apply a write current pulse to the second conductive line 230 when the delay circuit 240 is coupled to the second conductive line 230. Figure 8 The delay circuit 240 is coupled to the second conductive line 230 and the write current pulse is applied as an example.

[0075] Figure 8 is a schematic diagram of performing write and read operations provided by the second embodiment of the present disclosure, wherein: Figure 8 Figure (a) shows the write operation. Figure 8 Figure (b) shows the read operation. Figure 8 In Figures (a) and (b), the resistor R and the word line WL are connected in series.

[0076] Reference Figure 8 As shown in FIG. (a), when performing a write operation, a write current pulse I can be applied to the word line WL. write , and couples the bit line BL to the ground terminal GND, thereby writing the memory cell 220 to the SET state or the RESET state. Figure 8 As shown in FIG. (b), when performing a read operation, a read voltage pulse V may be applied to the word line WL. read The bit line BL is coupled to the ground terminal GND to sense the current flowing through the memory cell 220. If the current is low, it is determined that the resistance of the memory cell 220 is high and the memory cell 220 is in the RESET state; if the current is high, it is determined that the resistance of the memory cell 220 is low and the memory cell 220 is in the SET state.

[0077] It is understandable that Figure 8 In the embodiment shown, the SOM device is written by current drive, and then a read voltage pulse V is applied. read , the storage state of the device is judged by the device current value. Write current pulse I write and read voltage pulse V read Both are applied to the side with series resistance R, that is, the write current pulse I write and read voltage pulse V read Both are applied to word line WL.

[0078] In other embodiments, combined Figure 8As shown, the delay circuit 240 may include a resistor R and a capacitor (not shown in the figure), the resistor R and the word line WL are connected in series, the first electrode plate of the capacitor is coupled to the node between the resistor R and the word line WL, and the second electrode plate of the capacitor is coupled to the ground terminal.

[0079] In some embodiments, the write driver 250 is configured to apply a write voltage pulse to the first conductive line 210 when the delay circuit 240 is coupled to the first conductive line 210. Figure 9 The delay circuit 240 is coupled to the first conductive line 210 and applies a write voltage pulse as an example.

[0080] Figure 9 is a schematic diagram of performing write and read operations provided by the third embodiment of the present disclosure, wherein: Figure 9 Figure (a) shows the write operation. Figure 9 Figure (b) shows the read operation. Figure 9 In (a) and (b) of FIG, the resistor R and the bit line BL are connected in series. Figure 7 The difference is that Figure 9 The write voltage pulse V is applied during the write operation. write .

[0081] Reference Figure 9 As shown in FIG. (a), when performing a write operation, a write voltage pulse V can be applied to the word line WL. write , and couples the bit line BL to the ground terminal GND, thereby writing the memory cell 220 to the SET state or the RESET state. Figure 9 As shown in FIG. 1(b), when performing a read operation, a read voltage pulse V may be applied to the bit line BL. read The word line WL is coupled to the ground terminal GND to sense the current flowing through the memory cell 220. If the current is low, it is determined that the resistance of the memory cell 220 is high and the memory cell 220 is in the RESET state; if the current is high, it is determined that the resistance of the memory cell 220 is low and the memory cell 220 is in the SET state.

[0082] It is understandable that Figure 9 In the embodiment shown, voltage driven writing is applied to the SOM device, and then a read voltage pulse V is applied. read , judge the storage state of the device by the device current value. Write voltage pulse V write Apply to the side without resistance R and read the voltage pulse V read Applied to the side with series resistance R. Considering that the delay effect of series resistance R on voltage is more obvious, Figure 9 In the embodiment shown, when voltage driven writing is used, the writing voltage pulse Vwrite It can be applied through a word line WL without a series resistor R, thereby ensuring that data is written correctly.

[0083] Similarly, combined Figure 9 As shown, the delay circuit 240 may include a resistor R and a capacitor (not shown in the figure), the resistor R and the bit line BL are connected in series, the first electrode plate of the capacitor is coupled to the node between the resistor R and the bit line BL, and the second electrode plate of the capacitor is coupled to the ground terminal.

[0084] In some embodiments, the write driver 250 is configured to apply a write voltage pulse to the second conductive line 230 when the delay circuit 240 is coupled to the second conductive line 230. Figure 10 The delay circuit 240 is coupled to the second conductive line 230 and applies a write voltage pulse as described below.

[0085] Figure 10 is a schematic diagram of performing write and read operations provided by the fourth embodiment of the present disclosure, wherein: Figure 10 Figure (a) shows the write operation. Figure 10 Figure (b) shows the read operation. Figure 10 In (a) and (b) of FIG, the resistor R and the word line WL are connected in series. Figure 8 The difference is that Figure 10 The write voltage pulse V is applied during the write operation. write .

[0086] Reference Figure 10 As shown in Figure (a), when performing a write operation, a write voltage pulse V can be applied to the bit line BL. write , and couples the word line WL to the ground terminal GND, thereby writing the memory cell 220 to the SET state or the RESET state. Figure 10 As shown in FIG. (b), when performing a read operation, a read voltage pulse V may be applied to the word line WL. read The bit line BL is coupled to the ground terminal GND to sense the current flowing through the memory cell 220. If the current is low, it is determined that the resistance of the memory cell 220 is high and the memory cell 220 is in the RESET state; if the current is high, it is determined that the resistance of the memory cell 220 is low and the memory cell 220 is in the SET state.

[0087] It is understandable that Figure 10 In the embodiment shown, voltage driven writing is applied to the SOM device, and then a read voltage pulse V is applied. read , judge the storage state of the device by the device current value. Write voltage pulse V write Apply to the side without resistance R and read the voltage pulse V readApplied to the side with series resistance R. Considering that the delay effect of series resistance R on voltage is more obvious, Figure 10 In the embodiment shown, when voltage driven writing is used, the writing voltage pulse V write It can be applied through the bit line BL without a series resistor R, thereby ensuring that the data is written correctly.

[0088] Similarly, combining Figure 10 As shown, the delay circuit 240 may include a resistor R and a capacitor (not shown in the figure), the resistor R and the word line WL are connected in series, the first electrode plate of the capacitor is coupled to the node between the resistor R and the word line WL, and the second electrode plate of the capacitor is coupled to the ground terminal.

[0089] In some embodiments, the write current pulse I write Or write voltage pulse V write The duration of is 1 nanosecond (ns) to 1000 nanoseconds. Figure 7 or Figure 8 The write current pulse I applied in write The duration of can be 1ns, 10ns, 100ns, 500ns or 1000ns, etc. For example, Figure 9 or Figure 10 The write voltage pulse V write The duration can be 1ns, 10ns, 100ns, 500ns or 1000ns.

[0090] In some embodiments, the read voltage pulse V read The duration of is 1 nanosecond to 1000 nanoseconds. Figures 7 to 10 In any embodiment, the read voltage pulse V read The duration of the pulse may be 1 ns, 10 ns, 100 ns, 500 ns or 1000 ns, etc. It should be noted that the duration of the pulse used in the present disclosure may be the pulse width.

[0091] Figure 11 1 is a schematic diagram showing changes in the threshold voltage and the threshold voltage difference of a memory cell in two storage states when no series resistor is connected, provided by an embodiment of the present disclosure. Figure 12 Schematic diagram of the change of the threshold voltage and threshold voltage difference of the memory cell in two storage states when the series resistor is provided in the embodiment of the present disclosure. It should be noted that, Figure 11 and Figure 12 The threshold voltage distributions of the RST (corresponding to RESET) and SET states corresponding to different sensing times are shown in FIG. For ease of comparison, the median of the threshold voltage distributions of the RST and SET states can be taken to obtain the median RST threshold voltage and the median SET threshold voltage.

[0092] Reference Figure 11 As shown in the figure, when no series resistor is connected, the threshold voltages of the RESET and SET states change in a similar fashion with respect to sensing time. Even when the sensing time is reduced to 200ns, the threshold voltage difference between the RESET and SET states remains almost unchanged. For example, the threshold voltage difference when the sensing time is 200ns is substantially the same as the threshold voltage difference when the sensing time is 700ns. The sensing time is the duration or pulse width of the read voltage pulse.

[0093] Reference Figure 12 As shown in FIG5 , after the bit line BL is connected in series with the resistor R, the threshold voltages of the RESET state and the SET state both increase with decreasing sensing time, and the threshold voltage of the RESET state increases more dramatically, so that the threshold voltage difference between the RESET state and the SET state increases significantly with decreasing sensing time. For example, when the sensing time decreases from 100 us to 500 ns, the threshold voltage difference between the RESET state and the SET state increases by about 7 times.

[0094] That is to say, compared with the case where no series resistor is connected, when a read operation is performed with a series resistor, the threshold voltages of the memory cells in the RESET state and the SET state are both increased, and the threshold voltage increment of the memory cell in the RESET state is greater than the threshold voltage increment of the memory cell in the SET state, thereby increasing the threshold voltage difference between the memory cells in the RESET state and the SET state, that is, increasing the read and write window.

[0095] Still refer to Figure 12 As shown in FIG, as the sensing time decreases, the threshold voltage difference between the RESET state and the SET state increases. Therefore, in practical applications, a short pulse signal can be used to perform a read operation on memory cells in different storage states to better distinguish different storage states.

[0096] Based on the above memory, an embodiment of the present disclosure provides a memory operating method, which can be used for the memory in any of the above embodiments, for example, for reading the voltage of the memory in any of the above embodiments.

[0097] Figure 13 This is a flow chart of a memory operation method provided by an embodiment of the present disclosure. It should be noted that: Figure 13 The steps shown in the operation are not exclusive, and other steps may be performed before, after, or between any steps in the operation shown; Figure 13 The steps shown in the following can be adjusted in order according to actual needs. Figure 13 As shown, the operation method includes the following steps:

[0098] Step S310: delaying a read voltage pulse applied to a first memory cell by a delay circuit of the memory so as to increase a threshold voltage corresponding to a first storage state;

[0099] Step S320: Delaying the read voltage pulse applied to the second memory cell through the memory delay circuit so that the threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

[0100] In an embodiment of the present disclosure, the memory may include multiple storage cells, the multiple storage cells including a first storage cell in a first storage state and a second storage cell in a second storage state, the threshold voltage corresponding to the second storage state is greater than the threshold voltage corresponding to the first storage state, and regarding the first storage cell and the second storage cell, reference may be made to the relevant description of the above embodiments.

[0101] In some embodiments, the operating method further includes: applying a write current pulse and a read voltage pulse to one of the first conductive line and the second conductive line. It is understood that in the embodiment of the present disclosure, current-driven writing can be used, and the write current pulse and the read voltage pulse are applied to the side with the delay circuit. For current-driven writing, please refer to Figure 7 and Figure 8 Related description.

[0102] In the embodiment of the present disclosure, the first conductive line and the second conductive line are respectively located on opposite sides of the memory cell. For example, the first conductive line is located on the side of the first electrode relatively far away from the memory layer, and the second conductive line is located on the side of the second electrode relatively far away from the memory layer. The first conductive line can be one of a word line and a bit line, and the second conductive line can be the other of the word line and the bit line. For more information about the first conductive line and the second conductive line, please refer to Figure 6 Related description.

[0103] In some embodiments, the operating method further includes: applying a write voltage pulse to one of the first conductive line and the second conductive line, and applying a read voltage pulse to the other of the first conductive line and the second conductive line. It is understood that voltage-driven writing can be used in the embodiments of the present disclosure. The write voltage pulse can be applied to the side without the delay circuit, and the read voltage pulse can be applied to the side with the delay circuit. For voltage-driven writing, please refer to Figure 9 and Figure 10 Related description.

[0104] In the embodiments of the present disclosure, the operating method can be executed by the memory in any of the aforementioned embodiments. The technical effects achieved by the memory in the aforementioned embodiments can also be achieved by the operating method, and will not be described in detail here. Regarding the operating method in the aforementioned embodiments, the specific implementation of each step has been described in detail in the relevant memory embodiments and will not be elaborated on here.

[0105] Based on the above memory, an embodiment of the present disclosure provides a memory system. The memory system includes: one or more of the above memories; and a memory controller coupled to the memory and configured to control the memory.

[0106] Based on the above memory system, an embodiment of the present disclosure provides an electronic device, including: the above memory system.

[0107] Figure 14 This is a schematic diagram of an electronic device provided by an embodiment of the present disclosure. Figure 14 The electronic device and memory system provided by the embodiments of the present disclosure are exemplarily described.

[0108] The electronic device 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. Figure 14 As shown, electronic device 400 may include a host 410 and a memory system 420, wherein the memory system 420 includes a memory controller 421 and a memory 422. Host 410 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of electronic device 400. Host 410 may be configured to send data to or receive data from memory system 420.

[0109] In some embodiments, the memory controller 421 is coupled to the memory 422 and the host 410 and is configured to control the memory 422. The memory controller 421 may manage data stored in the memory 422 and communicate with the host 410.

[0110] In some embodiments, the memory controller 421 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0111] In other embodiments, the memory controller 421 is designed to operate in a high duty cycle environment, such as a Solid State Drive (SSD) or an Embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0112] In some embodiments, the memory 422 includes one or more types of memory. For example, the memory 422 includes a SOM device and a non-volatile memory. The SOM device can be used as a cache, and the non-volatile memory can be used as a memory. The non-volatile memory includes but is not limited to NAND flash memory. For more information about the SOM device, please refer to Figures 6 to 10 Related description of memory 200 in .

[0113] Of course, in other embodiments, the memory 422 may also include dynamic random access memory (DRAM), which may also be used as a cache. In some embodiments, the SOM device and DRAM may be configured in a hierarchical cache configuration, such that the SOM device is positioned between DRAM and NAND flash memory to bridge the performance gap between DRAM and NAND flash memory.

[0114] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0115] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0116] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0117] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0118] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A memory, characterized in that: include: a plurality of memory cells, the plurality of memory cells comprising a first memory cell in a first memory state and a second memory cell in a second memory state, wherein a threshold voltage corresponding to the second memory state is greater than a threshold voltage corresponding to the first memory state; a delay circuit coupled to the plurality of storage units; the delay circuit being configured to: delaying a read voltage pulse applied to the first memory cell so that a threshold voltage corresponding to the first memory state increases; The read voltage pulse applied to the second memory cell is delayed so that a threshold voltage corresponding to the second memory state increases; wherein the threshold voltage increment corresponding to the second memory state is greater than the threshold voltage increment corresponding to the first memory state.

2. The memory according to claim 1, wherein The memory cell includes a first electrode, a storage layer, and a second electrode stacked in sequence; the memory further includes: a first conductive line, the first conductive line being located on a side of the first electrode relatively far from the storage layer and extending along a first direction, the first direction being perpendicular to the stacking direction; a second conductive line, the second conductive line being located on a side of the second electrode relatively far from the storage layer and extending along a second direction, the second direction being perpendicular to the stacking direction and intersecting the first direction; The delay circuit is coupled to the first conductive line or the second conductive line.

3. The memory according to claim 2, wherein: The memory further includes a write driver; the write driver is configured to: In a case where the delay circuit is coupled to the first conductive line, a write current pulse is applied to the first conductive line or a write voltage pulse is applied to the second conductive line.

4. The memory according to claim 2, wherein: The memory further includes a write driver; the write driver is configured to: In a case where the delay circuit is coupled to the second conductive line, a write current pulse is applied to the second conductive line or a write voltage pulse is applied to the first conductive line.

5. The memory according to claim 3 or 4, characterized in that: The duration of the write current pulse or the write voltage pulse is 1 nanosecond to 1000 nanoseconds. The memory according to claim 1 , wherein: The delay circuit includes at least one of a resistor and a capacitor.

7. The memory according to claim 6, wherein: The resistance of the resistor ranges from 0.1 kilo-ohms to 20 kilo-ohms.

8. The memory according to claim 1, wherein: The duration of the read voltage pulse is 1 nanosecond to 1000 nanoseconds.

9. A method for operating a memory, characterized in that: Used to read the voltage of the memory according to any one of claims 1 to 8; the operation method comprises: delaying a read voltage pulse applied to the first memory cell by a delay circuit of the memory so that a threshold voltage corresponding to the first storage state increases; The read voltage pulse applied to the second storage unit is delayed by the delay circuit of the memory so that the threshold voltage corresponding to the second storage state increases; wherein the threshold voltage increment corresponding to the second storage state is greater than the threshold voltage increment corresponding to the first storage state.

10. The operating method according to claim 9, characterized in that: The operation method further includes: applying a write current pulse and the read voltage pulse to one of the first conductive line and the second conductive line; or, applying a write voltage pulse to one of the first conductive line and the second conductive line, and applying the read voltage pulse to the other of the first conductive line and the second conductive line; The first conductive line and the second conductive line are respectively located on two opposite sides of the storage unit.

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