Operation method of memory system, operation method of memory, and memory system

Abstract

The invention provides an operation method of a memory system, an operation method of a memory, and a memory system. According to the method, in the programming process, hard bit data and soft bit data corresponding to at least one programming state sent by a memory after one programming operation is executed can be obtained through a memory controller. And then sending first indication information to the memory according to the hard bit data and the soft bit data, and indicating an adjustment strategy of a second programming parameter when the memory executes a second programming operation through the first indication information. Through the mode, the programming parameters of the subsequent programming state of the programming address or all the programming states of the next programming address can be adjusted according to the bit error rate corresponding to a part of programming states in a certain programming operation, so that the programming quality and the programming performance are dynamically balanced, and the dynamic influence of various application scene factors is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to an operating method of a memory system, a memory operating method, and a memory system. Background Art

[0002] In the process of programming a three-dimensional memory (e.g., 3D NAND memory), the sum of the overlapping parts of the threshold voltages of all two adjacent programming states in the memory cell (denoted as ESUM) and the programming time (denoted as Tprog) are two very important indicators. Among them, ESUM determines the programming quality of the memory cell, and Tprog determines the programming performance of the memory cell. However, programming quality and programming performance are easily affected by the dynamic factors of various application scenarios. Summary of the invention

[0003] The embodiments of the present disclosure provide a method for operating a memory system, a method for operating a memory, and a memory system, aiming to solve the problem that the programming quality and programming performance of a three-dimensional memory during a programming process are easily affected by various application scenario factors.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a method for operating a memory system is provided, which can be executed by a memory controller. When executing, the memory controller can first obtain hard bit data and soft bit data corresponding to at least one programming state sent by the memory after executing a first programming operation. The first programming operation is executed based on a first programming parameter. Then, in response to the hard bit data and the soft bit data, a first indication information is sent to the memory. Among them, the first indication information is used to indicate the adjustment strategy of the second programming parameter when the memory performs a second programming operation. The first programming parameter and the second programming parameter both include incremental step pulse programming parameters and programming verification voltage. Based on this, the memory controller can dynamically adjust parameters such as incremental step pulse programming parameters and programming verification voltage of subsequent programming operations according to the hard bit data and soft bit data corresponding to at least one programming state after executing a programming operation, balance programming quality and programming performance, and reduce the dynamic impact of various application scenario factors.

[0006] In a possible implementation, in response to the hard bit data and the soft bit data, when sending the first indication information to the memory, the hard bit data and the soft bit data can be compared to determine the bit error rate of at least one programming state. Then, the first indication information is generated according to the bit error rate. Based on this, the memory controller can generate the above-mentioned first indication information according to the detected bit error rate, so as to more accurately instruct the memory to adjust the programming parameters of the subsequent programming operation.

[0007] In a possible implementation, when the bit error rate is lower than the first threshold, the adjustment strategy is: increase at least one of the incremental step pulse programming parameter and the programming verification voltage. Based on this, if the bit error rate is lower than the set threshold (i.e., the bit error rate is very low), the programming time can be reduced and the programming performance can be improved by increasing the incremental step pulse programming parameter or increasing the programming verification voltage.

[0008] In a possible implementation, when the bit error rate is higher than the second threshold, the adjustment strategy is: reduce at least one of the incremental step pulse programming parameter and the programming verification voltage. Based on this, if the bit error rate is higher than the set threshold (i.e., the bit error rate is too high), the incremental step pulse programming parameter and the programming verification voltage can be reduced to reduce the bit error rate and improve the programming quality.

[0009] In one possible implementation, the first threshold is smaller than the second threshold.

[0010] In a possible implementation, when the bit error rate is within the range from the first threshold to the second threshold, the adjustment strategy is: keep the second programming parameter unchanged. Based on this, the bit error rate within the range from the first threshold to the second threshold can be regarded as an acceptable range, and the second programming parameter is not adjusted.

[0011] In one possible implementation, the first threshold is equal to the second threshold.

[0012] In a possible implementation, when the bit error rate is equal to the first threshold, the adjustment strategy is: keep the second programming parameter unchanged. Based on this, it is also possible to choose not to adjust the second programming parameter when the bit error rate is the first threshold.

[0013] In a possible implementation, the first programming operation and the second programming operation correspond to different programming states of the same programming address. Based on this, during the programming process, the programming parameters of the programming state to be programmed subsequently can be adjusted according to the bit error rate corresponding to the programming state programmed at the same programming address.

[0014] In a possible implementation, the first programming operation and the second programming operation correspond to the same programming state or different programming states of different programming addresses. Based on this, the programming parameters of the next programming address can be adjusted according to the bit error rate of the previous programming address.

[0015] In a possible implementation, the first indication information is also used to indicate the read voltage and erase voltage of the programming state obtained by programming according to the adjustment strategy. Based on this, the read voltage and erase voltage of the subsequent programming state can also be adjusted when adjusting the subsequent programming parameters.

[0016] In a second aspect, a method for operating a memory is provided. After executing a first programming operation, the processor outputs hard bit data and soft bit data corresponding to at least one programming state. The first programming operation is performed based on a first programming parameter. Then, the memory receives a first indication information returned in response to the hard bit data and the soft bit data. The first indication information is used to indicate an adjustment strategy of a second programming parameter when the memory executes a second programming operation. The second programming parameter includes an incremental step pulse programming parameter and a programming verification voltage. Finally, the memory executes the adjustment strategy in response to the first indication information.

[0017] In a possible implementation, when generating the first indication information, the memory may compare the hard bit data with the soft bit data to determine the bit error rate of at least one programming state, and then generate the first indication information according to the bit error rate.

[0018] In a possible implementation, when the bit error rate is lower than the first threshold, the adjustment strategy is: increasing at least one of the incremental step pulse programming parameter and the programming verification voltage.

[0019] In a possible implementation, when the bit error rate is higher than the second threshold, the adjustment strategy is: reducing at least one of the incremental step pulse programming parameter and the programming verification voltage.

[0020] In one possible implementation, the first threshold is smaller than the second threshold.

[0021] In a possible implementation, when the bit error rate is between the first threshold and the second threshold, the adjustment strategy is: keep the second programming parameter unchanged.

[0022] In one possible implementation, the first threshold is equal to the second threshold.

[0023] In a possible implementation, when the bit error rate is equal to the first threshold, the adjustment strategy is: keep the second programming parameter unchanged.

[0024] In a possible implementation, the first indication information is also used to indicate a read voltage and an erase voltage of a programming state obtained by programming according to the adjustment strategy.

[0025] In a possible implementation, the first programming operation and the second programming operation correspond to different programming states of the same programming address.

[0026] In a possible implementation, the first programming operation and the second programming operation correspond to the same programming state or different programming states at different programming addresses.

[0027] In a third aspect, a memory system is provided. The memory system includes one or more memories; and a memory controller coupled to the memory. The memory controller is configured to: receive hard bit data and soft bit data corresponding to at least one programming state sent by the memory after executing a first programming operation. The first programming operation is performed based on a first programming parameter. Then, in response to the hard bit data and the soft bit data, a first indication information is sent to the memory. The first indication information is used to indicate an adjustment strategy for a second programming parameter when the memory executes a second programming operation. The second programming parameter includes an incremental step pulse programming parameter and a programming verification voltage.

[0028] The memory is configured to: receive first indication information and execute an adjustment strategy in response to the first indication information.

[0029] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method of any one of the first aspect or the second aspect.

[0030] In a fifth aspect, a computer program product is provided, which is executed by a processor to implement the method of any one of the first aspect or the second aspect.

[0031] It can be understood that the beneficial effects that can be achieved by the second to fifth aspects provided by the above-mentioned embodiments of the application can refer to the beneficial effects of the first aspect above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0033] Figure 1 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0034] Figure 2 A schematic diagram of a topological structure of a memory provided in an embodiment of the present application;

[0035] Figure 3 A schematic diagram of ISPP programming provided in an embodiment of the present application;

[0036] Figure 4A graph showing the relationship between ESUM and programming performance provided in an embodiment of the present application;

[0037] Figure 5 A flow chart of an operating method of a memory system provided in an embodiment of the present application;

[0038] Figure 6 A schematic diagram of reading hard bit data and soft bit data provided in an embodiment of the present application;

[0039] Figure 7 A schematic diagram of a programming parameter adjustment method provided in an embodiment of the present application;

[0040] Figure 8 A schematic diagram of another method for adjusting programming parameters provided in an embodiment of the present application;

[0041] Fig. 9 A schematic diagram of another method for adjusting programming parameters provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0043] In the description of the present disclosure, it is to be understood that, unless the context otherwise requires, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplary" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] like Figure 1 As shown, a memory system 100 is usually provided in an electronic device 10. The memory system 100 includes a memory 120 and a memory controller 110. The memory controller 110 is coupled to the memory 120, and data can be read from the memory 120 or written to the memory 120 through the memory controller 110.

[0050] It is understood that the memory system 100 may include a memory controller 110 and one or more memories 120. For example, in one embodiment, the memory controller 110 and the single memory 120 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash card (CF card for short), a smart media card (SM card for short), a memory stick (memory stick), a multimedia card (MMC), a secure digital card (SD card for short), a universal flash storage (UFS), etc. Among them, the multimedia card can be divided into MMC, reduced-size MMC (RS-MMC), mini MMC (MMCmicro), etc.; the secure digital card includes SD, mini SD card (miniSD), micro SD card (microSD), high-capacity SD card (secure digital high capacity, SDHC), etc. Further, the memory card may also include a memory card connector for coupling the memory card to the host. In another embodiment, the controller 300 and the plurality of memories 120 may be integrated into a solid state disk (SSD). The SSD may further include an SSD connector for coupling the SSD to a host. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the electronic device 10 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc., and the embodiments of the present disclosure do not impose specific restrictions on this.

[0051] In some embodiments, the memory controller 110 may be configured to manage data stored in the memory 120 and communicate with an external device (e.g., the host 200). In some embodiments, the memory controller 110 may also be configured to control operations of the memory 120, such as programming, reading, and erasing operations. In some embodiments, the memory controller 110 may also be configured to manage various functions regarding data stored or to be stored in the memory 120, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the memory controller 110 is also configured to process error correction codes regarding data read from the memory 120 or written to the three-dimensional memory 120.

[0052] Of course, the memory controller 110 may also perform any other suitable functions, such as formatting the memory 120 ; for example, the memory controller 110 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0053] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0054] like Figure 2 As shown, the memory 120 generally includes a memory array 121 and peripheral circuits. The peripheral circuits include a connection terminal 1221, a control logic circuit 1222, a register 1223, a voltage generator 1224, a row driver 1225, a column driver 1226, and a page buffer 1227. The connection terminal 1221 is mainly used to receive a read instruction and a programming instruction sent by the memory controller 110, and to send the read data to the memory controller 110. The control logic circuit 1222 is mainly used to receive a control instruction sent by the memory controller, and to control the row driver 1225, the voltage generator 1224, and the column driver 1226 according to the received control instruction, so as to perform read, program, and erase operations on the memory cells in the memory array.

[0055] Specifically, when programming a memory cell, a step-by-step method is usually used. Figure 3As shown, the more commonly used programming method at present is to use incremental step-pulse programming (ISPP) for programming. Among them, ISPP gradually increases the word line bias voltage based on the step voltage while programming the selected storage page several times. The amplitude of the "step" (the value of each pulse relative to the previous adjacent pulse) is recorded as ΔV. Between two adjacent pulses, a programming verification operation is performed to check whether the selected storage cell has a threshold voltage that has been increased to a level above the programming verification voltage of the storage cell. However, the programming quality of the storage cell will be affected by many factors such as temperature, voltage, process changes and program / erase cycle (PE). At present, in order to obtain better programming quality, the programming parameters are usually adjusted in a step-by-step manner during the test phase to obtain or screen out chips that meet the ESUM requirements or programming time requirements of the product. In the actual application of the memory, ESUM will change in real time due to various dynamic factors, and the programming parameters cannot track the changes in ESUM in real time, resulting in a decrease in programming quality / programming performance. As shown in FIG. Figure 4 As shown in the figure, the black curve is the relationship curve between programming performance and ESUM, while the hollow circles (b1 and b2) are the fluctuation points under the influence of the external environment, and the solid circle (a) is the best point to meet the needs. If the changes of ESUM cannot be tracked during the programming process, the best balance between programming quality and programming performance cannot be achieved.

[0056] In order to solve the above problems, Figure 5 As shown, an embodiment of the present application provides an operating method of a memory system, and the specific execution process of the operating method is as follows.

[0057] S501. The memory controller sends a programming instruction to the memory.

[0058] When data needs to be stored, the host can send the data to be stored to the memory controller. After receiving the data, the memory controller sends a corresponding programming instruction to the control logic circuit in the memory.

[0059] S502. The control logic circuit performs a first programming operation according to a first programming parameter.

[0060] After receiving the programming instruction, the control logic circuit in the memory may first perform the first programming operation according to the first programming parameter. The first programming parameter corresponding to the first programming operation includes an incremental step pulse programming parameter and a programming verification voltage. The first programming operation may complete the programming of some programming states of the same programming address in the storage unit, or may complete the programming of all programming states of the same programming address, and the embodiment of the present application does not impose any specific restrictions on this.

[0061] In a possible implementation, the first programming parameter corresponding to the first programming operation can be stored in a fixed address divided in the memory by a characteristic writing method. When programming is required, the memory controller can send a corresponding control instruction to the control logic circuit to control the control logic circuit to read the first programming parameter and perform the first programming operation according to the first programming parameter.

[0062] S503. The memory controller sends a read instruction to the control logic circuit.

[0063] The above steps are optional steps. After executing the first programming operation, the control logic circuit can read the soft bit data and hard bit data corresponding to at least one programming state through the read instruction sent by the memory controller. Of course, the read operation can also be added to the first programming parameter corresponding to the first programming operation, and then saved in the fixed address divided in the memory by the characteristic writing method. After executing the first programming operation, the control logic circuit can then read the soft bit data and hard bit data corresponding to at least one programming state.

[0064] S504. After completing the first programming operation, the control logic circuit reads the soft bit data and the hard bit data corresponding to at least one programming state.

[0065] Among them, refer to Figure 6 , specific examples of hard bit data (hard bit, HB) and soft bit data (soft bit, SB) are described. Figure 6 3 is a schematic diagram showing the relationship between the distribution of the threshold voltages of the memory cells in the “B” programming state and the “A” programming state and the hard bit data and the soft bit data.

[0066] like Figure 6 As shown in FIG. 1 , due to the influence of read disturbance or data retention, the width of the threshold voltage distribution of each programming state is sometimes expanded, and the lower ends of adjacent threshold voltage distributions overlap each other ( Figure 6 In this case, if a read operation is performed, the memory cell corresponding to the overlapped area at the lower end is more likely to become a failed bit. More specifically, for example, when the read voltage V A When performing a read operation corresponding to the "B" programming state, the read voltage V A A memory cell in the "A" programming state above the threshold voltage has a read voltage less than V A The memory cell in the "B" programming state with a threshold voltage of 0.04077 becomes a failure bit. If the number of failure bits generated is too high (ie, the bit error rate is too high), it is difficult to read the data correctly.

[0067] Therefore, in this embodiment, in the read operation of one programming state, two read voltages are set across the region where the lower ends of the threshold voltage distribution overlap. More specifically, for the "B" programming state, two offset read voltages V AL and V AH . The offset read voltage V AL is less than the read voltage V A The voltage of AL =V A -△, △ is the offset voltage. Offset reading voltage V AH is higher than the read voltage V A The voltage, V AL =V A +△. The area where the "A" programming state overlaps with the "B" programming state is located at the read voltage V AL With the read voltage V AH In addition, the voltage V AL With the read voltage V A The voltage difference can be read as V A With the read voltage V AH The voltage difference can be the same or different.

[0068] For example, when using the read voltage V AL In the read operation, the threshold voltage is less than the read voltage V AL The data of the memory cell is "1". The threshold voltage is the read voltage V AL The data of the above memory cells is "0".

[0069] In addition, when using the read voltage V AH In the read operation, the threshold voltage is less than the read voltage V AH The data of the memory cell is "1". The threshold voltage is the read voltage V AH The data of the above memory cells is "0".

[0070] In this embodiment, according to the read voltage V A The read data is defined as hard bit data.

[0071] The soft bit data is calculated by a logical operation (for example, an XOR operation) of the two offset read voltage read data. Figure 6 In the example, the threshold voltage is less than the offset read voltage V AL The soft bit data of the memory cell is "0". The threshold voltage is the offset read voltage V AL Above and less than the offset read voltage V AH The soft bit data of the memory cell is "1". The threshold voltage is the offset read voltage V AHThe soft bit data of the above storage unit is "0". In addition, the operation of the soft bit data is not limited to the XOR operation. The operation of the soft bit data can be set based on the definition of the soft bit data. For example, when the threshold voltage is set to the offset read voltage V AL Above and less than the offset read voltage V AH When the soft bit data of the storage cell is defined as "0", the soft bit data can also be calculated using an XNOR (exclusive NOT OR) operation.

[0072] Therefore, the soft bit data indicates whether the threshold voltage is near the boundary of two adjacent threshold voltage distributions. After completing the first programming operation, the memory controller can read the corresponding hard bit data according to the read voltage transformation of each programming state and read the corresponding soft bit data according to the offset read voltage.

[0073] S505. The control logic circuit sends the read hard bit data and soft bit data corresponding to at least one programming state to the memory controller.

[0074] S506. The memory controller receives hard bit data and soft bit data corresponding to at least one programming state sent by the control logic circuit, and compares the hard bit data with the soft bit data to confirm the bit error rate of at least one programmed programming state.

[0075] Among them, Figure 6 As shown, the soft bit data of the overlapping portion of the threshold voltages in two adjacent programming states is 1. By comparing the hard bit data with the soft bit data, the ratio of the threshold voltage distribution of the overlapping portion to the threshold voltage distribution of one programming state can be obtained, thereby obtaining the bit error rate corresponding to the programming state.

[0076] S507. The memory controller generates first indication information according to the bit error rate and sends it to the control logic circuit.

[0077] The first indication information is used to indicate the adjustment strategy of the second programming parameter when the memory performs the second programming operation. The second programming parameter also includes the incremental step pulse programming parameter and the programming verification voltage.

[0078] S508. The control logic circuit executes a corresponding adjustment strategy according to the first indication information to adjust a second programming parameter of the second programming operation.

[0079] In a possible implementation, the second programming parameter corresponding to the second programming operation, the adjustment strategy of the second programming parameter, etc. can also be saved in the fixed address divided in the memory by feature writing. When the control logic circuit receives the first indication information, the corresponding adjustment strategy can be read according to the first indication information, and the second programming parameter can be frequently adjusted according to the adjustment strategy for programming. Among them, the first indication information can be a control instruction, wherein the control instruction includes a flag bit (for example, 0 or 1). When the memory controller sends the first indication information to the control logic circuit, the adjustment strategy of the second programming parameter can be represented by the value on the flag bit. For example, if the flag bit in the control instruction is 0, at least one of the incremental step pulse programming parameter and the programming verification voltage is increased. If the flag bit in the control instruction is 1, at least one of the incremental step pulse programming parameter and the programming verification voltage is reduced. If the flag bit is empty, the second programming parameter is not adjusted.

[0080] In a possible implementation, the adjustment strategy of the second programming parameter may be determined according to a set threshold.

[0081] Exemplarily, when the bit error rate is lower than the first threshold value K1, the adjustment strategy of the second programming parameter may be: increasing at least one of the incremental step pulse programming parameter and the programming verification voltage. When the bit error rate is lower than the second threshold value K2, the adjustment strategy of the second programming parameter may be: decreasing at least one of the incremental step pulse programming parameter and the programming verification voltage.

[0082] The first threshold value may be less than the second threshold value, and when the bit error rate is within the range from the first threshold value to the second threshold value, the second programming parameter may remain unchanged. Of course, the first threshold value may also be equal to the second threshold value, and when the bit error rate is equal to the first threshold value, the second programming parameter may remain unchanged.

[0083] In the above implementation process, the first threshold and the second threshold can be set according to actual needs with reference to any one of the above two methods, and the embodiment of the present application does not impose specific limitations on this.

[0084] In a possible implementation, the first programming operation and the second programming operation may be different programming states of the same programming address. If, after the first programming operation is completed, the bit error rate corresponding to a certain programming state is lower than the first threshold value K1, at least one of the incremental step pulse programming parameter and the programming verification voltage in the second programming operation may be increased.

[0085] For example, Figure 7As shown, assuming that when programming is performed through the first programming parameter of the first programming operation, a certain programming state corresponds to three step-by-step programming pulses (P1, P2 and P3). The amplitude of the "step" is △V, and the first programming operation applies a programming verification voltage after each application of the programming pulse. After the programming of the programming state is completed, the control logic circuit can read the hard bit data and soft bit data corresponding to the programming state. Then, the read hard bit data and soft bit data are sent to the memory controller. If the memory controller compares the hard bit data and the soft bit data and confirms that the bit error rate of the programming state is lower than the first threshold K1, the memory controller sends a first indication message to the control logic circuit, and instructs the control logic circuit to increase the incremental step pulse programming parameters and the programming verification voltage in the second programming parameters through the first indication message. The amplitude of the increase of the incremental step pulse programming parameters is V1; and / or the amplitude of the increase of the programming verification voltage is △Ver1. For example, Figure 7 In the example, the two subsequent programming pulses (P4 and P5) belong to the next programming state. After applying one programming pulse, the increased programming verification voltage can be applied. Because the amplitude of the "step" is increased, the number of programming pulses corresponding to each subsequent programming state will be relatively reduced. In addition, increasing the programming verification voltage can also more accurately verify whether the storage cell is programmed to the voltage of the corresponding programming state, thereby improving programming performance.

[0086] In the above implementation process, the amplitude V1 of the incremental step pulse programming parameter increase and the amplitude △Ver1 of the programming verification voltage increase can be set according to the actual needs of each programming state, and the embodiment of the present application does not impose specific restrictions on this. In addition, the number of programming pulses corresponding to each programming state can be adjusted according to the type of storage cell, and the embodiment of the present application does not impose specific restrictions on this. The amplitude of the programming verification voltage reduction of each programming state may also be different, and the embodiment of the present application does not impose specific restrictions on this.

[0087] For example, Figure 8As shown, assuming that when programming is performed through the first programming parameter of the first programming operation, a certain programming state corresponds to three step-by-step programming pulses (P1, P2 and P3), and the two programming pulses (P4 and P5) applied subsequently belong to the next programming state. The amplitude of the "step" is △V, and the first programming operation applies a programming verification voltage after each application of the programming pulse. After the programming of the programming state is completed, the control logic circuit can read the hard bit data and soft bit data corresponding to the programming state. Then, the read hard bit data and soft bit data are sent to the memory controller. If the memory controller compares the hard bit data and the soft bit data and confirms that the bit error rate of the programming state is higher than the second threshold K2, the memory controller sends a first indication information to the control logic circuit, and through the first indication information, instructs the control logic circuit to reduce at least one of the incremental step pulse programming parameter and the programming verification voltage in the second programming parameter. The amplitude of the reduction of the incremental step pulse programming parameter is V2; and / or, the amplitude of the reduction of the programming verification voltage of each programming state is △Ver2. In this way, the threshold voltage distribution of each programming state is more convergent, thereby reducing the overlapping threshold voltage distribution interval and improving the programming quality. In addition, when the bit error rate after the first programming operation exceeds the set threshold, the programming verification voltage is reduced, which can also verify more accurately and improve the programming performance. Therefore, in actual operation, at least one of reducing the incremental step pulse programming parameter and reducing the programming verification voltage can be selected.

[0088] In the above implementation process, the amplitude V2 of the incremental step pulse programming parameter reduction and the amplitude △Ver2 of the programming verification voltage reduction can be set according to the actual needs of each programming state, and the embodiment of the present application does not impose specific restrictions on this. In addition, the number of programming pulses corresponding to each programming state can be adjusted according to the type of storage cell, and the embodiment of the present application does not impose specific restrictions on this. The amplitude of the programming verification voltage reduction of each programming state may also be different, and the embodiment of the present application does not impose specific restrictions on this.

[0089] In a possible implementation, the first programming operation and the second programming operation correspond to the same programming state or different programming states at different programming addresses. If the bit error rate corresponding to a certain programming state is lower than the first threshold value K1 after the first programming operation is completed, at least one of the incremental step pulse programming parameter and the programming verification voltage in the second programming operation can be increased.

[0090] For example, Fig. 9 As shown in FIG. 1 , assuming that when programming is performed using the first programming parameter of the first programming operation, a certain programming state corresponds to three step-by-step programming pulses (P1, P2, and P3), and the two programming pulses (P4 and P5) applied subsequently belong to the next programming state. The amplitude of the "step" is △V, and the first programming operation applies a programming verification voltage after each programming pulse is applied (refer to Figure 3 ). After the programming of the programming state is completed, the control logic circuit can read the hard bit data and soft bit data corresponding to the programming state. Then, the read hard bit data and soft bit data are sent to the memory controller. If the memory controller compares the hard bit data and the soft bit data and confirms that the bit error rate of the programming state is lower than the first threshold K1, the memory controller sends a first indication information to the control logic circuit, and instructs the control logic circuit to increase at least one of the incremental step pulse programming parameters and the programming verification voltage in the second programming parameter through the first indication information. Among them, the amplitude of the increase of the incremental step pulse programming parameter is V3; and / or, the amplitude of the increase of the programming verification voltage of each programming state is △Ver3. For example, Fig. 9 In the example, when the programming address of the first programming operation is different from the programming address of the second programming operation, when the second programming operation is performed, the programming start voltage, the "step" amplitude, and the programming verification voltage in the first three programming pulses (P1, P2, and P3) in the second programming operation can be increased, and the "step" amplitude and programming verification voltage of the two programming pulses (P4 and P5) applied subsequently can be increased. Because the "step" amplitude is increased, the number of programming pulses corresponding to each subsequent programming state will be relatively reduced. In addition, increasing the programming verification voltage can also perform verification more accurately and improve programming performance.

[0091] Of course, when the bit error rate of the programming state is higher than the second threshold value K2, at least one of the incremental step pulse programming parameter and the programming verification voltage in the second programming parameter can also be increased. The embodiments of the present application are not described in detail here. In addition, the number of programming pulses corresponding to each programming state, the amplitude of the programming pulse adjustment, and the amplitude of the programming verification voltage adjustment can be adjusted according to actual needs, and the embodiments of the present application do not impose specific restrictions on this. The amplitudes of the programming verification voltage adjustment of each programming state may also be different, and the embodiments of the present application do not impose specific restrictions on this.

[0092] In this way, programming parameters of the same programming state and / or different programming states of the next programming address can be adjusted according to the bit error rate of at least one programming state in the previous programming address, thereby improving the programming quality or programming performance of the next programming address.

[0093] S509. Perform programming according to the adjusted programming parameters.

[0094] Among them, the adjusted programming parameters can be used to program the programming state programmed in the same programming address as the first programming operation, or can be used to program all or part of the programming states in the programming address different from the first programming operation. The specific programming method can be executed according to the adjustment strategy corresponding to the second programming parameter of the second programming operation, and the embodiments of the present application do not impose specific restrictions on this.

[0095] In a possible implementation, when adjusting the programming parameters of the second programming operation, the first indication information may also be used to indicate the read voltage and erase voltage of the programming state obtained by programming according to the above adjustment strategy, so as to more accurately read and erase the programmed data.

[0096] Furthermore, some embodiments of the present application also provide a computer-readable storage medium storing computer program instructions, which can implement the above method steps when the computer program instructions are executed by a processor. The above-mentioned storage medium can be a read-only memory, a USB flash drive, a magnetic disk, or an optical disk, etc., and the embodiments of the present application do not specifically limit this.

[0097] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A method for operating a memory system, characterized in that: include: Acquire hard bit data and soft bit data corresponding to at least one programming state sent by the memory after executing the first programming operation; The first programming operation is performed based on a first programming parameter; In response to the hard bit data and the soft bit data, sending first indication information to the memory; The first indication information is used to indicate an adjustment strategy of a second programming parameter when the memory performs a second programming operation; the first programming parameter and the second programming parameter both include an incremental step pulse programming parameter and a programming verification voltage.

2. The method according to claim 1, characterized in that In response to the hard bit data and the soft bit data, sending first indication information to the memory includes: comparing the hard bit data with the soft bit data to determine a bit error rate of the at least one programming state; The first indication information is generated according to the bit error rate.

3. The method according to claim 2, characterized in that When the bit error rate is lower than the first threshold, the adjustment strategy is: At least one of the incremental step pulse programming parameter and the program verification voltage is increased.

4. The method according to claim 3, characterized in that When the bit error rate is higher than the second threshold, the adjustment strategy is: At least one of the incremental step pulse programming parameter and the program verification voltage is reduced.

5. The method according to claim 4, characterized in that The first threshold is smaller than the second threshold.

6. The method according to claim 5, characterized in that When the bit error rate is within the range from the first threshold to the second threshold, the adjustment strategy is: The second programming parameter is maintained unchanged.

7. The method according to claim 4, characterized in that The first threshold is equal to the second threshold.

8. The method according to claim 7, characterized in that When the bit error rate is equal to the first threshold, the adjustment strategy is: The second programming parameter is maintained unchanged.

9. The method according to any one of claims 1 to 8, characterized in that: The first programming operation and the second programming operation correspond to different programming states of the same programming address.

10. The method according to any one of claims 1 to 8, characterized in that: The first programming operation and the second programming operation correspond to the same programming state or different programming states at different programming addresses.

11. The method according to claim 1, characterized in that: The first indication information is also used to indicate a read voltage and an erase voltage of a programming state obtained by programming according to the adjustment strategy.

12. A method for operating a memory, characterized in that: include: After executing the first programming operation, outputting hard bit data and soft bit data corresponding to at least one programming state; The first programming operation is performed based on a first programming parameter; receiving first indication information returned in response to the hard bit data and the soft bit data; The first indication information is used to indicate an adjustment strategy of a second programming parameter when the memory performs a second programming operation; the second programming parameter includes an incremental step pulse programming parameter and a programming verification voltage; In response to the first indication information, the adjustment strategy is executed.

13. The method according to claim 12, characterized in that The first indication information is generated in the following manner: comparing the hard bit data with the soft bit data to determine a bit error rate of the at least one programming state; The first indication information is generated according to the bit error rate.

14. The method according to claim 13, characterized in that When the bit error rate is lower than the first threshold, the adjustment strategy is: At least one of the incremental step pulse programming parameter and the program verification voltage is increased.

15. The method according to claim 13, characterized in that When the bit error rate is higher than the second threshold, the adjustment strategy is: At least one of the incremental step pulse programming parameter and the program verification voltage is reduced.

16. The method according to claim 15, characterized in that The first threshold is smaller than the second threshold.

17. The method according to claim 16, characterized in that When the bit error rate is between the first threshold and the second threshold, the adjustment strategy is: The second programming parameter is maintained unchanged.

18. The method according to claim 15, characterized in that The first threshold is equal to the second threshold.

19. The method according to claim 18, characterized in that When the bit error rate is equal to the first threshold, the adjustment strategy is: The second programming parameter is maintained unchanged.

20. The method according to claim 1, characterized in that The first indication information is also used to indicate a read voltage and an erase voltage of a programming state obtained by programming according to the adjustment strategy.

21. The method according to any one of claims 12 to 20, characterized in that: The first programming operation and the second programming operation correspond to different programming states of the same programming address.

22. The method according to any one of claims 12 to 20, characterized in that: The first programming operation and the second programming operation correspond to the same programming state or different programming states at different programming addresses.

23. A memory system, characterized in that: comprising one or more memories; and a memory controller coupled to the memories; The memory controller is configured to: receiving hard bit data and soft bit data corresponding to at least one programming state sent by the memory after executing a first programming operation; the first programming operation is performed based on a first programming parameter; In response to the hard bit data and the soft bit data, sending first indication information to the memory; The first indication information is used to indicate an adjustment strategy of a second programming parameter when the memory performs a second programming operation; the second programming parameter includes an incremental step pulse programming parameter and a programming verification voltage; The memory is configured as: receiving the first indication information; In response to the first indication information, the adjustment strategy is executed.

24. A computer-readable storage medium, characterized in that: Computer program instructions are stored, and the computer program instructions are executed by a processor to implement the method according to any one of claims 1 to 11, or to implement the method according to any one of claims 12 to 22.

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