Memory device with memory repair mechanism and method of operating same

Abstract

The invention relates to a memory device with a memory repair mechanism and a method of operating the same. A memory device includes a fuse and a latch for storing a repair segment locator and a repair address for each repair of one or more defective memory cells. A segment address determination circuit generates a valid segment address based on the repair address according to the repair segment locator and an address for a read or write operation. A comparator circuit is configured to determine whether the valid segment address matches the address for the read or write operation to replace the one or more defective memory cells with a plurality of redundant cells when the address for the read / write operation corresponds to the one or more defective memory cells.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the invention name “Memory device with memory repair mechanism and operation method thereof”, application number 202010824444.2 and application date August 17, 2020. Technical Field

[0003] The disclosed embodiments relate to devices, and in particular to semiconductor memory devices having a memory repair mechanism and methods of operating the same. Background Art

[0004] A memory device may include semiconductor circuits configured to utilize electrical energy to store and access information. Some examples of memory devices include volatile memory devices, nonvolatile memory devices, or a combination device.

[0005] Some memory devices, such as random access memory (RAM), such as dynamic RAM (DRAM), may include circuits configured to repair bit failures. Figure 1 1 is a partial block diagram of a memory device 100 that includes a set of repairable memory cells. The memory device 100 includes repair circuitry coupled to and / or integral with the memory cells 102 and configured to repair / replace one or more defective cells 104 within the corresponding set of memory cells 102. The memory cells 102 include repair or redundant cells as part of the repair circuitry that are designated to replace the defective cells 104. In other words, the repair cells are configured as spare memory cells that are not utilized in normal operation unless they are used to replace the actual / primary memory cells 102. Similar to the other memory cells 102, the repair cells are arranged in rows and columns (e.g., redundant rows 112 and redundant columns 114).

[0006] In replacing defective cells 104, memory device 100 may perform row repair and / or column repair. For row repair, memory device 100 may deploy and utilize redundant rows 112 to replace rows including defective cells 104. Figure 1 As illustrated in , the memory device 100 may replace the row R0 containing the defective cell 104 with the redundant row RR0. For column repair, the memory device 100 may deploy and utilize the redundant column 114 to replace the column including the defective cell 104. Figure 1 , memory device 100 may replace column C0 containing defective cell 104 therein with redundant column RC1.

[0007] The repair circuit includes fuse blocks configured to facilitate memory cell replacement. Each of the blocks includes a set of fuse latches directly coupled (i.e., one-to-one dedicated and fixed electrical and functional connections) to a redundant row or redundant column. The memory device 100 includes fuses or nonvolatile memory (not shown) located in a fuse array on the die. The information stored in the fuse array is broadcast and loaded into the fuse blocks in each bank at initialization.

[0008] As in Figure 1 , the fuse blocks include row fuse blocks 122 that are each directly coupled to one of the redundant rows 112, and column fuse blocks 124 that are each directly coupled to each of the redundant columns 114. Each fuse block is configured to store the address of the row / column that includes the defective cell 104. For example, when a redundant column is used to replace a defective column, the fuse block for the corresponding redundant column can be programmed (via, for example, blowing / setting fuse latches and / or associated fuses) to store the address of the defective column. The defective column can be effectively removed from the operation of the memory device 100. Subsequently, the redundant column is used to store and provide access to data in place of the replaced defective column. Summary of the invention

[0009] One aspect of the present invention relates to a memory device, comprising: a memory array including a plurality of memory cells and a plurality of redundant cells configured to replace one or more defective memory cells of the plurality of memory cells; a set of locator latches configured to latch a repair segment locator representing a segment within the memory array including the one or more defective memory cells; a set of address latches configured to latch a repair address representing a location of the one or more defective memory cells within the segment; a segment address determination circuit coupled to the set of locator latches and the set of address latches, the segment address determination circuit configured to generate an effective segment address based on the repair address according to the repair segment locator and at least a portion of an address for an operation; and a comparator circuit coupled to the segment address determination circuit and configured to determine whether the effective segment address matches the address for the operation to replace the one or more defective memory cells with the plurality of redundant cells when the address for the operation corresponds to the one or more defective memory cells.

[0010] Another aspect of the present invention relates to a method of operating a memory device, the memory device including a plurality of memory cells and a plurality of redundant cells configured to replace one or more defective memory cells among the plurality of memory cells, the method comprising: obtaining a repair segment locator representing a segment within the memory array including the one or more defective memory cells; obtaining a repair address representing a location of the one or more defective memory cells within the segment; receiving an operation address for a read or write operation; providing the repair address as a valid segment address when the repair segment locator matches the operation address or a portion thereof; and replacing the one or more defective memory cells based on the valid segment address, wherein when an address for the read / write operation corresponds to the one or more defective memory cells, the one or more defective memory cells are replaced using the plurality of redundant cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a portion of a memory device including a set of repairable memory cells.

[0012] Figure 2 is a block diagram of an example memory device in accordance with an embodiment of the present technology.

[0013] Figure 3A According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0014] Figure 3B is a detailed block diagram of a selection circuit according to an embodiment of the present technology.

[0015] Figure 3C is a detailed block diagram of a selection circuit according to an embodiment of the present technology.

[0016] Figure 4A is a block diagram of a portion of a memory device according to an embodiment of the present technology.

[0017] Figure 4B is a detailed block diagram of a segment address determination circuit according to an embodiment of the present technology.

[0018] Figure 4C is a detailed block diagram of a segment address determination circuit according to an embodiment of the present technology.

[0019] Figure 4D is a detailed block diagram of a segment address determination circuit according to an embodiment of the present technology.

[0020] Figure 4E is a detailed block diagram of a segment address determination circuit according to an embodiment of the present technology.

[0021] Figure 5A is a detailed block diagram of a segment address determination circuit according to an embodiment of the present technology.

[0022] Figure 5B is an example block diagram of a segmented matching circuit according to an embodiment of the present technology.

[0023] Figure 6 According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0024] Figure 7 is a flowchart illustrating an example method of operating a device according to an embodiment of the present technology.

[0025] Figure 8 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. DETAILED DESCRIPTION

[0026] As described in more detail below, the technology disclosed herein relates to an apparatus (e.g., a memory device, a memory system), a system having one or more memory devices, a related method for repairing a memory cell, etc. The apparatus includes a segment address determination circuit located between a local fuse latch and an address decoder and configured to allocate fuses according to defects and repair memory cells. The local fuse latch may include an additional fuse configured to store an address of an affected domain including a defective cell. The segment address determination circuit may use the domain address to replace the defective cell with a redundant cell.

[0027] Conventional devices have a set of repair fuse latches that are hardwired (i.e., dedicated one-to-one electrical and functional connections) directly to the corresponding redundant memory cells. Therefore, the repair capabilities of these conventional devices are limited by the worst performing repair area (e.g., a portion within the memory array). Due to the unpredictability of failures, each redundant element on the die, such as each redundant column and each redundant row, includes a set of repair fuse latches. However, in a typical setting, only one pair of repair areas per die uses all repairs, which leaves many of the repair elements (e.g., tens of thousands or more) and even more (e.g., tens of thousands) of fuses and fuse latches unused.

[0028] In contrast, the segmented address determination circuit allows the embodiments described below to associate repair fuse latch groups with defects rather than repair elements (e.g., redundant columns). Thus, the embodiments described below may include both a reduced number of fuse latches per bank logic and the size of the fuse array to minimize to no impact on yield. The reduction may be achieved by adding fuses and fuse latches that address repair regions or segments while reducing the number of fuse groups to match the worst case defect rate, thereby resulting in a net fuse reduction.

[0029] Figure 2 2 is a block diagram of an example memory device 200 (e.g., a semiconductor die assembly including a three-dimensional integration (3DI) device or a die stack package) according to an embodiment of the present technology. For example, the memory device 200 may include a DRAM or a portion thereof including one or more dies / chips.

[0030] The memory device 200 may include a memory cell array such as a memory array 250. The memory array 250 may include a plurality of banks (e.g., banks 0 to 15), and each bank may include: a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a number of different memory media types (including capacitive, magnetoresistive, ferroelectric, phase change, etc.). The selection of the word lines WL may be performed by a row decoder 240, and the selection of the bit lines BL may be performed by a column decoder 245. A sense amplifier (SAMP) may be provided for the corresponding bit lines BL and may be connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transfer gate (TG) that may be used as a switch. The memory array 250 may also include plate lines and corresponding circuitry for managing their operation.

[0031] The memory device 200 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus, respectively, to receive a command signal (CMD) and an address signal (ADDR). The memory device 200 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, and VDDQ.

[0032] The command terminal and address terminal can be provided with address signals and bank address signals from the outside ( Figure 2 200). The address signal and the bank address signal supplied to the address terminal may be transferred to the address decoder 210 via the command / address input circuit 205. The address decoder 210 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 240, and supply a decoded column address signal (YADD) to the column decoder 245. The address decoder 210 may also receive the bank address signal and supply the bank address signal to both the row decoder 240 and the column decoder 245.

[0033] The command and address terminals may be provided with a command signal (CMD), an address signal (ADDR), and a chip select signal (CS) from a memory controller and / or a nefarious chipset. The command signal may represent various memory commands from the memory controller (e.g., including access commands that may include a read command and a write command). The chip select signal may be used to select the memory device 200 in response to the command and address provided to the command and address terminals. When a valid chip select signal is provided to the memory device 200, the command and address may be decoded and a memory operation may be performed. The command signal may be provided to the command decoder 215 as an internal command signal ICMD via the command / address input circuit 205. The command decoder 215 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). Command decoder 215 may further include one or more registers for tracking various counts or values ​​(eg, a count of refresh commands received by memory device 200 or self-refresh operations performed by memory device 200).

[0034] Read data may be read from a memory cell specified by a row address (e.g., an address with a valid command) and a column address (e.g., an address with a read) in the memory array 250. The read command may be received by the command decoder 215, which may provide an internal command to the input / output circuit 260, so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 255 and the input / output circuit 260 according to the RDQS clock signal. The read data may be output from the data terminals DQ, RDQS, DBI, and DMI in the memory device 200, for example, in the mode register ( Figure 2 The read data is provided at a time defined by the read delay information RL programmed in the memory device 200 (not shown). The read delay information RL may be defined in terms of clock cycles of the CK clock signal. For example, when providing the associated read data, after receiving a read command by the memory device 200, the read delay information RL may be a number of clock cycles of the CK signal.

[0035] The write data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 215, which provides an internal command to the input / output circuit 260, so that the write data may be received by the data receiver in the input / output circuit 260 and supplied to the memory array 250 via the input / output circuit 260 and the read / write amplifier 255. The write data may be written into the memory cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write delay WL information. The write delay WL information may be programmed in the memory device 200, for example, in the mode register. The write delay WL information may be defined according to the clock cycle of the CK clock signal. For example, when the associated write data is received, after the write command is received by the memory device 200, the write delay information WL may be several clock cycles of the CK signal.

[0036] The power supply terminal may be provided with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 270. The internal voltage generator circuit 270 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 240, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 250, and the internal potential VPERI may be used in many other circuit blocks.

[0037] The power supply terminal may also be provided with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 260 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 260 so that the power supply noise generated by the input / output circuit 260 is not propagated to other circuit blocks.

[0038] The clock terminal and the data clock terminal may be provided with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, WCKF may be supplied to the clock input circuit 220. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have relative clock levels and simultaneously switch between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal switches from a low clock level to a high clock level, the complementary clock signal switches from a high clock level to a low clock level, and when the clock signal switches from a high clock level to a low clock level, the complementary clock signal switches from a low clock level to a high clock level.

[0039] The input buffer included in the clock input circuit 220 may receive an external clock signal. For example, when enabled by the clock / enable signal from the command decoder 215, the input buffer may receive the clock / enable signal. The clock input circuit 220 may receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 230. The internal clock circuit 230 may generate an internal clock signal ICLK based on the received internal clock signal ICLK and the clock enable ( Figure 2 For example, the internal clock circuit 230 may include a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 215. Figure 2 200 ). The internal clock circuit 230 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 260 and may be used as a timing signal to determine the output timing of read data and / or the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from or input to the memory device 200 at different data rates. When a higher memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 235 and various internal clock signals may be generated accordingly.

[0040] The memory device 200 may be connected to any of a number of electronic devices or components thereof that are capable of using the memory for temporary or permanent storage of information. For example, the host device of the memory device 200 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a number of other products. In one embodiment, the host device may be directly connected to the memory device 200; although in other embodiments, the host device may be indirectly connected to the memory device (e.g., via a networking connection or through an intermediate device).

[0041] The memory device 200 may include a repair circuit 211 that may be coupled to one or more address decoders, such as the address decoder 210, the row decoder 240, and / or the column decoder 245. The repair circuit 211 may be configured to repair defects in memory cells. For example, the repair circuit 211 may replace defective memory cells with redundant memory cells in the memory array 250. As described in more detail below, the repair circuit 211 may include fuses and local fuse latches configured to store location information (e.g., addresses and / or affected domain identifiers) associated with the defective memory cells. The repair circuit 211 may further include a segment address determination circuit configured to apply redundant memory cells and / or addresses stored in the fuses according to the location information. In this way, fuses may be utilized across domains (i.e., column domains) within the memory array 250, such as by connecting / assigning to different redundant cells / domains rather than being limited to dedicated connections. Therefore, the number of repairs, fuses, and fuse latches may be reduced to account for the actual failure rate, thereby reducing resources and / or device footprint associated with the repairs, fuses, latches, etc.

[0042] Figure 3A According to an embodiment of the present invention Figure 2 200. For example, Figure 3A The diagram illustrates the repair circuit 211, the position decoder (e.g., Figure 2 Column decoder 245) and Figure 2 2. In some embodiments, the repair circuit 211 may include a local fuse latch region 302 coupled to a selection circuit 304 and a comparator circuit 306. In some embodiments, the memory device 200 may include a grouping of one selection circuit 304 and one comparator circuit 306 for each redundant memory grouping (e.g., for each redundant column or row).

[0043] The local fuse latch area 302 may include fuse latches and / or fuses configured to store / latch location information (e.g., address) associated with the repair. The selection circuit 304 may include circuitry configured to select a repair location / address corresponding to the current read / write operation. The comparator circuit 306 may compare an incoming address (e.g., a read or write address from a host) with a latched address for any match. The output of the comparator circuit 306 may be used by a location decoder to access a target location within a regional plane 310 (e.g., a portion of the memory array 250, such as an area within one of the arrays). The regional plane 310 may include memory cells grouped according to function or purpose. For example, the memory array 250 includes segmentation 312 (e.g., column and / or row segmentation) and / or redundant memory 314 (i.e., redundant columns and / or redundant rows).

[0044] As an illustrative example, information stored in the fuse (e.g., an address associated with a repair) may be loaded or latched into a corresponding latch in the local fuse latch area 302. Thus, the local fuse latch area 302 may store a repair address 322 (e.g., an address of an original memory cell, such as a column including one or more defective cells). The selection circuit 304 may select one of the repair addresses 322 associated with the segment 312 that is valid for the current read / write operation (corresponding to the redundant memory 314, such as one of the redundant columns). In some embodiments, the selection includes selecting one of the direct connections that ties the fuse latch to the redundant memory 314 of each of the segments 312.

[0045] Using column repair as an illustrative example, the repair address 322 may represent a memory column that includes one or more defective cells. The repair address may be used by the select circuit 304 and the comparator circuit 306 to determine when a read or write operation is directed to a defective memory column. In some embodiments, the select circuit 304 may receive a column segment identifier (e.g., the output of the column row segment select circuit (CRSegSelect)) based on an effective row address (ACT RA) associated with the read or write command. The comparator circuit 306 may receive the output of the select circuit 304 (e.g., the repaired main array column select) and the read / write column address (RD / WRCA) for comparison. When the RD / WR CA (e.g., the address of the defective column) matches the output of the select circuit 304 (e.g., the repair address 322), the comparator circuit 306 may generate a flag. The decoder may use the output of the comparator to access a redundant column that is assigned to replace the defective column for reading or writing instead of the defective column itself.

[0046] To facilitate repair, the local fuse latch area 302 may include a number of fuses and / or fuse latches corresponding to the first measurement 332 and the second measurement 334. For example, the first measurement 332 may correspond to a number of segments and / or a number of available repairs (e.g., redundant columns). In one example embodiment, an array area (e.g., a bank, a die, and / or an array) may correspond to 1 Gb or more of memory. The memory cells in the array area may be further configured as four column planes (e.g., four examples of the area plane 310), each including four redundant columns. Each column plane may include 10 column segments, which in some embodiments may be decoded by RA<15:4>. Based on this configuration, four repairs may be available for each column segment (i.e., 40 repairs per column plane and 160 repairs per bank). Therefore, the first measurement 332 may correspond to the total number of repairs available for the column plane (e.g., 40 repairs). In other words, the first measurement 332 may correspond to the number of fuse latch groups that each correspond to a repair. Also, the second measurement 334 may correspond to the amount of information (e.g., the number of bits) required for each repair. In some embodiments, the second measurement 334 may correspond to eight bits (i.e., seven column address bits and one enable bit) of the repair address 322. Thus, the local fuse latch area 302 may include 40 fuse latch groups (i.e., 320 total fuse latches) each including eight latches.

[0047] In some embodiments, each redundant column select (RCS) in each column segment (e.g., each redundant column) may include a repair fuse set. The read address may be decoded to a hot bus representing the segment containing the valid row. The corresponding fuse set may be multiplexed to the RCS match for column time comparison. To illustrate the details of the selection circuit 304 and the comparator circuit 306, Figure 3B and Figure 3C 3 is a block diagram of a portion of a memory device 200 (eg, a selection circuit 304 and a comparator circuit 306) according to an embodiment of the present technology. For example, Figure 3B Illustrated is a control circuit 380 (eg, selection circuit 304, comparator circuit 306, and / or portions thereof) including a buffer 382 for controlling assignment or repair using redundant column RCSO.

[0048] As discussed above, the local (column) fuse latch region 302 may include 10 instances of a repair address 322 that is each eight bits long (ie, one repair address per column segment 312). 1-9Each of the buffers 382 may be received by each of the buffers 382. Each of the buffers 382 is controlled by a column segment identifier 384 (e.g., an output of a column row segment select circuit (CRSegSelect)) that identifies a column segment associated with a read / write address. In other words, the column segment identifier 384 may be valid when the address of the read / write operation is associated with the corresponding column segment. Thus, the select circuit 304 may generate an effective segment address 386 (ActiveSeg RCS0<7:0>) as a repair address 322, which is associated with the column segment targeted by the read / write command. The comparator circuit 306 may receive and compare the effective segment address 386 with a read / write column address 388 (CA<6:0>) to generate a match flag 389 for the redundant column RCS0. As described above, the column decoder may access the redundant column RCS0 in place of the replaced column indicated by the read / write column address 388.

[0049] and, Figure 3C The diagram illustrates a control circuit 390 (e.g., selection circuit 304, comparator circuit 306, and / or portions thereof) including a multiplexer 392 for controlling assignment or repair using redundant column RCSO. Similar to control circuit 380, control circuit 390 may correspond to 10 instances of repair address 322. Repair address 322 may be received by multiplexer 392. Multiplexer 392 may be controlled by column segment identifier 384 (ColSeg<9:0>) to generate valid segment address 386. In other words, multiplexer 392 may generate valid segment address 386 by selecting one of repair addresses 322 according to column segment identifier 384. As described above, comparator circuit 306 may generate match flag 389 based on comparing valid segment address 386, read / write column address 388.

[0050] Figure 4A According to an embodiment of the present invention Figure 2 200. For example, Figure 4A The diagram illustrates the repair circuit 211, the position decoder (e.g., Figure 2 Column decoder 245) and Figure 2 2. In some embodiments, the repair circuit 211 may include a local fuse latch region 402 coupled to a segment address determination circuit 404 including a comparator circuit 406. In some embodiments, the memory device 200 may include a grouping of one selection circuit 304 and one comparator circuit 306 for each redundant memory grouping (e.g., for each redundant column or row).

[0051] The local fuse latch area 402 may include fuse latches and / or fuses configured to store / latch location information (e.g., addresses) associated with the repair. The segment address determination circuit 404 may include circuits configured to determine a replacement / defective location based on a segment (e.g., one of the regional planes, such as a column plane) that includes a defect. The comparator circuit 406 may compare an incoming address (e.g., a read or write address from a host) with a latched address for any match. The output of the comparator circuit 406 may be used by a location decoder to access a target location within a regional plane 410 (e.g., a portion of the memory array 250, such as a region within one of the arrays). The regional plane 410 may include memory cells grouped according to function or purpose. For example, the memory array 250 includes segmentation 412 (e.g., column and / or row segmentation) and / or redundant memory 414 (i.e., redundant columns and / or redundant rows). Furthermore, the memory array 250 may include one or more repair planes 415 (e.g., dedicated column planes) that include redundant memory cells designated for global repair. Similarly, the memory device 200 may use the comparator circuit 406 or its derivatives in implementing global repair and swapping memory input / output (MIO) from the repair plane 415 with a repaired primary array plane (e.g., defective column plane) in the data path.

[0052] As an illustrative example, information stored in the fuse (e.g., an address associated with a repair) may be loaded or latched into a corresponding latch in the local fuse latch area 402. Thus, the local fuse latch area 402 may store a repair address 422 (e.g., an address of an original memory cell, such as a column including one or more defective cells). The local fuse latch area 402 may further include repair segment locators 424 that each correspond to one of the repair addresses 422. The repair segment locators 424 may identify the segment 412 associated with the corresponding repair address 422. Using the repair segment locators 424, the segment address determination circuit 404 may determine the repair address 422 according to the segment 412 that is valid for the current read / write operation. In other words, the repair segment locators 424 represent fuse addresses indicating the segments 412 for each fuse and fuse latch group.

[0053] Using column repair as an illustrative example, repair address 422 may represent a memory column that includes one or more defective cells. Thus, segment 412 may represent a column segment / domain. Repair segment locators 424 may each identify a column segment that includes a defective column that is replaced by redundant memory. As described in detail below, segment address determination circuit 404 and comparator circuit 406 may use repair address 422 and repair segment locator 424 to determine when a read or write is directed to a corresponding defective memory column. In some embodiments, segment address determination circuit 404 may receive a column segment identifier (e.g., an output of a column row segment select circuit (CRSegSelect)) based on an effective row address (ACT RA) associated with a read or write command. Comparator circuit 406 may receive the output of segment address determination circuit 404 (e.g., a redundant column select (RCS) address associated with a column segment corresponding to a reader write command) and a read / write column address (RD / WR CA) for comparison. Comparator circuit 406 may generate a flag when RD / WR CA (e.g., the address of the defective column) matches the output of segment address determination circuit 404 (e.g., repair address 422). The decoder may use the output of the comparator to access a redundant column assigned to replace the defective column for reading or writing instead of the defective column itself.

[0054] To facilitate repair, the local fuse latch region 402 may include a number of fuses and / or fuse latches corresponding to a first measurement 426 and a second measurement 428. For example, the first measurement 426 may correspond to a number of segments and / or a number of available repairs, and the second measurement 428 may correspond to the amount of information (e.g., a number of bits) required for each repair. Based on the repair segment locator 424, the second measurement 428 may be greater than Figure 3A However, since fuses and / or fuse latches can be targeted to different column planes, the total number of repairs can be reduced to match the actual failure rate rather than all possible failure scenarios. Therefore, the first measurement 426 can be less than Figure 3A The first measurement 332 of and reduces the total number of fuses, fuse latches and / or repairs.

[0055] In one example embodiment, an array region (e.g., a bank) may correspond to 1 Gb of memory. The memory cells in the array region may be further configured as four column planes (e.g., four instances of region plane 410) each including four redundant columns. Each column plane may include 10 column segments, which in some embodiments may be decoded by RA<15:4>. Based on the repair segment locator 424, the segment address determination circuit 404, the repair may be independent of (i.e., not directly tied to) the column segment. Thus, the first measurement 426 may be 10 or less (e.g., representing 3 or 4 repairs per column plane, and 12 or 16 repairs per bank), which is less than the value corresponding to the above for 15:4>. Figure 3A The first measurement 332 of 40 repairs (ie, repairing four redundant columns and 10 column segments) is described in the example illustrated in FIG.

[0056] The increase in the second measurement 428 (eg, Figure 3A ) may correspond to the number of column segments. For example, the repair segment locator 424 may be four bits long to identify 10 unique column segments. When the repair address 422 is eight bits long (as described above), the second measurement 428 may be 12 bits. However, the increase in the second measurement 428 may be offset by the decrease in the first measurement 426, thereby reducing the total number of fuses and / or fuse elements in the local fuse latch area 402. For example, the first measurement 426 may be reduced to 12 fuse latch groups (i.e., 12 repairs), which enables up to four repairs and any segment, up to 12 repairs per region and / or 48 repairs per bank. Since each repair requires 12 bits, the local fuse latch area 402 may include 144 total latches, instead of 144. Figure 3A 320 total fuse latches in the local fuse latch area 302.

[0057] To illustrate the details of the segment address determination circuit 404 and the comparator circuit 406, Figure 4B , Figure 4C , Figure 4D and Figure 4E 4 is a block diagram of a portion of a memory device 200 (eg, a segment address determination circuit 404 and a comparator circuit 406) according to an embodiment of the present technology. For example, Figure 4B Illustrated is a control circuit 430 (eg, segment address determination circuit 404, comparator circuit 406, and / or portions thereof) that includes a segment matching circuit 432 for controlling assignment or repair using redundant column RCSO.

[0058] As discussed above, the local (column) fuse latch area 402 may include a reduced number of repair addresses 422 (Def0-2RCS0<7:0>), each having a corresponding repair segment locator 424 (Def0-2RCS0<11:8>). Each of the segment matching circuits 432 (e.g., a comparator circuit) may receive one repair address 422 and one repair segment locator 424 corresponding to a defective memory location. The segment matching circuit 432 may receive a column segment identifier 434 (ColSegEnc<3:0>) (e.g., an output of a column row segment select circuit (CRSegSelect)) that identifies a column segment associated with a read / write address. The segment matching circuit 432 may generate an effective segment address 436 (ActiveSeg RCS0<7:0>) for a redundant column (e.g., RCS0) based on the column segment identifier 434. For example, when the paired repair segment locator 424 (e.g., 4 blown ColSeg bits) matches the column segment identifier 434 (ColSegEnc), the segment matching circuit 432 may output the repair address 422 as the effective segment address 436, e.g., at a row time. In other words, the effective segment address 436 may be the repair address 422 associated with the column segment targeted by the read / write command. The comparator circuit 406 may receive and compare the effective segment address 436 with the read / write column address 438 (CA<6:0>) to generate a match flag 439 for the redundant column. As described above, the column decoder may access the redundant column in place of the replaced column indicated by the read / write column address 438.

[0059] Figure 4C The diagram illustrates a control circuit 450 (e.g., segment address determination circuit 404, comparator circuit 406, and / or portions thereof) including a multiplexer 456 for controlling assignment or repair using a redundant column (e.g., RCS0). The control circuit 450 may be similar to the control circuit 450 described above. Figure 4B The control circuit 430 of the embodiment of the present invention can be used to control the control circuit 430 of the embodiment of the present invention. For example, the local (column) fuse latch area 402 can include a reduced number of repair addresses 422 (Def0-2 RCS0<7:0>), each of which has a corresponding repair segment locator 424 (Def0-2 RCS0<11:8>). Moreover, the comparator circuit 406 can receive the effective segment address 436 (ActiveSeg RCS0<7:0>) and compare it with the read / write column address 438 (CA<6:0>). Based on the comparison, the comparator circuit 406 can generate a match flag 439 for the redundant column.

[0060] The control circuit 450 may include segment matching circuits 452 for controlling assignment or repair using redundant columns (e.g., RCS0). Each of the segment matching circuits 452 (e.g., comparator circuits) may receive one repair segment locator 424 corresponding to a defective memory location and a column segment identifier 434 (ColSegEnc<3:0>) for comparison. Based on the comparison, the segment matching circuits 452 may generate one or more selection signals 454 indicating whether one or more of the repair segment locators 424 correspond to the column segment identifier 434. For example, each of the segment matching circuits 452 may generate a unique selection signal 454 indicating whether the received repair segment locator 424 matches the column segment identifier 434.

[0061] The control circuit 450 may further include a multiplexer 456 that receives the repair address 422 along with the select signal 454. The multiplexer 456 may be configured to generate the effective segment address 436 according to the select signal 454. For example, the multiplexer 456 may generate the effective segment address 436, which is one of the repair addresses 422 that matches the repair segment locator 424 indicated by the select signal 454. In other words, the segment matching circuit 452 may identify which of the repair segment locators 424 corresponds to the current row address and generate the select signal 454 accordingly. The multiplexer 456 may transmit one of the repair addresses 422 that matches the repair segment locator 424 indicated by the select signal 454.

[0062] In some embodiments, multiplexer 456 may be configured to handle mismatch situations (e.g., when the current read / write address is unrelated to the segment associated with the stored address). For example, multiplexer 456 may precharge or implement a weak pull-up or pull-down (via, for example, enabling XOR) on the Active Seg enable fuse / bit switch so that if any of the defects do not match the segment, then RCS matching is disabled. Multiplexer 456 may generate an output default setting based on the NOR of select signal 454. For mismatch situations, the output of the NOR may be routed to comparator circuit 406 and force matching to be disabled.

[0063] Figure 4D The diagram illustrates a control circuit 470 (e.g., segment address determination circuit 404, comparator circuit 406, and / or portions thereof) including a buffer 472 for controlling assignment or repair using a redundant column (e.g., RCS0). The control circuit 470 may be similar to the control circuit 470 described above. Figure 4CThe control circuit 470 may include a segment matching circuit 452 that generates a selection signal 454 based on comparing the repair segment locator 424 to the column segment identifier 434, as described above. Also, the comparator circuit 406 may receive the effective segment address 436 (ActiveSeg RCS0<7:0>) and compare it to the read / write column address 438 (CA<6:0>). Based on the comparison, the comparator circuit 406 may generate a match flag 439 for the redundant column.

[0064] In some embodiments, the control circuit 470 may include a buffer 472 configured to generate the effective segment address 436 according to the selection signal 454. Each of the buffers 472 may receive one of the repair addresses 422 and be controlled by one of the selection signals 454. Thus, the buffers 472 may generate the effective segment address 436 based on releasing or transmitting one or more of the repair addresses according to the selection signal 454. In other words, the segment matching circuit 452 may identify which of the repair segment locators 424 corresponds to the current read / write address and generate the selection signal 454 accordingly. The buffer 472 may transmit one of the repair addresses 422 that matches the repair segment locator 424 indicated by the selection signal 454.

[0065] In some embodiments, the control circuit 470 may include a repair disable circuit 474 configured to handle mismatch situations (e.g., when the current read / write address is unrelated to the segment associated with the stored address). For example, the repair disable circuit 474 may include a buffer that receives a default disable repair address 476, which is coupled to or controlled by a NOR gate that receives the select signal 454. The repair disable circuit 474 may pre-charge or implement a weak pull-up or pull-down on the Active Seg enable fuse / bit switch (via, for example, enabling XOR) so that if any of the defects are evenly matched segments, then RCS matching is disabled. The repair disable circuit 474 may generate a default disable repair address 476 (e.g., for mismatch situations) based on the NOR of the select signal 454.

[0066] Figure 4E The diagram illustrates a control circuit 490 (e.g., segment address determination circuit 404, comparator circuit 406, and / or portions thereof) including a buffer 472 for controlling assignment or repair using a redundant column (e.g., RCS0). The control circuit 490 may be similar to the control circuit 490 described above. Figure 4C The control circuit 450 and / or Figure 4DFor example, the control circuit 490 may include a segment match circuit 452 that generates a select signal 454 based on comparing the repair segment locator 424 to the column segment identifier 434, as described above. Also, the comparator circuit 406 may receive the effective segment address 436 (ActiveSeg RCS0<7:0>) and compare it to the read / write column address 438 (CA<6:0>). Based on the comparison, the comparator circuit 406 may generate a match flag 439 for the redundant column. The control circuit 490 may further include a buffer 472 (or alternatively, a buffer 472) configured to generate the effective segment address 436 according to the select signal 454. Figure 4C Multiplexer 456).

[0067] In some embodiments, the control circuit 490 may include a repair disabling circuit 492 that generates a mismatch signal 494 based on the selection signal 454. The repair disabling circuit 492 may be similar to Figure 4D The repair disable circuit 474 of FIG. 4A is shown in FIG. 4B , but a separate signal (mismatch signal 494) is provided instead of providing Figure 4D The default disabled repair address 476 of the comparator circuit 406 is used as the effective segment address 436. For example, the repair disable circuit 492 can be a NOR gate that generates the mismatch signal 494 as the NOR of the select signal 454. The mismatch signal 494 can indicate a mismatch condition to the comparator circuit 406. Therefore, the comparator circuit 406 can deactivate the match flag 439 to indicate a mismatch based on the active state of the mismatch signal 494 independent of the effective segment address 436.

[0068] The segment address determination circuit 404 and / or the repair disable circuit 474 / 494 provide for Figure 2 The reduced resources and reduced circuit footprint of the memory device 200 of the embodiment of the present invention. The number and / or size of multiplexers, routing, and logic associated with the fuse latch groups can be reduced along with the reduction in the number of fuse latch groups. Figure 3A and Figure 4A ), the segment address determination circuit 404 and / or the repair disable circuit 474 / 494 may increase the number and / or size of multiplexers, routing, and logic from a multiple of 10 (e.g., for Figure 3A 10 fuse latch group instances) to a multiple of 3 (e.g., for Figure 4A 3 fuse latch group examples).

[0069] Figure 5A is a segment address determination circuit (eg, control circuit 502, for example, for Figure 4ADetailed block diagram of the segment address determination circuit 404, comparator circuit 406, and / or portions thereof, illustrated in FIG. 5 . The control circuit 502 is configured to control assignment or repair using a redundant column (e.g., RCS0). The control circuit 502 may be configured to utilize an coded column segmentation (ECS) scheme, where the segmentation is coded and fuse-supported in each column repair fuse set. The control circuit 502 may compare each repaired fused segment with the accessed segment after an activate command.

[0070] Due to varying digit line lengths, the number of segments per region may be non-binary, which may result in unused decodings from segment fuses that are not aligned with the physical segments. When the number of segments is binary, new decodings may be added. Figure 2 The memory device 200 and / or control circuitry 502 may be configured to use one or more of the unused decodes to indicate (via, for example, corresponding fuse settings or CA) a defective full column selection. A defective full column selection may correspond to a defect across many sectors and segments in higher metal levels within the array. The unused decodes may indicate a defective full column selection instead of a defective digit line or local column selection, for example, for a defect across at most two sectors or segments in the array.

[0071] As discussed in detail below, control circuitry 502 may include logic to make a positive match when a fused segment address is blown to a decode corresponding to a defective full column selection (e.g., for responding to a higher level defect). Control circuitry 502 may include logic to make a positive match when a fused segment address matches an activated segment address and / or when a fused segment address is blown to a decode reserved for full column repair. Control circuitry 502 may allow the reserved decode to match on any segment and remove the limitation of tying one repair directly to a single row space. The control circuit 502 may include segment matching circuits 504 (e.g., comparator circuits) that each receive a column segment identifier 434 (ColSegEnc<3:0>, e.g., an output of a column row segment select circuit (CRSegSelect)) and one repair segment locator 508 corresponding to a defective memory location and / or a retained decoding (e.g., one of Rep0 RCS0<11:8>-Rep8 RCS0<11:8> for RCS0). One of the repair segment locators 508 may correspond to a retained decoding that corresponds to a defective full column selection, e.g., for responding to / repairing a higher level defect. Each of the segment matching circuits 504 may generate a unique selection signal 506 indicating whether the received repair segment locator 508 matches the column segment identifier 434.

[0072] The control circuit 502 may include a buffer 503 for controlling assignment or repair using a redundant column (e.g., RCS0). The buffer 503 may be configured to generate a valid segment address 436 according to a select signal 506. Each of the buffers 503 may receive one of the repair addresses 510 and be controlled by one of the select signals 506. Thus, the buffer 503 may generate a valid segment address 436 based on releasing or transmitting one or more of the repair addresses according to the select signal 506. In other words, the segment matching circuit 504 may identify which of the repair segment locators 508 corresponds to the current read / write address and generate the select signal 506 accordingly. The buffer 503 may transmit one of the repair addresses 510 that matches the repair segment locator 508 indicated by the select signal 506.

[0073] The control circuit 502 may include a control circuit similar to the control circuit (eg, Figure 4D The control circuit 470 and / or Figure 4E For example, the control circuit 502 may include a comparator circuit 406 that receives an active segment address 436 (ActiveSeg RCS0<7:0>) and compares it to a read / write column address 438 (CA<6:0>). Based on the comparison, the comparator circuit 406 may generate a match flag 439 for a redundant column (e.g., RCS0). The control circuit 502 may also include a repair disable circuit 512 that generates a mismatch signal 494 based on the select signal 506. The repair disable circuit 512 may be similar to Figure 4D Repair of the deactivation circuit 474 and / or Figure 4E The repair disable circuit 492 of FIG. 4A is shown in FIG. 4B , but a separate signal (mismatch signal 494) is provided instead of providing Figure 4D The default disabled repair address 476 of the comparator circuit 406 is used as the effective segment address 436. For example, the repair disable circuit 512 can be a NOR gate that generates the mismatch signal 510 as the NOR of the select signal 506. The mismatch signal 494 can indicate a mismatch condition to the comparator circuit 406. Therefore, the comparator circuit 406 can deactivate the match flag 439 to indicate a mismatch based on the active state of the mismatch signal 494 independent of the effective segment address 436.

[0074] The segment matching circuit 504 and / or the repair disabling circuit 512 provide reduced resources and reduced circuit footprint for the memory device 2002. The number and / or size of multiplexers, routing, and logic associated with the fuse latch groups can be reduced along with the reduction in the number of fuse latch groups. Figure 3A and Figure 4A), the segment matching circuit 504 and / or the repair disabling circuit 512 can reduce the number and / or size of multiplexers, routing, and logic. For example, the segment matching circuit 504 and / or the repair disabling circuit 512 can reduce the resources used for routing and logic by reducing the routing / multiplexing of the column fuse sets from 10:1 to 4:1. In addition, the control circuit 502 can use fewer (e.g., one) repair fuse sets and / or fewer full RCS to implement repairs for full column / global column defects. In contrast (i.e., without the control circuit 502), the repair for full column / global column defects can use each repair fuse set without leaving any repair fuse set for any other hard column defects or single bits. In this way, the control circuit 502 provides improved yield benefits and reduced occupied area caused by reduced fuse sets. In addition, for the ECS scheme, the control circuit 502 can make the repair usage the same as the conventional non-ECS scheme.

[0075] Figure 5B is an example block diagram of a segment matching circuit (e.g., one of the segment matching circuits 504) according to an embodiment of the present technology. In some embodiments, the column region may be divided into 13 column segments. As such, four bits may be used to decode one of the 13 segments targeted for repair, thereby leaving unused decodings (i.e., three decodings corresponding to the difference between the 13 segments and the 16 available 4-bit values). One or more of the remaining unused decodings (e.g., "0000" and "1111") may be used to indicate whether the repair is unused or disabled. One or more of the remaining unused decodings (e.g., "1110") may be used to indicate that the associated fused CA addresses a full column defect, where each segment needs to be activated.

[0076] The segment matching circuit 504 may include a circuit configured to determine Figure 5A Does the column segment identifier 434 match Figure 5A The segment portion 552 (eg, circuitry / logic) of the repair segment locator 508. In some embodiments, the segment portion 552 may be configured to be in the column segment identifier 434 (Act SEG <0> -Act SEG <3> ) and repair segment locator 508 (fuse SEG <0> - SEG Fused <3> ). For example, the segment portion 552 may include NOR gates (XNORs) that each compare the corresponding bits of the column segment identifier 434 and the repair segment locator 508. The output of the XNOR may be provided to a logical AND to determine whether the column segment identifier 434 matches the repair segment locator 508.

[0077] The segment matching circuit 504 may further include a full column defect portion 554 (e.g., circuitry / logic) configured to determine whether the repair segment locator 508 matches a full column defect portion 554 reserved for activating the decoding of each segment. For example, the full column defect portion 554 may include one or more inverters corresponding to the reserved decoded values ​​and a logical AND configured to detect when the repair segment locator 508 matches the reserved decoded values. Figure 5B In the example illustrated in FIG. , the retained decoded value may correspond to “1110”. Thus, the full column defect portion 554 may include a portion for the blown SEG. <0> Thus, when the repair segment locator 508 matches the retained decoded value, the corresponding logical AND of the column defect portion 554 may produce a logical "1" indicating a match.

[0078] The segment matching circuit 504 may include a combining portion 556 (e.g., a logical OR) configured to compare the comparison results described above (e.g., the outputs from the segment portion 552 and the full column defect portion 554, such as corresponding logical ANDs). The output of the combining portion 556 (SegMatch) may identify whether the column segment identifier 434 matches the repair segment locator 508, and / or whether the repair segment locator 508 matches the decode reserved for activating each segment. The SegMatch output may correspond to Figure 5A The selection signal 506 is provided.

[0079] Figure 6 According to an embodiment of the present invention Figure 2 2 is a block diagram of a portion of a memory device 200. Figure 6 Graphic instructions for use Figure 4A Redundant memory 414 and / or Figure 4A Repair plane 415 for Figure 4A An example of repair of the area plane 410. Figure 6 The diagrams may correspond to Figure 2 The local fuse latch region 402 or a portion thereof may be a repair fuse latch, and / or may correspond to Figure 4A The segment address determination circuit 404 and Figure 4B The matching circuit of the comparator circuit 406.

[0080] For a global column repair scheme, columns (e.g., redundant memory 414) may be located in a separate column plane (e.g., repair plane 415) and separate from the main array column plane (e.g., zone plane 410). In some embodiments (e.g., for DDR4), the global column repair scheme may include redundant column planes as separate sub-arrays (e.g., illustrated on the left, RYD ED) parallel to other main array column planes. Figure 6In the example illustrated in FIG, the dashed line may represent a repair that may be mapped to a single redundant column plane. This repair may be performed once per x8 region.

[0081] Figure 7 is a diagram illustrating the operation of a device (e.g., Figure 2 200) is a flowchart of an example method 700 of a memory device 200. For example, the method 700 may be used to operate Figure 4A The local fuse latch area 402, Figure 4A The segment address determination circuit 404 and / or Figure 4A The comparator circuit 406 is based on Figure 4A Repair address 422 and Figure 4A Repair segment locator 424 and / or Figure 5A Repair segment locator 508 and Figure 5B The method 700 may effectively or functionally couple (i.e., not have or replace a direct one-to-one connection) the fuses and / or fuse latches for the repair address 422 / 510 to the repair address 510 of the memory cell or cells with a redundant memory cell. Figure 4A Redundant memory 414.

[0082] At block 702, the memory device 200 may detect defective memory (eg, Figure 1 In some embodiments, the memory device 200 may implement a built-in self-test (BIST) design that may be online and / or offline to test the memory cells (e.g., Figure 2 200). For example, the memory device 200 may perform a test sequence (via, for example, a memory controller, a finite state machine, and / or a processor) using a predetermined sequence of test elements including memory operations, data patterns, and / or addresses. For testing, the memory device 200 may write a predetermined data pattern to a corresponding address and then read the same address to confirm the same data pattern. When the read pattern does not match the predetermined written data pattern, the memory device 200 may identify the memory cell corresponding to the difference as defective.

[0083] At block 704, the memory device 200 may identify a defect location (e.g., a location of a defective memory cell). For example, the memory device 200 may identify an internal address of a defective memory cell. Using a predetermined table and / or a predetermined procedure, the memory device 200 may identify a memory cell that includes one or more defective memory cells. Figure 4A Segment 412, Figure 4A area plane 410 , columns and / or rows within memory array 250 .

[0084] At block 706, the memory device 200 may determine the identification Figure 4A The memory device 200 may determine a segment locator associated with an identified segment 412 and / or a regional plane 410 that includes a defective memory cell. Also, for global repair, the memory device 200 may determine a segment locator that identifies the regional plane 410 that was swapped out. At block 708, the memory device 200 may determine a repair address for the defective memory cell (e.g., an address of a column that includes a defective memory cell, such as the repair address 422 and / or the repair address 510). For global repair, the memory device 200 may determine a segment locator that identifies the regional plane 410 that was swapped out. Figure 4A The repair address of the repair plane 415.

[0085] At block 710, the memory device 200 may store defect locations for repairing defective memory cells. The memory device 200 may store defect locations, for example, by setting fuses and / or writing to other non-volatile memory. In storing the defect locations, the memory device 200 may store both the repair address 422 / 510 and the repair segment locator 424 / 508 for each defective memory cell or each group thereof. For example, at block 712, the memory device 200 may store the repair segment locator 424 / 508 in a first set of fuses associated with a region plane 410 (e.g., a column plane or a library) that includes the columns / rows having defective cells therein. Also, at block 714, the memory device 200 may store the repair address 422 / 510 in a second set of fuses that is paired with the first set of fuses and associated with the region plane 410.

[0086] The stored location information of the defective memory cells may be used for repair, for example, by accessing / utilizing redundant memory cells in place of the defective memory cells. As an illustrative example, the memory device 200 may load the stored repair addresses 422 / 510 and the stored repair segment locators 424 / 508 into corresponding latches (e.g., Figure 4A When a memory operation references a column, row, and / or plane that includes a defective memory cell, the memory device 200 may use or access a redundant column, row, and / or plane associated with the defective memory cell.

[0087] At block 752, the memory device 200 may issue an active command (ACT). Based on the active command, the memory device 200 may activate the idle bank, thereby causing that row to be read into the array of banks of column sense amplifiers. In other words, the memory device 200 may issue an active command to turn on a row.

[0088] At block 754, the memory device 200 may obtain a segment locator (e.g., stored repair segment locator 424 / 508). The memory device 200 may use the segment locator to access / obtain a repair address (e.g., stored repair address 422 / 510). The memory device 200 may obtain the repair information (e.g., receive and / or recall the broadcasted information) based on loading the information from the first and second paired fuse sets into corresponding fuse latches, as described above. Also, the memory device 200 may provide the latched information to, for example, Figure 4B The segment matching circuit 432, Figure 4C / 4D / 4E segment matching circuit 452, Figure 4C Multiplexer 456, Figure 5A The segment matching circuit 504, Figure 4D / 4E buffer 472 and / or Figure 5A The subsequent circuit of the buffer 503 obtains the information.

[0089] At block 756, the memory device 200 may begin performing an operation (e.g., a read or write operation) in response to a command from the host. At block 758, the memory device 200 may receive an operation address associated with the operation (e.g., a read or write address). For example, the memory device 200 may determine a column address associated with the commanded operation (e.g., a Figure 4B Read / write column address 438).

[0090] At block 762, the memory device 200 may generate a segment identifier (eg, Figure 4B For example, the memory device 200 may supply the effective row address to the column segment identifier 434. Figure 4A The CRSegSelect circuitry may generate the column segment identifier 434 as described above. In some embodiments, the memory device 200 may generate the segment identifier after or concurrently with accessing the repair information. For global repair, the memory device 200 may similarly generate a segment identifier that identifies the valid region (column plane) associated with the operation.

[0091] At decision block 764, the memory device 200 (e.g., the segment matching circuit 452) may determine whether the repair segment locator 424 / 508 matches the column segment identifier 434. In other words, the memory device 200 may determine whether the commanded operation is associated with a segment that includes a defective / swapped cell. In some embodiments, the memory device 200 may compare the repair segment locator 424 / 508 to the column segment identifier 434 using the segment matching circuit.

[0092] When the repair segment locator 424 / 508 does not match the column segment identifier 434, such as illustrated at block 766, the memory device 200 may determine a mismatch scenario. In some embodiments, the memory device 200 may use Figure 4D Repair of deactivation circuit 474, Figure 4E Repair of the deactivation circuit 492 and / or Figure 5A The repair disabling circuit 512 of the memory device 200 determines the mismatch scenario. For example, the memory device 200 may compare the positions based on the analysis (via, for example, applying NOR to the Figure 4C / 4D / 4E selection signal 454 and / or Figure 5A In some embodiments, the segment address determination circuit 404 (eg, the repair disable circuit 474) may generate a signal including Figure 4D The default deactivation fix for address 476 Figure 4D In some embodiments, the repair disable circuit 492 / 512 may generate Figure 4E / 5A mismatch signal 494 to inform the comparator circuit 406 of the mismatch situation. Therefore, the comparator circuit 406 can generate Figure 4B The corresponding match flag 439 (having, for example, an invalid state or value) of .

[0093] At block 768, the memory device 200 may access an operation address (e.g., a read / write column address 438) for the read / write operation based on the resulting match flag 439. Since the operation address is for a segment that does not include the defective / repaired memory cells indicated by the comparison, the memory device 200 may utilize the location originally referenced to perform the memory operation.

[0094] When the repair segment locator 424 matches the column segment identifier 434, such as illustrated at decision block 770, the memory device 200 may determine whether the address (e.g., the valid segment address 436) matches the operation address (e.g., the read / write column address 438). In some embodiments, when the repair segment locator 424 / 508 matches the column segment identifier 434, the segment address determination circuit 404 may generate the valid segment address 436. The segment address determination circuit 404 (e.g., the segment matching circuit 432 / 452 / 504, the multiplexer 456, and / or the buffer 472 / 503) may generate the valid segment address 436 based on transmitting the repair address 422 / 510 paired with the repair segment locator 424 / 508 matching the column segment identifier 434. The comparator circuit 406 may compare the valid segment address 436 with the operation address and generate a match flag 439 accordingly.

[0095] When the valid segment address 436 does not match the operation address (i.e., the read / write operation involves a non-defective group of memory cells and the match flag 439 is invalid), the memory cell may access the operation address as described above for block 768. Otherwise (i.e., when the match flag 439 is activated), the memory device 200 may identify the access to the defective / repaired memory cell via the match flag 439. At block 774, the memory device 200 (e.g., the column decoder and / or the row decoder) may access the valid segment address 436 (i.e., the repair address 422 / 510) for the read / write operation instead of the intended operation address. In other words, based on the valid setting of the match flag 439, the memory device 200 implements the repair by accessing the redundant column or plane instead of the intended column or plane including the defective / replaced memory cell.

[0096] As described above, method 700 functionally couples address latches to redundant rows / columns / planes that are not directly connected via repair segment locators 424 / 508 and segment address determination circuit 404. Thus, the number of repairs and the corresponding number of fuses / fuse latches can be decoupled from the number of sectors, thereby reducing Figure 4A The second measurement 428 of and the total number of fuses / fuse latches, as described above. The reduction in the number of total fuses / fuse latches provides a smaller circuit footprint for the memory device 200, reduced cost, and increased efficiency.

[0097] Figure 8 is a schematic diagram of a system including a device according to an embodiment of the present technology. Figures 2 to 7 Any of the foregoing apparatus (e.g., memory devices) described may be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are schematically shown in FIG. Figure 8 The system 880 in FIG. 880 may include a memory device 800, a power supply 882, a driver 884, a processor 886, and / or other subsystems or components 888. The memory device 800 may include a substantially similar Figures 2 to 7 The system 880 may include features of those features of the apparatus described herein, and may therefore include various features for performing direct read requests from a host device. The resulting system 880 may perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems 880 may include, without limitation, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of system 880 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communications network). The components of system 880 may also include any of a wide variety of computer-readable media and remote devices.

[0098] In light of the foregoing, it should be understood that, although specific embodiments of the present technology have been described herein for the purpose of illustration, various modifications may be made without departing from the present invention. In addition, certain aspects of the new technology described in the context of specific embodiments may also be combined or eliminated in other embodiments. Moreover, although the advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments must exhibit such advantages to fall within the scope of the present technology. Therefore, the present invention and associated technology may encompass other embodiments not explicitly shown or described herein.

[0099] In the illustrated embodiments above, the apparatus has been described in the context of DRAM devices. However, apparatus configured in accordance with other embodiments of the present technology may include other types of suitable storage media in addition to or in place of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0100] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transferring and / or manipulating data structures. The term data structure includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. As used herein, in addition, the term "dynamic" describes a process, function, action, or implementation that occurs during operation, use, or deployment of a corresponding device, system, or embodiment and after or while running manufacturer or third-party firmware. A process, function, action, or implementation that occurs dynamically may occur after or subsequent to design, manufacturing, and initial testing, setup, or configuration.

[0101] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the art will appreciate that the present technology may have additional embodiments and may be used without reference below. Figures 2 to 8 The present technology is practiced without the use of numerous details of the described embodiments.

Claims

1. A method comprising: performing a built-in self-test process by a memory device, the built-in self-test process comprising testing a memory array at the memory device using one or more predetermined data patterns; storing information to the memory device indicating whether one or more addresses of the memory array include one or more failures based at least in part on the built-in self-test process; reading the information after the built-in self-test process is completed; as well as A repair operation is performed based at least in part on the information indicating that the one or more addresses include the one or more failures.

2. The method of claim 1, wherein reading the information comprises: The information is read during initialization of the memory device.

3. The method of claim 1, wherein prior to performing the repair operation, a bank of memory cells associated with the one or more addresses is in an idle state.

4. The method according to claim 1, further comprising: An activate command is issued to activate the one or more addresses for repair, wherein performing the repair operation is based at least in part on issuing the activate command.

5. The method according to claim 1, further comprising: The one or more failures are detected using the one or more predetermined data patterns, wherein performing the repair operation is based at least in part on detecting the one or more failures.

6. The method according to claim 1, further comprising: receiving an operation address for an operation associated with accessing the memory array; as well as As part of the repair operation, one or more defective memory cells associated with the one or more failures are replaced with one or more redundant memory cells based at least in part on the operation address matching the one or more addresses indicated as including the one or more failures.

7. The method according to claim 1, wherein: Storing the information comprises writing the information to a non-volatile memory of the memory device; and Reading the information includes loading the information from the non-volatile memory.

8. A device comprising: one or more memory devices; as well as a processing circuit coupled to the one or more memory devices and configured to cause the apparatus to: performing a built-in self-test process by a memory device of the one or more memory devices, the built-in self-test process comprising testing a memory array at the memory device using one or more predetermined data patterns; storing information to the memory device indicating whether one or more addresses of the memory array include one or more failures based at least in part on the built-in self-test process; reading the information after the built-in self-test process is completed; as well as A repair operation is performed based at least in part on the information indicating that the one or more addresses include the one or more failures.

9. The apparatus of claim 8, wherein to read the information, the processing circuit is configured such that the apparatus: The information is read during initialization of the memory device.

10. The apparatus of claim 8, wherein prior to performing the repair operation, a bank of memory cells associated with the one or more addresses is in an idle state.

11. The apparatus of claim 8, wherein the processing circuit is further configured such that the apparatus: An activate command is issued to activate the one or more addresses for repair, wherein performing the repair operation is based at least in part on issuing the activate command.

12. The apparatus of claim 8, wherein the processing circuit is further configured such that the apparatus: The one or more failures are detected using the one or more predetermined data patterns, wherein performing the repair operation is based at least in part on detecting the one or more failures.

13. The apparatus of claim 8, wherein the processing circuit is further configured such that the apparatus: receiving an operation address for an operation associated with accessing the memory array; and As part of the repair operation, one or more defective memory cells associated with the one or more failures are replaced with one or more redundant memory cells based at least in part on the operation address matching the one or more addresses indicated as including the one or more failures.

14. The apparatus of claim 8, wherein: To store the information, the processing circuit is configured to cause the apparatus to write the information to a non-volatile memory of the memory device; and To read the information, the processing circuit is configured to cause the apparatus to load the information from the non-volatile memory.

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