Memory time sequence testing device, system and method
By providing a memory timing testing device including an interface circuit and a control circuit, the problem of lack of a memory timing verification device in the prior art is solved, and effective verification of memory timing is realized to ensure normal memory performance.
Patent Information
- Application Number
- CN202411456883.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-18
- Publication Date
- 2025-02-18
AI Technical Summary
There is now a lack of a device that can verify the timing of the memory.
Provided is a memory timing testing device, including an interface circuit and a control circuit. The control circuit includes a timing selection module and a control module for receiving multiple timing sequences to be tested, determining the target timing sequence to be tested according to the selection signal, and reading and writing the memory to be tested Control to obtain timing test results.
Effective verification of memory timing is achieved to ensure that the memory performs normally before it is put into use.
Smart Images
Figure CN119479750A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of testing technology, and in particular to a memory timing testing device, system and method. Background Art
[0002] Memory is a memory component used to store data and instructions in electronic computers. At present, due to the popularity of computers, memory has also been widely used. After the memory is manufactured, it is generally necessary to test the memory to ensure that the memory put into use has normal performance.
[0003] Currently, there is a lack of a device capable of verifying the timing of a memory. Summary of the invention
[0004] Based on this, it is necessary to provide a memory timing test device, system and method that can perform timing verification on the memory in order to solve the above technical problems.
[0005] In a first aspect, the present application provides a memory timing test device, the device comprising:
[0006] An interface circuit, used for receiving a plurality of timing sequences to be tested;
[0007] A control circuit comprises a timing selection module and a control module, wherein the timing selection module is used to generate a selection signal according to a received control instruction, the control module is respectively connected to the interface circuit and the timing selection module, the control module is used to connect to a memory to be tested, and the control module is also used to obtain the multiple timings to be tested, and determine a target timing to be tested from the multiple timings to be tested according to the selection signal, so as to perform read and write control on the memory to be tested according to the target timing to be tested, and determine a timing test result of the memory to be tested corresponding to the target timing to be tested according to the read feedback information.
[0008] In one embodiment, the timing selection module includes: a plurality of switch units, wherein the first end of each of the switch units is respectively used to receive a first voltage and is connected to the control module, the second end of each of the switch units is grounded, and the switch unit is used to generate a selection signal according to a received control instruction; wherein the control module is used to determine different target timings to be tested according to the selection signals generated by different switch units.
[0009] In one embodiment, the control module includes: a control unit, a download unit and a storage unit;
[0010] The control unit is connected to the interface circuit, the download unit and the storage unit respectively. The control unit is used to receive the multiple timing sequences to be tested, control the download unit to download the timing sequences to be tested, and control the storage unit to store the timing sequences to be tested. The control unit is also used to read the target timing sequence to be tested in the storage unit according to the control signal, send the target timing sequence to be tested to the memory to be tested, and read the feedback information of the memory to be tested.
[0011] In one embodiment, the control unit has a plurality of first input-output pins, and the memory to be tested has a plurality of second input-output pins, wherein the number of the first input-output pins is greater than or equal to the number of the second input-output pins, and the memory to be tested includes at least one type, and different types of the memory to be tested have different numbers of second input-output pins.
[0012] In one embodiment, the control circuit further includes:
[0013] A reset module is connected to the control unit and is used to reset the control unit according to a received reset instruction when the control unit is in an abnormal state.
[0014] In one embodiment, the reset unit includes:
[0015] a first resistor, wherein a first end of the first resistor is used to receive a first voltage;
[0016] a first capacitor, wherein a first end of the first capacitor is respectively connected to a second end of the first resistor and a reset pin of the control unit, and a second end of the first capacitor is grounded;
[0017] A first switch, wherein a first end of the first switch is respectively connected to a first end of the first capacitor and a reset pin of the control unit, and a second end of the first switch is grounded.
[0018] In one embodiment, the device further comprises a test motherboard, a test daughterboard, a first connector, a second connector and a third connector, wherein the first connector, the second connector, the control circuit and the interface circuit are respectively located on the test motherboard, and the third connector and the memory to be tested are respectively located on the test daughterboard;
[0019] The control circuit is connected to the interface circuit through the first connector and the second connector, and the control circuit is also connected to the memory to be tested through the first connector and the third connector.
[0020] In one embodiment, the control circuit further includes:
[0021] The display module is connected to the control unit and is used for displaying the timing test result of the memory to be tested corresponding to the target timing to be tested under the control of the control unit.
[0022] In a second aspect, the present application provides a memory timing test system, the system comprising: a host computer, a memory to be tested, and the memory timing test device described in any one of the above embodiments.
[0023] In a third aspect, the present application provides a memory timing test method, which is applied to the memory timing test device described in any one of the above embodiments; the method comprises:
[0024] Accepting and storing the time sequences to be tested sent by the host computer;
[0025] In case of receiving a selection signal, determining a target timing sequence to be tested from the plurality of timing sequences to be tested according to the selection signal;
[0026] Performing read and write control on the memory to be tested according to the target timing sequence to be tested;
[0027] The timing test result of the memory to be tested corresponding to the target timing to be tested is displayed according to the read feedback information.
[0028] The above-mentioned memory timing test device, system and method include an interface circuit for receiving multiple timings to be tested; a control circuit, including a timing selection module and a control module, wherein the timing selection module is used to generate a selection signal according to the received control instruction, the control module is respectively connected to the interface circuit and the timing selection module, the control module is used to connect to the memory to be tested, and the control module is also used to obtain multiple timings to be tested, and determine the target timing to be tested from the multiple timings to be tested according to the selection signal, so as to perform read and write control on the memory to be tested according to the target timing to be tested, and determine the timing test result of the memory to be tested corresponding to the target timing to be tested according to the read feedback information. In the present application, the control module receives and stores multiple timings to be tested through the interface circuit, and under the control of the timing selection module, uses the target timing to be tested to test the memory to be tested, and obtains the feedback information of the memory to be tested and determines the test result, thereby realizing the timing verification of the memory to be tested. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0030] FIG1 is a schematic diagram of the structure of a memory timing test device in one embodiment;
[0031] FIG2 is a schematic diagram of the structure of an interface circuit in one embodiment;
[0032] FIG3 is a schematic diagram of the structure of a timing selection module in one embodiment;
[0033] FIG4 is a schematic structural diagram of a memory timing test device in another embodiment;
[0034] FIG5 is a schematic diagram of the structure of a control unit in one embodiment;
[0035] FIG6 is a schematic diagram of the structure of a download unit in one embodiment;
[0036] FIG7 is a schematic diagram of the structure of a download protection unit in one embodiment;
[0037] FIG8 is a schematic diagram of the structure of a storage unit in one embodiment;
[0038] FIG9 is a schematic structural diagram of a memory timing test device in yet another embodiment;
[0039] FIG10 is a schematic structural diagram of a reset module in one embodiment;
[0040] FIG11 is a schematic structural diagram of a memory timing test device in another embodiment;
[0041] FIG12 is a schematic diagram of the structure of a display unit in one embodiment;
[0042] FIG13 is a schematic structural diagram of a memory timing test device in another embodiment;
[0043] FIG14 is a schematic diagram of the structure of a clock module in one embodiment;
[0044] FIG15 is a schematic diagram of the structure of a power supply module in one embodiment;
[0045] FIG. 16 is a flow chart of a memory timing test method in one embodiment. DETAILED DESCRIPTION
[0046] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0048] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.
[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0050] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.
[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.
[0052] In one embodiment, the present application provides a memory timing test device, which includes an interface circuit 1 and a control circuit 2 .
[0053] The interface circuit 1 is used to receive multiple timing sequences to be tested sent by the host computer 3. The control circuit 2 includes a timing selection module 21 and a control module 22, wherein the timing selection module 21 is used to generate a selection signal according to the received control instruction, the control module 22 is connected to the interface circuit 1 and the timing selection module 21 respectively, the control module 22 is used to connect to the memory 4 to be tested, and the control module 22 is also used to obtain multiple timing sequences to be tested, and determine the target timing sequence to be tested from the multiple timing sequences to be tested according to the selection signal, so as to perform read and write control on the memory 4 to be tested according to the target timing sequence to be tested, and determine the timing test result of the memory 4 to be tested corresponding to the target timing sequence to be tested according to the read feedback information.
[0054] Specifically, referring to Figure 1, the memory timing test device of the present application may include a test motherboard 100 and a test daughter board 200. The interface circuit 1 and the control circuit 2 are both located on the test motherboard 100 and are interconnected. When it is necessary to perform a timing test on the memory 2 to be tested, the memory 2 to be tested can be installed on the test daughter board 200, and the memory 4 to be tested can be connected to the control circuit 2.
[0055] It can be understood that the host computer can be a computer, and its data interface is generally a USB (Universal Serial Bus) interface, but the control module of the present application is a control chip, which does not have a USB interface. Therefore, an interface circuit 1 needs to be set on the test motherboard. For example, please refer to Figure 2. The interface circuit 1 can be a USB to serial port circuit. U1 in Figure 2 can be a MINIUSB, which is used to provide communication between the control module 22 and the host computer 3. The UD+ pin and UD- pin of the U2 chip can be directly connected to the D+ data line and D- data line of the USB bus to receive the timing to be tested in the form of USB signals. The TXD pin of the U2 chip is a serial data output pin, and the RXD pin is a serial data input pin. Through the USB to serial port circuit, the USB signal can be converted into serial data that can be accepted by the control module 22. Furthermore, the control module 22 can receive and store multiple groups of timings to be tested sent by the host computer 3 through the interface circuit 1.
[0056] When the control module 22 has completed storing each test timing sequence, the relevant technical personnel can input a control instruction to the timing selection module 21. The timing selection module 21 will send a corresponding selection signal to the control module 22 according to the received control instruction. After the control module 22 receives the selection signal, it can determine the target test timing sequence from each test timing sequence, and perform read and write control on the test memory 4 according to the target test timing sequence, as well as obtain feedback information of the test memory 4 and determine the test results.
[0057] The above-mentioned memory timing test device includes an interface circuit for receiving multiple timings to be tested; a control circuit including a timing selection module and a control module, wherein the timing selection module is used to generate a selection signal according to the received control instruction, the control module is respectively connected to the interface circuit and the timing selection module, the control module is used to connect to the memory to be tested, and the control module is also used to obtain multiple timings to be tested, and determine the target timing to be tested from the multiple timings to be tested according to the selection signal, so as to perform read and write control on the memory to be tested according to the target timing to be tested, and determine the timing test result of the memory to be tested corresponding to the target timing to be tested according to the read feedback information. In the present application, the control module receives and stores multiple timings to be tested through the interface circuit, and under the control of the timing selection module, uses the target timing to be tested to test the memory to be tested, and obtains the feedback information of the memory to be tested and determines the test result, thereby realizing the timing verification of the memory to be tested.
[0058] In one embodiment, please refer to Figure 3, the timing selection module 21 includes: multiple switch units, the first end of each switch unit is used to receive the first voltage and is connected to the control module 22, the second end of each switch unit is grounded, and the switch unit is used to generate a selection signal according to the received control instruction; wherein, the control module 22 determines different target timings to be tested according to the selection signals generated by different switch units.
[0059] Among them, a switch unit may include a selection switch, a pull-up resistor and a buffer resistor, wherein the first end of the pull-up resistor is used to receive a first voltage, VCC_3V3 in the figure represents a first voltage of 3.3V, the second end of the pull-up resistor is respectively connected to the first end of the selection switch and the first end of the buffer resistor, the second end of the selection switch is grounded, and the second end of the buffer resistor is connected to the control module 22. When a selection switch is turned on, the corresponding port in the control module 22 obtains a low-level signal; when no selection switch is turned on, each corresponding port of the control module 22 obtains a high-level signal, and relevant technicians can control the selection control module to output the test timing of the memory to be tested through each selection switch.
[0060] In one example, please refer to Figure 3. Taking the timing selection module 21 including four switch units as an example, assuming that the host computer 3 sends six test timings H1, H2, H3, H4, H5 and H6 to the control module 22, when the selection switch S1 is pressed, the control module 22 can perform read and write control on the test memory 4 according to the test timing H1; when the selection switch S2 is pressed, the control module 22 can perform read and write control on the test memory 4 according to the test timing H2; ...; when the selection switch S4 is pressed, the control module 22 can perform read and write control on the test memory 4 according to the test timing H4; when the selection switches S1 and S3 are pressed at the same time, the control module 22 can perform read and write control on the test memory 4 according to the test timing H5; when the selection switches S2 and S4 are pressed at the same time, the control module 22 can perform read and write control on the test memory 4 according to the test timing H6.
[0061] In one embodiment, referring to FIG. 4 , the control module 22 includes: a control unit 221 , a download unit 222 , and a storage unit 223 .
[0062] The control unit 221 is connected to the interface circuit 1, the download unit 222 and the storage unit 223 respectively. The control unit is used to receive multiple test timings, control the download unit 222 to download the test timings, and control the storage unit 223 to store the test timings. The control unit 221 is also used to read the target test timing in the storage unit 223 according to the control signal, send the target test timing to the test memory 4, and read the feedback information of the test memory 4.
[0063] In this embodiment, the control unit 221 can be an FPGA control chip, please refer to Figure 5, Figure 5 is a schematic diagram of a partial circuit structure of the control unit 221, please refer to Figure 2 and Figure 5, it can be seen that the two IO pins in the control unit 221 are respectively connected to the RXD pin and the TXD pin of the interface circuit 1, and then, the control unit 221 can receive the various timings to be tested sent by the host computer and various configuration information for the control unit 221 through the TXD pin of the interface circuit. In an example, please refer to Figure 6, Figure 6 is a circuit structure diagram of the download unit 222, the control unit 221 and the download unit 222 are connected according to the corresponding relationship shown in Figures 5 and 6, when the control unit 221 receives various configuration information and the timings to be tested, the download unit 222 can be controlled to download the timing to be tested. In addition, please refer to Figure 7, a download protection circuit can also be configured in this application, and the download protection circuit can include a TVS diode of the SRV05-4 model. It can be understood that due to the presence of static electricity and instantaneous pulse voltage, it is relatively easy to burn the JTAG download pin of the control unit 221, so a TVS diode is added to the circuit to protect the control unit 221.
[0064] Please continue to refer to FIG8, which is a schematic diagram of the circuit structure of the storage unit 223. The control unit 221 and the storage unit 223 are connected according to the corresponding relationship shown in FIG5 and FIG8. After the download unit 222 downloads all configuration information and all test sequences, the control unit 221 can control the storage unit 223 to store various configuration information and all test sequences. Further, please continue to refer to FIG3 and FIG5, and the relevant technicians can control the control unit 221 to select the test sequence output by the test memory through each selection switch. When the control unit 221 detects that a switch is turned on, the target test sequence can be determined from the test sequences, and the read and write control of the test memory is performed according to the target test sequence, and the feedback information of the test memory 4 is received. After the control unit 221 receives the feedback information of the test memory 4, the control unit 221 can send the feedback information to the host computer through the RXD pin of the interface circuit 1.
[0065] In one embodiment, the control unit 221 has multiple first input and output pins, and the memory to be tested 4 has multiple second input and output pins, wherein the number of first input and output pins is greater than or equal to the number of second input and output pins, and the memory to be tested includes at least one type, and different types of memories to be tested have different numbers of second input and output pins.
[0066] It can be understood that in addition to some input and output pins (IO pins) as shown in FIG5 , the control unit 221 also has a plurality of first input and output pins, and the memory to be tested 4 also has a plurality of second input and output pins, wherein some of the first input and output pins and some of the second input and output pins are used to receive or send data information, and the remaining first input and output pins and second input and output pins are used to receive or send address information. When the control unit 221 tests the memory to be tested 4 according to the target timing sequence to be tested, the target timing sequence to be tested is hidden in the transmitted data information and address information. In addition, in the present application, the number of the first input and output pins is set to be greater than or equal to the number of the second input and output pins, so that the memory timing test device of the present application can test various types of memories.
[0067] In one embodiment, referring to FIG. 9 and FIG. 10 , the control circuit 2 further includes a reset module 23 , which is connected to the control unit 221 and is used to reset the control unit 221 according to a received reset instruction when the control unit 221 is in an abnormal state.
[0068] Exemplarily, the reset unit 23 includes: a first resistor R1, a first capacitor C1 and a first switch SW1. The first end of the first resistor R1 is used to receive the first voltage. The first end of the first capacitor C1 is respectively connected to the second end of the first resistor R1 and the reset pin of the control unit 221, and the second end of the first capacitor C1 is grounded. The first end of the first switch SW1 is respectively connected to the first end of the first capacitor C1 and the reset pin 221 of the control unit, and the second end of the first switch SW1 is grounded.
[0069] In this application, an RC power-on reset and manual reset circuit is used. When the control unit 221 is powered on, since the charge stored in the first capacitor C1 is 0, the RESET pin of the control unit 221 is at a low level, so that the control unit 221 is reset. As the first capacitor C1 is charged, the level on RESET gradually changes from a low level to a high level, thus completing the power-on reset operation. At the same time, the first switch SW1 can use a 2.54 pitch 2pin pin, which can be directly short-circuited for hardware reset when the control unit 221 is working.
[0070] In one embodiment, referring to FIG. 11 , the control circuit further includes a display module 24 , which is connected to the control unit 221 and is used to display the timing test result of the memory under test corresponding to the target timing under test under the control of the control unit 221 .
[0071] In one example, the display module 24 may include a lighting effect circuit as shown in FIG12 , in which the colors of the light emitted by each diode may be different, for example, diode D1 may emit green light, diode D2 may emit red light, diode D3 may emit blue light, and diode D4 may emit yellow light. The equivalent circuit of the present application adopts a common anode connection method, and the diode drive is based on the current value, not the voltage. For example, the typical value of the maximum current of the diode used is 20 mA. The larger the current, the brighter the light. However, too high a current may cause the diode chip to break down or affect the service life. When using current drive, a current limiting resistor must be added to adjust the current. The circuit can use a 1 kΩ resistor to limit the current. The brightness display is appropriate. When the corresponding port voltage is at a low level, the corresponding diode is lit, otherwise it is extinguished.
[0072] In one embodiment, referring to FIG. 13 , the memory timing test device of the present application further includes a first connector 5, a second connector 6, and a third connector 7. The first connector 5, the second connector 6, the control circuit 2, and the interface circuit 1 are respectively located on the test motherboard, and the third connector 7 and the memory to be tested 4 are respectively located on the test daughterboard 200. The control circuit 2 is connected to the interface circuit 1 through the first connector 5 and the second connector 6, and the control circuit 2 is also connected to the memory to be tested 4 through the first connector 5 and the third connector 7.
[0073] Specifically, the interface circuit 1, the timing selection module 21 and the display module 24 are connected to the control unit 221 through the second connector and the first connector respectively, and the memory to be tested 4 is connected to the control unit 221 through the third connector and the first connector. In application, the interface circuit 1, the timing selection module 21 and the display module 24 can be separately set on a PCB board.
[0074] Continuing to refer to FIG. 13 , the memory timing test device of the present application also includes a clock module 25 and a power supply module 26. Specifically, please refer to FIG. 14 , which is a circuit structure diagram of the clock module 25 . The clock module 25 mainly provides a clock beat signal for the control unit 221 , and uses a 50MHz active chip crystal oscillator to provide an operating clock for the control unit 221 . A stable external clock is the guarantee for the normal operation of the control unit 221 . In order to generate a stable clock, two capacitor filters are added to the power supply of the clock module 25 to filter out the influence of high-frequency noise on the power supply. The clock output is connected to an ohmic resistor to play a buffering role and reduce interference with other modules on the test motherboard.
[0075] 15 is a circuit diagram of the power supply module 26. The power supply module 26 can receive a 5V power supply and convert the 5V voltage into 3.3V, 2.5V and 1.2V voltages to power the chips and components on the test motherboard and the test daughterboard respectively.
[0076] In one embodiment, the memory timing test device of the present application may further include a temperature control box. In an application, the test sub-board may be placed in the temperature control box, thereby applying temperature stress to the memory to be tested while performing a timing test on the memory to be tested.
[0077] In addition, the timing verification test code of the memory is divided into three modules, including the top-level module user_test and two sub-modules flash_access and design_1_wrapper.
[0078] The top-level module user_test is used to generate test data and chip operation commands. It includes functions such as erasing, writing, reading and verifying storage units. The sub-module flash_access is the storage unit control module. It is used to parse the top-level module commands, generate chip control timing, and control the chip's erasing and reading and writing functions. The sub-module design_1_wrapper calls the microblaze soft core. When the chip write and read data verification is successful, the control unit serial port prints out FLASH TEST OK!
[0079] First, the top-level module generates sector erase, chip erase, write and read commands in sequence. The control module parses the upper-level module commands and generates corresponding control timing and programming commands respectively, and performs corresponding operations on the chip. During the erasing and writing process, the relevant technicians can use an oscilloscope to measure the chip erase and write time of the data signal on the test motherboard, and finally verify the read data with the initially written data. After the verification is successful, the serial port prints out FLASH TEST OK!
[0080] In one embodiment, the present application provides a memory timing test system, the system comprising: a host computer, a memory to be tested, and the memory timing test device in any one of the above embodiments.
[0081] In one embodiment, referring to FIG. 16 , the present application provides a memory timing test method, which is applied to the memory timing test device in any of the above embodiments. The method includes S1601 to S1604 .
[0082] S1601: Receive and store each test sequence sent by the host computer.
[0083] In the application, when the timing test of the memory is required, it is only necessary to design the corresponding test daughter board according to the model of the memory to be tested, and then install the memory to be tested on the test daughter board. After that, the test mother board can be connected to the host computer through the interface circuit, and the control unit can receive the configuration information and each timing to be tested sent by the host computer, and control the download unit to download the configuration information and each timing to be tested and control the storage unit to store the configuration information and each timing to be tested.
[0084] S1602: When a selection signal is received, a target timing sequence to be tested is determined from a plurality of timing sequences to be tested according to the selection signal.
[0085] Afterwards, the operator can control the control unit through the timing selection module to determine the target timing sequence to be tested from the multiple timing sequences to be tested.
[0086] S1603: Perform read and write control on the memory to be tested according to the target test timing.
[0087] After that, the control unit can write data to the memory under test and read the feedback information of the memory under test according to the target test timing. For example, it can carry out full space traversal and burning of all 0s, all 1s, 5555, AAAA, and read the register value of the memory under test through the control unit to perform data verification.
[0088] S1604: Displaying the timing test result of the memory under test corresponding to the target timing under test according to the read feedback information.
[0089] After reading the feedback information, the control unit can display the test results of each timing sequence to be tested by controlling the light emission of each diode in the display module, or, when the host computer is still in working state, the control unit can also send the feedback information to the host computer through the interface circuit.
[0090] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0091] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0092] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A memory timing test device, characterized in that: The device comprises: An interface circuit, used for receiving a plurality of timing sequences to be tested; A control circuit comprises a timing selection module and a control module, wherein the timing selection module is used to generate a selection signal according to a received control instruction, the control module is respectively connected to the interface circuit and the timing selection module, the control module is used to connect to a memory to be tested, and the control module is also used to obtain the multiple timings to be tested, and determine a target timing to be tested from the multiple timings to be tested according to the selection signal, so as to perform read and write control on the memory to be tested according to the target timing to be tested, and determine a timing test result of the memory to be tested corresponding to the target timing to be tested according to the read feedback information.
2. The memory timing test device according to claim 1, characterized in that: The timing selection module includes: multiple switch units, the first end of each switch unit is used to receive a first voltage and is connected to the control module, the second end of each switch unit is grounded, and the switch unit is used to generate a selection signal according to a received control instruction; wherein the control module determines different target timings to be tested according to the selection signals generated by different switch units.
3. The memory timing test device according to claim 1, characterized in that: The control module includes: a control unit, a download unit and a storage unit; The control unit is connected to the interface circuit, the download unit and the storage unit respectively. The control unit is used to receive the multiple timing sequences to be tested, control the download unit to download the timing sequences to be tested, and control the storage unit to store the timing sequences to be tested. The control unit is also used to read the target timing sequence to be tested in the storage unit according to the control signal, send the target timing sequence to be tested to the memory to be tested, and read the feedback information of the memory to be tested.
4. The memory timing test device according to claim 3, characterized in that: The control unit has a plurality of first input-output pins, and the memory to be tested has a plurality of second input-output pins, wherein the number of the first input-output pins is greater than or equal to the number of the second input-output pins, and the memory to be tested includes at least one type, and different types of the memory to be tested have different numbers of second input-output pins.
5. The memory timing test device according to claim 1, characterized in that: The control circuit further comprises: A reset module is connected to the control unit and is used to reset the control unit according to a received reset instruction when the control unit is in an abnormal state.
6. The memory timing test device according to claim 5, characterized in that: The reset unit includes: a first resistor, wherein a first end of the first resistor is used to receive a first voltage; a first capacitor, wherein a first end of the first capacitor is respectively connected to a second end of the first resistor and a reset pin of the control unit, and a second end of the first capacitor is grounded; A first switch, wherein a first end of the first switch is respectively connected to a first end of the first capacitor and a reset pin of the control unit, and a second end of the first switch is grounded.
7. The memory timing test device according to claim 1, characterized in that: The device further comprises a test motherboard, a test daughterboard, a first connector, a second connector and a third connector, wherein the first connector, the second connector, the control circuit and the interface circuit are respectively located on the test motherboard, and the third connector and the memory to be tested are respectively located on the test daughterboard; The control circuit is connected to the interface circuit through the first connector and the second connector, and the control circuit is also connected to the memory to be tested through the first connector and the third connector.
8. The memory timing test device according to claim 1, characterized in that: The control circuit further comprises: The display module is connected to the control unit and is used for displaying the timing test result of the memory to be tested corresponding to the target timing to be tested under the control of the control unit.
9. A memory timing test system, characterized in that: The system comprises: a host computer, a memory to be tested and the memory timing test device according to any one of claims 1 to 8.
10. A memory timing test method, characterized in that: A memory timing test device according to any one of claims 1 to 8; the method comprising: Accepting and storing the time sequences to be tested sent by the host computer; In case of receiving a selection signal, determining a target timing sequence to be tested from the plurality of timing sequences to be tested according to the selection signal; Performing read and write control on the memory to be tested according to the target timing sequence to be tested; The timing test result of the memory to be tested corresponding to the target timing to be tested is displayed according to the read feedback information.