Repair method and repair device

Abstract

The embodiment of the invention provides a repairing method and device, and the method comprises the steps: obtaining a target fault statistical table; the target fault statistical table comprises a plurality of target storage addresses and the fault number corresponding to each target storage address; wherein the target storage address is a storage address with a single-bit fault in the storage array; the target storage address comprises a target row address and a target column address; generating a processing list based on the fault number corresponding to each target storage address; the processing list comprises at least one repair allocation scheme, the repair allocation scheme comprises a target redundant row number and a target redundant column number, and the target redundant row number and the target redundant column number represent the number of redundant rows and redundant columns required for repairing each target storage address; and repairing each target storage address according to the repair allocation scheme. Therefore, all the target storage addresses can be repaired at the same time, so that the target storage addresses are repaired quickly, and the repairing efficiency is high.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a repair method and a repair device. Background Art

[0002] In the manufacturing process of semiconductor memory, due to reasons such as manufacturing process, some storage cells in the storage array may fail, among which single-bit failures account for a large number of all failure types. In the related art, although the failures in the storage array can be repaired by the redundancy analysis (RA) method, the single-bit failures account for a large number, so the single-bit failure repair is slow and the repair efficiency is not high. Summary of the invention

[0003] The embodiments of the present disclosure provide a repair method and a repair device.

[0004] In a first aspect, an embodiment of the present disclosure provides a repair method, the method comprising:

[0005] Obtain a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each of the target storage addresses; wherein the target storage address is a storage address having a single-bit fault in the storage array; the target storage address includes a target row address and a target column address;

[0006] Generate a processing list based on the number of failures corresponding to each of the target storage addresses; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each of the target storage addresses;

[0007] Repair each of the target storage addresses according to the repair allocation scheme.

[0008] In some embodiments, the step of obtaining a target fault statistics table includes:

[0009] Obtaining an initial fault statistics table; the initial fault statistics table includes a number of initial storage addresses and the number of faults corresponding to each of the initial storage addresses; wherein the initial storage address is a storage address in the storage array where at least one bit of fault exists; the initial storage address includes an initial row address and an initial column address;

[0010] In the initial fault statistics table, determining the plurality of target storage addresses;

[0011] The target fault statistics table is obtained according to the plurality of target storage addresses and the number of faults corresponding to the target storage addresses.

[0012] In some embodiments, the initial fault statistics table includes an initial fault row statistics table and an initial fault column statistics table, the initial fault row statistics table includes at least one initial row address and the number of faults corresponding to each initial row address, and the initial fault column statistics table includes at least one initial column address and the number of faults corresponding to each initial column address; the storage array includes at least one row address and at least one column address; and obtaining the initial fault statistics table includes:

[0013] Performing fault analysis on the storage array to respectively determine the number of faults corresponding to each row address and each column address;

[0014] Determine the row address with at least one bit failure as the initial row address to obtain at least one initial row address; and determine the column address with at least one bit failure as the initial column address to obtain at least one initial column address;

[0015] The initial fault row statistics table is generated according to each of the initial row addresses and the number of faults corresponding to the initial row addresses; and the initial fault column statistics table is generated according to each of the initial column addresses and the number of faults corresponding to the initial column addresses.

[0016] In some embodiments, the initial fault row statistics table includes N initial row addresses and corresponding fault numbers, and the initial fault column statistics table includes M initial column addresses and corresponding fault numbers; in the initial fault statistics table, determining the plurality of target storage addresses includes:

[0017] If the number of faults corresponding to the i-th initial row address and the number of faults corresponding to the j-th initial column address are both 1, and the fault in the i-th initial row address and the fault in the j-th initial column address are the same fault, then the i-th initial row address is determined to be the target row address, and the j-th initial column address is determined to be the target column address;

[0018] Wherein, i is an integer greater than 0 and less than or equal to N, and j is an integer greater than 0 and less than or equal to M.

[0019] In some embodiments, the target fault statistics table includes a target fault row statistics table and a target fault column statistics table; the target fault statistics table is obtained according to the plurality of target storage addresses and the number of faults corresponding to the target storage addresses, including:

[0020] A target fault row statistics table is generated according to the target row address and the number of faults corresponding to the target row address; and a target fault column statistics table is generated according to the target column address and the number of faults corresponding to the target column address.

[0021] In some embodiments, generating a processing list based on the number of failures corresponding to each of the target storage addresses includes:

[0022] Sum the number of failures corresponding to each of the target storage addresses to determine the total number of failures;

[0023] Acquire the number of redundant rows and the number of redundant columns, wherein the number of redundant rows indicates the number of redundant rows that can be used to repair the target storage row, and the number of redundant columns indicates the number of redundant columns that can be used to repair the target storage column;

[0024] Determine at least one of the repair allocation schemes according to preset rules; wherein the preset rules include: a rule that the sum of the target number of redundant rows and the target number of redundant columns is equal to the total number of faults, and the target number of redundant rows is less than or equal to the number of redundant rows, and the target number of redundant columns is less than or equal to the number of redundant columns;

[0025] According to each of the repair allocation schemes, the processing list is generated.

[0026] In some embodiments, the number of faults corresponding to each of the target row addresses is summed to determine the total number of faulty rows; the number of faults corresponding to each of the target column addresses is summed to determine the total number of faulty columns; the processing list includes 2 columns, and each row of the processing list corresponds to a repair allocation scheme; the determining of at least one of the repair allocation schemes according to a preset rule also includes:

[0027] In the first column of the processing list, sorting the target redundant row numbers in descending order from the first redundant row number to the second redundant row number;

[0028] In the second column of the processing list, sorting the target redundant column quantities in ascending order from the second redundant column quantity to the first redundant column quantity;

[0029] Among them, the first redundant row number is the smaller of the redundant row number and the total number of faulty rows, the first redundant column number is the smaller of the redundant column number and the total number of faulty columns; the second redundant row number is the difference between the total number of faults and the first redundant column number; the second redundant column number is the difference between the total number of faults and the first redundant row number.

[0030] In some embodiments, repairing each of the target storage addresses according to the repair allocation scheme includes:

[0031] Determining the target number of redundant rows and the target number of redundant columns according to the repair allocation scheme;

[0032] The target storage row is repaired by using the redundant rows of the target redundant row quantity; and the target storage column is repaired by using the redundant columns of the target redundant column quantity.

[0033] In some embodiments, in the target fault statistics table, the number of faults corresponding to the target row address and the number of faults corresponding to the target row address are both 1.

[0034] In a second aspect, an embodiment of the present disclosure provides a repair device, which is applied to a repair method of a target faulty unit, wherein the target faulty unit is a storage unit with a single-bit fault in a storage array, and the device comprises:

[0035] An acquisition module is configured to acquire a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each of the target storage addresses; wherein the target storage address is a storage address having a single-bit fault in the storage array; the target storage address includes a target row address and a target column address;

[0036] A generating module is configured to generate a processing list based on the number of failures corresponding to each of the target storage addresses; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each of the target storage addresses;

[0037] The repair module is configured to repair each of the target storage addresses according to the repair allocation scheme.

[0038] The embodiment of the present disclosure provides a repair method and a repair device, wherein the repair method comprises: first, obtaining a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each target storage address; wherein the target storage address is a storage address with a single-bit fault in a storage array; the target storage address includes a target row address and a target column address; secondly, generating a processing list based on the number of faults corresponding to each target storage address; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target redundant row number and a target redundant column number, and the target redundant row number and the target redundant column number represent the number of redundant rows and redundant columns required to repair each target storage address; finally, repairing each target storage address according to the repair allocation scheme. In this way, since the processing list is generated by the number of faults corresponding to each target storage address after obtaining the target fault statistics table, each target storage address can be directly repaired based on the repair allocation scheme in the processing list; that is, based on the repair allocation scheme in the processing list, all target storage addresses with single-bit faults in the storage array can be repaired at the same time, so that the target storage address is repaired faster and with higher repair efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a repair method provided in an embodiment of the present disclosure Figure 1 ;

[0040] Figure 2 A schematic diagram of a repair method provided in an embodiment of the present disclosure Figure 2 ;

[0041] Figure 3 A schematic diagram of a repair method provided in an embodiment of the present disclosure Figure 3 ;

[0042] Figure 4 A schematic diagram of a storage array provided in an embodiment of the present disclosure Figure 1 ;

[0043] Figure 5 A schematic diagram of an initial fault row statistics table and an initial fault column statistics table provided in an embodiment of the present disclosure;

[0044] Figure 6 A schematic diagram of a storage array provided in an embodiment of the present disclosure Figure 2 ;

[0045] Figure 7 A schematic diagram of a determination flow for determining a target row address and a target column address provided in an embodiment of the present disclosure;

[0046] Figure 8A schematic diagram of a target fault row statistics table and a target fault column statistics table provided in an embodiment of the present disclosure;

[0047] Fig. 9 A schematic diagram of a repair method provided in an embodiment of the present disclosure Figure 4 ;

[0048] Fig.10 A schematic diagram of a processing list provided in an embodiment of the present disclosure Figure 1 ;

[0049] Fig.11 A schematic diagram of a processing list provided in an embodiment of the present disclosure Figure 2 ;

[0050] Fig.12 A schematic diagram of a repair method provided in an embodiment of the present disclosure Figure 5 ;

[0051] Fig.13 A schematic diagram of the structure of a repair device provided in an embodiment of the present disclosure;

[0052] Fig.14 A hardware entity schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0055] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0056] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0057] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0058] Fail Bit Map (FBM);

[0059] Shared Address;

[0060] Faults;

[0061] Single Bit Faults;

[0062] Redundancy Analysis (RA);

[0063] Faulty line;

[0064] Fault Group;

[0065] Fail Address;

[0066] Storage array (Array);

[0067] Solution List;

[0068] Redundant Row;

[0069] Redundant Column.

[0070] At present, in actual FBM, due to various reasons such as manufacturing process, shared address type faults (i.e., there are multi-bit faults in a row address or a column address) may occur, but in most cases, single-bit faults (i.e., the row address and column address where the fault is located only have this fault) will account for a large part. There are many repair analysis methods for shared address type faults in traditional RA methods. For example, the redundancy analysis speed and repair rate are improved by processing faulty lines or fault groups. However, no repair method specifically for single-bit faults has been proposed. The processing of single-bit faults is placed after the repair analysis of shared address type faults and then repaired one by one, which makes the repair of single-bit faults slow and the repair efficiency is not high.

[0071] Based on this, the embodiment of the present disclosure provides a repair method, including: obtaining a target fault statistics table; the target fault statistics table includes a number of target storage addresses and the number of faults corresponding to each target storage address; wherein the target storage address is a storage address with a single-bit fault in the storage array; the target storage address includes a target row address and a target column address; based on the number of faults corresponding to each target storage address, a processing list is generated; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target redundant row number and a target redundant column number, the target redundant row number and the target redundant column number represent the number of redundant rows and redundant columns required to repair each target storage address; and each target storage address is repaired according to the repair allocation scheme. In this way, since the processing list is generated by the number of faults corresponding to each target storage address after obtaining the target fault statistics table, each target storage address can be directly repaired based on the repair allocation scheme in the processing list; that is, based on the repair allocation scheme in the processing list, all target storage addresses with single-bit faults in the storage array can be repaired at the same time, so that the repair of the target storage address is faster and the repair efficiency is higher.

[0072] According to the above analysis, it can be seen that in the related art, single-bit faults need to be searched and repaired one by one, while the present disclosure recognizes the distribution pattern of single-bit faults, thereby eliminating the need to search single-bit faults one by one, thereby achieving rapid analysis of single-bit faults and improving the accuracy of repair; further, a processing list is generated according to the fault address of the single-bit fault, and the single-bit fault is repaired through the processing list, so that the repair efficiency of the single-bit fault is higher.

[0073] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0074] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of a repair method provided by an embodiment of the present disclosure. Figure 1 As shown, the repair method includes: step S110 to step S130.

[0075] Step S110: Obtain a target fault statistics table; the target fault statistics table includes a number of target storage addresses and the number of faults corresponding to each target storage address; wherein the target storage address is a storage address with a single-bit fault in the storage array; the target storage address includes a target row address and a target column address.

[0076] It should be noted that the storage array includes at least one row address and at least one column address; there is no shared row address and / or shared column address between the single-bit fault and any other fault.

[0077] It should also be noted that the target fault statistics table includes a target fault row statistics table and a target fault column statistics table; the target fault row statistics table includes several target row addresses and the number of faults corresponding to each target row address, and the target fault column statistics table includes several target column addresses and the number of faults corresponding to each target column address.

[0078] That is, in this embodiment, the target storage address is a faulty unit located by the target row address and target column address of the same fault, and its corresponding fault quantity refers to: the fault quantity corresponding to the target row address where the target storage address is located and the fault quantity corresponding to the target column address where the target storage address is located.

[0079] Furthermore, since the target storage address is a storage address with a single-bit fault in the storage array, the number of faults corresponding to each target row address and the number of faults corresponding to each target column address are both 1.

[0080] Step S120: Generate a processing list based on the number of faults corresponding to each target storage address; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, and the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each target storage address.

[0081] Here, the number of failures corresponding to each target storage address refers to: summing the number of failures corresponding to the target storage addresses to obtain the total number of failures, and continuing to execute subsequent steps based on the obtained total number of failures; wherein the total number of failures can be obtained by summing the number of failures corresponding to each target row address or by summing the number of failures corresponding to each target column address.

[0082] In addition, since the number of faults corresponding to each target row address and each target column address is 1, the total number of faults corresponding to the target storage addresses is equal to the number of target row addresses and equal to the number of target column addresses; for example, the number of target row addresses and the number of target column addresses are both 4 and equal to the total number of faults corresponding to the target storage addresses.

[0083] Furthermore, the sum of the number of target row addresses that need to be repaired and the number of target column addresses that need to be repaired can be determined by the total number of faults corresponding to the target storage address. It can be understood that for each single-bit fault, it is only necessary to repair the target row address or the target column address where it is located, so as to repair the single-bit fault, without having to repair both the target row address and the target column address where the single-bit fault is located. For example, if the total number of faults corresponding to the target storage address is 4, then the number of faulty units that need to be repaired is 4, and these 4 faulty units are located at different target row addresses and different target column addresses in the storage array, and the sum of the corresponding number of target row addresses that need to be repaired and the number of target column addresses that need to be repaired is 4; when implementing the repair, the number of target row addresses that need to be repaired and the number of target column addresses that need to be repaired can be set as needed, so as to repair each target storage address in the storage array.

[0084] It should be noted that when repairing a target storage address, only the target row address or target column address of the target storage address needs to be repaired; for example, when repairing the column where the target storage address is located, there is no need to repair the row where the target storage address is located. In this way, repeated repair of a target storage address is avoided, thereby improving the utilization rate of the target redundant rows and target redundant columns.

[0085] In addition, in DRAM and other memories, in addition to the normally working storage array, there is also a redundant storage array, which is used to repair the storage address in the storage array when it fails. The target redundant row and target redundant column refer to the redundant row and redundant column in the redundant storage array that can be used for repair, respectively. The target redundant row and target redundant column are used to replace the failed row / column in the storage array to work and achieve repair. The number of target redundant rows and target redundant columns is allocated according to the total number of faults corresponding to the target storage address, and at least one repair allocation scheme is obtained; for example, the total number of faults corresponding to the target storage address is 4, if the number of target redundant rows and target redundant columns are both 3, 3 repair allocation schemes can be obtained, which are: 1 target redundant row and 3 target redundant columns; 2 target redundant rows and 2 target redundant columns; 3 target redundant rows and 1 target redundant column.

[0086] It should be noted that the total number of faults corresponding to the target storage address is less than the sum of the number of target redundant rows and target redundant columns. Otherwise, some target storage addresses cannot be repaired. In this way, each target storage address in the storage array can be repaired, so that the repair accuracy is high.

[0087] In the disclosed embodiment, when repairing the target storage address, since each target storage address is relatively independent, it is not dependent on the type of redundant resources, and both the target redundant row and the target redundant column can be used for repair allocation.

[0088] Step S130: repairing each target storage address according to the repair allocation plan.

[0089] Here, the repair allocation scheme in the processing list can be selected according to actual needs to repair the storage array, so as to repair each target storage address; still taking the total number of faults as 4 as an example, 1 target row address and 3 target column addresses can be repaired respectively through 1 target redundant row and 3 target redundant columns; for another example, 2 target row addresses and 2 target column addresses can be repaired respectively through 2 target redundant rows and 2 target redundant columns; for another example, 3 target row addresses and 1 target column address can be repaired respectively through 3 target redundant rows and 1 target redundant column.

[0090] In the disclosed embodiment, after obtaining the target fault statistics table, a processing list is generated according to the number of faults corresponding to each target storage address, so that each target storage address can be directly repaired based on the repair allocation plan in the processing list; that is, based on the repair allocation plan in the processing list, all target storage addresses with single-bit faults in the storage array can be repaired at the same time, so that the target storage addresses can be repaired faster and with higher repair efficiency.

[0091] The repair method in the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0092] In some embodiments, please refer to Figure 1 and Figure 2 , step S110, obtaining a target fault statistics table, including: steps S111 to S113.

[0093] Step S111: obtaining an initial fault statistics table; the initial fault statistics table includes a number of initial storage addresses and the number of faults corresponding to each initial storage address; wherein the initial storage address is a storage address in the storage array having at least one bit fault; the initial storage address includes an initial row address and an initial column address.

[0094] Here, the initial fault statistics table includes an initial fault row statistics table and an initial fault column statistics table. The initial fault row statistics table includes at least one initial row address and the number of faults corresponding to each initial row address. The initial fault column statistics table includes at least one initial column address and the number of faults corresponding to each initial column address.

[0095] In some embodiments, please refer to Figures 2 to 5, step S111, obtaining an initial fault statistics table, including: steps S111a to S111c.

[0096] Step S111a: performing fault analysis on the storage array to determine the number of faults corresponding to each row address and each column address.

[0097] Please refer to Figure 4 , the storage array 100 includes 9 row addresses and 9 column addresses, wherein the horizontal direction represents the row address and the vertical direction represents the column address. Perform fault analysis on the storage array 100 to determine the number of faults corresponding to each row address and each column address. For example, the number of faults corresponding to the 0th row address is 0; the number of faults corresponding to the 1st row address is 2; ...; the number of faults corresponding to the 8th row address is 1; and the number of faults corresponding to the 9th row address is 0. And, the number of faults corresponding to the 0th column address is 0; the number of faults corresponding to the 1st column address is 2; ...; the number of faults corresponding to the 8th column address is 1; and the number of faults corresponding to the 9th column address is 0.

[0098] It should be noted that the embodiments of the present disclosure are based on Figure 4 The memory array 100 in the embodiment is used as an example for description; in other embodiments, the number of row addresses and column addresses in the memory array 100 may be any achievable number, and the number of faults in the memory array 100 is obtained according to actual fault analysis.

[0099] Step S111b: determining a row address with at least one bit failure as an initial row address to obtain at least one initial row address; and determining a column address with at least one bit failure as an initial column address to obtain at least one initial column address.

[0100] Please continue to refer to Figure 4 , since the number of faults corresponding to the first row address is 2 (i.e., there are two-bit faults), the first row address is determined as the initial row address; ...; the number of faults corresponding to the eighth row address is 1 (i.e., there is one-bit fault), so the eighth row address is determined as the initial row address. And, the number of faults corresponding to the first column address is 2 (i.e., there are two-bit faults), so the first column address is determined as the initial column address; ...; the number of faults corresponding to the eighth column address is 1 (i.e., there is one-bit fault), so the eighth column address is determined as the initial column address.

[0101] Step S111c: Generate an initial fault row statistics table according to each initial row address and the number of faults corresponding to the initial row address; and generate an initial fault column statistics table according to each initial column address and the number of faults corresponding to the initial column address.

[0102] Please refer to Figure 5, generate an initial fault row statistics table according to each initial row address obtained in step S111b and the number of faults corresponding to the initial row address; wherein, in order to facilitate analysis in subsequent steps, the number of faults in the initial fault row statistics table can be arranged in order from large to small, or from small to large.

[0103] Please continue to refer to Figure 5 According to each initial column address obtained in step S111b and the number of faults corresponding to the initial column address, an initial fault column statistics table is generated. In order to facilitate the analysis in the subsequent steps, the number of faults in the initial fault column statistics table can be arranged in order from large to small, or from small to large.

[0104] Step S112: Determine a number of target storage addresses in the initial fault statistics table.

[0105] Here, the initial fault row statistics table includes N initial row addresses and the corresponding fault numbers, and the initial fault column statistics table includes M initial column addresses and the corresponding fault numbers; for details, please continue to refer to Figure 5 , N=6, M=8, the initial fault row statistics table includes 6 initial row addresses and the corresponding fault numbers, and the initial fault column statistics table includes 8 initial column addresses and the corresponding fault numbers.

[0106] In some embodiments, step S112, in the initial fault statistics table, determines a number of target storage addresses, specifically including: if the number of faults corresponding to the ith initial row address and the number of faults corresponding to the jth initial column address are both 1, and the fault in the ith initial row address and the fault in the jth initial column address are the same fault, then determines the ith initial row address as the target row address, and determines the jth initial column address as the target column address.

[0107] Wherein, i is an integer greater than 0 and less than or equal to N, and j is an integer greater than 0 and less than or equal to M. In a specific example, please continue to refer to Figure 4 and Figure 5, i is an integer greater than 0 and less than or equal to 6, and j is an integer greater than 0 and less than or equal to 8. For example, the number of faults corresponding to the 4th initial row address and the number of faults corresponding to the 3rd initial column address are both 1, and the fault in the 4th initial row address is the same as the fault in the 3rd initial column address, then the 4th initial row address is determined as the target row address, and the 3rd initial column address is determined as the target column address; for another example, the number of faults corresponding to the 8th initial row address and the number of faults corresponding to the 5th initial column address are both 1, and the fault in the 8th initial row address is the same as the fault in the 5th initial column address, then the 8th initial row address is determined as the target row address, and the 5th initial column address is determined as the target column address. For another example, although the 6th initial column address contains only one-bit fault, the fault also belongs to the 3rd initial row address, and the 3rd initial row address contains 3-bit faults, so the 6th initial column address cannot be used as the target column address, and so on.

[0108] In the embodiment of the present disclosure, the target row address and the target column address may be determined in the following two ways, but are not limited to the following two ways:

[0109] The first one: please refer to Figure 6 According to RA logic, single-bit faults are often analyzed and repaired last. That is, after all non-single-bit faults are repaired, the initial row addresses of all remaining faults are the target row addresses, and the column addresses are the target column addresses. For example, non-single-bit faults such as Figure 6 As shown in the middle dotted line mark, after the non-single-bit type fault is repaired, the remaining 4th initial row address, 5th initial row address, 7th initial row address and 8th initial row address are all target row addresses; and the 2nd initial column address, 3rd initial column address, 5th initial column address and 7th initial column address are all target column addresses.

[0110] The second method: when the non-single-bit type fault is not repaired, the target row address and the target column address can also be directly determined. Specifically, it is determined whether the number of the i-th initial row address is 1. When the number of faults in the i-th initial row address is 1, it is determined whether the number of faults in the initial column address in the initial fault column statistics table is 1 according to a preset order, and when the judgment result is yes, it is determined whether the fault in the initial column address with the number of faults of 1 is the same fault as the fault in the i-th initial row address, until the number of faults corresponding to the i-th initial row address and the number of faults corresponding to the j-th initial column address are both 1, and the fault in the i-th initial row address and the fault in the j-th initial column address are the same fault, the i-th initial row address is determined to be the target row address, and the j-th initial column address is determined to be the target column address.

[0111] When implementing, please refer to Figure 4 and Figure 7 , determine whether the number of the 4th initial row address is 1. When the number of faults in the 4th initial row address is 1, determine whether the number of faults in the 2nd initial column address in the initial fault column statistics table is 1 in a preset order (for example, from top to bottom, i.e., in ascending order of the number of faults), and when the judgment result is yes, determine whether the fault in the 2nd initial column address is the same fault as the fault in the 4th initial row address. When the fault in the 2nd initial column address is not the same fault as the fault in the 4th initial row address, continue to determine in a preset order until the number of faults corresponding to the 4th initial row address and the number of faults corresponding to the 3rd initial column address are both 1, and when the fault in the 4th initial row address is the same fault as the fault in the 3rd initial column address, determine the 4th initial row address as the target row address, and determine the 3rd initial column address as the target column address.

[0112] Next, it is determined whether the number of the fifth initial row address is 1. If the number of faults in the fifth initial row address is 1, it is determined whether the number of faults in the second initial column address in the initial fault column statistics table is 1 in a preset order (e.g., from top to bottom). If the judgment result is yes, it is determined whether the fault in the second initial column address is the same fault as the fault in the fifth initial row address. If the fault in the second initial column address is not the same fault as the fault in the fifth initial row address, it is determined that the fourth initial column address, the fifth initial column address, and the like are judged in sequence in a preset order until the number of faults corresponding to the fifth initial row address and the number of faults corresponding to the seventh initial column address are both 1, and the fault in the fifth initial row address is the same fault as the fault in the seventh initial column address. Then, the fifth initial row address is determined to be the target row address, and the seventh initial column address is determined to be the target column address. And so on, and the embodiments of the present disclosure will not be repeated in detail.

[0113] Alternatively, determine whether the number of the j-th initial column address is 1. When the number of faults in the j-th initial column address is 1, determine whether the number of faults in the initial row address in the initial fault row statistics table is 1 in a preset order, and when the judgment result is yes, determine whether the faults in the initial row address with the fault number of 1 are the same faults as the faults in the j-th initial column address, until the number of faults corresponding to the ith initial row address and the number of faults corresponding to the j-th initial column address are both 1, and the faults in the ith initial row address and the faults in the j-th initial column address are the same faults, determine the ith initial row address as the target row address, and determine the j-th initial column address as the target column address.

[0114] When implementing, please refer to Figure 4 and Figure 7 , determine whether the number of the second initial column address is 1, and if the number of faults in the second initial column address is 1, determine whether the number of faults in the fourth initial row address is 1 in a preset order (e.g., from top to bottom), and if the judgment result is yes, determine whether the fault in the fourth initial row address is the same fault as the fault in the second initial column address, and continue to determine in a preset order. If the second initial column address is not the same fault as any initial row address with a fault number of 1, then the second initial column address is not the target column address. In this way, each initial row address and each initial column address are determined in turn to obtain a target row address and a target column address, and the embodiment of the present disclosure will not be repeated.

[0115] It should also be noted that the preset order may also be from bottom to top, that is, in descending order of the number of faults, and there is no specific limitation on this.

[0116] According to the above analysis, it can be seen that since the number of faults corresponding to the target row address and the target column address is counted in the redundant analysis preprocessing stage, it is possible to directly determine whether the fault distribution belongs to a single-bit type of fault based on the fault values ​​corresponding to the target row address and the target column address, so that the target row address and / or target column address can be directly repaired in the subsequent process.

[0117] Step S113: obtaining a target fault statistics table according to a number of target storage addresses and the number of faults corresponding to the target storage addresses.

[0118] In some embodiments, step S113 obtains a target fault statistics table based on a number of target storage addresses and the number of faults corresponding to the target storage addresses, specifically including: generating a target fault row statistics table based on the target row address and the number of faults corresponding to the target row address; and generating a target fault column statistics table based on the target column address and the number of faults corresponding to the target column address.

[0119] Please refer to Figure 8 , a target fault statistical table is generated according to each target row address and the number of faults corresponding to the target row address obtained in step S112; wherein the number of faults corresponding to each target row address in the target fault row statistical table is 1.

[0120] Please continue to refer to Figure 8 , a target fault statistics table is generated according to each target column address and the number of faults corresponding to the target column address obtained in step S112; wherein, in the target fault statistics table, the number of faults corresponding to the target row address and the number of faults corresponding to the target row address are both 1.

[0121] It should be noted that, since the number of faults corresponding to each target row address and each target column address is 1, the total number of faults corresponding to the target storage address is equal to the number of target row addresses and the number of target column addresses; for example, please continue to refer to Figure 8 , the total number of faults corresponding to the target storage address is 4, and the number of target row addresses and the number of target column addresses are also 4.

[0122] In some embodiments, please refer to Figure 1 and Fig. 9 , step S120, generating a processing list based on the number of failures corresponding to each target storage address, including: steps S121 to S124.

[0123] Step S121: summing the number of failures corresponding to each target storage address to determine the total number of failures.

[0124] Here, each target storage address can be summed to determine the total number of faults. In addition, the number of faults corresponding to each target row address can be summed to determine the total number of faulty rows; the number of faults corresponding to each target column address can be summed to determine the total number of faulty columns; wherein the total number of faults is equal to the total number of faulty rows and equal to the total number of faulty columns.

[0125] Please refer to Figure 6 and Figure 8 , for example, the total number of faults is 4, which is equal to the total number of faulty rows, which is equal to the total number of faulty columns.

[0126] Step S122: Obtain the number of redundant rows and the number of redundant columns, where the number of redundant rows indicates the number of redundant rows that can be used to repair the target storage row, and the number of redundant columns indicates the number of redundant columns that can be used to repair the target storage column.

[0127] Specifically, the number of redundant rows is the number of redundant rows in the redundant storage array that can be used to repair the target storage row, and the number of redundant columns is the number of redundant columns in the redundant storage array that can be used to repair the target storage row. For example, the number of redundant rows and the number of redundant columns are both 3, and for another example, the number of redundant rows and the number of redundant columns are both 4.

[0128] Step S123: Determine at least one repair allocation scheme according to preset rules; wherein the preset rules include: the rule that the sum of the target number of redundant rows and the target number of redundant columns is equal to the total number of faults, and the target number of redundant rows is less than or equal to the number of redundant rows, and the target number of redundant columns is less than or equal to the number of redundant columns.

[0129] Here, since the sum of the number of target row addresses to be repaired and the number of target column addresses to be repaired is equal to the total number of faults, the sum of the target number of redundant rows and the target number of redundant columns is equal to the total number of faults. During implementation, the target number of redundant rows and the target number of redundant columns can be set as needed, so as to repair each target storage address in the storage array.

[0130] In some embodiments, please refer to Fig.10 The processing list includes 2 columns, and each row of the processing list corresponds to a repair allocation scheme; step S123, determining at least one repair allocation scheme according to a preset rule, further comprising:

[0131] Step S123a: In the first column of the processing list, the target redundant row quantities are sorted in descending order from the first redundant row quantity to the second redundant row quantity.

[0132] Please continue to refer to Fig.10 , the first redundant row number is min(SR, max_nr), and the second redundant row number is Tf-min(SC, max_nc); wherein SR represents the number of redundant rows, SC represents the number of redundant columns, max_nc represents the total number of faulty columns, max_nr represents the total number of faulty rows, and Tf represents the total number of faults.

[0133] That is, the first redundant row number is the smaller one of the redundant row number and the total number of faulty rows, and the second redundant row number is the difference between the total number of faulty rows and the first redundant row number.

[0134] Step S123b: In the second column of the processing list, the target redundant column quantities are sorted in ascending order from the second redundant column quantity to the first redundant column quantity.

[0135] Please continue to refer to Fig.10 , the number of second redundant columns is Tf-min(SR, max_nr), and the number of first redundant columns is Min(SC, max_nc).

[0136] That is, the first redundant column quantity is the smaller one of the redundant column quantity and the total number of faulty columns; the second redundant column quantity is the difference between the total number of faulty columns and the first redundant column quantity.

[0137] Step S124: Generate a processing list according to each repair allocation scheme.

[0138] Here, when the total number of faults corresponding to the target storage address is 4, and the number of target redundant rows and target redundant columns is 3, three repair allocation schemes can be obtained, which are: 1 target redundant row and 3 target redundant columns; 2 target redundant rows and 2 target redundant columns; 3 target redundant rows and 1 target redundant column. The generated processing list is as follows: Fig.11As shown in the middle left figure; when the total number of faults corresponding to the target storage address is 4, and the number of target redundant rows and target redundant columns is 4, 5 repair allocation schemes can be obtained, which are: 0 target redundant rows and 4 target redundant columns; ...; 4 target redundant rows and 0 target redundant columns. The generated processing list is as follows Fig.11 As shown in the middle right picture.

[0139] In the disclosed embodiment, the target redundant rows and target redundant columns can be allocated according to the number of total faults, and a processing list can be directly generated; based on the processing list, the target storage row address and the target storage column address can be repaired at the same time, so that the analysis speed is greatly improved and the repair efficiency is good. In addition, when repairing the target storage address, since each target storage address is relatively independent, it is not dependent on the type of redundant resources, and both the target redundant rows and target redundant columns can be used for repair allocation; when generating the processing list, the processing list includes each allocation scheme that can be used for repair, so that the normalized repair rate is 100%.

[0140] In some embodiments, please refer to Figure 1 and Fig.12 , step S130, repairing each target storage address according to the repair allocation plan, including: step S131 to step S132.

[0141] Step S131: Determine the target number of redundant rows and the target number of redundant columns according to the repair allocation scheme.

[0142] Here, you can select the repair allocation scheme in the processing list according to actual needs. Fig.11 In the middle left figure, 1 target redundant row and 3 target redundant columns are selected; for example, according to Fig.11 In the middle right figure, 2 target redundant rows and 2 target redundant columns are selected.

[0143] Step S132: repair the target storage row using the target redundant row number redundant rows; and repair the target storage column using the target redundant column number redundant columns.

[0144] Specifically, for example, one target row address and three target column addresses can be repaired respectively through one target redundant row and three target redundant columns, thereby repairing each target storage address; for another example, two target row addresses and two target column addresses can be repaired respectively through two target redundant rows and two target redundant columns, thereby repairing each target storage address.

[0145] It should be noted that when repairing the target storage address, only the target row address or the target column address in the target storage address needs to be repaired; for example, please refer to Figure 6When repairing the row where the 4th target row address is located, there is no need to repair the column where the 4th target row address is located (i.e., the 3rd target column address). In this way, repeated repair of a target storage address is avoided, and the utilization rate of the target redundant rows and target redundant columns is improved.

[0146] In the disclosed embodiment, after obtaining the target fault statistics table, a processing list is generated according to the number of faults corresponding to each target storage address, so that each target storage address can be directly repaired based on the repair allocation plan in the processing list; that is, all target storage addresses in the storage array can be repaired at the same time based on the repair allocation plan in the processing list, so that the target storage addresses can be repaired faster and with higher repair efficiency.

[0147] In short, the disclosed embodiment adopts a method for pattern recognition of single-bit fault distribution. In the process of single-bit redundant analysis and solution matching, it is no longer necessary to match the faults one by one. Instead, a processing list is directly generated according to the fault address, and the single-bit fault can be directly matched according to the processing list. In other words, since the method of directly generating the processing list is adopted, it is not necessary to match each single bit one by one, so the matching efficiency will be greatly improved. And the analysis can be performed only based on the fault numerical information obtained by preprocessing. Compared with other RA methods, there is no solution search process in theory, and the analysis speed will be greatly improved.

[0148] In another embodiment of the present disclosure, Fig.13 As shown, it shows a schematic diagram of the composition structure of a repair device provided by an embodiment of the present disclosure, which is applied to a repair method of a target faulty unit, where the target faulty unit is a storage unit with a single-bit fault in a storage array, such as Fig.13 As shown, the repair device 20 includes:

[0149] The acquisition module 21 is configured to acquire a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each target storage address; wherein the target storage address is a storage address having a single-bit fault in the storage array; the target storage address includes a target row address and a target column address;

[0150] The generating module 22 is configured to generate a processing list based on the number of faults corresponding to each target storage address; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each target storage address;

[0151] The repair module 23 is configured to repair each target storage address according to the repair allocation scheme.

[0152] In some embodiments, the acquisition module 21 includes: a first acquisition submodule, a first determination submodule and a second determination submodule; wherein: the first acquisition submodule is configured to acquire an initial fault statistics table; the initial fault statistics table includes a number of initial storage addresses and the number of faults corresponding to each initial storage address; wherein the initial storage address is a storage address in the storage array where there is at least one bit of fault; the initial storage address includes an initial row address and an initial column address; the first determination submodule is configured to determine a number of target storage addresses in the initial fault statistics table; the second determination submodule is configured to obtain a target fault statistics table based on a number of target storage addresses and the number of faults corresponding to the target storage addresses.

[0153] In some embodiments, the initial fault statistics table includes an initial fault row statistics table and an initial fault column statistics table, the initial fault row statistics table includes at least one initial row address and the number of faults corresponding to each initial row address, and the initial fault column statistics table includes at least one initial column address and the number of faults corresponding to each initial column address; the storage array includes at least one row address and at least one column address; the first acquisition submodule includes: a first determination unit, a second determination unit and a generation unit; wherein: the first determination unit is configured to perform fault analysis on the storage array, and determine the number of faults corresponding to each row address and each column address respectively; the second determination unit is configured to determine the row address with at least one bit fault as the initial row address, and obtain at least one initial row address; and determine the column address with at least one bit fault as the initial column address, and obtain at least one initial column address; the generation unit is configured to generate the initial fault row statistics table according to each initial row address and the number of faults corresponding to the initial row address; and generate the initial fault column statistics table according to each initial column address and the number of faults corresponding to the initial column address.

[0154] In some embodiments, the initial fault row statistics table includes N initial row addresses and corresponding fault numbers, and the initial fault column statistics table includes M initial column addresses and corresponding fault numbers; the first determination submodule is specifically configured to determine the i-th initial row address as the target row address, and determine the j-th initial column address as the target column address if the fault number corresponding to the i-th initial row address and the fault number corresponding to the j-th initial column address are both 1, and the fault in the i-th initial row address and the fault in the j-th initial column address are the same fault; wherein i is an integer greater than 0 and less than or equal to N, and j is an integer greater than 0 and less than or equal to M.

[0155] In some embodiments, the target fault statistics table includes a target fault row statistics table and a target fault column statistics table; the second determination submodule is specifically configured to generate a target fault row statistics table based on the target row address and the number of faults corresponding to the target row address; and to generate a target fault column statistics table based on the target row address and the number of faults corresponding to the target row address.

[0156] In some embodiments, the generation module 22 includes: a third determination submodule, a second acquisition submodule, a fourth determination submodule and a generation submodule; wherein: the third determination submodule is configured to sum the number of faults corresponding to each target storage address to determine the total number of faults; the second acquisition submodule is configured to acquire the number of redundant rows and the number of redundant columns, the number of redundant rows represents the number of redundant rows that can be used to repair the target storage row, and the number of redundant columns represents the number of redundant columns that can be used to repair the target storage column; the fourth determination submodule is configured to determine at least one repair allocation scheme according to preset rules; wherein the preset rules include: the rule that the sum of the target number of redundant rows and the target number of redundant columns is equal to the total number of faults, and the target number of redundant rows is less than or equal to the number of redundant rows, and the target number of redundant columns is less than or equal to the number of redundant columns; the generation submodule is configured to generate a processing list according to each repair allocation scheme.

[0157] In some embodiments, the number of faults corresponding to each target row address is summed to determine the total number of faulty rows; the number of faults corresponding to each target column address is summed to determine the total number of faulty columns; the processing list includes 2 columns, and each row of the processing list corresponds to a repair allocation scheme; the fourth determination submodule is also configured to sort the target redundant row number in the first column of the processing list in descending order from the first redundant row number to the second redundant row number; in the second column of the processing list, sort the target redundant column number in ascending order from the second redundant column number to the first redundant column number; wherein the first redundant row number is the smaller of the redundant row number and the total number of faulty rows, and the first redundant column number is the smaller of the redundant column number and the total number of faulty columns; the second redundant row number is the difference between the total number of faults and the first redundant column number; the second redundant column number is the difference between the total number of faults and the first redundant row number.

[0158] In some embodiments, the repair module 23 includes: a fifth determination submodule and a repair submodule; wherein: the fifth determination submodule is configured to determine the target number of redundant rows and the target number of redundant columns according to the repair allocation plan; the repair submodule is configured to repair the target storage rows using the target number of redundant rows; and repair the target storage columns using the target number of redundant columns.

[0159] In some embodiments, in the target fault statistics table, the number of faults corresponding to the target row address and the number of faults corresponding to the target row address are both 1.

[0160] In the disclosed embodiment, after obtaining the target fault statistics table, a processing list is generated according to the number of faults corresponding to each target storage address, so that each target storage address can be directly repaired based on the repair allocation plan in the processing list; that is, all target storage addresses in the storage array can be repaired at the same time based on the repair allocation plan in the processing list, so that the target storage addresses can be repaired faster and with higher repair efficiency.

[0161] It should be noted that the description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects as the method embodiment. For technical details not disclosed in the device embodiment of the present disclosure, please refer to the description of the method embodiment of the present disclosure for understanding.

[0162] It should be noted that in the embodiments of the present disclosure, if the above method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of commands to enable an electronic device (which can be a personal computer, server, etc.) to execute all or part of the methods of each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a ROM (Read Only Memory), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0163] Correspondingly, an embodiment of the present disclosure provides an electronic device, including: a memory and a processor, the memory stores a computer program that can be run on the processor, and when the processor executes the program, the steps in the method of repairing the device provided in the above embodiment are implemented.

[0164] Correspondingly, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps in the method of repairing the device are implemented.

[0165] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and electronic device embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure for understanding.

[0166] Fig.14 A hardware entity diagram of an electronic device provided by an embodiment of the present disclosure, such as Fig.14As shown, the hardware entity of the electronic device 30 includes: a processor 31, a communication interface 32 and a memory 33, wherein the processor 31 generally controls the overall operation of the electronic device 30; the communication interface 32 enables the electronic device 30 to communicate with other electronic devices or servers or platforms through a network.

[0167] The processor 31 , the communication interface 32 and the memory 33 are connected via a bus.

[0168] The memory 33 is configured to store commands and applications executable by the processor 31, and can also cache data to be processed or processed by the processor 31 and various modules in the electronic device 30 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (Flash) or random access memory (Random Access Memory, RAM).

[0169] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0170] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0171] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0172] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0173] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0174] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0175] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A repair method, characterized in that: The method comprises: Obtain a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each of the target storage addresses; wherein the target storage address is a storage address having a single-bit fault in the storage array; the target storage address includes a target row address and a target column address; Generate a processing list based on the number of failures corresponding to each of the target storage addresses; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each of the target storage addresses; Repair each of the target storage addresses according to the repair allocation scheme.

2. The repair method according to claim 1, characterized in that: The step of obtaining a target fault statistics table includes: Obtaining an initial fault statistics table; the initial fault statistics table includes a number of initial storage addresses and the number of faults corresponding to each of the initial storage addresses; wherein the initial storage address is a storage address in the storage array where at least one bit of fault exists; the initial storage address includes an initial row address and an initial column address; In the initial fault statistics table, determining the plurality of target storage addresses; The target fault statistics table is obtained according to the plurality of target storage addresses and the number of faults corresponding to the target storage addresses.

3. The repair method according to claim 2, characterized in that: The initial fault statistics table includes an initial fault row statistics table and an initial fault column statistics table, wherein the initial fault row statistics table includes at least one initial row address and the number of faults corresponding to each initial row address, and the initial fault column statistics table includes at least one initial column address and the number of faults corresponding to each initial column address; the storage array includes at least one row address and at least one column address; The obtaining of the initial fault statistics table includes: Performing fault analysis on the storage array to respectively determine the number of faults corresponding to each row address and each column address; Determine the row address with at least one bit failure as the initial row address to obtain at least one initial row address; and determine the column address with at least one bit failure as the initial column address to obtain at least one initial column address; The initial fault row statistics table is generated according to each of the initial row addresses and the number of faults corresponding to the initial row addresses; and the initial fault column statistics table is generated according to each of the initial column addresses and the number of faults corresponding to the initial column addresses.

4. The repair method according to claim 3, characterized in that: The initial fault row statistics table includes N initial row addresses and corresponding fault numbers, and the initial fault column statistics table includes M initial column addresses and corresponding fault numbers; In the initial fault statistics table, determining the plurality of target storage addresses includes: If the number of faults corresponding to the i-th initial row address and the number of faults corresponding to the j-th initial column address are both 1, and the fault in the i-th initial row address and the fault in the j-th initial column address are the same fault, then the i-th initial row address is determined to be the target row address, and the j-th initial column address is determined to be the target column address; Wherein, i is an integer greater than 0 and less than or equal to N, and j is an integer greater than 0 and less than or equal to M.

5. The method according to claim 4, characterized in that The target fault statistics table includes a target fault row statistics table and a target fault column statistics table; the target fault statistics table is obtained according to the plurality of target storage addresses and the number of faults corresponding to the target storage addresses, including: A target fault row statistics table is generated according to the target row address and the number of faults corresponding to the target row address; and a target fault column statistics table is generated according to the target column address and the number of faults corresponding to the target column address.

6. The method according to claim 1, characterized in that The generating a processing list based on the number of failures corresponding to each of the target storage addresses includes: Sum the number of failures corresponding to each of the target storage addresses to determine the total number of failures; Acquire the number of redundant rows and the number of redundant columns, wherein the number of redundant rows indicates the number of redundant rows that can be used to repair the target storage row, and the number of redundant columns indicates the number of redundant columns that can be used to repair the target storage column; Determine at least one of the repair allocation schemes according to preset rules; wherein the preset rules include: a rule that the sum of the target number of redundant rows and the target number of redundant columns is equal to the total number of faults, and the target number of redundant rows is less than or equal to the number of redundant rows, and the target number of redundant columns is less than or equal to the number of redundant columns; According to each of the repair allocation schemes, the processing list is generated.

7. The method according to claim 6, characterized in that The number of faults corresponding to each of the target row addresses is summed to determine the total number of faulty rows; the number of faults corresponding to each of the target column addresses is summed to determine the total number of faulty columns; the processing list includes 2 columns, and each row of the processing list corresponds to a repair allocation scheme; The determining at least one of the repair allocation schemes according to the preset rules further includes: In the first column of the processing list, sorting the target redundant row numbers in descending order from the first redundant row number to the second redundant row number; In the second column of the processing list, sorting the target redundant column quantities in ascending order from the second redundant column quantity to the first redundant column quantity; Among them, the first redundant row number is the smaller of the redundant row number and the total number of faulty rows, the first redundant column number is the smaller of the redundant column number and the total number of faulty columns; the second redundant row number is the difference between the total number of faults and the first redundant column number; the second redundant column number is the difference between the total number of faults and the first redundant row number.

8. The repair method according to claim 1, characterized in that: Repairing each of the target storage addresses according to the repair allocation scheme includes: Determining the target number of redundant rows and the target number of redundant columns according to the repair allocation scheme; The target storage row is repaired by using the redundant rows of the target redundant row quantity; and the target storage column is repaired by using the redundant columns of the target redundant column quantity.

9. The method according to any one of claims 1 to 8, characterized in that: In the target fault statistics table, the number of faults corresponding to the target row address and the number of faults corresponding to the target row address are both 1.

10. A repair device, characterized in that: A repair method applied to a target faulty unit, wherein the target faulty unit is a storage unit with a single-bit fault in a storage array, and the device comprises: An acquisition module is configured to acquire a target fault statistics table; the target fault statistics table includes a plurality of target storage addresses and the number of faults corresponding to each of the target storage addresses; wherein the target storage address is a storage address having a single-bit fault in the storage array; the target storage address includes a target row address and a target column address; A generating module is configured to generate a processing list based on the number of failures corresponding to each of the target storage addresses; the processing list includes at least one repair allocation scheme, the repair allocation scheme includes a target number of redundant rows and a target number of redundant columns, the target number of redundant rows and the target number of redundant columns represent the number of redundant rows and redundant columns required to repair each of the target storage addresses; The repair module is configured to repair each of the target storage addresses according to the repair allocation scheme.

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