Operation method of memory, memory and memory system

Abstract

The embodiment of the invention provides an operation method of a memory, the memory and a memory system. The operation method comprises the following steps: in a PPR (Post-Package Repair) mode, in response to the fact that a first defective storage unit row in a plurality of storage unit rows is repaired before packaging, enabling a first repair strategy for repairing the first defective storage unit row before packaging to be invalid; and configuring a second repair strategy for repairing the first defective storage unit row, and storing the second repair strategy.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a memory operation method, a memory, and a memory system. Background Art

[0002] In a memory, information may be stored in memory cells, which may be organized into rows (word lines) and columns (bit lines). At various times in the manufacture and use of a memory, one or more memory cells may fail (e.g., become unable to store information, inaccessible by the memory, etc.) and may require repair. Summary of the invention

[0003] Some embodiments of the present application provide a memory operating method, a memory, and a memory system.

[0004] In one aspect, an embodiment of the present application provides a method for operating a memory, wherein the memory includes a plurality of memory cell rows; the method includes:

[0005] In a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, a first repair strategy for repairing the first defective memory cell row before packaging is invalidated;

[0006] A second repair strategy for repairing the first defective memory cell row is configured, and the second repair strategy is stored.

[0007] In the above solution, the memory further includes a read-only memory device ROM; the method of disabling the first repair strategy for repairing the first defective memory cell row before packaging includes:

[0008] Acquire first record information stored in the ROM; the first record information includes the first repair strategy;

[0009] Setting the first control position in the first record information to a first preset value;

[0010] When the first control bit is the first preset value, the first repair strategy is in an invalid state.

[0011] In the above scheme, the memory further includes a content addressable memory device CAM coupled to the plurality of memory cell rows; the method further includes:

[0012] Acquire first address information of the first defective memory cell row;

[0013] comparing the first address information with the address information stored in the CAM;

[0014] In response to the comparison result including that address information identical to the first address information is stored in the CAM, indication information is generated, wherein the indication information is used to indicate that the first defective memory cell row has been repaired.

[0015] In the above solution, the obtaining of the first record information stored in the ROM includes:

[0016] In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage;

[0017] acquiring the first record information from the ROM according to the second address information;

[0018] The indication information is used to indicate that the first defective storage unit row has been repaired.

[0019] In the above solution, the memory further includes a plurality of first redundant cell rows; the configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy includes:

[0020] Selecting a first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective memory cell row; the second mapping relationship is the second repair strategy;

[0021] generating second record information according to the second repair strategy;

[0022] storing the second record information in the ROM;

[0023] The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

[0024] In the above solution, the method further includes:

[0025] When performing an operation on the memory, determining whether the first repair strategy is effective or the second repair strategy is effective;

[0026] In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row;

[0027] In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

[0028] In the above solution, determining whether the first repair strategy is effective or the second repair strategy is effective includes:

[0029] Acquire the first record information and the second record information;

[0030] Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information;

[0031] The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

[0032] In the above scheme, the memory also includes multiple second redundant cell rows different from the multiple first redundant cell rows; the first repair strategy includes a mapping relationship between the first defective storage cell row and a second redundant cell row among the multiple second redundant cell rows.

[0033] In the above solution, the first record information also includes a second control bit; the second control bit is used to indicate whether the first repair strategy is to be enabled.

[0034] In the above solution, the operation includes powering on the memory.

[0035] On the other hand, an embodiment of the present application further provides a memory, including:

[0036] A storage array, comprising: a plurality of storage unit rows;

[0037] The peripheral circuit is coupled to the memory array and is configured to:

[0038] In a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, a first repair strategy for repairing the first defective memory cell row before packaging is invalidated;

[0039] A second repair strategy for repairing the first defective memory cell row is configured, and the second repair strategy is stored.

[0040] In the above solution, the memory further includes a read-only memory device ROM; and the peripheral circuit is further configured as follows:

[0041] Acquire first record information stored in the ROM; the first record information includes the first repair strategy;

[0042] Setting the first control position in the first record information to a first preset value;

[0043] When the first control bit is the first preset value, the first repair strategy is in an invalid state.

[0044] In the above solution, the memory further includes a content addressable memory device CAM coupled to the plurality of memory cell rows, and the peripheral circuit is further configured as:

[0045] Acquire first address information of the first defective memory cell row; and transmit the first address information to the CAM;

[0046] The CAM is configured to: compare the first address information with the address information stored in the CAM; and in response to the comparison result including address information stored in the CAM that is identical to the first address information, generate indication information, wherein the indication information is used to indicate that the first defective storage cell row has been repaired.

[0047] In the above solution, the peripheral circuit is further configured as:

[0048] In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage;

[0049] acquiring the first record information from the ROM according to the second address information;

[0050] The indication information is used to indicate that the first defective storage unit row has been repaired.

[0051] In the above solution, the storage array further includes a plurality of first redundant cell rows; and the peripheral circuit is further configured as follows:

[0052] Selecting a first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective memory cell row; the second mapping relationship is the second repair strategy;

[0053] generating second record information according to the second repair strategy;

[0054] storing the second record information in the ROM;

[0055] The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

[0056] In the above solution, the peripheral circuit is further configured to: when performing an operation on the memory, determine whether the first repair strategy is effective or the second repair strategy is effective;

[0057] In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row;

[0058] In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

[0059] In the above solution, the peripheral circuit is further configured to: obtain the first record information and the second record information;

[0060] Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information;

[0061] The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

[0062] In the above scheme, the storage array also includes multiple second redundant cell rows different from the multiple first redundant cell rows; the first repair strategy includes a mapping relationship between the first defective storage cell row and a second redundant cell row among the multiple second redundant cell rows.

[0063] On the other hand, an embodiment of the present application further provides a memory system, comprising: one or more memories of any of the aforementioned items; and a memory controller coupled to and controlling the memory.

[0064] On the other hand, a computer system includes: the aforementioned memory system and an image processor, which is coupled to the memory system and controls the memory system.

[0065] The embodiments of the present application provide a method for operating a memory, a memory, and a memory system. The operating method includes: in a post-package repair (PPR) mode, in response to a first defective memory cell row among the multiple memory cell rows having been repaired before packaging, invalidating a first repair strategy for repairing the first defective memory cell row before packaging; configuring a second repair strategy for repairing the first defective memory cell row, and storing the second repair strategy. The operating method provided by the embodiments of the present application, in a post-package repair (PPR) mode, invalidates the first repair strategy used for the first defective cell row that has been repaired; then, reconfigures the second repair strategy to avoid conflicts in subsequent use caused by repeated repairs of the same defective cell row. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0067] Figure 1 A schematic diagram of an exemplary system having a memory system according to some aspects of the present application;

[0068] Figure 2 A schematic diagram of an exemplary electronic device having a memory system according to some aspects of the present application;

[0069] Figure 3 A schematic diagram of the composition principle of a memory provided according to some aspects of the present application;

[0070] Figure 4 Schematic diagram of the distribution of storage arrays and peripheral circuits provided according to some aspects of the present application Figure 1 ;

[0071] Figure 5 A top view of the distribution of a storage array and peripheral circuits in an exemplary memory provided according to some aspects of the present application Figure 1 ;

[0072] Figure 6 Schematic diagram of the distribution of storage arrays and peripheral circuits in an exemplary memory provided according to an embodiment of the present application Figure 2 ;

[0073] Figure 7 A top view of the distribution of a storage array and peripheral circuits in an exemplary memory provided according to an embodiment of the present application Figure 2 ;

[0074] Figure 8 and Fig. 9 A schematic diagram for exemplarily illustrating the conflict described in the present application according to an embodiment of the present application;

[0075] Fig.10 A schematic diagram of a memory operation method according to an embodiment of the present application Figure 1 ;

[0076] Fig.11 A schematic diagram of a memory operation method according to an embodiment of the present application Figure 2 ;

[0077] Figures 12 to 15 A flowchart for implementing the operating method provided by the present application according to an embodiment of the present application;

[0078] Fig.16 A schematic diagram of the structure of a memory provided according to an embodiment of the present application;

[0079] Fig.17 A schematic diagram of the structure of a memory system provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0080] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0081] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0082] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0083] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0084] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0085] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0086] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0087] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0088] Figure 1 A block diagram of an exemplary system having a memory system is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, the system 100 may include a host 108 and a memory system 102, wherein the memory system 102 has one or more memories 104 and a memory controller 106; the host 108 may be (for example, a central processing unit (CPU) or a graphics processing unit (GPU)). The host 108 may be configured to send data to the memory 104 or receive data from the memory 104 through the memory controller 106.

[0089] The memory controller 106 is coupled to the memory 104 and the host 108, and is configured to control the memory 104. The memory controller 106 may manage data stored in the memory 104, and communicate with the host 108.

[0090] The memory controller 106 may be configured to control operations of the memory 104, such as read, erase, write, and refresh operations. In some implementations, the memory controller 106 is also configured to process error correction codes (ECC) on data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol.

[0091] In some specific embodiments, one or more memories 104 and memory controller 106 can be integrated into various types of storage devices. For example, multiple memories 104 can be integrated into a memory stick; the memory controller 106 can be integrated into the north bridge of the motherboard or directly integrated into the CPU. In other words, the memory system 102 can be implemented and packaged into different types of terminals or electronic products.

[0092] In such Figure 2In a system example shown in , the system includes a system-on-chip (SoC) and one or more memories; the memory includes DRAM 204, and the SoC includes: a graphics processing unit (GPU) 208, a DRAM controller 206, and a DRAM physical layer 210; wherein the DRAM controller 206 is responsible for the scheduling of read and write instructions and the timing control of DRAM 204; the DRAM physical layer 210 is responsible for encoding the scheduled instructions according to the requirements of DRAM 204, and sending the corresponding write data to DRAM 204, and receiving the data read from DRAM 204. Wherein, PCB represents a printed circuit board.

[0093] Figure 3 A schematic diagram of an exemplary memory DRAM according to an embodiment of the present application; Figure 3 The right side shows the circuit of the storage unit in DRAM. Each DRAM chip 304 (Die) includes a storage array, which includes multiple storage cells 301 arranged in an array. Each storage cell 301 includes a transistor T (Transistor) and a capacitor C (Capacitor). The main working principle of the storage unit is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. The storage cells are arranged in an array, which can be regarded as a typical mesh structure. The storage array uses rows (Row) and columns (Column) to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of DRAM), the memory controller can independently access each storage cell in the DRAM chip and read or write the data stored in it.

[0094] In some embodiments, a memory may include a storage array and peripheral circuits, wherein the storage array includes a plurality of storage banks, each of which may be divided into a plurality of storage blocks or storage bodies, each of which includes a plurality of storage cell rows and a plurality of storage cell columns, each of which is coupled to a corresponding word line, and each of which is coupled to a corresponding bit line; the peripheral circuits may include a series of complementary metal-oxide-semiconductor (CMOS) control circuits; for example, the series of CMOS control circuits include: control circuits corresponding to each storage block, such as a sensing amplifier circuit (SA) and a word line driver circuit (WLD); control circuits corresponding to each storage bank, such as a row decoder, a column decoder, and the like; and control circuits corresponding to all storage banks, such as a command buffer, a command decoder, an address buffer, a data buffer, a mode register, and the like.

[0095] In actual application, the layout between the memory array and the peripheral circuit is different. In some embodiments, the memory array and the peripheral circuit are arranged in parallel on the same substrate. Figure 4 A schematic diagram showing the distribution of a storage array and peripheral circuits in the exemplary memory shown; Figure 5 A top view schematic diagram of the distribution of the storage array and peripheral circuits in the exemplary memory shown. Figure 4 As shown, the storage array 401 and the peripheral circuit 402 are arranged in parallel. More specifically, the storage array includes M banks, each bank includes N storage blocks, at least one side of each storage block is provided with a control circuit corresponding to the storage block, at least one side of each storage bank is provided with a control circuit corresponding to the storage bank, every K storage banks in the M storage banks form a storage bank row, the M storage banks form M / K storage bank rows, and the peripheral circuits corresponding to all the storage banks are arranged between the two middle storage bank rows. It should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0096] For example, Figure 5 As shown, the storage array 401 includes 16 storage banks (Bank) 401-1, each storage bank includes a plurality of storage blocks (Block), each storage block is relatively surrounded by SA and WLD corresponding to the storage block, each storage bank is provided with a column decoder 504 and a row decoder 506 corresponding to the storage bank on both sides, every 4 storage banks form a storage bank row, 16 storage banks form 4 storage bank rows, and a control circuit 502 is provided between the two middle storage bank rows. It should be noted that Figure 5The number of storage repositories in the memory is for example only and is not intended to limit the number of storage repositories in the memory in this application.

[0097] In some embodiments, the memory array 401 and the peripheral circuit 402 may also be disposed on two substrates. Figure 6 As shown, it includes: a first substrate 100, including at least a storage array 401;

[0098] The second substrate 200 at least includes a peripheral circuit 402; the first substrate 100 and the second substrate 200 are stacked and connected by bonding.

[0099] Here, the first substrate 100 may include but is not limited to a silicon substrate. The first substrate 100 may include at least a memory array 401. In the following text, the first substrate 100 may also include a dummy memory array. The memory array 401 may include a plurality of memory banks (Banks), the plurality of memory banks are arranged in an array, each memory bank includes a plurality of memory blocks (Blocks) or referred to as memory bodies, the plurality of memory blocks are arranged in an array, each memory block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row and each memory cell column includes a plurality of memory cells, and the memory array 401 may also include a plurality of word lines and a plurality of bit lines, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line.

[0100] Here, the second substrate 200 is a different substrate from the first substrate, and the second substrate includes but is not limited to a silicon substrate. In the following text, the second substrate 200 includes a peripheral circuit 402; the peripheral circuit 402 may include a control circuit corresponding to a storage block and / or a control circuit corresponding to a storage bank. Here, the peripheral circuit 402 also includes control circuits corresponding to all storage banks, for example, a command buffer, a command decoder, an address buffer, a data buffer, a mode register, etc.

[0101] In some embodiments, Figure 6 The memory shown may further include: a bonding interface located between the first substrate and the second substrate;

[0102] a first interconnect layer, located between the first substrate and the bonding interface;

[0103] a second interconnect layer, located between the second substrate and the bonding interface;

[0104] The first substrate and the second substrate are connected through the first interconnect layer and the bonding interface and the second interconnect layer.

[0105] Here, the memory may also include a bonding interface, a first interconnect layer and a second interconnect layer. Wherein, the first interconnect layer and the second interconnect layer may each include a plurality of bonding contacts and a dielectric that electrically isolates the bonding contacts. In some specific embodiments, the bonding contacts may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof; the dielectric may include but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k (dielectric constant less than 3.9) dielectric or any combination thereof. In some specific embodiments, a first interconnect layer is formed on a first substrate; a second interconnect layer is formed on a second substrate; and then the memory array contained in the first substrate and the peripheral circuit contained in the second substrate are bonded at the bonding interface, and the bonding contacts and the surrounding dielectric may be connected by hybrid bonding. That is, in some embodiments, the bonding interface is vertically formed between the first interconnect layer and the second interconnect layer. In some embodiments, the memory array in the first substrate and the peripheral circuit in the second substrate are bonded at the bonding interface through the bonding contacts contained in the first interconnect layer and the bonding contacts contained in the second interconnect layer to achieve the connection between the memory array and the peripheral circuit.

[0106] For example, Figure 7 As shown, it shows a top view schematic diagram of the distribution of the storage array and peripheral circuits in the memory. It should be noted that Figure 7 The first substrate 100 is located above the second substrate 200, and Figure 7 The structure corresponding to the solid line is located in the first substrate 100, and the structure corresponding to the dotted line is located in the second substrate 200. For ease of understanding, the structure in the second substrate 200 is shown in perspective.

[0107] For example, Figure 7 As shown, the storage array 401 includes 16 storage banks (Bank) 401-1, each storage bank includes a plurality of storage blocks (Block), and directly below each storage block are arranged a first SA and a second SA that are arranged relatively to the storage block along a first direction, and a first WLD and a second WLD that are arranged relatively to the storage block along a second direction, and below both sides of each storage bank are arranged a column decoder 504 and a row decoder 506 that correspond to the storage bank, and every 4 storage banks form a storage bank row, and 16 storage banks form 4 storage bank rows, and a control circuit 502 is arranged below the two middle storage bank rows.

[0108] It should be noted that Figure 7 The number of memory banks is only used as an example and is not used to limit the number of memory banks in the memory of the present application. The space originally used to place the control circuit corresponding to each memory block in the first substrate can be freed up to provide a larger layout space for the memory cells, word lines and bit lines.

[0109] It should be noted that Figure 7 The size relationship between a storage block and the sizes of the surrounding SA and word line driver shown in the figure is for example only and is not used to limit the size relationship between a storage block in the memory and the sizes of a programming logic sub-unit and the surrounding SA and word line driver in the present application.

[0110] It should be noted that the above are only two exemplary layouts of storage arrays and peripheral circuits. In fact, there may be other layouts. The focus of this application is no longer on the layout of storage arrays and peripheral circuits, and more layouts will not be described here. The operating method provided in the embodiments of this application is applicable to storage arrays and peripheral circuits of various layouts.

[0111] In some embodiments, some memory cells of the memory array 401 described above are defective due to manufacturing errors and / or failures. For such reasons, the memory array 401 includes some redundant memory cell rows (coupled with redundant word lines WL) to repair the defective memory cell rows. In some embodiments, some defective memory cell rows in the memory array can be repaired using redundant memory cell rows during wafer sorting. In another embodiment, the defective memory cell rows in the memory array can be repaired by the user using redundant memory cell rows after packaging, and this process can also be referred to as post-packaging repair (PPR). In actual application, when the memory is used by the user, the memory controller coupled to the memory is not clear whether the defective memory cell row has been repaired during the wafer sorting process. Therefore, for the defective memory cell row, if the defective memory cell row has been repaired during the wafer sorting process after using PPR, then the defective memory cell row corresponds to two redundant memory cell rows, and conflicts will occur in subsequent use (such as, during use, it is impossible to determine which redundant memory cell row the defective memory cell row is remapped to, resulting in storage data errors, etc.). For the understanding of the above conflict, as Figure 8 and Fig. 9 As shown. Figure 8 In normal cases, when users use PPR to repair defective storage cell rows, one defective storage cell row corresponds to one redundant storage cell row; during the wafer sorting process, the repair of a defective storage cell row is also one defective storage cell row corresponds to one redundant storage cell row. The same defective storage cell row is repaired by PPR operation or by wafer sorting process, and there is no conflict between the two. In actual situations, such as Fig. 9 As shown in the figure, when the user uses PPR to repair a defective storage cell row, it is not clear whether the defective storage cell row has been repaired in the wafer sorting process, so the following error occurs: Fig. 9 The conflict shown is that one defective memory cell row corresponds to two redundant memory cell rows.

[0112] In order to resolve the above conflict, one feasible method is as follows: for the defective storage cell row, the priority of the repair strategy after PPR is higher than the repair strategy performed during the wafer sorting process. Therefore, in subsequent use, the defective storage cell row is remapped to the redundant storage cell row corresponding to the PPR.

[0113] For the conflicts described above, an embodiment of the present application provides a method for operating a memory, by disabling a first repair strategy used for a first defective cell row that has been repaired in a PPR mode; then, reconfiguring a second repair strategy to avoid conflicts in subsequent use caused by repeated repairs of the same defective cell row.

[0114] like Fig.10 As shown, the specific steps of the operation method can be as follows:

[0115] S1001: in a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, invalidating a first repair strategy for repairing the first defective memory cell row before packaging;

[0116] S1002: Configuring a second repair strategy for repairing the first defective memory cell row, and storing the second repair strategy.

[0117] It should be noted that the memory may include a memory array such as the aforementioned; the memory array includes a plurality of memory cell rows. Some of the memory cells in the plurality of memory cell rows may be defective, and the row containing the defective memory cells may be referred to as a defective row (or bad row). As mentioned above, in some cases, after the memory is packaged (such as sealed in a chip package), the memory cell row may become defective during use. The memory may perform one or more types of PPR operations to resolve defective rows. As in the aforementioned conflict, when performing a PPR operation, if a defective memory cell row (such as a first defective memory cell) has been repaired before packaging (a first repair strategy already exists), and then a PPR operation is performed (forming a second repair strategy), the two repair strategies correspond to a defective memory cell row (word line WL), and thus there is a conflict. Based on this, the present application as Fig.10The described operation method is that in the PPR mode, when the first defective storage unit has been repaired before packaging, the first repair strategy for repairing the first defective storage unit row before packaging is invalidated (that is, the first repair strategy does not work); then, a second repair strategy for repairing the first defective storage unit is configured, and the second repair strategy is stored for later use. The first defective storage unit here is any one of a plurality of storage unit rows. The embodiment of the present application takes the first defective storage unit row as an example to illustrate the inventive concept, and is not a limitation on quantity.

[0118] Specifically, Fig.11 As shown, the memory further includes a read-only memory device (ROM); the first repair strategy for repairing the first defective memory cell row before packaging is invalidated, and may include:

[0119] S1101: Acquire first record information stored in the ROM; the first record information includes the first repair strategy;

[0120] S1102: Setting a first control bit in the first record information to a first preset value;

[0121] When the first control bit is the first preset value, the first repair strategy is in an invalid state.

[0122] It should be noted that the process described here is a step of how to make the first repair strategy fail. The ROM mentioned here may be included in the aforementioned peripheral circuit; it may also not be included in the peripheral circuit, but coupled to the peripheral circuit, which is only determined by the different division methods of the circuits or devices in the memory other than the storage array. In some division methods, the ROM is included in the peripheral circuit, and more specifically, the ROM may be included in the control circuit described above. The specific method for making the first repair strategy fail may include: first obtaining the first record information containing the first repair strategy stored from the ROM; then, setting the first control bit in the first record information to a first preset value. Wherein, when the first control bit is the first preset value, the first repair strategy is in a failed state, that is, it will not work in the subsequent use. In other words, when it is used in the subsequent use, the first defective storage unit row will not be remapped to the corresponding redundant storage unit row according to the first repair strategy. Wherein, in some embodiments, the first preset value may be "1".

[0123] In some embodiments, S1101 may include:

[0124] In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage;

[0125] acquiring the first record information from the ROM according to the second address information;

[0126] The indication information is used to indicate that the first defective storage unit row has been repaired.

[0127] It should be noted that the first address information may refer to the address information of the first defective storage cell row in a storage array such as the aforementioned one. The second address information may refer to the address information stored in the first repair strategy corresponding to the first defective storage cell row. The above specific process is: according to the first address information, the second address information stored in the first repair strategy corresponding to the first address information is found from the pre-stored first mapping relationship; then, the ROM is addressed according to the second address information, and the first record information is obtained from the ROM. It should be understood that the first address information and the second address information are only two different addresses described, and the two are not limited in quantity.

[0128] In some embodiments, the memory further includes a content addressable memory (CAM) device coupled to the plurality of memory cell rows; the method may further include:

[0129] Acquire first address information of the first defective memory cell row;

[0130] comparing the first address information with the address information stored in the CAM;

[0131] In response to the comparison result including that address information identical to the first address information is stored in the CAM, indication information is generated, wherein the indication information is used to indicate that the first defective memory cell row has been repaired.

[0132] It should be noted that, as mentioned above, the defective row repair before packaging is the repair of the defective row during the wafer sorting process, and the user cannot know whether the first defective storage unit row has been repaired during the wafer sorting process. Then, in the PPR mode, it is necessary to first determine whether the first defective storage unit row is repaired before packaging, so that the first repair strategy can be invalidated under the premise that the first defective storage unit row is repaired before packaging. The process described here is an implementation method for determining that the first defective storage unit has been repaired before packaging. Before explaining the implementation method in detail, the meaning and function of CAM are explained first. CAM is a content-addressable storage device. The CAM may be included in the peripheral circuit or not. As mentioned above, it is only a difference in the division method, which has no effect on its actual position. In some embodiments, the CAM can be set as follows: Figure 5 and Figure 7 The periphery of the storage body of the storage array, such as the CAM, includes a control circuit 502. The working principle of the CAM is to compare the input data with the data already stored inside the CAM. If there are identical contents, the address data stored by the identical data and the search success signal are output. Otherwise, the search success signal is not output. In the embodiment of the present application, the function of the CAM is to store the repair strategy corresponding to a defective storage cell row so as to actually repair the defective storage cell row. For example, it is assumed that the first repair strategy (not volatile upon power failure) is stored in the ROM. During the use of the memory, when it is necessary to perform an operation on the first defective storage cell row, the first repair strategy in the ROM is loaded into the CAM (volatile upon power failure), and then the CAM actually repairs the first defective storage cell according to the first repair strategy.

[0133] In fact, the specific steps of the aforementioned implementation method for determining whether the first defective storage cell row is repaired before packaging can be understood as follows: first obtain the first address information of the first defective storage cell row; then compare the first address information with the address information stored in the CAM; if the comparison result includes address information stored in the CAM that is the same as the first address information, generate indication information (that is, the query success signal mentioned above), that is, the address information of the first defective storage cell row is stored in the CAM, that is, when the indication information is generated, it indicates that the first defective storage cell row has been repaired before packaging. On the contrary, when the indication information is not generated, it indicates that the first defective storage cell row has not been repaired before packaging. At this time, the first repair strategy does not exist, and the PPR operation can be directly performed to generate the second repair strategy (that is, the repair strategy under the PPR operation).

[0134] In some embodiments, the memory further includes a plurality of first redundant cell rows; the configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy comprises:

[0135] Select one first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective storage cell row; the second mapping relationship is the second repair strategy;

[0136] generating second record information according to the second repair strategy;

[0137] storing the second record information in the ROM;

[0138] The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

[0139] It should be noted that the first redundant cell row mentioned here is also the redundant storage cell row described above. The configuration of the second repair strategy is to select the first redundant cell row from multiple first redundant cell rows and establish a second mapping relationship with the first defective storage cell row. The storage of the second repair strategy is to store the established second mapping relationship in the aforementioned ROM. At this time, the first control bit in the second record information stored in the ROM is set to the second preset value, wherein, when the first control bit in the second record information is the second preset value, the second repair strategy is in an effective state, that is, in subsequent use, the second repair strategy will be used to repair the first defective storage cell row. In some embodiments, the second preset value can be "0".

[0140] In some embodiments, the memory further comprises a plurality of second redundant cell rows different from the plurality of first redundant cell rows; the first repair strategy comprises a mapping relationship between the first defective memory cell row and a second redundant cell row among the plurality of second redundant cell rows.

[0141] That is, the redundant cell rows used by the first repair strategy and the second repair strategy are different. Figure 8 and 9 As shown, the plurality of first redundant cell rows may refer to redundant memory cell rows allocated for use in a PPR operation; the plurality of second redundant cell rows may refer to redundant memory cell rows allocated for repairing defective memory cell rows during wafer sorting.

[0142] In some embodiments, the method may further include:

[0143] When performing an operation on the memory, determining whether the first repair strategy is effective or the second repair strategy is effective;

[0144] In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row;

[0145] In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

[0146] Here, the operation may include powering on the memory.

[0147] That is to say, after the memory is powered on, it is determined whether the first repair strategy or the second repair strategy is valid. If the first repair strategy is valid, the first repair strategy is loaded, and the first defective memory cell row is repaired using the first repair strategy; if the second repair strategy is valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

[0148] Specifically, in some embodiments, determining whether the first repair strategy is effective or the second repair strategy is effective may include:

[0149] Acquire the first record information and the second record information;

[0150] Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information;

[0151] The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

[0152] It should be noted that when determining whether to use the first repair strategy or the second repair strategy, the first repair strategy or the second repair strategy is determined to be effective based on the first control bit in the first record information containing the first repair strategy and the second record information containing the second repair strategy obtained from the ROM. In practice, the first repair strategy and the second repair strategy can only use one repair strategy to repair the first defective storage unit, so the values ​​set by the first control bit in the first record information and the second control bit in the second record information are always different.

[0153] In some embodiments, the first record information further includes a second control bit; the second control bit is used to indicate whether the first repair strategy is to be enabled.

[0154] In actual application, the first record information also includes a second control bit, which is used to indicate whether the first repair strategy is to be enabled. The second control bit has a different function from the first control bit. The first control bit is a control bit that indicates whether the first repair strategy is effective when it is determined that the first defective storage unit row is to be repaired; and the second control bit is a control bit that is used to determine whether the first defective storage unit is to be repaired. Only when the second control bit is at a third preset value (such as 1), it indicates that the first repair strategy will be enabled.

[0155] To sum up, the operating method provided by the embodiment of the present application is described above. In summary, it includes two steps: the first step is to obtain a defective memory cell row that has been repaired (such as the aforementioned first defective memory cell row), and to invalidate the repair strategy (such as the first repair strategy) stored in the ROM for repairing the defective memory cell row, and to configure the repair strategy (such as the second repair strategy) for repairing the defective memory cell row in the PPR mode, and store the reconfigured repair strategy; the second step is to load the reconfigured repair strategy from the ROM to the CAM for use after the memory is powered on next time.

[0156] In order to understand the present application, the first defective memory cell behavior is used as an example to illustrate the present application. Figures 12 to 15 As shown, Fig.12 A schematic diagram of the implementation flow of the first step of the operation method provided according to an embodiment of the present application; Fig.13 A schematic diagram of an implementation flow of disabling a first repair strategy for a first defective memory cell row according to an embodiment of the present application; Fig.14 A schematic diagram of an implementation flow of the second step of the operating method provided in an embodiment of the present application; Fig.15 To implement the embodiment of the present application Fig.14 A specific implementation diagram of the process.

[0157] exist Fig.12 In the first step, the specific process can be as follows:

[0158] S1201: The memory enters the PPR mode in response to the received PPR command; wherein the PPR command may refer to a combination of the mode register command MRS4 and the address information (such as A13). In actual application, the memory enters the PPR mode based on the combination of the mode register command MRS4 and the address information (such as A13).

[0159] S1202: The memory receives a bank group address BG_f, a bank address BA_f, a row address RA_f and an activation command ACT that collectively indicate the location of a bad memory cell row;

[0160] S1203: Determine whether the defective memory cell row to be repaired (such as the first defective memory cell row) has been repaired; if it has been repaired, execute step S1204; if not, execute step S1205;

[0161] S1204: Invalidate the repair strategy (such as the first repair strategy) stored in the ROM corresponding to the defective memory cell row.

[0162] S1205: Configure a repair strategy (such as a second repair strategy) corresponding to the defective storage cell row in the PPR mode; store the repair strategy corresponding to the defective storage cell row in the PPR mode in the ROM; for example, store the second repair strategy in the ROM.

[0163] S1206: Exit PPR mode.

[0164] exist Fig.13 The specific process of disabling the first repair strategy of the first defective storage cell row can be as follows: the control circuit of the memory obtains the first address information of the first defective storage cell row defect wl; and compares the first address information with the address information stored in the CAM (set near the Bank); when the first address information is the same as the address information in the CAM, an indication information red_wl_ind is generated; then, the strategy address decoder responds to the indication information, parses the first address information, and obtains the second address information sol_addr of the first repair strategy stored in the ROM; according to sol_addr, the first record information is obtained from the ROM, and the first control bit in the first record information is set to a first preset value, thereby disabling the first repair strategy.

[0165] exist Fig.14 In the second step, the specific process can be as follows:

[0166] S1401: Perform a power on reset (POR) operation on the memory;

[0167] S1402: Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit dis in the first record information and the first control bit dis in the second record information;

[0168] S1403: when the first control bit dis in the first record information is a second preset value, the first repair strategy is valid, the first repair strategy is loaded, and the first defective storage cell row is repaired using the first repair strategy;

[0169] S1404: the first control bit dis in the second record information is a second preset value, the second repair strategy is valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy;

[0170] S1405: The power-on operation is completed.

[0171] exist Fig.15 In the example, the first preset value is 1; the second preset value is 0. When the first control bit dis in the first record information is 1, the first repair strategy is invalid; at this time, the first control bit dis in the second record information is 0, and the second repair strategy is valid. It should be noted that at this time, the second control bit en in the first record information and the second record information are both 1, and the repair is to be started.

[0172] like Fig.16 As shown, the embodiment of the present application further provides a memory 1600, including:

[0173] The memory array 1601 includes: a plurality of memory cell rows;

[0174] The peripheral circuit 1602 is coupled to the storage array and is configured as follows:

[0175] In a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, a first repair strategy for repairing the first defective memory cell row before packaging is invalidated;

[0176] A second repair strategy for repairing the first defective memory cell row is configured, and the second repair strategy is stored.

[0177] In some embodiments, the memory further includes a read-only memory device ROM; and the peripheral circuit is further configured to:

[0178] Acquire first record information stored in the ROM; the first record information includes the first repair strategy;

[0179] Setting the first control position in the first record information to a first preset value;

[0180] When the first control bit is the first preset value, the first repair strategy is in an invalid state.

[0181] In some embodiments, the memory further includes a content addressable memory device CAM coupled to the plurality of memory cell rows, and the peripheral circuit is further configured to:

[0182] Acquire first address information of the first defective memory cell row; and transmit the first address information to the CAM;

[0183] The CAM is configured to: compare the first address information with the address information stored in the CAM; and in response to the comparison result including address information stored in the CAM that is identical to the first address information, generate indication information, wherein the indication information is used to indicate that the first defective storage cell row has been repaired.

[0184] In some embodiments, the peripheral circuit is further configured to:

[0185] In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage;

[0186] acquiring the first record information from the ROM according to the second address information;

[0187] The indication information is used to indicate that the first defective storage unit row has been repaired.

[0188] In some embodiments, the memory array further includes a plurality of first redundant cell rows; and the peripheral circuit is further configured to:

[0189] Select one first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective storage cell row; the second mapping relationship is the second repair strategy;

[0190] generating second record information according to the second repair strategy;

[0191] storing the second record information in the ROM;

[0192] The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

[0193] In some embodiments, the peripheral circuit is further configured to: when performing an operation on the memory, determine whether the first repair strategy is effective or the second repair strategy is effective;

[0194] In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row;

[0195] In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

[0196] In some embodiments, the peripheral circuit is further configured to: obtain the first record information and the second record information;

[0197] Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information;

[0198] The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

[0199] In some embodiments, the storage array further comprises a plurality of second redundant cell rows different from the plurality of first redundant cell rows; the first repair strategy comprises a mapping relationship between the first defective storage cell row and a second redundant cell row among the plurality of second redundant cell rows.

[0200] It should be noted that the memory provided in the embodiment of the present application is the main body for executing the aforementioned operating method. Therefore, the steps to be executed by each device described here have been described in detail in the aforementioned operating method and will not be repeated here.

[0201] like Fig.17 As shown, an embodiment of the present application further provides a memory system 1700, comprising: one or more memories 1600 as described in any of the aforementioned items; and a memory controller 1701 coupled to the memory and controlling the memory.

[0202] It should be noted that the memory system includes the memory described above. Therefore, for the description of the memory, please refer to the understanding of the above description and will not be repeated here.

[0203] An embodiment of the present application further provides a computer system, comprising: the aforementioned memory system and an image processor, which is coupled to the memory system and controls the memory system.

[0204] In some embodiments, the image processor and the memory controller are integrated on the same die; the die and the memory are integrated on the same printed circuit board. For the specific structure, please refer to the above Figure 2 shown.

[0205] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as those available to those skilled in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features can be combined together to simplify the application. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the attached claims and the full scope of the equivalents given by these claims.

Claims

1. A method for operating a memory, characterized in that: The memory comprises a plurality of memory cell rows; the method comprises: In a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, a first repair strategy for repairing the first defective memory cell row before packaging is invalidated; A second repair strategy for repairing the first defective memory cell row is configured, and the second repair strategy is stored.

2. The operating method according to claim 1, characterized in that: The memory further includes a read-only memory device ROM; the method of disabling the first repair strategy for repairing the first defective memory cell row before packaging includes: Acquire first record information stored in the ROM; the first record information includes the first repair strategy; Setting the first control position in the first record information to a first preset value; When the first control bit is the first preset value, the first repair strategy is in an invalid state.

3. The operating method according to claim 1, characterized in that: The memory further comprises a content addressable memory device CAM coupled to the plurality of memory cell rows; the method further comprises: Acquire first address information of the first defective memory cell row; comparing the first address information with the address information stored in the CAM; In response to the comparison result including that address information identical to the first address information is stored in the CAM, indication information is generated, wherein the indication information is used to indicate that the first defective memory cell row has been repaired.

4. The operating method according to claim 2, characterized in that: The obtaining of the first record information stored in the ROM includes: In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage; acquiring the first record information from the ROM according to the second address information; The indication information is used to indicate that the first defective storage unit row has been repaired.

5. The operating method according to claim 2, characterized in that: The memory further includes a plurality of first redundant cell rows; the configuration of a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy include: Selecting a first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective memory cell row; the second mapping relationship is the second repair strategy; generating second record information according to the second repair strategy; storing the second record information in the ROM; The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

6. The operating method according to claim 5, characterized in that: The method further comprises: When performing an operation on the memory, determining whether the first repair strategy is effective or the second repair strategy is effective; In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row; In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

7. The operating method according to claim 6, characterized in that: The determining whether the first repair strategy is effective or the second repair strategy is effective includes: Acquire the first record information and the second record information; Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information; The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

8. The operating method according to claim 5, characterized in that: The memory further comprises a plurality of second redundant cell rows different from the plurality of first redundant cell rows; the first repair strategy comprises a mapping relationship between the first defective memory cell row and one of the plurality of second redundant cell rows.

9. The operating method according to claim 2, characterized in that: The first record information also includes a second control bit; the second control bit is used to indicate whether the first repair strategy is to be enabled.

10. The operating method according to claim 6, characterized in that: The operation includes powering on the memory.

11. A memory, characterized in that: include: A storage array, comprising: a plurality of storage unit rows; The peripheral circuit is coupled to the memory array and is configured to: In a post-packaging repair (PPR) mode, in response to a first defective memory cell row among the plurality of memory cell rows having been repaired before packaging, a first repair strategy for repairing the first defective memory cell row before packaging is invalidated; A second repair strategy for repairing the first defective memory cell row is configured, and the second repair strategy is stored.

12. The memory according to claim 11, characterized in that: The memory also includes a read-only memory device ROM; the peripheral circuit is further configured as: Acquire first record information stored in the ROM; the first record information includes the first repair strategy; Setting the first control position in the first record information to a first preset value; When the first control bit is the first preset value, the first repair strategy is in an invalid state.

13. The memory according to claim 11, characterized in that: The memory further includes a content addressable memory device CAM coupled to the plurality of memory cell rows, and the peripheral circuit is further configured as follows: Acquire first address information of the first defective memory cell row; and transmit the first address information to the CAM; The CAM is configured to: compare the first address information with the address information stored in the CAM; and in response to the comparison result including address information stored in the CAM that is identical to the first address information, generate indication information, wherein the indication information is used to indicate that the first defective storage cell row has been repaired.

14. The memory according to claim 12, characterized in that: The peripheral circuit is further configured as: In response to the indication information, second address information of the first record information storage is obtained according to the first address information of the first defective memory cell row and a first mapping relationship; the first mapping relationship includes a correspondence between the address information of the defective memory cell row and the address information of the corresponding record information storage; acquiring the first record information from the ROM according to the second address information; The indication information is used to indicate that the first defective storage unit row has been repaired.

15. The memory according to claim 12, characterized in that: The storage array further includes a plurality of first redundant cell rows; the peripheral circuit is further configured as: Select one first redundant cell row from the plurality of first redundant cell rows to establish a second mapping relationship with the first defective storage cell row; the second mapping relationship is the second repair strategy; generating second record information according to the second repair strategy; storing the second record information in the ROM; The first control bit in the second record information is a second preset value; when the first control bit is the second preset value, the second repair strategy is in a valid state.

16. The memory according to claim 15, characterized in that: The peripheral circuit is further configured to: when performing an operation on the memory, determine whether the first repair strategy is effective or the second repair strategy is effective; In response to the first repair strategy being effective, loading the first repair strategy, and using the first repair strategy to repair the first defective memory cell row; In response to the second repair strategy being valid, the second repair strategy is loaded, and the first defective memory cell row is repaired using the second repair strategy.

17. The memory according to claim 16, characterized in that: The peripheral circuit is further configured to: obtain the first record information and the second record information; Determine whether the first repair strategy is valid or the second repair strategy is valid according to the first control bit in the first record information and the first control bit in the second record information; The first control bit corresponding to the first repair strategy and the first control bit corresponding to the second repair strategy always have different values.

18. The memory according to claim 15, characterized in that: The storage array further includes a plurality of second redundant cell rows different from the plurality of first redundant cell rows; the first repair strategy includes a mapping relationship between the first defective storage cell row and one of the plurality of second redundant cell rows.

19. A memory system, characterized in that: include: One or more memories according to any one of claims 11 to 18; and a memory controller coupled to the memory and controlling the memory.

20. A computer system, characterized in that: include: The memory system of claim 19; and an image processor coupled to the memory system and controlling the memory system.

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