Interposer, method of manufacturing the same, three-dimensional package structure, and method of manufacturing the same

Abstract

The application discloses an interposer and a manufacturing method thereof, a three-dimensional packaging structure and a manufacturing method thereof, and relates to the technical field of semiconductor devices. The interposer comprises a substrate and a re-routed layer. The substrate has a plurality of through holes penetrating from a first surface to a second surface, each through hole being filled with a conductive material to form a conductive through hole. The substrate has a groove penetrating from the first surface to the second surface, the groove dividing the substrate into a plurality of connection areas separated by the groove, one connection area being configured to connect one chip, and the chip being electrically connected to the conductive through hole in the corresponding connection area. The re-routed layer is arranged on the second surface and has flexibility and is electrically connected to the conductive through hole. The conductive through hole in one connection area is electrically connected to the conductive through hole in another connection area through the re-routed layer, so as to realize the interconnection between the chip corresponding to one connection area and another chip corresponding to another connection area. The application can overcome the stress problem of the interposer and the chip or the packaging substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, in particular to an interposer, a manufacturing method thereof, a three-dimensional packaging structure and a manufacturing method thereof. BACKGROUND

[0002] With the development of artificial intelligence, high-performance computing and other technologies, the demand for chip computing power is increasing, and high-performance chips generally adopt 2.5D packaging form. In order to reduce power consumption and improve performance, multiple HBM (High Bandwidth Memory) and XPU are usually integrated together in 2.5D packaging. The development of multi-chip packaging technology makes the size of the interposer continuously increase, and the height and pitch of the bumps on the bottom of the interposer continuously decrease, which makes the requirements for the TTV (total thickness variation), bump height uniformity, material CTE (coefficient of thermal expansion) matching and other indicators of the interposer higher and higher. The CTE mismatch between the super-large size interposer and the IC Substrate (packaging substrate) material also has problems such as bump welding failure and other reliability problems, which will seriously affect the subsequent process, thereby reducing the yield. SUMMARY

[0003] The technical problem solved by the present application is the mismatch of the thermal expansion coefficients of the interposer, the bumps on the bottom of the interposer and the packaging substrate material in the existing packaging structure, which causes stress.

[0004] According to a first aspect, an embodiment provides an interposer, which in an embodiment comprises: a substrate and a redistribution layer;

[0005] The substrate has opposite first and second surfaces, and the substrate has a plurality of through holes penetrating from the first surface to the second surface, each through hole being filled with a conductive material to form a conductive via;

[0006] The substrate has a groove penetrating from the first surface to the second surface, the groove divides the substrate into a plurality of connection regions separated by the groove, and one connection region is configured to connect one chip, and the chip is electrically connected to the conductive via in the corresponding connection region;

[0007] The redistribution layer is disposed on the second surface, and the redistribution layer has flexibility and is electrically connected to the conductive via;

[0008] The conductive via in one connection region is electrically connected to the conductive via in another connection region through the redistribution layer, so as to realize the interconnection between the chip corresponding to one connection region and another chip corresponding to another connection region.

[0009] In one embodiment, the redistribution layer includes a metal layer and a dielectric layer, the dielectric layer has flexibility, the metal layer is electrically connected with the conductive via, and the dielectric layer is made of resin.

[0010] In one embodiment, the interposer further includes a plurality of first solder joints.

[0011] The first solder joint is disposed on the first surface and is electrically connected with the conductive via, and the first solder joint is configured to be electrically connected with the chip.

[0012] In one embodiment, the interposer further includes a plurality of second solder joints.

[0013] The second solder joint is disposed on a surface of the redistribution layer away from the substrate, the second solder joint is electrically connected with the redistribution layer, and the second solder joint is configured to be electrically connected with the package substrate.

[0014] According to the second aspect, in one embodiment, a three-dimensional packaging structure is provided, including a plurality of chips and the interposer described in the first aspect.

[0015] The plurality of chips includes at least a first chip and a second chip.

[0016] The first chip and the second chip are respectively attached to the corresponding connection areas on the interposer, and the first chip and the second chip are electrically connected with the redistribution layer through the conductive via on the interposer.

[0017] In one embodiment, the first chip is a storage chip, and the second chip is a processing chip.

[0018] In one embodiment, the three-dimensional packaging structure further includes a package substrate.

[0019] The interposer further includes a plurality of second solder joints.

[0020] The second solder joint is disposed on a surface of the redistribution layer away from the substrate, the second solder joint is electrically connected with the redistribution layer, and the second solder joint is electrically connected with the package substrate.

[0021] In one embodiment, the three-dimensional packaging structure further includes an insulating adhesive, the insulating adhesive is disposed between the substrate and the chip, and the insulating adhesive wraps the solder joint electrically connected between the substrate and the chip.

[0022] According to the third aspect, in one embodiment, a manufacturing method of an interposer is provided, including:

[0023] providing a substrate; wherein the substrate has opposite first and second surfaces; the substrate has a plurality of through holes penetrating from the first surface to the second surface, each through hole is filled with conductive material to form a conductive via; a redistribution layer is disposed on the second surface, the redistribution layer has flexibility, and the redistribution layer is electrically connected with the conductive via;

[0024] The substrate is patterned to form a groove; wherein the groove penetrates from the first surface to the second surface, the groove divides the substrate into a plurality of connection regions separated by the groove, and one connection region is configured to connect one chip, and the chip is electrically connected to the conductive via in the corresponding connection region.

[0025] According to a fourth aspect, a manufacturing method of a three-dimensional packaging structure is provided in an embodiment, comprising:

[0026] The manufacturing method of the interposer is adopted to prepare the interposer;

[0027] At least two chips are attached to the corresponding connection regions, the at least two chips comprising a first chip and a second chip, and the first chip and the second chip are electrically connected to the redistribution layer through the conductive via;

[0028] The interposer with the chips is attached to the packaging substrate, and the packaging substrate is electrically connected to the redistribution layer.

[0029] According to the above-mentioned embodiments of the interposer and the manufacturing method thereof, the three-dimensional packaging structure and the manufacturing method thereof, the substrate is provided with the conductive via along the thickness direction thereof, the conductive via is electrically connected to the chip; the redistribution layer is arranged on the second surface of the interposer, the redistribution layer is flexible, and the redistribution layer is connected to the packaging substrate; a plurality of chips are stacked on the first surface of the interposer and are interconnected through the conductive via and the redistribution layer; the groove penetrates from the first surface to the second surface of the interposer along the gap between the chips, i.e., the groove is cut from the front surface of the interposer to the redistribution layer, and the redistribution layers of the connection regions are connected. By cutting the groove in the middle of the substrate, the stress buffering effect of the substrate can be achieved, the problems such as soldering failure and material delamination caused by the mismatch of the thermal expansion coefficients among the substrate, the bottom bump and the packaging substrate can be reduced, and the flexible redistribution layer can further eliminate most of the stress and solve the warping problem of the large-size packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural schematic diagram of the interposer is provided for an embodiment of the present application;

[0031] Figure 2 A structural schematic diagram of the three-dimensional packaging structure is provided for an embodiment of the present application;

[0032] Figure 3 A Figure 1 top view;

[0033] Figure 4 A process schematic diagram (I) of the manufacturing method of the interposer is provided for an embodiment of the present application;

[0034] Figure 5 A process schematic diagram (II) of the manufacturing method of the interposer is provided for an embodiment of the present application;

[0035] Figure 6 A schematic diagram illustrating the manufacturing process of a three-dimensional packaging structure provided in another embodiment of this application.

[0036] Reference numerals: 001-3D packaging structure; 1-intermediate layer; 2-groove; 3-chip; 11-substrate; 12-rewiring layer; 121-metal layer; 122-dielectric layer; 111-conductive via; 13-first solder joint; 14-second solder joint; 4-packing substrate; 131-first conductive bump; 132-first solder ball; 141-second conductive bump; 142-second solder ball; 52-temporary bonding adhesive; 51-carrier plate; 53-photoresist; 54-photolithographic groove; 55-V-groove. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0038] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0039] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0040] With the development of multi-chip packaging technology, the size of the interposer will continue to increase, while the height and pitch of the interposer bottom bump / solder joint will continue to decrease, and the requirements for the total thickness variation, bump height uniformity, material thermal expansion coefficient matching, etc. of the interposer will be higher and higher. The super large size interposer and the packaging substrate material will also have the problem of mismatch of thermal expansion coefficient, and it is very easy to have reliability problems such as solder joint failure, which will seriously affect the subsequent process, thereby causing the product yield to decrease.

[0041] In this application, an interposer 1 and a three-dimensional packaging structure 001 are proposed, specifically a slot is opened on the interposer 1, which can effectively solve the reliability problems such as solder joint failure caused by the mismatch of the thermal expansion coefficient of the interposer 1 and the solder joint and the packaging substrate 4 material due to the continuous increase in the size of the interposer 1.

[0042] Embodiment one

[0043] As shown in Figure 1 , the interposer 1 provided in the embodiment of the present application can include: a substrate 11 and a redistribution layer 12 (RDL layer). ， The RDL layer).

[0044] The substrate 11 has opposite first surface (upper surface in Figure 1 , or front surface) and second surface (lower surface in Figure 1 , or bottom surface), the substrate 11 has a plurality of through holes penetrating from the first surface to the second surface, each through hole is filled with conductive material to form a conductive via 111.

[0045] The substrate 11 has a groove 2 penetrating from the first surface to the second surface, the groove 2 divides the substrate 11 into a plurality of connection areas (or sub-interposers) separated by the groove, one connection area is configured to connect one chip 3, the chip 3 is electrically connected with the conductive via 111 in the corresponding connection area.

[0046] The redistribution layer 12 is arranged on the second surface, the redistribution layer 12 has flexibility and is electrically connected with the conductive via 111.

[0047] The conductive via 111 in one connection area is electrically connected with the conductive via 111 in another connection area through the redistribution layer 12, so as to realize the interconnection between the chip 3 corresponding to one connection area and another chip 3 corresponding to another connection area.

[0048] For example, the interposer 1 may have a first solder joint 13 on the front side and a second solder joint 14 on the back side. The interposer 1 consists of a substrate 11 and a redistribution layer 12. The substrate 11 has conductive vias 111 along its thickness direction, and its front side is bonded to the chip 3 via the first solder joint 13. The redistribution layer 12 is disposed on the back side of the interposer 1 and is connected to the packaging substrate 4 via the second solder joint 14. Multiple chips 3 are stacked on the front side of the interposer 1 and interconnected with the redistribution layer 12 on the back side of the substrate 11 via the front side lines of the substrate 11 (such as conductive vias 111 and the first solder joint 13). The groove 2 cuts from the front side of the interposer 1 to the redistribution layer 12 along the gap between the chips 3. The interposer 1 is divided into multiple sub-interposers by the groove 2, and the bottom RDL layers of each sub-interposer are connected. The bottom RDL layers are electrically connected to the conductive vias 111 and the chips 3.

[0049] Among them, along the thickness direction of intermediary layer 1 ( Figure 1 The upper and lower directions are provided with conductive vias 111, which can realize vertical interconnection of the interposer layer 1 and reduce the package height.

[0050] For example, the substrate 11 can be made of silicon, or inorganic materials such as glass, SiC, or GaN. When the substrate 11 is made of silicon, the conductive via 111 can be called a through-silicon via (TSV). The substrate 11 has conductive vias 111 along its thickness direction, and the front side is bonded to the chip 3. The redistribution layer 12 can be connected to the packaging substrate 4 (such as a PCB board) to form an electrical interconnect. The chip 3 is stacked on the front side of the interposer 1 and interconnected through the front-side wiring of the substrate 11 and the back-side redistribution layer 12.

[0051] By slotting the middle of the substrate 11, stress buffering can be provided for the substrate 11, reducing CTE mismatch issues caused by the excessive size of the substrate 11 during interconnection with the PCB and reliability testing. Even if stress still exists due to the mismatch in coefficients of thermal expansion, most of the stress can be further eliminated by the flexible redistribution layer 12, solving the warpage problem of large-size package structures.

[0052] like Figure 1 and Figure 3 As shown, the groove 2 cuts along the gap between the chips 3 from the front side of the interposer 1 to the redistribution layer 12, so that the substrate 11 is cut into individual sub-blocks, and the groove 2 becomes a stress buffer between the interposer 1 and the substrate 11 / package substrate 4. The shape of the groove 2 can be a straight groove or a V-groove / trapezoidal groove.

[0053] like Figure 1 As shown, in one embodiment, the redistribution layer 12 may include a metal layer 121 or metal conductive line and a dielectric layer 122. The dielectric layer 122 is flexible. The metal layer 121 is electrically connected to the conductive via 111. The material of the dielectric layer 122 may be resin.

[0054] The redistribution layer 12 is disposed on the back surface of the interposer 1, and is made of a metal conductive line such as silver, copper, aluminum, gold, etc. and a resin such as polyimide, epoxy resin, acrylic resin, etc. In the embodiments of the present application, the dielectric layer 122 is made of a resin material, so that the dielectric layer 122 is flexible, and the metal layer 121 itself is ductile and elastic, and can be combined with the dielectric layer 122, so that the redistribution layer 12 as a whole is flexible.

[0055] As shown in FIG. 1, in an embodiment, the interposer 1 can further include a plurality of first soldering points 13; the first soldering points 13 are disposed on the first surface and are electrically connected to the conductive vias 111, and the first soldering points 13 are configured to be electrically connected to the chip 3. The front surface of the interposer 1 can be bonded and connected to the chip 3 through the first soldering points 13. Figure 1 For example, the first soldering points 13 can include first conductive bumps 131 and first soldering balls 132, and the first soldering balls 132 are disposed on the first conductive bumps 131, so that the flexible interposer 1 and the chip 3 package module can be electrically connected, and the connection between the interposer 1 and the chip 3 is more firm.

[0056] In some embodiments, the number of conductive vias 111 on each connection area is N, and the number of first soldering points 13 is M, and the ratio of N to M can be 1:1, n:1 or 1:n. According to the actual setting of the soldering points or pins of the connected chip 3, generally, the first soldering points 13 are one-to-one corresponding to the soldering points of the chip 3, but the conductive vias 111 and the first soldering points 13 can not be one-to-one corresponding, at this time, an interconnection layer or the like can be provided to realize the connection. Therefore, the interposer 1 can further include an interconnection layer, the interconnection layer is disposed on the first surface and is located between the first soldering points 13 and the substrate 11, and the first soldering points 13 are electrically connected to the conductive vias 111 through the interconnection layer. The interconnection layer can also include a metal layer and a dielectric layer, and the metal layer realizes the electrical connection between the first soldering points 13 and the conductive vias 111.

[0057] As shown in FIG. 1, in an embodiment, the interposer 1 can further include a plurality of second soldering points 14; the second soldering points 14 are disposed on the surface of the redistribution layer 12 away from the substrate 11, and the second soldering points 14 are electrically connected to the redistribution layer 12, and the second soldering points 14 are configured to be electrically connected to the package substrate 4. The redistribution layer 12 can be connected to the package substrate 4 through the second soldering points 14 to form electrical interconnection.

[0058] Figure 1

[0059] ​​For example, the second solder joint 14 can include a second conductive bump 141 and a second solder ball 142, the second solder ball 142 is arranged on the second conductive bump 141, and the second solder ball 142 can be used to electrically connect the interposer 1 and the package substrate 4.

[0060] The substrate 11 is provided with a conductive via 111 along the thickness direction thereof, and the front surface is bonded to the chip 3. The redistribution layer 12 is arranged on the back surface of the flexible interposer 1, and the redistribution layer 12 can be connected to the package substrate 4. A plurality of chips 3 can be stacked on the front surface of the interposer 1, and the chips 3 are interconnected by the front surface circuit of the substrate 11 (such as the conductive via 111 and the first solder joint 13) and the back surface redistribution layer 12 of the substrate 11. The groove 2 is cut from the front surface of the interposer 1 to the redistribution layer 12 along the gap between the chips 3, and the bottom surface RDL layers of the sub-interposers are connected. By cutting a slot in the middle of the substrate 11, the stress buffering effect of the substrate 11 can be achieved, and the problems such as solder failure or material delamination caused by the mismatch of the thermal expansion coefficient during the interconnection with the PCB and the reliability process can be reduced. Even if there is still stress caused by the mismatch of the thermal expansion coefficient, most of the stress can be further eliminated through the flexible redistribution layer 12, and the warping problem of the large-size package structure can be solved.

[0061] Embodiment two

[0062] As shown in Figure 2 the embodiment of the present application also provides a three-dimensional package structure 001, which can include a plurality of chips 3 and the interposer 1 described in embodiment one.

[0063] The plurality of chips 3 at least includes a first chip and a second chip. The first chip and the second chip are respectively attached to the corresponding connection areas on the interposer, and the first chip and the second chip are electrically connected through the conductive via 111 and the redistribution layer on the interposer.

[0064] The interposer 1 is composed of a substrate 11 and a redistribution layer 12. The substrate 11 is provided with a conductive via 111 along the thickness direction thereof, and the front surface can be bonded to the chip 3 through the first solder joint 13. The redistribution layer 12 is arranged on the back surface of the interposer 1, and the redistribution layer 12 is connected to the package substrate 4 through the second solder joint 14. A plurality of chips 3 are stacked on the front surface of the interposer 1, and the chips 3 are interconnected by the front surface circuit of the substrate 11 and the back surface redistribution layer 12 of the substrate 11. The groove 2 is cut from the front surface of the interposer 1 to the redistribution layer 12 along the gap between the chips 3, and the interposer 1 is divided into a plurality of sub-interposers (connection areas) by the groove 2. The bottom surface RDL layers of the sub-interposers are connected. The bottom surface RDL layer has electrical connection with the conductive via 111 and the chip 3, and the chips 3 are interconnected by the front surface circuit of the substrate 11 and the back surface redistribution layer 12, so as to maintain the signal transmission between the chips 3.

[0065] It should be noted that the three-dimensional packaging structure 001 provided in this application embodiment may also include other chips such as a third chip and a fourth chip. Taking the third chip as an example, the third chip may be interconnected with either the first chip or the second chip; or it may be interconnected with both the first and second chips; or it may not be interconnected with either the first or second chip; or it may be interconnected with the fourth chip. Therefore, the three-dimensional packaging structure 001 does not limit the specific number of chips 3, nor does it limit the interconnection arrangements, as long as the first chip and the second chip are at least interconnected.

[0066] In one embodiment, the first chip can be a storage chip, and the second chip can be a processing chip. The storage chip can be a memory chip using HBM, DRAM (Dynamic Random Access Memory), SDRAM (Synchronous Dynamic Random-Access Memory), etc.; the processing chip can be an XPU. The concept of XPU encompasses a variety of different processor technologies, including CPU, GPU, FPGA, ASIC, etc., which are integrated into a unified architecture to adapt to specific computing needs.

[0067] like Figure 2 As shown, in one embodiment, the three-dimensional packaging structure 001 may further include a packaging substrate 4; the packaging substrate 4 may be made of organic substrate or glass substrate, such as a commonly used PCB (Printed Circuit Board). The packaging substrate 4 may have circuits printed or deposited on it, and solder joints / pads may be formed on its upper and lower surfaces. The interposer layer 1 may further include a plurality of second solder joints 14; the second solder joints 14 are disposed on the surface of the redistribution layer 12 away from the substrate 11, and the redistribution layer 12 and the packaging substrate 4 are electrically connected through the second solder joints 14.

[0068] In one embodiment, the three-dimensional packaging structure 001 may further include an insulating adhesive disposed between the substrate 11 and the chip 3, and the insulating adhesive wrapping the solder joints / pads that electrically connect the substrate 11 and the chip 3. The underfill layer can protect the solder pads / pads on the one hand, and make the connection between the chip 3 and the interposer layer 1 more secure on the other hand.

[0069] The groove 2 cuts along the gap between the chips 3 from the front side of the interposer 1 to the redistribution layer 12, thus dividing the substrate 11 into sub-blocks. The groove 2 serves as a stress buffer between the interposer 1 and the substrate 11. A flexible conductive metal redistribution layer 12 exists between the substrate 11 and the package substrate 4. The flexible conductive metal redistribution layer 12 allows multiple substrates 11 to be electrically interconnected, while also reducing stress caused by CTE mismatch.

[0070] The first solder joint 13 is welded with the chip 3 to realize the electrical connection between the interposer 1 and the chip 3, and the connection between the interposer 1 and the chip 3 is more firm. The underfilling glue can be used between the interposer 1 and the chip 3, which can protect the solder pad and make the connection between the chip 3 and the interposer 1 more firm. The second solder joint 14 can realize the electrical connection between the interposer 1 and the packaging substrate 4. The conductive via 111 is arranged along the thickness direction of the interposer 1, which can realize the vertical electrical interconnection of the flexible interposer 1 and effectively reduce the packaging height.

[0071] In addition, the three-dimensional packaging structure 001 of the embodiment also has the technical effects of the interposer 1 of the first embodiment, which will not be described again.

[0072] Embodiment three

[0073] As shown in Figure 4 and Figure 5 The application embodiment also provides a manufacturing method of the interposer 1, which can be used to manufacture the interposer 1 described in the first embodiment, and can include the following steps:

[0074] Step 1, as shown in (A) in Figure 4 and (A) in Figure 5 provides a substrate 11; the substrate 11 has opposite first and second surfaces; the substrate 11 has a plurality of through holes penetrating from the first surface to the second surface, each through hole being filled with a conductive material to form a conductive via 111; and a redistribution layer 12 is arranged on the second surface, the redistribution layer 12 being flexible and electrically connected with the conductive via 111.

[0075] Step 2, the substrate 11 is subjected to a patterning process to form a groove 2; the groove 2 penetrates from the first surface to the second surface, and the groove 2 divides the substrate 11 into a plurality of connection areas separated by the groove, one connection area being configured to connect one chip 3, and the chip 3 is electrically connected with the conductive via 111 in the corresponding connection area.

[0076] In step 1, the substrate 11 can be pre-fabricated with the conductive via 111 and the redistribution layer 12, and can also be pre-fabricated with the first solder joint 13 and the second solder joint 14. The following steps can also be used to manufacture them:

[0077] Step 100, providing a substrate 11, and subjecting the substrate 11 to a patterning process to form a plurality of through holes penetrating from the first surface to the second surface.

[0078] Step 101, filling the through holes with a conductive material to form a conductive via 111.

[0079] Step 102: Form a plurality of first solder joints 13 on the first surface of the substrate 11.

[0080] Step 103: Form a redistribution layer 12 on the second surface of substrate 11.

[0081] Step 104: Form a plurality of second solder joints 14 on the surface of the redistribution layer 12 away from the substrate 11. The order of steps 102 and 103 is not limited.

[0082] In step 2, as Figure 4 (C) and Figure 5 As shown in (C), depending on different requirements, the groove 2 can be formed as a straight groove or a V-groove. For example, a straight groove can be formed by dry etching / laser grooving / mechanical grooving / wet etching, etc. A V-groove can be formed by wet etching.

[0083] Below, two specific implementation methods are provided for different groove types 2; the process scheme for straight grooves is as follows: Figure 4 As shown, the specific steps are as follows:

[0084] Step 310: Using temporary bonding, the interlayer 1 is bonded to the carrier plate 51 with temporary bonding adhesive 52.

[0085] Step 320, as follows Figure 4 As shown in (A) and (B), photoresist 53 is coated on the interposer layer 1, and the photoresist 53 that needs to be photolithographically etched into the groove 54 is removed by exposure and development.

[0086] Step 330, as follows Figure 4 As shown in (C), the depth of the trench is made up to the redistribution layer 12 by means of dry etching / laser grooving / mechanical grooving / wet etching, etc.

[0087] Step 340, as Figure 4 As shown in (D), the photoresist 53 on the surface of the interposer 1 is removed by wet cleaning.

[0088] The process scheme for V-groove cutting is as follows: Figure 5 As shown, the specific steps are as follows:

[0089] Step 410: Using temporary bonding, the intermediate layer 1 is bonded to the carrier plate 51 with temporary bonding adhesive 52.

[0090] Step 420, as follows Figure 5 As shown in (A) and (B), photoresist 53 is coated on the interposer layer 1, and the photoresist 53 that needs to be photolithographically etched into the groove 54 is removed by exposure and development.

[0091] Step 430, as Figure 5As shown in (C) of FIG. 6, the groove is opened to the rewiring layer 12 by a wet etching method to form a V-shaped groove 55.

[0092] Step 440, as shown in (A) of FIG. 7, the temporary bonding glue 52 is removed from the intermediate layer 1. Figure 5 Step 450, as shown in (D) of FIG. 6, the photoresist 53 on the surface of the intermediate layer 1 is removed by a wet cleaning method.

[0093] The manufacturing method of the embodiment can be used to manufacture the intermediate layer 1 of the embodiment one, and the technical effects of the intermediate layer 1 of the embodiment one are not repeated here.

[0094] Embodiment four

[0095] As shown in Figure 6 , the embodiment of the application further provides a manufacturing method of the three-dimensional packaging structure 001, which can be used to manufacture the three-dimensional packaging structure 001 described in the embodiment two, and can include the following steps:

[0096] Step 10, the manufacturing method of the intermediate layer 1 described in the embodiment three is used to manufacture the intermediate layer 1.

[0097] Step 20, at least two chips 3 are attached to the connection area, the at least two chips 3 include a first chip and a second chip, and the first chip and the second chip are electrically connected to the rewiring layer 12 through the conductive via 111, for example, the soldering method is used to connect the soldering points of the chips to the conductive via 111, such as soldering the soldering points of the chips to the first soldering point 13.

[0098] Step 30, the intermediate layer 1 with the chip 3 is attached to the packaging substrate 4, and the packaging substrate 4 is electrically connected to the rewiring layer 12, for example, the soldering method is used to connect the soldering points of the packaging substrate 4 to the rewiring layer 12, such as soldering the soldering points of the packaging substrate 4 to the second soldering point 14.

[0099] A specific implementation is provided below, as shown in Figure 5 , the manufacturing method of the three-dimensional packaging structure 001 can include the following steps:

[0100] Step 510, as shown in (A) of FIG. 8 and (A) of FIG. 9, the intermediate layer 1 is temporarily bonded to the carrier plate 51 by the temporary bonding glue 52. Figure 4 Figure 5 Step 520, as shown in (A) of FIG. 8, the intermediate layer 1 is slotted in the manner as shown in

[0101] Step 530, as shown in (A) of FIG. 8, the intermediate layer 1 is slotted in the manner as shown in Figure 6 or Figure 4 , so that the intermediate layer 1 is divided into different sub-blocks (connection areas). Figure 5 Step 530, as shown in (A) of FIG. 8, the intermediate layer 1 is slotted in the manner as shown in

[0102] Figure 6 ​​As shown in (B) of FIG. 1, the chip 3 is attached to each sub-interposer (connection area) through the first soldering point 13 on the front surface of the interposer 1.

[0103] As shown in step 540 of FIG. 4, the substrate 11 is cut along the groove 2. Figure 6 As shown in (C) of FIG. 1, the carrier plate 51 is removed by debonding, and the temporary bonding glue 52 is removed by wet cleaning. After the interposer 1 is cleaned, the substrate 11 is cut.

[0104] As shown in step 550 of FIG. 4, the cut substrate 11 is attached to the packaging substrate 4 through the second soldering point 14 on the back surface of the interposer 1. Figure 6 As shown in (D) of FIG. 1, the cut substrate 11 is attached to the packaging substrate 4 through the second soldering point 14 on the back surface of the interposer 1.

[0105] The manufacturing method of the embodiment can prepare the three-dimensional packaging structure 001 of Embodiment Two, which has the technical effects of the three-dimensional packaging structure 001 of Embodiment Two, and will not be described here.

[0106] In summary, the interposer 1 and the manufacturing method thereof, the three-dimensional packaging structure 001 and the manufacturing method thereof provided by the present application have the following advantages. The substrate 11 is provided with a conductive via 111 in the thickness direction, and the front surface is bonded and connected with the chip 3 through the soldering point. The redistribution layer 12 is arranged on the back surface of the flexible interposer 1, and the redistribution layer 12 is connected with the packaging substrate 4 through the soldering point. The plurality of chips 3 are stacked on the front surface of the interposer 1, and are interconnected through the front surface circuit of the substrate 11 and the redistribution layer 12 on the back surface of the substrate 11. The groove 2 is cut from the front surface of the interposer 1 to the redistribution layer 12 along the gap between the chips 3, and the bottom RDL layers of the sub-interposers are connected. By cutting the substrate 11 in the middle, the stress buffering effect of the substrate 11 can be achieved, and the problems such as soldering failure and material delamination caused by the mismatch of the thermal expansion coefficients between the substrate 11, the bottom bump and the packaging substrate 4 can be reduced. Even if there is still stress caused by the mismatch of the thermal expansion coefficients, most of the stress can be further eliminated through the flexible redistribution layer 12, and the warping problem of the large-size packaging structure can be solved.

[0107] Those skilled in the art can understand that all or part of the functions of various methods in the above embodiments can be realized by hardware or by a computer program. When all or part of the functions in the above embodiments are realized by a computer program, the program can be stored in a computer readable storage medium, which can include: read-only memory, random access memory, magnetic disk, optical disk, hard disk, etc. The above functions are realized by executing the program by a computer. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, the above all or part of the functions are realized. In addition, when all or part of the functions in the above embodiments are realized by a computer program, the program can also be stored in a storage medium such as a server, another computer, a disk, an optical disk, a flash disk, or a mobile hard disk, and is saved in the memory of the local device by downloading or copying, or the system of the local device is updated, and when the program in the memory is executed by the processor, all or part of the functions in the above embodiments are realized.

[0108] Various exemplary embodiments are described herein. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope hereof. For example, various operational steps and components for carrying out the operational steps can be implemented in different sequences, or in different manners, depending on the particular application or the number of cost functions associated with implementing the system.

[0109] While the principles of the present disclosure have been illustrated and described in various embodiments, many modifications, adaptations, and variations can be applied to the structures, arrangements, proportions, elements, materials, and components used in or otherwise employed in the practice of the present disclosure without departing from the principles of the present disclosure. Such modifications and variations are intended to be included within the scope of the present disclosure.

[0110] The foregoing detailed description has been presented for purposes of illustration and description. However, various modifications and changes are possible in the implementation of the disclosure. Accordingly, the disclosure is intended to embrace all modifications and alterations within the scope and spirit of the disclosure. Thus, the scope of the disclosure is not intended to be limited to the particular form set forth herein, but includes all features that might be provided within the scope and spirit of the disclosure. Likewise, the benefits and advantages of the various embodiments, other advantages, and solutions to problems have been presented in the foregoing detailed description. However, the scope of the disclosure should be determined, not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The claims are not intended to include, by virtue of their reference to various embodiments, features, aspects, and / or steps, those features, aspects, and / or steps that are not present in some embodiments. The use of the terms "include," "include," "including," and "includes" are not meant to be transitive. The terms "coupled" and "coupled to" are intended to mean physically connected, electrically connected, magnetically connected, optically connected, communicatively connected, functionally connected, and / or any other connection.

[0111] Those skilled in the art will recognize that many modifications can be made to the details of the above-described embodiments without departing from the underlying principles of the present invention. The scope of the present invention should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. The claims are not intended to include, by virtue of their reference to various embodiments, features, aspects, and / or steps that are not present in some embodiments. The use of the terms "include," "include," "including," and "includes" are not meant to be transitive. The terms "coupled" and "coupled to" are intended to mean physically connected, electrically connected, magnetically connected, optically connected, communicatively connected, functionally connected, and / or any other connection.

Claims

1. An interposer, characterized by The intermediate layer (1) comprises: a substrate (11) and a redistribution layer (12); the substrate (11) has opposite first and second surfaces, the substrate (11) has a plurality of through holes penetrating from the first surface to the second surface, each of the through holes being filled with conductive material to form a conductive via (111); the substrate (11) has a groove (2) penetrating from the first surface to the second surface, the groove (2) is formed by patterning the substrate (11), the groove (2) divides the substrate (11) into a plurality of connection areas separated by the groove, one of the connection areas is configured to connect one chip (3), the chip (3) is electrically connected with the conductive via (111) in the corresponding connection area; the redistribution layer (12) is disposed on the second surface, the redistribution layer (12) has flexibility and is electrically connected with the conductive via (111); the conductive via (111) in one of the connection areas is electrically connected with the conductive via (111) in another of the connection areas through the redistribution layer (12), so as to realize interconnection between the chip (3) corresponding to one of the connection areas and another chip (3) corresponding to another of the connection areas.

2. The interposer of claim 1, wherein, The redistribution layer (12) comprises a metal layer (121) and a dielectric layer (122), the dielectric layer (122) has flexibility, the metal layer (121) is electrically connected with the conductive via (111), and the material of the dielectric layer (122) is resin.

3. The interposer of claim 1, wherein, The intermediate layer (1) further comprises a plurality of first solder joints (13); The first solder joint (13) is disposed on the first surface and is electrically connected with the conductive via (111), and the first solder joint (13) is configured to be electrically connected with the chip (3).

4. The interposer of claim 1, wherein, The intermediate layer (1) further comprises a plurality of second solder joints (14); The second solder joint (14) is disposed on the surface of the redistribution layer (12) away from the substrate (11), is electrically connected with the redistribution layer (12), and is configured to be electrically connected with a packaging substrate (4).

5. A three-dimensional packaging structure, characterized by comprising: The three-dimensional packaging structure comprises a plurality of chips (3) and the intermediate layer (1) according to any one of claims 1-4; The plurality of chips (3) at least comprises a first chip and a second chip; The first chip and the second chip are respectively attached to the corresponding connection areas on the intermediate layer, and the first chip and the second chip are electrically connected with the redistribution layer (12) through the conductive via (111) on the intermediate layer.

6. The three-dimensional package structure of claim 5, wherein, The first chip is a storage chip, and the second chip is a processing chip.

7. The three-dimensional package structure of claim 5, wherein the first and second semiconductor chips are electrically connected to the first and second substrates, respectively, by wire bonding. The three-dimensional packaging structure further comprises a packaging substrate (4); The intermediate layer (1) further comprises a plurality of second solder joints (14); The second solder joint (14) is disposed on the surface of the redistribution layer (12) away from the substrate (11), is electrically connected with the redistribution layer (12), and is electrically connected with the packaging substrate (4).

8. The three-dimensional package structure of claim 5, wherein the first and second semiconductor chips are electrically connected to the first and second substrates, respectively, by wire bonding. The three-dimensional packaging structure further comprises an insulating glue, which is arranged between the substrate (11) and the chip (3) and wraps the solder joint electrically connected between the substrate (11) and the chip (3).

9. A method of manufacturing an interposer, characterized by: Comprise: A substrate (11) is provided; wherein the substrate (11) has opposite first and second surfaces; the substrate (11) has a plurality of through holes penetrating from the first surface to the second surface, each of which is filled with conductive material to form a conductive via (111); and a redistribution layer (12) is arranged on the second surface, the redistribution layer (12) being flexible and electrically connected to the conductive via (111); The substrate (11) is subjected to a patterning process to form a groove (2); wherein the groove (2) penetrates from the first surface to the second surface, and the groove (2) divides the substrate (11) into a plurality of connection areas separated by grooves, one of the connection areas being configured to connect one chip (3), the chip (3) being electrically connected to the conductive via (111) in the corresponding connection area; the conductive via (111) in one of the connection areas is electrically connected to the conductive via (111) in another of the connection areas through the redistribution layer (12), so as to realize interconnection between the chip (3) corresponding to one of the connection areas and another chip (3) corresponding to another of the connection areas.

10. A method of manufacturing a three-dimensional package structure, characterized by: Comprise: A manufacturing method of the interposer (1) of claim 9 is used to prepare the interposer (1); At least two chips (3) are attached to the corresponding connection areas, the at least two chips (3) comprising a first chip and a second chip, the first chip and the second chip being electrically connected to the conductive via (111) and the redistribution layer (12); The interposer (1) with the chip (3) is attached to a packaging substrate (4), and the packaging substrate (4) is electrically connected to the redistribution layer (12).

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