Semiconductor device and method of manufacturing the same

Abstract

This invention provides a semiconductor device and its manufacturing method. The semiconductor device includes: a substrate; a capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; a conductive structure and an inductor structure, the conductive structure being formed on the lower electrode surrounding the upper electrode, the inductor structure being formed on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode. The technical solution of this invention solves the problem of excessive chip area occupied by the combination of capacitor and inductor structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] In radio frequency (RF) products, capacitors and inductors are often used in combination as passive components. However, the following problems exist:

[0003] (1) Capacitors and inductors are horizontally arranged on the chip, occupying a large chip area (for example, they occupy about 30% of the chip area in total);

[0004] (2) In order to prevent the generation of parasitic capacitance and signal interference to capacitors and inductors, it is required that no metal interconnects, virtual metal layers and device structures be designed directly below the capacitors and inductors, which would lead to a waste of chip area.

[0005] Therefore, improvements are needed to the structure combining capacitors and inductors to solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which solves the problem of excessive chip area occupied by the combination of capacitor and inductor structures.

[0007] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0008] Base;

[0009] A capacitor structure includes a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, wherein the lower electrode extends to the periphery of the upper electrode;

[0010] A conductive structure and an inductive structure are provided, wherein the conductive structure is formed on the lower electrode plate surrounding the upper electrode plate, and the inductive structure is formed on the upper electrode plate. The conductive structure is connected to the lower electrode plate, and the inductive structure is connected to the upper electrode plate.

[0011] Optionally, the inductor structure is a serpentine winding structure.

[0012] Optionally, the conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductor structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

[0013] Optionally, the array of second conductive plugs is arranged such that the inductor structure winds around from the top of the outermost second conductive plug to the top of the innermost second conductive plug, so that the inductor structure can be wound multiple times.

[0014] Optionally, the conductive structure is not enclosed and surrounds the inductor structure.

[0015] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0016] Provide a base;

[0017] A capacitor structure is formed, the capacitor structure including a lower electrode plate, a dielectric layer and an upper electrode plate formed from bottom to top on the substrate, the lower electrode plate extending to the periphery of the upper electrode plate;

[0018] A conductive structure is formed on the lower electrode plate surrounding the upper electrode plate, and an inductive structure is formed on the upper electrode plate. The conductive structure is connected to the lower electrode plate, and the inductive structure is connected to the upper electrode plate.

[0019] Optionally, the inductor structure is a serpentine winding structure.

[0020] Optionally, the conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductor structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

[0021] Optionally, the array of second conductive plugs is arranged such that the inductor structure winds around from the top of the outermost second conductive plug to the top of the innermost second conductive plug, so that the inductor structure can be wound multiple times.

[0022] Optionally, the conductive structure is not enclosed and surrounds the inductor structure.

[0023] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0024] 1. The semiconductor device of the present invention comprises: a substrate; a capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; a conductive structure and an inductor structure, the conductive structure being formed on the lower electrode surrounding the upper electrode, the inductor structure being formed on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode. This solves the problem of excessive chip area occupied by the combination of the capacitor and inductor structures.

[0025] 2. The semiconductor device manufacturing method of the present invention includes: providing a substrate; forming a capacitor structure, the capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; forming a conductive structure on the lower electrode surrounding the upper electrode; and forming an inductor structure on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode. This solves the problem of excessive chip area occupied by the combination of capacitor and inductor structures. Attached Figure Description

[0026] Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 yes Figure 1 The diagram shows a cross-sectional view of the semiconductor device along the AA' direction;

[0028] Figure 3 yes Figure 1 A top view schematic diagram of the inductor and conductor structures in the semiconductor device shown;

[0029] Figure 4 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0030] Among them, the appendix Figures 1-4 The annotations in the attached figures are explained as follows:

[0031] 111-Lower electrode plate; 112-Dielectric layer; 113-Upper electrode plate; 121-First conductive plug; 122-Conductive structure; 131-Second conductive plug; 132-Inductor structure. Detailed Implementation

[0032] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] An embodiment of the present invention provides a semiconductor device, comprising: a substrate; a capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; a conductive structure and an inductor structure, the conductive structure being formed on the lower electrode surrounding the upper electrode, the inductor structure being formed on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode.

[0034] See below. Figures 1-3 The semiconductor device provided in this embodiment is described in detail.

[0035] The substrate (not shown) may include a substrate and a first insulating dielectric layer located on the substrate.

[0036] Metal interconnect structures may be formed in the first insulating dielectric layer.

[0037] The substrate can be any suitable substrate known to those skilled in the art, such as at least one of the following materials: silicon, germanium, silicon germanium, silicon carbon, silicon carbon germanium, indium arsenide, gallium arsenide, indium phosphide, or semiconductor on insulator (SOI, such as silicon on insulator).

[0038] Device structures such as transistors can be formed on the substrate, the first insulating dielectric layer covers the device structure, and the metal interconnect structure can be electrically connected to the device structure.

[0039] The capacitor structure is formed on the first insulating dielectric layer.

[0040] The capacitor structure includes a lower electrode 111, a dielectric layer 112, and an upper electrode 113 formed from bottom to top on the substrate, with the lower electrode 111 extending to the periphery of the upper electrode 113.

[0041] The dielectric layer 112 may be located only between the lower electrode plate 111 and the upper electrode plate 113, that is, the dielectric layer 112 and the upper electrode plate 113 are stacked on a portion of the lower electrode plate 111; or, the dielectric layer 112 may extend to the periphery of the upper electrode plate 113, that is, the dielectric layer 112 is located on the entire lower electrode plate 111, and the upper electrode plate 113 is located on a portion of the dielectric layer 112.

[0042] The lower electrode 111 is made of metal nitride, metal, or polycrystalline silicon, and the upper electrode 113 is made of metal nitride, metal, or polycrystalline silicon. The materials of the lower electrode 111 and the upper electrode 113 may be the same or different.

[0043] When the lower electrode 111 and the upper electrode 113 are made of metal nitride or metal, the capacitor structure is a MIM capacitor; when the lower electrode 111 and the upper electrode 113 are made of polycrystalline silicon, the capacitor structure is a PIP capacitor; when one electrode of the lower electrode 111 and the upper electrode 113 is made of metal nitride or metal, and the other electrode is made of polycrystalline silicon, the capacitor structure is a PIM capacitor.

[0044] The dielectric layer 112 is preferably made of a high-k (relative permittivity) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the dielectric layer 112 may also be made of at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0045] The conductive structure 122 is formed on the lower electrode 111 surrounding the upper electrode 113, and the inductor structure 132 is formed on the upper electrode 113.

[0046] The conductive structure 122 is connected to the lower electrode plate 111, and the inductor structure 132 is connected to the upper electrode plate 113.

[0047] The inductor structure 132 is a serpentine coil structure.

[0048] In one embodiment, the conductive structure 122 is electrically connected to the lower electrode plate 111 via a plurality of first conductive plugs 121; the inductor structure 132 is electrically connected to the upper electrode plate 113 via a plurality of second conductive plugs 131. The plurality of first conductive plugs 121 and the plurality of second conductive plugs 131 are fabricated simultaneously, as are the conductive structure 122 and the inductor structure 132. In other embodiments, the first conductive plugs 121 and the second conductive plugs 131 may not be formed; the conductive structure 122 is directly connected to the lower electrode plate 111, and the inductor structure 132 is directly connected to the upper electrode plate 113.

[0049] The second conductive plugs 131 are arranged in an array, and the inductor structure 132 winds around from the top of the outermost second conductive plug 131 to the top of the innermost second conductive plug 131, so that the inductor structure 132 can be wound multiple times.

[0050] The conductive structure 122 is not enclosed and surrounds the inductor structure 132, so that the inductor structure 132 can be connected.

[0051] The conductive structure 122 and the inductor structure 132 are located on the same layer, and the conductive structure 122 is non-enclosed and surrounds the inductor structure 132.

[0052] exist Figures 1-3 In the illustrated embodiment, the plurality of second conductive plugs 131 form a rectangular array, the plurality of first conductive plugs 121 surround the plurality of second conductive plugs 131 on three sides, and the conductive structure 122 surrounds the inductor structure 132 on three sides, so that as many first conductive plugs 121 as possible are disposed on the lower electrode plate 111 surrounding the upper electrode plate 113, thereby reducing the contact resistance between the lower electrode plate 111 and the plurality of first conductive plugs 121. In other embodiments, the conductive structure 122 may also surround the inductor structure 132 on four sides, as long as a gap is left for connecting the inductor structure 132.

[0053] The projections of the plurality of first conductive plugs 121 in the direction perpendicular to the substrate surface can be completely located within the projection range of the conductive structure 122 in the direction perpendicular to the substrate surface, and the projections of the plurality of second conductive plugs 131 in the direction perpendicular to the substrate surface can be completely located within the projection range of the inductor structure 132 in the direction perpendicular to the substrate surface.

[0054] A second insulating dielectric layer (not shown) may be formed on the substrate, the second insulating dielectric layer covering the capacitor structure, the conductive structure 122 and the inductor structure 132.

[0055] Conductive interconnect structures (not shown) may also be formed in the second insulating dielectric layer on the conductive structure 122 and the inductor structure 132, the conductive interconnect structures being used to connect the conductive structure 122 and the inductor structure 132 respectively.

[0056] As can be seen from the above, since the inductor structure 132 is formed on the upper electrode 113 of the capacitor structure, the capacitor structure and the inductor structure 132 are vertically connected, and the lower electrode 111 is then electrically connected from the conductive structure 122. That is, the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, thereby significantly reducing the chip area occupied by the combination of the capacitor structure and the inductor structure 132.

[0057] To prevent parasitic capacitance and signal interference to the capacitor and inductor structures 132, it is required that no metal interconnect structures, virtual metal layers, or device structures be formed directly below the capacitor and inductor structures 132, which would result in wasted chip area. However, in this invention, since the capacitor and inductor structures 132 share the same horizontal area of ​​the chip, the saved chip area can be used to set up metal interconnect structures, virtual metal layers, and device structures, thereby reducing the amount of wasted chip area.

[0058] In existing capacitor structures, to achieve a high quality factor, it is necessary to reduce the contact resistance between the upper plate and the multiple conductive plugs on it. This requires increasing the number of conductive plugs to enlarge the total contact area between all the plugs and the upper plate. Consequently, large metal blocks need to be formed on the conductive plugs to connect them. However, the fabrication process of these large metal blocks presents challenges: Firstly, the large metal blocks are fabricated together with other film layers in the same layer, and the etching rate for forming the large metal blocks is higher than that for forming the smaller film layers. This means that by the time the large metal blocks are etched, the smaller film layers have already been etched, affecting their formation. Secondly, during the fabrication of the conductive interconnect structure above the large metal blocks, the grinding of the metal on the surface of the insulating dielectric layer on the large metal blocks can create a grinding load effect, resulting in metal residue defects on the surface of the insulating dielectric layer in areas where large metal blocks are not formed, indicating uneven grinding. In this invention, by forming the inductor structure 132 on the upper electrode plate 113, i.e., the upper electrode plate 113 is connected through the inductor structure 132, the inductor structure 132 is not a large-area metal layer, but a serpentine coil structure. This allows the etching of the inductor structure 132 to be performed on a small area, meaning the etching rate of the inductor structure 132 is consistent with the etching rate of other film layers located on the same layer as the inductor structure 132, without affecting the fabrication of other film layers. Furthermore, during the fabrication of the conductive interconnect structure above the inductor structure 132, when the metal on the surface of the second insulating dielectric layer on the inductor structure 132 is polished, the polishing load effect can be reduced, avoiding metal residue defects on the surface of the second insulating dielectric layer in areas where the inductor structure 132 is not formed, thereby improving the uniformity of polishing. Therefore, when the number of the second conductive plugs 131 below the inductor structure 132 is increased in order to improve the quality factor of the capacitor structure, only the number of turns of the inductor structure 132 will increase, without increasing the manufacturing difficulty.

[0059] Furthermore, in existing capacitor structures, to obtain a larger capacitance value, the area of ​​the upper electrode plate needs to be increased, which leads to an increase in the area of ​​the metal block, making the manufacturing process of the metal block more difficult. Therefore, in order to increase the capacitance value of the capacitor structure while avoiding increasing the area of ​​the metal block, the only way to obtain a larger capacitance value is to design multiple capacitor structures in parallel on the horizontal plane of the chip, which leads to an increase in the chip area occupied. However, in this invention, when the area of ​​the upper electrode plate 113 is increased to increase the capacitance value of the capacitor structure, since the inductor structure 132 is not a large area metal layer, the manufacturing process of the inductor structure 132 is not increased, and it is not necessary to design multiple capacitor structures in parallel.

[0060] In summary, this invention provides a semiconductor device comprising: a substrate; a capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; a conductive structure and an inductor structure, the conductive structure being formed on the lower electrode surrounding the upper electrode, the inductor structure being formed on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode. The semiconductor device provided by this invention solves the problem of excessive chip area occupied by the combination of capacitor and inductor structures.

[0061] Based on the same inventive concept, one embodiment of the present invention provides a method for manufacturing a semiconductor device, see below. Figure 4 ,from Figure 4 As can be seen from the above, the manufacturing method of the semiconductor device includes:

[0062] Step S1, provide a substrate;

[0063] Step S2, forming a capacitor structure, the capacitor structure including a lower electrode plate, a dielectric layer and an upper electrode plate formed from bottom to top on the substrate, the lower electrode plate extending to the periphery of the upper electrode plate;

[0064] Step S3: A conductive structure is formed on the lower electrode plate surrounding the upper electrode plate, and an inductive structure is formed on the upper electrode plate. The conductive structure is connected to the lower electrode plate, and the inductive structure is connected to the upper electrode plate.

[0065] See below. Figures 1-3 The manufacturing method of the semiconductor device provided in this embodiment will be described in detail.

[0066] According to step S1, a substrate (not shown) is provided.

[0067] The substrate may include a substrate and a first insulating dielectric layer located on the substrate.

[0068] Metal interconnect structures may be formed in the first insulating dielectric layer.

[0069] The substrate can be any suitable substrate known to those skilled in the art, such as at least one of the following materials: silicon, germanium, silicon germanium, silicon carbon, silicon carbon germanium, indium arsenide, gallium arsenide, indium phosphide, or semiconductor on insulator (SOI, such as silicon on insulator).

[0070] Device structures such as transistors can be formed on the substrate, the first insulating dielectric layer covers the device structure, and the metal interconnect structure can be electrically connected to the device structure.

[0071] According to step S2, a capacitor structure is formed, the capacitor structure including a lower electrode plate 111, a dielectric layer 112 and an upper electrode plate 113 formed from bottom to top on the substrate, the lower electrode plate 111 extending to the periphery of the upper electrode plate 113.

[0072] The capacitor structure is formed on the first insulating dielectric layer.

[0073] The dielectric layer 112 may be located only between the lower electrode plate 111 and the upper electrode plate 113, that is, the dielectric layer 112 and the upper electrode plate 113 are stacked on a portion of the lower electrode plate 111; or, the dielectric layer 112 may extend to the periphery of the upper electrode plate 113, that is, the dielectric layer 112 is located on the entire lower electrode plate 111, and the upper electrode plate 113 is located on a portion of the dielectric layer 112.

[0074] Taking the dielectric layer 112 as an example located only between the lower electrode 111 and the upper electrode 113, the steps for forming the capacitor structure may include: first, forming a lower electrode material layer, a dielectric material layer, and an upper electrode material layer from bottom to top on the substrate; then, etching the upper electrode material layer and the dielectric material layer to expose the lower electrode material layer, with the remaining upper electrode material layer and the dielectric material layer serving as the upper electrode 113 and the dielectric layer 112, respectively; then, etching a portion of the exposed lower electrode material layer to expose the substrate, with the remaining lower electrode material layer serving as the lower electrode 111.

[0075] The lower electrode 111 is made of metal nitride, metal, or polycrystalline silicon, and the upper electrode 113 is made of metal nitride, metal, or polycrystalline silicon. The materials of the lower electrode 111 and the upper electrode 113 may be the same or different.

[0076] When the lower electrode 111 and the upper electrode 113 are made of metal nitride or metal, the capacitor structure is a MIM capacitor; when the lower electrode 111 and the upper electrode 113 are made of polycrystalline silicon, the capacitor structure is a PIP capacitor; when one electrode of the lower electrode 111 and the upper electrode 113 is made of metal nitride or metal, and the other electrode is made of polycrystalline silicon, the capacitor structure is a PIM capacitor.

[0077] The dielectric layer 112 is preferably made of a high-k (relative permittivity) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the dielectric layer 112 may also be made of at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0078] According to step S3, a conductive structure 122 is formed on the lower electrode plate 111 surrounding the upper electrode plate 113, and an inductive structure 132 is formed on the upper electrode plate 113.

[0079] The conductive structure 122 is connected to the lower electrode plate 111, and the inductor structure 132 is connected to the upper electrode plate 113.

[0080] The inductor structure 132 is a serpentine coil structure.

[0081] In one embodiment, the conductive structure 122 is electrically connected to the lower electrode plate 111 via a plurality of first conductive plugs 121; the inductor structure 132 is electrically connected to the upper electrode plate 113 via a plurality of second conductive plugs 131. The plurality of first conductive plugs 121 and the plurality of second conductive plugs 131 are fabricated simultaneously, as are the conductive structure 122 and the inductor structure 132. In other embodiments, the first conductive plugs 121 and the second conductive plugs 131 may not be formed; the conductive structure 122 is directly connected to the lower electrode plate 111, and the inductor structure 132 is directly connected to the upper electrode plate 113.

[0082] The second conductive plugs 131 are arranged in an array, and the inductor structure 132 winds around from the top of the outermost second conductive plug 131 to the top of the innermost second conductive plug 131, so that the inductor structure 132 can be wound multiple times.

[0083] The conductive structure 122 is not enclosed and surrounds the inductor structure 132, so that the inductor structure 132 can be connected.

[0084] The conductive structure 122 and the inductor structure 132 are located on the same layer, and the conductive structure 122 is non-enclosed and surrounds the inductor structure 132.

[0085] exist Figures 1-3 In the illustrated embodiment, the plurality of second conductive plugs 131 form a rectangular array, the plurality of first conductive plugs 121 surround the plurality of second conductive plugs 131 on three sides, and the conductive structure 122 surrounds the inductor structure 132 on three sides, so that as many first conductive plugs 121 as possible are disposed on the lower electrode plate 111 surrounding the upper electrode plate 113, thereby reducing the contact resistance between the lower electrode plate 111 and the plurality of first conductive plugs 121. In other embodiments, the conductive structure 122 may also surround the inductor structure 132 on four sides, as long as a gap is left for connecting the inductor structure 132.

[0086] The projections of the plurality of first conductive plugs 121 in the direction perpendicular to the substrate surface can be completely located within the projection range of the conductive structure 122 in the direction perpendicular to the substrate surface, and the projections of the plurality of second conductive plugs 131 in the direction perpendicular to the substrate surface can be completely located within the projection range of the inductor structure 132 in the direction perpendicular to the substrate surface.

[0087] A second insulating dielectric layer (not shown) may be formed on the substrate, covering the capacitor structure, the conductive structure 122, and the inductor structure 132. The conductive structure 122 and the inductor structure 132 can be formed by etching the second insulating dielectric layer and depositing metal material in the etched vias and / or grooves.

[0088] Conductive interconnect structures (not shown) may also be formed in the second insulating dielectric layer on the conductive structure 122 and the inductor structure 132, the conductive interconnect structures being used to connect the conductive structure 122 and the inductor structure 132 respectively.

[0089] As can be seen from the above, since the inductor structure 132 is formed on the upper electrode 113 of the capacitor structure, the capacitor structure and the inductor structure 132 are vertically connected, and the lower electrode 111 is then electrically connected from the conductive structure 122. That is, the capacitor structure and the inductor structure 132 share the same horizontal area of ​​the chip, thereby significantly reducing the chip area occupied by the combination of the capacitor structure and the inductor structure 132.

[0090] To prevent parasitic capacitance and signal interference to the capacitor and inductor structures 132, it is required that no metal interconnect structures, virtual metal layers, or device structures be formed directly below the capacitor and inductor structures 132, which would result in wasted chip area. However, in this invention, since the capacitor and inductor structures 132 share the same horizontal area of ​​the chip, the saved chip area can be used to set up metal interconnect structures, virtual metal layers, and device structures, thereby reducing the amount of wasted chip area.

[0091] In existing capacitor structures, to achieve a high quality factor, it is necessary to reduce the contact resistance between the upper plate and the multiple conductive plugs on it. This requires increasing the number of conductive plugs to enlarge the total contact area between all the plugs and the upper plate. Consequently, large metal blocks need to be formed on the conductive plugs to connect them. However, the fabrication process of these large metal blocks presents challenges: Firstly, the large metal blocks are fabricated together with other film layers in the same layer, and the etching rate for forming the large metal blocks is higher than that for forming the smaller film layers. This means that by the time the large metal blocks are etched, the smaller film layers have already been etched, affecting their formation. Secondly, during the fabrication of the conductive interconnect structure above the large metal blocks, the grinding of the metal on the surface of the insulating dielectric layer on the large metal blocks can create a grinding load effect, resulting in metal residue defects on the surface of the insulating dielectric layer in areas where large metal blocks are not formed, indicating uneven grinding. In this invention, by forming the inductor structure 132 on the upper electrode plate 113, i.e., the upper electrode plate 113 is connected through the inductor structure 132, the inductor structure 132 is not a large-area metal layer, but a serpentine coil structure. This allows the etching of the inductor structure 132 to be performed on a small area, meaning the etching rate of the inductor structure 132 is consistent with the etching rate of other film layers located on the same layer as the inductor structure 132, without affecting the fabrication of other film layers. Furthermore, during the fabrication of the conductive interconnect structure above the inductor structure 132, when the metal on the surface of the second insulating dielectric layer on the inductor structure 132 is polished, the polishing load effect can be reduced, avoiding metal residue defects on the surface of the second insulating dielectric layer in areas where the inductor structure 132 is not formed, thereby improving the uniformity of polishing. Therefore, when the number of the second conductive plugs 131 below the inductor structure 132 is increased in order to improve the quality factor of the capacitor structure, only the number of turns of the inductor structure 132 will increase, without increasing the manufacturing difficulty.

[0092] Furthermore, in existing capacitor structures, to obtain a larger capacitance value, the area of ​​the upper electrode plate needs to be increased, which leads to an increase in the area of ​​the metal block, making the manufacturing process of the metal block more difficult. Therefore, in order to increase the capacitance value of the capacitor structure while avoiding increasing the area of ​​the metal block, the only way to obtain a larger capacitance value is to design multiple capacitor structures in parallel on the horizontal plane of the chip, which leads to an increase in the chip area occupied. However, in this invention, when the area of ​​the upper electrode plate 113 is increased to increase the capacitance value of the capacitor structure, since the inductor structure 132 is not a large area metal layer, the manufacturing process of the inductor structure 132 is not increased, and it is not necessary to design multiple capacitor structures in parallel.

[0093] In summary, this invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a capacitor structure, the capacitor structure including a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, the lower electrode extending to the periphery of the upper electrode; forming a conductive structure on the lower electrode surrounding the upper electrode; and forming an inductor structure on the upper electrode, the conductive structure being connected to the lower electrode, and the inductor structure being connected to the upper electrode. The semiconductor device manufacturing method provided by this invention solves the problem of excessive chip area occupied by the combination of capacitor and inductor structures.

[0094] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Base; A capacitor structure includes a lower electrode, a dielectric layer, and an upper electrode formed from bottom to top on the substrate, wherein the lower electrode extends to the periphery of the upper electrode; A conductive structure and an inductive structure are provided, wherein the conductive structure is formed on the lower electrode plate surrounding the upper electrode plate, and the inductive structure is formed on the upper electrode plate. The conductive structure is electrically connected to the lower electrode plate, and the inductive structure is electrically connected to the upper electrode plate.

2. The semiconductor device as claimed in claim 1, characterized in that, The inductor structure is a serpentine coil structure.

3. The semiconductor device as described in claim 1, characterized in that, The conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductor structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

4. The semiconductor device as described in claim 3, characterized in that, The array of second conductive plugs is arranged such that the inductor structure winds around from the top of the outermost second conductive plug to the top of the innermost second conductive plug, allowing the inductor structure to be wound multiple times.

5. The semiconductor device as claimed in claim 1, characterized in that, The conductive structure is non-enclosed and surrounds the inductive structure.

6. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; A capacitor structure is formed, the capacitor structure including a lower electrode plate, a dielectric layer and an upper electrode plate formed from bottom to top on the substrate, the lower electrode plate extending to the periphery of the upper electrode plate; A conductive structure is formed on the lower electrode plate surrounding the upper electrode plate, and an inductive structure is formed on the upper electrode plate. The conductive structure is electrically connected to the lower electrode plate, and the inductive structure is electrically connected to the upper electrode plate.

7. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The inductor structure is a serpentine coil structure.

8. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The conductive structure is electrically connected to the lower electrode plate through a plurality of first conductive plugs, and the inductor structure is electrically connected to the upper electrode plate through a plurality of second conductive plugs.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The array of second conductive plugs is arranged such that the inductor structure winds around from the top of the outermost second conductive plug to the top of the innermost second conductive plug, allowing the inductor structure to be wound multiple times.

10. The method for manufacturing a semiconductor device as described in claim 6, characterized in that, The conductive structure is non-enclosed and surrounds the inductive structure.

Images