Full parallel signal processing method and device, electronic equipment and storage medium

Abstract

The invention relates to a full parallel signal processing method and device, electronic equipment and a storage medium, and the method comprises the steps: receiving a modulation signal of a target PN code transmitted by a transmitter, and carrying out the parallel convolution operation through employing the modulation signal and a preset analog signal, and obtaining an optimal sampling point of the modulation signal; performing parallel channel estimation and parallel channel equalization operation based on the optimal sampling point of the modulation signal to obtain equalization data of the modulation signal; and performing parallel de-mapping operation on the balanced data of the modulation signal to generate soft bit data of the modulation signal, and performing Viterbi decoding on the modulation signal by using the soft bit data to obtain an original input sequence of a full parallel signal corresponding to the modulation signal. Therefore, the problems that all modulation and demodulation algorithms cannot be realized in parallel, the core rate is difficult to reduce, the calculation speed is low and the like are solved.

Description

Technical Field

[0001] The present application relates to the technical field of digital signal processing, and in particular to a method, device, electronic device and storage medium for processing a fully parallel signal. Background Art

[0002] Among many broadband wireless communication technologies, Orthogonal Frequency Division Multiplexing (OFDM) is one of the most promising technologies. Among the fading characteristics of the channel, multipath fading and Doppler frequency shift have the greatest impact on broadband wireless mobile services. OFDM can not only effectively suppress the inter-symbol interference caused by multipath by inserting the cyclic prefix (CP) method, but also flexibly design the system's symbol length by reasonably estimating the channel's time-varying characteristics, thereby reducing the impact of the channel's time-varying characteristics on system performance. Due to these technical characteristics of OFDM, the use of complex time-domain equalizers and adaptive tracking algorithms in the receiver is avoided. In addition, by using fast Fourier transform, reliable and stable communication quality can be guaranteed under a relatively simple system hardware structure.

[0003] Therefore, OFDM technology has been widely adopted by various wireless communication standards. Although the system structure can eliminate inter-symbol interference, the OFDM system still requires accurate channel information for channel equalization to fully compensate for multipath fading. OFDM's channel estimation and equalization technology have a decisive influence on the performance of the entire system.

[0004] In the actual engineering of digital signal processing in optical communication, as the AD sampling rate becomes higher and higher, FPGA (Field Programmable Gate Array) cannot process full bandwidth data in real time. Generally, phase splitting (that is, serial-to-parallel conversion) is adopted inside FPGA to reduce the processing speed. In the design of modulation and demodulation algorithm, N-channel parallel modulation is adopted.

[0005] In the prior art, the basic modulation model is as follows Figure 1 As shown, each subcarrier contains an integer multiple of periods in one OFDM symbol period, and adjacent subcarriers differ by one period; OFDM signal modulation can be achieved through IFFT (Inverse Fast Fourier Transform), and at the receiving end, a simple FFT (Fast Fourier Transform) can also be used to demodulate the signal.

[0006] The spectrum of OFDM signal and the OFDM wireless communication system model are as follows: Figure 2, Figure 3 As shown in FIG. 1 , the spectrum of each subcarrier is in the shape of a Sinc function, and the subcarriers overlap each other. However, due to the position of the integer subcarrier spacing (such as Figure 2 As shown by the arrow in the middle, each subcarrier remains orthogonal. Therefore, there is no interference between subcarriers at this position, the data can be ideally recovered at the receiving end, and data can be transmitted at the Nyquist symbol rate.

[0007] However, the existing technology cannot implement all modulation and demodulation algorithms in parallel, it is difficult to reduce the core rate, and the calculation speed is slow, which needs to be solved urgently. Summary of the invention

[0008] The present application provides a fully parallel signal processing method, device, electronic device and storage medium to solve the problems of being unable to implement all modulation and demodulation algorithms in parallel, difficulty in reducing the core rate, slow computing speed, etc.

[0009] The first aspect of the present application provides a method for processing a fully parallel signal, comprising the following steps: receiving a modulation signal of a target PN code sent by a transmitter, performing a parallel convolution operation on the modulation signal and a preset analog signal to obtain an optimal sampling point of the modulation signal; performing parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulation signal to obtain equalized data of the modulation signal; and performing a parallel demapping operation on the equalized data of the modulation signal to generate soft bit data of the modulation signal, and using the soft bit data to perform Viterbi decoding on the modulation signal to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal.

[0010] Optionally, in one embodiment of the present application, the method of performing parallel convolution operation on the modulated signal and the preset analog signal to obtain the optimal sampling point of the modulated signal includes: based on the modulated signal and the preset analog signal, calculating N / 8 parallel convolutions according to a preset superframe duration to obtain the optimal sampling point of the modulated signal, wherein N is a positive integer.

[0011] Optionally, in one embodiment of the present application, the parallel channel estimation and parallel channel equalization operations are performed based on the optimal sampling point of the modulation signal to obtain the equalized data of the modulation signal, including: based on the optimal sampling point of the modulation signal, performing a fast Fourier transform on the modulation signal of the target PN code to obtain the actual value of the modulation signal; performing parallel Cordic phase estimation through the actual value of the modulation signal to obtain the phase deviation of the modulation signal; removing the time domain CP of each information frame in the target PN code, and performing the fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame; based on the actual value of the frequency domain, the phase deviation and a preset amplitude coefficient, obtaining the equalized data of the modulation signal.

[0012] Optionally, in one embodiment of the present application, the equalization data of the modulated signal is subjected to a parallel demapping operation to generate soft bit data of the modulated signal, and the modulated signal is Viterbi decoded using the soft bit data to obtain an original input sequence of the fully parallel signal corresponding to the modulated signal, including: calculating the real symbol, real amplitude, imaginary symbol, and imaginary amplitude of the equalization data of the modulated signal; determining the decision symbol and soft bit data of the modulated signal based on the real symbol, real amplitude, imaginary symbol, and imaginary amplitude; and decoding the modulated signal using the decision symbol and the soft bit data according to a preset Viterbi decoding method to obtain the original input sequence of the fully parallel signal corresponding to the modulated signal.

[0013] The second aspect of the present application provides a fully parallel signal processing device, including: a convolution module, used to receive a modulation signal of a target PN code sent by a transmitter, and use the modulation signal and a preset analog signal to perform a parallel convolution operation to obtain an optimal sampling point of the modulation signal; an equalization module, used to perform parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulation signal to obtain equalized data of the modulation signal; and a decoding module, used to perform a parallel demapping operation on the equalized data of the modulation signal to generate soft bit data of the modulation signal, and use the soft bit data to perform Viterbi decoding on the modulation signal to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal.

[0014] Optionally, in one embodiment of the present application, the convolution module includes: a calculation unit, used to calculate N / 8 parallel convolutions based on the modulation signal and the preset analog signal according to a preset superframe duration to obtain the optimal sampling point of the modulation signal, wherein N is a positive integer.

[0015] Optionally, in one embodiment of the present application, the equalization module includes: a first transformation unit, used to perform a fast Fourier transform on the modulation signal of the target PN code based on the optimal sampling point of the modulation signal to obtain the actual value of the modulation signal; a first calculation unit, used to perform parallel Cordic phase estimation through the actual value of the modulation signal to obtain the phase deviation of the modulation signal; a second transformation unit, used to remove the time domain CP of each information frame in the target PN code, and perform the fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame; a second calculation unit, used to obtain the equalization data of the modulation signal based on the actual value of the frequency domain, the phase deviation and a preset amplitude coefficient.

[0016] Optionally, in one embodiment of the present application, the decoding module includes: a third calculation unit, used to calculate the real sign, real amplitude, imaginary sign, and imaginary amplitude of the equalized data of the modulated signal; a determination unit, used to determine the decision symbol and soft bit data of the modulated signal based on the real sign, real amplitude, imaginary sign, and imaginary amplitude; a decoding unit, used to decode the modulated signal using the decision symbol and the soft bit data according to a preset Viterbi decoding method to obtain the original input sequence of the fully parallel signal corresponding to the modulated signal.

[0017] The third aspect of the present application provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the fully parallel signal processing method as described in the above embodiment.

[0018] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the program is executed by a processor, it implements the above-mentioned method for processing fully parallel signals.

[0019] Therefore, the embodiments of the present application have the following beneficial effects:

[0020] The embodiment of the present application can obtain the optimal sampling point of the modulated signal by receiving the modulation signal of the target PN code sent by the transmitter, and performing parallel convolution operation with the modulation signal and the preset analog signal; performing parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulation signal to obtain the equalized data of the modulation signal; and performing parallel demapping operations on the equalized data of the modulation signal to generate soft bit data of the modulation signal, and using the soft bit data, Viterbi decoding the modulation signal to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal. The present application obtains the original input sequence through time domain PN parallel synchronization, parallel FFT, channel estimation, demapping, and deconvolution code, so as to realize all the modulation and demodulation algorithms in parallel, reduce the core rate, improve the calculation speed, realize the calculation of the bit error rate, and achieve the goal of testing the performance of the channel. Therefore, the problems of not being able to realize all the modulation and demodulation algorithms in parallel, difficulty in reducing the core rate, and slow calculation speed are solved.

[0021] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0023] Figure 1 It is a schematic diagram of a basic modulation model;

[0024] Figure 2 A schematic diagram of a virtual subcarrier and frequency division multiplexing;

[0025] Figure 3 A schematic diagram of a simple OFDM wireless communication system model provided for one embodiment of the present application;

[0026] Figure 4 A flowchart of a fully parallel signal processing method provided according to an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the internal principle of a modulation chip provided for one embodiment of the present application;

[0028] Figure 6 A schematic diagram of the execution logic of a fully parallel signal processing method provided for one embodiment of the present application;

[0029] Figure 7 A schematic diagram of the internal principle of a demodulation chip provided for one embodiment of the present application;

[0030] Figure 8is an exemplary diagram of a fully parallel signal processing device according to an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0032] Among them, 10-a fully parallel signal processing device, 100-a convolution module, 200-an equalization module, 300-a decoding module, 901-a memory, 902-a processor, and 903-a communication interface. DETAILED DESCRIPTION

[0033] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0034] The following describes the fully parallel signal processing method, device, electronic device and storage medium of the embodiment of the present application with reference to the accompanying drawings. In view of the problems mentioned in the above background technology, the present application provides a fully parallel signal processing method, in which the optimal sampling point of the modulated signal is obtained by receiving the modulation signal of the target PN code sent by the transmitter, and the modulation signal is used to perform parallel convolution operation with the preset analog signal; based on the optimal sampling point of the modulation signal, parallel channel estimation and parallel channel equalization operations are performed to obtain the equalized data of the modulation signal; and the equalized data of the modulation signal is parallel demapped to generate soft bit data of the modulation signal, and the modulated signal is Viterbi decoded using the soft bit data to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal. The present application obtains the original input sequence through time domain PN parallel synchronization, parallel FFT, channel estimation, demapping, and deconvolution code, so that the modulation and demodulation algorithms are all implemented in parallel, the core rate is reduced, the calculation speed is improved, the bit error rate calculation is realized, and the goal of testing the channel performance is achieved. Therefore, the problems of being unable to implement all the modulation and demodulation algorithms in parallel, being difficult to reduce the core rate, and having a slow calculation speed are solved.

[0035] Specifically, Figure 4 A flowchart of a fully parallel signal processing method provided in an embodiment of the present application.

[0036] like Figure 4 As shown, the fully parallel signal processing method includes the following steps:

[0037] In step S401, a modulation signal of a target PN code sent by a transmitter is received, and a parallel convolution operation is performed on the modulation signal and a preset analog signal to obtain an optimal sampling point of the modulation signal.

[0038] In the design of the transmitter of the embodiment of the present application, each information frame uses a CP of N / 8 length, and every 24 information frames use a PN code with an m-sequence in the frequency domain, and each information frame is uniformly subjected to an inverse fast Fourier transform to be modulated into a baseband signal, such as Figure 5 As shown, the baseband signal is filtered and time-domain equalized through an external circuit, and a DC bias is added to obtain a modulated signal, which is transmitted to the optical detector through an RF and DC port (RFDC, Radio Frequency Direct Current).

[0039] Furthermore, the optical detector of the embodiment of the present application transmits the analog signal to the FPGA after AGC (Automatic Gain Control), such as Figure 6 As shown, the modulation signal of the PN code sent by the receiving transmitter after filtering and time domain equalization and other operations is processed, and the optimal sampling point of the modulation signal is obtained through time domain PN parallel synchronization operation, thereby providing reliable data support for the subsequent realization of visible light full parallel demodulation.

[0040] Optionally, in one embodiment of the present application, a parallel convolution operation is performed on the modulated signal and the preset analog signal to obtain the optimal sampling point of the modulated signal, including: based on the modulated signal and the preset analog signal, N / 8 parallel convolutions are calculated according to a preset superframe duration to obtain the optimal sampling point of the modulated signal, where N is a positive integer.

[0041] The embodiments of the present application can adopt time domain PN parallel synchronous operation, and the receiving end stores the time domain estimation value of the m-sequence PN code in the intermediate frequency domain of the transmitting end after the inverse fast Fourier transform, and performs N / 8 parallel convolution calculations with the analog signal input by the AD (Analog to Digital Converter) to obtain the optimal sampling point.

[0042] It should be noted that, in the above-mentioned convolution process, the embodiment of the present application may use a register to store N / 8 data paths of AD, and calculate the convolution according to the super-frame length. Before the threshold convolution range is not reached, each super-frame length may cause the register to shift back 1 symbol. The theoretical maximum search time is: super-frame length * N / 8, where N is a positive integer.

[0043] Therefore, the embodiment of the present application obtains the optimal sampling point of the modulated signal through time domain PN parallel synchronization, thereby providing data guarantee for the execution of subsequent parallel channel estimation and other operations.

[0044] In step S402, parallel channel estimation and parallel channel equalization operations are performed based on the optimal sampling point of the modulated signal to obtain equalized data of the modulated signal.

[0045] After obtaining the optimal sampling point of the modulated signal, the embodiment of the present application can further perform operations such as parallel channel estimation and parallel channel equalization, such as Figure 7 As shown, the optimal sampling points obtained above are analyzed and processed to obtain the equalized data of the modulated signal.

[0046] Optionally, in one embodiment of the present application, parallel channel estimation and parallel channel equalization operations are performed based on the optimal sampling point of the modulation signal to obtain equalized data of the modulation signal, including: based on the optimal sampling point of the modulation signal, performing a fast Fourier transform on the modulation signal of the target PN code to obtain the actual value of the modulation signal; performing parallel Cordic phase estimation through the actual value of the modulation signal to obtain the phase deviation of the modulation signal; removing the time domain CP of each information frame in the target PN code, and performing a fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame; based on the actual value of the frequency domain, the phase deviation phase and the preset amplitude coefficient, the equalized data of the modulation signal is obtained.

[0047] It should be noted that the specific steps of performing parallel channel estimation and parallel channel equalization operations on the optimal sampling points of the modulated signal in the embodiment of the present application are as follows:

[0048] 1. Parallel channel estimation:

[0049] (1) After the PN parallel synchronization operation in the time domain, the estimated value of the PN code position is the same as the PN code of the m-sequence in the frequency domain of the transmitting end, and the actual value of the PN code is the FFT result of the PN code of the synchronization position at the receiving end;

[0050] (2) A parallel Cordic algorithm is used to perform a parallel Cordic phase estimation operation to obtain a phase deviation, which is recorded as Phase Cordic. The modulus of the real and imaginary parts of the PN code after FFT is the amplitude estimation value, which is recorded as Amplitude Cordic. Thus, the parallel Cordic algorithm is used to divide the channel estimation into two dimensions: phase and amplitude, avoiding the direct use of complex multiplication and reducing resource utilization.

[0051] 2. Parallel channel equalization:

[0052] (1) After removing the time domain CP from each information frame in the PN code, perform FFT to obtain the actual value of the information frame in the frequency domain;

[0053] (2) Multiply the actual value of the information frame in the frequency domain by the phase deviation Phase Cordic, and the phase of the actual value in the frequency domain obtained has been adjusted to amplitude-free data;

[0054] (3) Divide the actual phase value in the frequency domain by the estimated amplitude value Amplitude Cordic to obtain the real data after equalization, that is, the equalized data.

[0055] Therefore, the embodiments of the present application perform parallel channel estimation and parallel channel equalization operations on the optimal sampling points of the modulated signal, thereby effectively eliminating interference and distortion in the communication process and improving the stability and reliability of signal transmission.

[0056] In step S403, a parallel demapping operation is performed on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and the modulated signal is Viterbi decoded using the soft bit data to obtain an original input sequence of the full parallel signal corresponding to the modulated signal.

[0057] After obtaining the equalized data of the modulated signal, the embodiments of the present application may further perform operations such as parallel demapping and parallel decoding on the data to obtain the original input sequence, thereby effectively reducing the bit error rate and achieving the goal of testing the channel performance.

[0058] Optionally, in one embodiment of the present application, a parallel demapping operation is performed on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and the modulated signal is Viterbi decoded using the soft bit data to obtain an original input sequence of the fully parallel signal corresponding to the modulated signal, including: calculating the real symbol, real amplitude, imaginary symbol, and imaginary amplitude of the equalized data of the modulated signal; determining the decision symbol and soft bit data of the modulated signal based on the real symbol, real amplitude, imaginary symbol, and imaginary amplitude; and decoding the modulated signal using the decision symbol and soft bit data according to a preset Viterbi decoding method to obtain the original input sequence of the fully parallel signal corresponding to the modulated signal.

[0059] It should be noted that the specific process of obtaining the original input sequence by using the equalized data through parallel demapping, parallel decoding and other operations in the embodiment of the present application is as follows:

[0060] 1. Parallel demapping:

[0061] Using parallel linear demapping, the 4 bits of information required for 16QAM are real sign, real amplitude, imaginary sign and imaginary amplitude. The soft bits after the information represent the degree of certainty and are used for soft decoding.

[0062] Among them, the parallel demapping in the embodiment of the present application can adopt the soft bit solution method to solve the real sign, real amplitude, imaginary sign and imaginary amplitude information, compare the distance between the actual point and the adjacent point of the real data after equalization, use the shortest distance as the judgment symbol of this point, and use this distance as a soft bit and output it to the parallel decoding functional unit.

[0063] 2. Parallel decoding:

[0064] Viterbi decoding is adopted to decode the soft bits and restore the code stream, so as to decode the modulated signal according to the decision symbol and the soft bit data to obtain the original input sequence of the full parallel signal corresponding to the modulated signal.

[0065] Therefore, the embodiments of the present application obtain the original input sequence through operations such as time domain PN parallel synchronization, parallel FFT, parallel channel estimation, parallel demapping and parallel decoding, so that the modulation and demodulation algorithms are all implemented in parallel, effectively reducing the core rate and improving the calculation speed.

[0066] According to the fully parallel signal processing method proposed in the embodiment of the present application, by receiving the modulation signal of the target PN code sent by the transmitter, the modulation signal and the preset analog signal are used to perform parallel convolution operations to obtain the optimal sampling point of the modulation signal; based on the optimal sampling point of the modulation signal, parallel channel estimation and parallel channel equalization operations are performed to obtain the equalized data of the modulation signal; and the equalized data of the modulation signal is parallel demapped to generate soft bit data of the modulation signal, and the soft bit data is used to perform Viterbi decoding on the modulation signal to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal. The present application obtains the original input sequence through time domain PN parallel synchronization, parallel FFT, channel estimation, demapping, and deconvolution code, so that all modulation and demodulation algorithms are implemented in parallel, which reduces the core rate, improves the calculation speed, realizes the calculation of the bit error rate, and achieves the goal of testing the performance of the channel.

[0067] Next, a fully parallel signal processing device proposed in accordance with an embodiment of the present application is described with reference to the accompanying drawings.

[0068] Figure 8 It is a block diagram of a fully parallel signal processing device according to an embodiment of the present application.

[0069] like Figure 8 As shown, the fully parallel signal processing device 10 includes: a convolution module 100, an equalization module 200 and a decoding module 300.

[0070] The convolution module 100 is used to receive a modulation signal of a target PN code sent by a transmitter, and perform a parallel convolution operation on the modulation signal and a preset analog signal to obtain an optimal sampling point of the modulation signal.

[0071] The equalization module 200 is used to perform parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulated signal to obtain equalized data of the modulated signal.

[0072] The decoding module 300 is used to perform a parallel demapping operation on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and use the soft bit data to perform Viterbi decoding on the modulated signal to obtain an original input sequence of the full parallel signal corresponding to the modulated signal.

[0073] Optionally, in one embodiment of the present application, the convolution module 100 includes: a calculation unit, used to calculate N / 8 parallel convolutions based on the modulated signal and the preset analog signal according to a preset superframe duration to obtain the optimal sampling point of the modulated signal, where N is a positive integer.

[0074] Optionally, in one embodiment of the present application, the equalization module includes: a first transformation unit, a first calculation unit, a second transformation unit and a second calculation unit.

[0075] Wherein, the first transformation unit is used to perform fast Fourier transformation on the modulation signal of the target PN code based on the optimal sampling point of the modulation signal to obtain the actual value of the modulation signal.

[0076] The first calculation unit is used to perform parallel Cordic phase estimation according to the actual value of the modulation signal to obtain the phase deviation of the modulation signal.

[0077] The second transform unit is used to remove the time domain CP of each information frame in the target PN code, and perform fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame.

[0078] The second calculation unit is used to obtain the equalization data of the modulated signal based on the actual value in the frequency domain, the phase deviation phase and the preset amplitude coefficient.

[0079] Optionally, in one embodiment of the present application, the decoding module includes: a third calculation unit, a determination unit and a decoding unit.

[0080] The third calculation unit is used to calculate the real sign, real amplitude, imaginary sign and imaginary amplitude of the equalized data of the modulated signal.

[0081] The determination unit is used to determine the decision symbol and soft bit data of the modulation signal based on the real part symbol, the real part amplitude, the imaginary part symbol, and the imaginary part amplitude.

[0082] The decoding unit is used to decode the modulated signal using the decision symbol and the soft bit data according to the preset Viterbi decoding method to obtain the original input sequence of the full parallel signal corresponding to the modulated signal.

[0083] It should be noted that the above explanation of the embodiment of the method for processing a fully parallel signal is also applicable to the apparatus for processing a fully parallel signal of this embodiment, and will not be described in detail here.

[0084] According to the fully parallel signal processing device proposed in the embodiment of the present application, a convolution module is used to receive the modulation signal of the target PN code sent by the transmitter, and the modulation signal is used to perform parallel convolution operation with the preset analog signal to obtain the optimal sampling point of the modulation signal; the equalization module is used to perform parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulation signal to obtain the equalized data of the modulation signal; and the decoding module is used to perform parallel demapping operations on the equalized data of the modulation signal, generate soft bit data of the modulation signal, and use the soft bit data to perform Viterbi decoding on the modulation signal to obtain the original input sequence of the fully parallel signal corresponding to the modulation signal. The present application obtains the original input sequence through time domain PN parallel synchronization, parallel FFT, channel estimation, demapping, and deconvolution code, so as to realize all the modulation and demodulation algorithms in parallel, reduce the core rate, improve the calculation speed, realize the calculation of the bit error rate, and achieve the goal of testing the channel performance.

[0085] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may include:

[0086] A memory 901 , a processor 902 , and a computer program stored in the memory 901 and executable on the processor 902 .

[0087] When the processor 902 executes the program, the full parallel signal processing method provided in the above embodiment is implemented.

[0088] Furthermore, the electronic device further comprises:

[0089] The communication interface 903 is used for communication between the memory 901 and the processor 902 .

[0090] The memory 901 is used to store computer programs that can be executed on the processor 902 .

[0091] The memory 901 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0092] If the memory 901, the processor 902 and the communication interface 903 are implemented independently, the communication interface 903, the memory 901 and the processor 902 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig. 9 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0093] Optionally, in a specific implementation, if the memory 901, the processor 902 and the communication interface 903 are integrated on a chip, the memory 901, the processor 902 and the communication interface 903 can communicate with each other through an internal interface.

[0094] The processor 902 may be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0095] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the above-mentioned method for processing fully parallel signals when executed by a processor.

[0096] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0097] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0098] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or N executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0099] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purpose of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or N wirings (electronic devices), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways as necessary and then storing it in a computer memory.

[0100] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above embodiment, the N steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0101] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0102] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0103] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for processing a fully parallel signal, characterized in that: The following steps are involved: A modulation signal of a target PN code sent by a transmitter is received, and a parallel convolution operation is performed using the modulation signal and a preset analog signal to obtain an optimal sampling point of the modulation signal; Performing parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulated signal to obtain equalized data of the modulated signal; as well as A parallel demapping operation is performed on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and the modulated signal is Viterbi decoded using the soft bit data to obtain an original input sequence of the full parallel signal corresponding to the modulated signal.

2. The method according to claim 1, characterized in that The method of performing a parallel convolution operation on the modulated signal and a preset analog signal to obtain an optimal sampling point of the modulated signal includes: Based on the modulated signal and the preset analog signal, N / 8 parallel convolutions are calculated according to a preset superframe duration to obtain the optimal sampling point of the modulated signal, wherein N is a positive integer.

3. The method according to claim 1 or 2, characterized in that: The performing parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulated signal to obtain equalized data of the modulated signal includes: Based on the optimal sampling point of the modulation signal, performing a fast Fourier transform on the modulation signal of the target PN code to obtain an actual value of the modulation signal; Performing parallel Cordic phase estimation based on the actual value of the modulation signal to obtain the phase deviation of the modulation signal; Removing the time domain CP of each information frame in the target PN code, and performing the fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame; Based on the actual value in the frequency domain, the phase deviation and the preset amplitude coefficient, the equalization data of the modulated signal is obtained.

4. The method according to claim 3, characterized in that: The performing a parallel demapping operation on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and using the soft bit data to perform Viterbi decoding on the modulated signal to obtain an original input sequence of a fully parallel signal corresponding to the modulated signal, comprises: Calculate the real sign, real amplitude, imaginary sign, and imaginary amplitude of the equalized data of the modulated signal; Determine the decision symbol and soft bit data of the modulated signal based on the real part sign, the real part amplitude, the imaginary part sign, and the imaginary part amplitude; According to a preset Viterbi decoding method, the modulated signal is decoded using the decision symbol and the soft bit data to obtain the original input sequence of the full parallel signal corresponding to the modulated signal.

5. A fully parallel signal processing device, characterized in that: include: A convolution module is used to receive a modulation signal of a target PN code sent by a transmitter, and to perform a parallel convolution operation using the modulation signal and a preset analog signal to obtain an optimal sampling point of the modulation signal; An equalization module, used for performing parallel channel estimation and parallel channel equalization operations based on the optimal sampling point of the modulated signal to obtain equalized data of the modulated signal; as well as The decoding module is used to perform a parallel demapping operation on the equalized data of the modulated signal to generate soft bit data of the modulated signal, and use the soft bit data to perform Viterbi decoding on the modulated signal to obtain an original input sequence of the full parallel signal corresponding to the modulated signal.

6. The device according to claim 5, characterized in that The convolution module comprises: A calculation unit is used to calculate N / 8 parallel convolutions based on the modulated signal and the preset analog signal according to a preset superframe duration to obtain the optimal sampling point of the modulated signal, wherein N is a positive integer.

7. The device according to claim 5 or 6, characterized in that The balancing module comprises: A first transform unit, configured to perform a fast Fourier transform on the modulation signal of the target PN code based on the optimal sampling point of the modulation signal to obtain an actual value of the modulation signal; A first calculation unit, configured to perform parallel Cordic phase estimation according to an actual value of the modulation signal to obtain a phase deviation of the modulation signal; A second transformation unit, used to remove the time domain CP of each information frame in the target PN code, and perform the fast Fourier transform on each information frame to obtain the actual value of the frequency domain corresponding to each information frame; The second calculation unit is used to obtain the equalization data of the modulated signal based on the actual value in the frequency domain, the phase deviation phase and a preset amplitude coefficient.

8. The device according to claim 7, characterized in that The decoding module comprises: A third calculation unit, used to calculate the real part sign, real part amplitude, imaginary part sign, and imaginary part amplitude of the equalized data of the modulated signal; A determination unit, configured to determine a decision symbol and soft bit data of the modulated signal based on the real part symbol, the real part amplitude, the imaginary part symbol, and the imaginary part amplitude; The decoding unit is used to decode the modulated signal using the decision symbol and the soft bit data according to a preset Viterbi decoding method to obtain the original input sequence of the full parallel signal corresponding to the modulated signal.

9. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the fully parallel signal processing method according to any one of claims 1 to 4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the full parallel signal processing method as described in any one of claims 1 to 4.

Images