Method for transceiver fusion processing based on AURORA simplex IP core

Abstract

The invention discloses a method for fusion processing of transmitting and receiving based on AURORA simplex IP core, belonging to the field of communication technology, the method comprising: creating an AURORA project and performing parameter configuration; wherein the AURORA project comprises a transmitting IP core and a receiving IP core; adjusting the modules in the transmitting IP core and the receiving IP core; interconnecting the adjusted transmitting IP core and the receiving IP core, and connecting the transmitting IP core and the receiving IP core to external interfaces respectively; constraining the positions of the connected transmitting IP core and the receiving IP core, and generating a bit stream to realize fusion processing of transmitting and receiving. The method can realize data transmission when the same channel TX and RX are connected to different peripherals.

Description

Technical Field

[0001] The present invention belongs to the field of communication technology, and in particular relates to a method for fusion processing of transceiver based on AURORA simplex IP core. Background Art

[0002] With the increasing demand for data transmission, high-speed serial interfaces play an important role in modern communication systems. The GT (Gigabit Transceiver) resources in FPGA (Field Programmable Gate Array) are the basis for high-speed interfaces. GT is integrated in the FPGA chip in the form of a hard core. Among them, a GT is called a channel, and each channel contains a TX (transmitter) and a RX (receiver). The two have independent functions. Four GTs form a group called a Quad. A Quad contains a QPLL (Quad phase-locked loop), and each GT contains a CPLL (Channel phase-locked loop). Each Quad can share the input reference clock of the adjacent Quad. You only need to configure the interface data and clock to realize the high-speed serial interface.

[0003] Xilinx has designed the AURORA IP Core to easily implement transceivers, and also provides a lightweight user interface on which designers can build serial links. AURORA is a commonly used high-speed serial communication protocol that uses differential transmission, 8b / 10b or 64b / 66b encoding, and has the characteristics of high bandwidth, low latency and high reliability. It supports full-duplex, simplex and other data communication modes, and can achieve high-speed data transmission between FPGAs or between FPGAs and other external devices.

[0004] Currently, in applications where FPGAs receive and forward large amounts of data, the TX and RX of the same channel usually need to be connected to different external devices for data transmission. When using AURORA's duplex mode transmission, such as Figure 1 As shown in the figure, the TX and RX of the two parties transmitting data need to be connected to each other for the link to be established, so the data transmission requirement of connecting the TX and RX of the same channel to different external devices is not met. When using AURORA's simplex mode transmission, since the TX and RX of each channel are used in pairs, if TX calls the AURORA IP core and constrains the pins, the corresponding RX will also be constrained, resulting in RX being unable to call the AURORA IP core, and vice versa.

[0005] In summary, the existing AURORA IP core cannot meet the data transmission requirements when the TX and RX of the same channel are connected to different external devices. Summary of the invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a method for fusion processing of transceiver based on AURORA simplex IP core. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] In a first aspect, the present invention proposes a method for fusion processing of transceiver based on AURORA simplex IP core, comprising:

[0008] Create an AURORA project and configure parameters. The AURORA project includes the transmitter IP core and the receiver IP core.

[0009] Adjust the modules in the transmitting IP core and the receiving IP core;

[0010] The adjusted transmitting IP core and receiving IP core are interconnected, and the transmitting IP core and receiving IP core are connected to external interfaces respectively;

[0011] Perform position constraints on the connected transmitting IP core and receiving IP core, and generate a bit stream to achieve transmitting and receiving fusion processing.

[0012] In one embodiment of the present invention, an AURORA project is created and parameter configuration is performed, specifically including:

[0013] Open the AURORA IP core, set the number of Lanes to n, and configure the line rate and clock parameters; where n is the number of channels in each IP core, and each channel includes a pair of receivers and transmitters;

[0014] The data flow mode is set to send-only simplex mode and receive-only simplex mode respectively, and the transmitting IP core and receiving IP core are generated accordingly.

[0015] In one embodiment of the present invention, the modules in the transmitting IP core and the receiving IP core are adjusted, including:

[0016] The high-speed transceiver module, phase-locked loop module and clock management module called in the transmitting IP core are deleted; at the same time, the high-speed transceiver module, phase-locked loop module and clock management module called in the receiving IP core are retained.

[0017] In one embodiment of the present invention, interconnecting the adjusted transmitting IP core and receiving IP core includes:

[0018] The core clock ports, transceiver control and status ports, and ports for interacting with the GT transceiver in the transmitting IP core and the receiving IP core are connected accordingly, thereby realizing the interconnection between the transmitting IP core and the receiving IP core.

[0019] In one embodiment of the present invention, connecting the transmitting IP core and the receiving IP core to the external interface respectively includes:

[0020] According to the AURORA protocol, the transmitting IP core and the receiving IP core are connected to the external interface respectively.

[0021] In one embodiment of the present invention, the modules in the transmitting IP core and the receiving IP core are adjusted, including:

[0022] The high-speed transceiver module, phase-locked loop module and clock management module called in the receiving IP core are deleted, while the high-speed transceiver module, phase-locked loop module and clock management module called in the transmitting IP core are retained.

[0023] In a second aspect, the present invention provides a transceiver module, which includes a receiving IP core and a transmitting IP core; the receiving IP core and the transmitting IP core are interconnected and respectively connected to an external interface; so as to realize simultaneous data transmission and reception;

[0024] The transceiver module is implemented using the method for transceiver fusion processing based on AURORA simplex IP core provided by the first aspect of the present invention.

[0025] In a third aspect, the present invention proposes a communication system, which includes at least one transceiver module and at least one user unit, the transceiver module is used to send data to the user unit and receive data sent by the user unit; wherein the transceiver module is the transceiver module provided in the second aspect of the present invention.

[0026] Beneficial effects of the present invention:

[0027] The method for AURORA simplex IP core transceiver fusion processing provided by the present invention creates a transmitting IP core and a receiving IP core, and after adjusting the modules in the two IP cores, interconnects the two IP cores, thereby realizing AURORA simplex IP core transceiver fusion. The method can realize simultaneous data transmission when the same channel TX and RX are connected to different external devices.

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a functional diagram of existing Aurora duplex mode data transmission;

[0030] Figure 2 It is a flow chart of a method for fusion processing of transceiver based on AURORA simplex IP core provided by an embodiment of the present invention;

[0031] Figure 3 It is a schematic diagram of the interconnection relationship between the transmitting IP core and the receiving IP core provided by an embodiment of the present invention;

[0032] Figure 4 This is a functional diagram of three modules performing data transmission provided by an embodiment of the present invention;

[0033] Figure 5 This is a diagram of the implementation result when TX and RX of three modules each having a group of channels are connected to each other provided by an embodiment of the present invention;

[0034] Figure 6 This is a diagram of the implementation result when TX and RX of multiple groups of channels in each of the three modules provided by an embodiment of the present invention are connected to each other. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The first aspect of the present invention provides a method for fusion processing of transceiver and transmit based on AURORA simplex IP core. Figure 2 It is a flow chart of a method for fusion processing of transceiver based on AURORA simplex IP core provided by an embodiment of the present invention, which specifically includes the following steps:

[0037] Step 1: Create an AURORA project and configure parameters; the AURORA project includes the transmitter IP core and the receiver IP core.

[0038] First, open the AURORA IP core, set the number of Lanes to n, and configure the line rate and clock parameters; where n is the number of channels in each IP core, and each channel includes a pair of receivers and transmitters. It can be understood that in each receiver module, there can be a group of channels with TX and RX connected to each other, or there can be multiple groups of channels with TX and RX connected to each other.

[0039] Then, the data flow mode is set to the simplex mode of sending only and the simplex mode of receiving only, and the transmitting IP core and the receiving IP core are generated accordingly.

[0040] The simplex mode of only sending can be described as TX-only Simplex, and the simplex mode of only receiving can be described as RX-only Simplex; the transmitting IP core can be recorded as Aurora_Tx, and the receiving IP core can be recorded as Aurora_Rx.

[0041] Step 2: Adjust the modules in the transmitting IP core and the receiving IP core.

[0042] Specifically, the transmitting end and the receiving end respectively instantiate a series of files with a suffix of .v generated by establishing their own IP cores, and then adjust the modules in their own IP cores.

[0043] Optionally, as an implementation, this embodiment may be adjusted in the following manner:

[0044] Delete the high-speed transceiver module Aurora_Tx_MULTI_GT, phase-locked loop module Aurora_Tx_gt_common_wrapper, and clock management module Aurora_Tx_gt_CLOCK_MODULE called in the transmitting IP core Aurora_Tx; at the same time, retain the high-speed transceiver module Aurora_Rx_MULTI_GT, phase-locked loop module Aurora_Rx_gt_common_wrapper, and clock management module Aurora_Rx_gt_CLOCK_MODULE called in the receiving IP core Aurora_Rx.

[0045] In another embodiment of the present invention, adjustment can also be performed in the following manner:

[0046] Delete the high-speed transceiver module Aurora_Rx_MULTI_GT, phase-locked loop module Aurora_Rx_gt_common_wrapper, and clock management module Aurora_Rx_gt_CLOCK_MODULE called in the receiving IP core Aurora_Rx, and retain the high-speed transceiver module Aurora_Tx_MULTI_GT, phase-locked loop module Aurora_Tx_gt_common_wrapper, and clock management module Aurora_Tx_gt_CLOCK_MODULE called in the transmitting IP core Aurora_Tx.

[0047] Step 3: interconnect the adjusted transmitting IP core and receiving IP core, and connect the transmitting IP core and receiving IP core to external interfaces respectively.

[0048] In this embodiment, the clock ports (Core Clock Ports), transceiver control and status ports (Transceiver Control and StatusInterface Ports), and ports used to interact with GT transceiver (Ports used to interact with GTTransceiver) in the transmitting IP core Aurora_Tx and the receiving IP core Aurora_Rx can be connected accordingly, thereby realizing the interconnection between the transmitting IP core and the receiving IP core.

[0049] Specifically, see Figure 3 , Figure 3 Schematic diagram of the interconnection relationship between the transmitting IP core and the receiving IP core provided by the embodiment of the present invention. Figure 3 On the left is the receiving IP core Aurora_Rx, whose clock ports mainly include user_clk_out and sync_clk_out; the transceiver control and status ports mainly include mmcm_not_locked_out, gt_qpllrefclklost_out, gt_qplllock_out, gt_txbufstatus_out[1:0], and gt_txresetdone_out; the ports used to interact with the GT transceiver mainly include gt_txdata_in[63:0], gt_gttxreset_in, gt_txuserrdy_in, gt_txheader_in[1:0], and gt_txsequence_in[6:0]. Figure 3 On the right side is the transmitting IP core Aurora_Tx, whose clock ports mainly include user_clk_in and sync_clk_in; the transceiver control and status ports mainly include mmcm_not_locked_in, gt_qpllrefclklost_in, gt_qplllock_in, txbufstatus_in[1:0], and txresetdone_in; the ports used to interact with the GT transceiver mainly include scrambled_data_out[63:0], gttxreset_out, txuserrdy_out, txheader_out[1:0], and txsequence_out[6:0].

[0050] It is understandable that the other ports of the transmitting IP core Aurora_Tx and the receiving IP core Aurora_Rx need to be connected to the external interface according to the AURORA protocol. Among them, the transmitting IP core Aurora_Tx and the receiving IP core Aurora_Rx share a reference clock.

[0051] It should be noted that for the case where there is a group of channels with TX and RX interconnected, they can be directly connected in the above manner. For the case where there are multiple groups of channels with TX and RX interconnected, the connection of the clock port is the same as the case where there is a group of channels with TX and RX interconnected. There are multiple groups of transceiver control and status ports and ports for interacting with GT transceivers, and the ports of the same channel are connected accordingly.

[0052] Step 4: Perform position constraints on the connected transmitting IP core and receiving IP core, and generate a bit stream to achieve transmitting and receiving fusion processing.

[0053] Specifically, after completing the connection between the transmitting IP core Aurora_Tx and the receiving IP core Aurora_Rx, they are synthesized through software, and then the Aurora_Tx module and the Aurora_Rx module are constrained to the Quad positions corresponding to TX and RX using pblock.

[0054] At this point, the fusion processing of transmitting and receiving based on AURORA simplex IP core has been realized.

[0055] After the AURORA simplex IP core transmit-receive fusion processing, an incremental number can be generated in the program and transmitted between different modules to verify the effect of data transmission after the processing of the present invention.

[0056] The method for AURORA simplex IP core transceiver fusion processing provided by the present invention creates a transmitting IP core and a receiving IP core, and after adjusting the modules in the two IP cores, interconnects the two IP cores, thereby realizing AURORA simplex IP core transceiver fusion. The method can realize simultaneous data transmission when the same channel TX and RX are connected to different external devices.

[0057] Furthermore, this embodiment also builds a hardware environment based on multiple data transmission scenarios and creates a program to be tested to verify the feasibility of the present invention.

[0058] For example, this embodiment selects three modules to simulate a multi-data transmission scenario. The functional diagram of the three modules performing data transmission is as follows: Figure 4 As shown, the AURORA project processed in Module1 according to the method provided by the present invention is used as the program to be tested, and the AURORA projects processed in the normal mode in Module2 and Module3 are used as auxiliary test programs. Module2 generates an incremental number and sends it to Module1, which then sends the data to Module3 after receiving it.

[0059] Specifically, for the situation where each of the three modules has a group of channel TX and RX connected to each other, first, create the AURORA project in Module1 according to the method of the present invention based on the AURORA simplex IP core transceiver fusion processing, select the number of Lanes as 1, and generate the bit file to be tested.

[0060] Then, use the normal mode of the AURORA IP core to create Figure 4 In the AURORA test project of Module2 and Module3, constrain the corresponding ports according to the TX and RX connection relationship shown in the figure, and generate their own bit files through the Generate Bitstream operation.

[0061] Finally, the generated bit file is burned into the FPGA corresponding to Module1, Module2 and Module3 for testing, and the clock and transmission status ports (Clock and Transceiver StatusInterface Ports) of AURORA in the three modules are observed, including gt_pll_lock, mmcm_not_locked, channel_up, lane_up, hard_err, soft_err; user data ports (User Flow Control Interface Ports), including tready, tdata, tvalid.

[0062] It is understandable that for simplex AURORA, we only need to focus on the receiving end status, and the receiving end results in Module1 and Module3 are as follows: Figure 5 shown.

[0063] For the situation where the TX and RX of three modules are connected to each other with multiple groups of channels, follow the steps below:

[0064] Taking 4 groups as an example, firstly, the AURORA project of Module 1 is created according to the method of the present invention based on the AURORA simplex IP core transceiver fusion processing, the number of Lanes is selected as 4, and a bit file to be tested is generated.

[0065] Then use the normal mode of the AURORA IP core to create the AURORA test projects for Module2 and Module3 corresponding to Module1. Figure 4 The 1 group of TX and RX connections in the example are expanded to 4 groups. The corresponding ports are constrained according to the connection relationship of the 4 lines. The respective bit files are generated through the Generate Bitstream operation.

[0066] Finally, the generated bit file is burned into the FPGA corresponding to Module1, Module2 and Module3 for testing, and the clock and transmission status ports (Clock and Transceiver StatusInterface Ports) of AURORA in the three modules are observed, including gt_pll_lock, mmcm_not_locked, channel_up, lane_up, hard_err, soft_err; user data ports (User Flow Control Interface Ports), including tready, tdata, tvalid.

[0067] Similarly, for simplex AURORA, we only need to focus on the receiving end status. The receiving end results in Module1 and Module3 are as follows: Figure 6 shown.

[0068] observe Figure 5 and Figure 6 The ports in each module, gt_pll_lock, channel_up, lane_up three states are all high level, mmcm_not_locked, hard_err, soft_err three states are all low level, indicating that the clock and transmission status port indications are normal. Observe the user data port tdata of each module. The data sent during the test is an increasing number of 0~99. The figure shows part of the intercepted data. It can be seen that the data received by Module1 is consistent with the data forwarded to Module3. The test result is normal, indicating that after the AURORA simplex IP core based on the present invention is used for transceiver fusion processing, data transmission can be realized when the same channel TX and RX are connected to different peripherals.

[0069] Based on the same inventive concept, the second aspect of the present invention also proposes a transceiver module, which includes a receiving IP core and a transmitting IP core; and the receiving IP core and the transmitting IP core are interconnected and respectively connected to external interfaces; to achieve simultaneous data reception and transmission; the transceiver module adopts the method based on AURORA simplex IP core reception and transmission fusion processing proposed in the first aspect of the present invention to realize data processing.

[0070] It should be pointed out here that the above description of the transceiver module embodiment is similar to the description of the above method embodiment based on the AURORA simplex IP core transceiver fusion processing, so the transceiver module can also realize the simultaneous transmission of data when the same channel TX and RX are connected to different external devices. For technical details not disclosed in the embodiment of the transceiver module of the embodiment of the present invention, please refer to the description of the method embodiment based on the AURORA simplex IP core transceiver fusion processing of the present invention.

[0071] Based on the same inventive concept, the third aspect of the present invention proposes a communication system, comprising at least one transceiver module and at least one user unit, wherein the transceiver module is used to send data to the user unit and receive data sent by the user unit; wherein the transceiver module comprises the transceiver module proposed in the second aspect of the present invention. Thus, the system can also realize simultaneous data transmission when the same channel TX and RX are connected to different external devices.

[0072] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for fusion processing of transceiver based on AURORA simplex IP core, characterized in that: include: Create an AURORA project and configure parameters; wherein the AURORA project includes a transmitting IP core and a receiving IP core; Adjusting the modules in the transmitting IP core and the receiving IP core; including: deleting the high-speed transceiver module, phase-locked loop module and clock management module called in the transmitting IP core, while retaining the high-speed transceiver module, phase-locked loop module and clock management module called in the receiving IP core; or deleting the high-speed transceiver module, phase-locked loop module and clock management module called in the receiving IP core, while retaining the high-speed transceiver module, phase-locked loop module and clock management module called in the transmitting IP core; The adjusted transmitting IP core and the receiving IP core are interconnected, and the transmitting IP core and the receiving IP core are respectively connected to external interfaces according to the AURORA protocol; wherein the adjusted transmitting IP core and the receiving IP core are interconnected, including: correspondingly connecting the core clock port, the transceiver control and status port, and the port for interacting with the GT transceiver in the transmitting IP core and the receiving IP core, so as to realize the interconnection between the transmitting IP core and the receiving IP core; The connected transmitting IP core and receiving IP core are positionally constrained by using pblock, and the two are constrained to the Quad positions corresponding to TX and RX, and a bit stream is generated to realize the fusion processing of transmitting and receiving.

2. The method for fusion processing of transmitting and receiving based on AURORA simplex IP core according to claim 1 is characterized in that: Create an AURORA project and configure the parameters, including: Open the AURORA IP core, set the number of Lanes to n, and configure the line rate and clock parameters; where n is the number of channels in each IP core, and each channel includes a pair of receivers and transmitters; The data flow mode is set to send-only simplex mode and receive-only simplex mode respectively, and the transmitting IP core and receiving IP core are generated accordingly.

3. A transceiver module, characterized in that: The transceiver module includes a receiving IP core and a transmitting IP core; the receiving IP core and the transmitting IP core are interconnected and respectively connected to an external interface; so as to realize simultaneous data transmission and reception; The transceiver module is implemented by the method for transceiver fusion processing based on AURORA simplex IP core as described in any one of claims 1-2.

4. A communication system, characterized in that: It comprises at least one transceiver module and at least one user unit, wherein the transceiver module is used to send data to the user unit and receive data sent by the user unit; wherein the transceiver module comprises the transceiver module described in claim 3.

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