A fire power two-bus power supply and communication method and device based on PWM

Abstract

The present application provides a PWM-based fire power two-bus power supply and communication method and device, which relates to the field of fire monitoring technology, including sending a PWM voltage signal from a master station to a slave station as a downlink signal, and sending a PWM current signal from a slave station to a master station as an uplink signal, and representing the signal logic based on a combination of PWM frequency and PWM duty cycle, defining the time length of a timer according to the minimum pulse width of PWM as a unit pulse width count value, making a comparison table containing hexadecimal numbers, binary numbers, PWM frequencies, PWM duty cycles, PWM low-level pulse width count values, PWM high-level pulse width count values, and PWM cycle values, using a single-byte lookup table method to encode and send codes based on the comparison table, and using a single-byte offset compression lookup table method to decode and receive codes based on the comparison table. The present application adopts bidirectional PWM communication and PWM waveform encoding, which improves the overall bus load capacity and bus distance. Digital communication based on PWM encoding can solve error problems through a verification mechanism and improve the anti-interference ability of communication.

Description

Technical Field

[0001] The present application relates to the field of fire monitoring technology, and more specifically, to a PWM-based fire power two-bus power supply and communication method and device. Background Art

[0002] In the field of fire monitoring, a two-wire system is used to connect the alarm controller to bus products such as smoke detectors and manual alarm buttons, in which the controller is the master station and the bus products such as smoke detectors are slave stations. The two wires connecting the controller and bus products such as smoke detectors are called the fire system alarm bus. The alarm bus is also called the fire second bus. When the second bus provides power for the bus products and provides master-slave communication for the bus products, it is a power second bus. The current problems with power second bus products are: on the one hand, the load capacity is poor and the communication distance is short, generally not exceeding 1 km; on the other hand, the communication anti-interference ability is poor and the communication rate is low. Generally, the effective communication baud rate does not exceed 1.2Kbps. The technical solutions based on two-bus communication in the prior art are:

[0003] (1) The Chinese invention patent with publication number CN112711215A discloses a bus terminal controller, a bus communication power supply system and a communication power supply method thereof. The external MOS tube module uses full-scale voltage transmission to modulate the control signal on the power supply cable. The microprocessor high-resolution counter modulates the duty cycle of the square wave to encode the level of a specific analog signal. The downlink data uses a voltage signal and the uplink data uses a current signal in the form of a tiny current signal return. This provides stability and anti-interference capabilities in applications with multiple points, long distances and complex wiring. The full-scale voltage transmission and current signal return method provide high communication anti-interference capabilities.

[0004] (2) The Chinese utility model patent with publication number CN206012357U discloses a battery thermal runaway detection system based on PWM communication, which sets different duty cycles according to the current battery normal state, thermal runaway alarm, start-up action execution device and other states. The fundamental frequency of PWM is set to 2.5Hz, and the duty cycles of 97.5%, 50%, and 75% are used to represent the battery normal state, thermal runaway alarm, and fire extinguisher start-up state. After the CPU core processing module determines the current warning level according to the thermal runaway model, the PWM generation circuit converts the current battery thermal runaway state into a corresponding pulse duty cycle, and after passing through the drive circuit, it is sent to the transmission line for the battery management system BMS, the vehicle control system VCU or the intelligent instrument to receive. After receiving the PWM signal, it undergoes shaping and fault-tolerant processing, measures the pulse period and width, and calculates the duty cycle, which corresponds to different thermal runaway information.

[0005] However, although the prior art uses duty cycle to express information and realizes two-bus communication of full-scale voltage transmission and current signal feedback, there is still a problem of insufficient communication rate. Summary of the invention

[0006] To solve the above problems, the technical solution adopted in this application is a PWM-based fire power two-bus power supply and communication method, comprising the following steps:

[0007] The master station sends a PWM voltage signal to the slave station as a downlink signal, and the slave station sends a PWM current signal to the master station as an uplink signal. The signal logic is represented based on the combination of PWM frequency and PWM duty cycle. The time length of the timer is defined as the unit pulse width count value according to the minimum pulse width of PWM. A comparison table containing hexadecimal numbers, binary numbers, PWM frequency, PWM duty cycle, PWM low-level pulse width count value, PWM high-level pulse width count value and PWM period value is made. A single-byte lookup table method is used to encode and send codes based on the comparison table, and a single-byte offset compression lookup table method is used to decode and receive codes based on the comparison table.

[0008] Optionally, the circuit of the master station includes: power supply from the power supply to the 24V-36V pulse switching circuit through the current protection circuit, sending data through the UART input circuit and inputting the PWM waveform encoding circuit to convert the digital signal into a PWM signal, the PWM output control circuit controls the switching state of the 0-15V pulse switching circuit and the 24V-36V pulse switching circuit according to the output of the PWM waveform encoding circuit, the current in the circuit is detected by the current sampling circuit, the detected current is improved by the differential amplifier circuit and the PWM hysteresis shaping circuit adjusts the phase of the PWM signal, and then inputs the PWM waveform decoding circuit to convert the PWM signal into a digital signal, outputs the received data through the UART output circuit, and supplies power and transmits signals through the PWM-based fire power bus 2. Before connecting to the PWM-based fire power bus 2, a capacitive absorption circuit and an electromagnetic compatibility protection circuit are provided to ensure stable operation of the circuit.

[0009] Optionally, the circuit of the slave station includes: power supply and signal transmission through the PWM-based fire power bus 2, before being connected from the PWM-based fire power bus 2, an electromagnetic compatibility and polarity protection circuit is set to protect the circuit, the level of the input signal is converted by the level conversion and PWM hysteresis circuit, the PWM signal is converted into a digital signal by the PWM waveform decoding circuit, the UART receiving circuit receives the signal for the bus product function module, and the UART sending circuit sends the bus product function module signal, the PWM waveform encoding circuit converts the digital signal into a PWM signal, a 40mA constant current source circuit provides a stable current source, and a stable low-voltage power supply is provided for the slave station circuit through a low-power linear regulator.

[0010] Optionally, the bus product functional modules include a smoke detection module, a manual fire alarm button module, a temperature detection module and a fire bus input and output interface module.

[0011] Optionally, the PWM frequencies representing the signal logic are 1.6 KHz, 2.0 KHz, 2.4 KHz, and 2.8 KHz, and the PWM duty cycles are 35%, 45%, 55%, and 65%.

[0012] Optionally, using a single-byte table lookup method to encode and send a code includes: splitting a byte of data into a high half byte and a low half byte, using the low half byte and the high half byte as a reference table lookup offset to look up a table, respectively, to obtain a count value of a PWM low-level pulse width and a high-level pulse width, and setting the single-byte hexadecimal number to be X;

[0013] S1: Mask the high nibble of X: X and the hexadecimal number 0x0F are ANDed, and the result is Y, Y=X&&0F, where Y is the low nibble data of X;

[0014] S2: Use Y as the offset to look up the table and obtain the low-level and high-level pulse width count values ​​LL and LH of the lower 4-bit PWM of the byte;

[0015] Shift X right 4 times, move the high half byte to the low half byte position, repeat the above steps S1 and S2, obtain the low and high level pulse width count values ​​HL and HH of the high 4-bit PWM of the byte, and send the PWM waveform in the order of sending the low bit first, the high bit second, and the stop bit last.

[0016] Optionally, using a single-byte offset compression table lookup method to decode and receive code includes: defining a received first offset, defining a redundant error of a PWM cycle value, comparing the values ​​of the PWM cycle value in the table to correspond to four PWM cycles of the PWM waveform and four PWM frequencies, sorting from small to large in combination with the redundant error range, and compressing the table lookup offset by dividing by 4, listing and looking up the table to determine the upper two bits of the half-byte data represented by the frequency PWM; determining the lower two bits of the half-byte data by counting the low-level pulse width of the frequency PWM in the same way; performing an OR operation on the numbers obtained from the two table lookups to obtain the half-byte logic value of the PWM;

[0017] The table lookup for the PWM low level pulse width count value is as follows:

[0018] Define the second offset received, define the redundant error, look up the 4 low-level pulse width count values ​​corresponding to the PWM frequency in the table in turn, sort the 4 duty cycles of the PWM frequency from small to large in combination with the redundant error, compress the lookup offset by dividing by 2, list and look up the table, and repeat the table lookup process for the PWM low-level pulse width count value for all PWM frequencies;

[0019] Through the above process, the upper two bits of the half-byte obtained by looking up the table and the lower two bits of the half-byte obtained by looking up the table are ORed to obtain the lower half-byte data in a byte; the same method is used to process the second PWM signal received to obtain the upper half-byte data in a byte, and finally the data of the byte is obtained through shifting and ORing.

[0020] Optionally, the power PWM bus frame format adopts a half-duplex communication mode, and one frame of data consists of three time periods: an idle domain, a downlink domain, and an uplink domain.

[0021] Optionally, during the idle domain, the power PWM bus is maintained at a high level of 24-36V by the master station to power the slave bus products. The downlink domain is sent by the master station to the slave station. The signal data is composed of a group address command byte, a frame length byte, a data byte, and a check byte, wherein the group address command byte is one byte, the upper 4 bits represent the group address, and the lower 4 bits are the command word. The uplink domain is controlled by the master station to generate 16 groups of 1ms high levels and 1.5ms low levels on the power PWM bus, wherein the 1ms high level is 24V-36V, which is used to replenish power for the slave bus products; the 1.5ms low level is 8V-15V, which is used as an uplink response mark for the slave bus products. The slave can upload data during this period.

[0022] The present application also provides a PWM-based fire power two-bus power supply and communication device, which uses any of the aforementioned PWM-based fire power two-bus power supply and communication methods for communication.

[0023] The beneficial effects of the PWM-based fire power two-bus power supply and communication method and device provided in this application are:

[0024] 1. The traditional fire protection bus data transmission is one bit at a time, the data rate is low, and there is a risk of delayed fire alarm. The power PWM bus of this application adopts bidirectional PWM communication and PWM waveform encoding, which increases the data transmission speed by 4 times and reduces the risk of delayed alarm.

[0025] 2. During the response period of the traditional fire protection bus, the transmission data needs to be replied one by one, and each bit of the reply signal consumes current, which consumes a lot of power and affects the bus load capacity and bus distance. The power PWM bus of this application uses PWM waveform encoding to reply data. One waveform represents 4 bits, which improves the efficiency by 4 times. The number of times the current is consumed during the data reply period is reduced by 4 times, so the average power consumption is reduced by four times, which improves the overall bus load capacity and bus distance.

[0026] 3. The traditional fire protection bus uses the current size to upload the signal during the bus product response period, which is an analog communication method with poor anti-interference ability. The power PWM bus of this application uses digital communication based on PWM coding for both uplink and downlink, which can solve the error problem through verification, feedback confirmation, retransmission mechanism and other means, and improve the communication anti-interference ability.

[0027] 4. This application proposes a fire-fighting power bus 2 based on PWM, which improves the load capacity and communication rate of the fire-fighting bus 2, and can increase the communication rate to 9.6Kbps; since PWM generator and PWM capture function have become the basic configuration of high-, medium- and low-end microcontrollers, the use of PWM communication will not increase additional costs; the power PWM bus uses PWM duty cycle and PWM frequency to represent digital communication logic, which can improve communication performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art.

[0029] Figure 1 It is a power PWM bus topology diagram provided in an embodiment of the present application;

[0030] Figure 2 It is the uplink and downlink signaling method provided in the embodiment of the present application;

[0031] Figure 3 It is a principle block diagram of the power PWM bus master station interface provided in the embodiment of the present application;

[0032] Figure 4 It is a principle block diagram of the power PWM bus slave interface provided in the embodiment of the present application;

[0033] Figure 5 is the duty cycle of the PWM current signal provided in the embodiment of the present application;

[0034] Figure 6 It is a PWM waveform coding diagram provided in the embodiment of the present application;

[0035] Figure 7This is a schematic diagram of single-byte transmission of a power PWM bus provided in an embodiment of the present application;

[0036] Figure 8 This is a diagram of the PWM waveform coding process using the offset table lookup method provided in the embodiment of the present application;

[0037] Fig. 9 This is a diagram of the PWM waveform decoding process using the offset compression table lookup method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] Example 1

[0040] Power PWM (Pulse Width Modulation, hereinafter referred to as PWM) bus protocol physical layer:

[0041] The transmission medium is copper twisted pair with a diameter of 1.0 mm² or more.

[0042] Topology diagram Figure 1-Figure 2 As shown:

[0043] like Figure 1 As shown, the fire protection power bus 2 based on PWM mode has improved the load capacity of the fire protection bus 2, and at the same time has greatly improved the communication rate, which can increase the communication rate to 9.6Kbps. This application refers to this bus mode as power PWM bus, referred to as P2B (POWER PWM BUS, abbreviated as PPB, written as P2B, read as P2B). The controller is the power PWM bus master station, and the bus product is the power PWM bus slave station.

[0044] The signal sent from the master to the slave is defined as downlink, and the signal sent from the slave to the master is defined as uplink. The master and slave stations, as well as the slave bus products, are connected with twisted pair cables.

[0045] like Figure 2 As shown, the PWM signal of the power PWM bus downstream is a voltage signal, the high level is 24-36V (corresponding to the idle level), and the low level is 8-15V. The PWM signal of the power PWM bus upstream is a current signal, the high level is 35-55mA, and the low level is 0-10mA (idle value).

[0046] The reason why the uplink signal of the power PWM bus uses a current signal is that the slave products of the power PWM bus have no power supply capability and can only receive power, or in other words, can only consume power. Therefore, a customizable power consumption state is used to represent the uplink information, that is, the uplink signal is represented by a current pulse. Since most interference signals are expressed in the form of voltage, it is difficult to form milliampere interference current, so using current as the uplink signal has the advantage of strong anti-interference ability.

[0047] like Figure 3 As shown, the power PWM bus master circuit consists of an overcurrent protection circuit, a 24-36V pulse switching circuit, a 0-15V pulse switching circuit, a UART (Universal Asynchronous Receiver / Transmitter, hereinafter referred to as UART) input / output circuit, a PWM waveform encoding / decoding circuit, a PWM output control circuit, a line capacitive absorption circuit, an EMC (Electromagnetic Compatibility, hereinafter referred to as EMC) protection circuit, a current sampling circuit, a differential amplifier circuit, and a PWM hysteresis shaping circuit.

[0048] The power supply is supplied to the 24V-36V pulse switch circuit through the current protection circuit, and the sending data is input into the PWM waveform encoding circuit through the UART input circuit to convert the digital signal into a PWM signal. The PWM output control circuit controls the switching state of the 0-15V pulse switch circuit and the 24V-36V pulse switch circuit according to the output of the PWM waveform encoding circuit. The current in the circuit is detected by the current sampling circuit. The detected current is input into the PWM waveform decoding circuit to convert the PWM signal into a digital signal after the differential amplifier circuit improves the signal resolution and the PWM hysteresis shaping circuit adjusts the phase of the PWM signal. The received data is output through the UART output circuit, and the power supply and signal transmission are carried out through the PWM-based fire power bus 2. Before connecting to the PWM-based fire power bus 2, a capacitive absorption circuit and an electromagnetic compatibility protection circuit are provided to ensure the stable operation of the circuit.

[0049] like Figure 4 As shown in the figure, the power PWM bus slave circuit consists of EMC and polarity protection circuit, level conversion and PWM hysteresis circuit, 40mA constant current source circuit, PWM waveform encoding / decoding circuit, UART receiving / transmitting circuit, bus product functional module circuit, low power consumption LDO (Low Dropout Regulator, low voltage difference linear regulator, hereinafter referred to as LDO), etc. The bus product functional module is a specific functional module, such as the smoke detection module for smoke detection, the manual fire alarm button module, the temperature detection module, the fire bus input and output interface module, etc.

[0050] Power supply and signal transmission are carried out through the PWM-based fire power bus 2. Before being connected from the PWM-based fire power bus 2, an electromagnetic compatibility and polarity protection circuit is set to protect the circuit. The level of the input signal is converted by the level conversion and PWM hysteresis circuit, and the PWM waveform decoding circuit converts the PWM signal into a digital signal. The UART receiving circuit receives the signal for the bus product function module, and the UART sending circuit sends the bus product function module signal. The PWM waveform encoding circuit converts the digital signal into a PWM signal. The 40mA constant current source circuit provides a stable current source, and a stable low-voltage power supply is provided for the slave circuit through a low-power linear regulator.

[0051] Logic definition and PWM waveform encoding:

[0052] like Figure 5 As shown in the figure, the high level of the signal here uses the voltage amplitude to represent the high and low levels in the downstream signal, while the current size is used to represent the high and low levels in the upstream signal. Different from the common logic representation method, the signal logic 1 or 0 is not represented by the level, but the duty cycle in the PWM signal waveform is used to represent the logic 0 or logic 1, with the occupied position on the right and the empty position on the left.

[0053] In order to increase the signal transmission rate, a combination of multiple PWM frequencies and multiple PWM duty cycles is used to represent the signal logic. In this way, a PWM signal cycle waveform does not represent a logic, but a logic group. As shown in Table 1, a PWM cycle waveform represents 4-bit logic.

[0054] Table 1 Half-byte PWM encoding method

[0055]

[0056] Table 1 and Figure 6 What is represented is the PWM with frequencies of 1.6KHz, 2.0KHz, 2.4KHz, and 2.8KHz and duty cycles of 35%, 45%, 55%, and 65% respectively, representing the logics 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, a total of 16 logics.

[0057] The PWM is 1.6KHz-2.8KHz and 35%-65% duty cycle because the PWM signal in this range can avoid the large loss of too narrow pulses on the power PWM bus, so as to ensure better signal quality on the 1km twisted pair cable commonly used in the fire protection field.

[0058] Power PWM bus single-byte signal transmission method:

[0059] Because of the Figure 6 PWM waveform encoding, to transmit one byte (8bit) of data, only Figure 6 The two waveforms of the PWM bus are used, so the baud rate is increased by 4 times compared to the traditional single-bit transmission of 8 waveforms per byte. In the uplink signal, taking uploading one byte of data as an example, only two current signals are needed to reply instead of 8 current signals, so the power consumption of bus products on the power PWM bus is also greatly reduced, which is conducive to improving the bus load capacity.

[0060] The following randomly selects the downlink hexadecimal number 3A (binary 0011 1010) and the uplink signal hexadecimal number 91 (1001 0001) as an example to further illustrate the power PWM bus signal transmission method.

[0061] Since the idle voltage of the power PWM bus is a high level in the power supply state, it is defined Figure 7 The stop bit and start bit shown in the figure can be represented by the falling edge of the first PWM empty bit of each byte; similarly, since the idle current of the power PWM bus is 0-10mA, the Figure 7 The start bit shown can be used for byte synchronization. The stop bit of each byte in the downstream can be represented by the falling edge of the current at the end of the last PWM waveform.

[0062] The pulse width of the start bit and stop bit is preferably defined as 0.1-1ms.

[0063] Power PWM bus baud rate and minimum pulse width calculation:

[0064] From Table 1 and Figure 6 It can be seen that through PWM waveform encoding, it is usually necessary to send 4 logic 1 or logic 0. The present application realizes replacing this process with a PWM waveform, thereby increasing the bus transmission rate. Compared with one waveform per bit, the baud rate is increased by nearly 4 times. Calculated according to the average PWM frequency of 2.4KHz in the table:

[0065] 2.4KHz×4=9.6KHz;

[0066] This allows baud rate transmission close to 9.6K.

[0067] 1) Minimum pulse width calculation

[0068] Signal period T=1 / F, F is PWM frequency

[0069] Figure 6 The highest PWM frequency is 2.8KHz, and the minimum duty cycle is 35%.

[0070] Then the minimum pulse width = (1 / 2.8KHz) × 0.35 = 0.125ms;

[0071] Usually, the pulse width signal that can be transmitted on a twisted pair cable of no less than 1mm² and 1km in length is no less than 0.1ms, so a pulse width of 0.125ms can ensure the communication quality.

[0072] 2) Calculation of minimum pulse width resolution

[0073] The minimum pulse width is 0.125ms=125us;

[0074] The second smallest pulse width = (1 / 2.8KHz) × 0.45 = 0.161ms = 161us;

[0075] The minimum resolution width of pulse width = 161us-125us = 36us;

[0076] Therefore, the PWM generation and capture defined by the power PWM bus can be realized by using a timer no longer than 18us.

[0077] The clock frequency corresponding to 18us is:

[0078] F=1 / (18us×2)=0.028MHz=28KHz;

[0079] Therefore, a CPU system clock of 500KHz or above will suffice.

[0080] Table lookup method to realize byte sending and receiving:

[0081] According to the calculation of the power PWM bus baud rate and the minimum pulse width, the minimum pulse width of the power PWM bus is 125us.

[0082] The timer for PWM and pulse width capture is set to 5us, and t=5us is defined.

[0083] The PWM occupied (corresponding waveform is high level) and empty (corresponding waveform is low level) pulse widths at different frequencies used by the power PWM bus are shown in Table 2, where H is the high level pulse width count value and L is the low level pulse width count value.

[0084] T=H+L is the PWM cycle value.

[0085] The stop bit Stop and start bit Start are defined as 250us, and the count value of the 5us timer is 250 / 5=50.

[0086] Table 2 Hexadecimal 0-F PWM low level L and high level H pulse width count value in units of 5us

[0087]

[0088] Calculation example of Table 2:

[0089] Taking the hexadecimal number 1 as an example, the PWM frequency f=1.6kHz;

[0090] Then the PWM period is 1 / f=1 / 1.6k=0.625ms=625us;

[0091] H=(625us×0.45) / 5us=56.25=56;

[0092] L=[625us×(1-0.45)] / 5us=68.75=69;

[0093] T=H+L=56+69=125.

[0094] Single-byte lookup table encoding method:

[0095] like Figure 8 As shown, one byte of data is split into an upper nibble and a lower nibble.

[0096] The low half byte and the high half byte are used as the table lookup offset to respectively look up the table to obtain the PWM low level pulse width and the high level count value.

[0097] Let this single-byte hexadecimal number be X.

[0098] a) First, mask the high nibble of X: X and the hexadecimal number 0x0F are ANDed, and the result is Y; Y = X&&0F, then Y is the low nibble of X.

[0099] b) Then use Y as the offset to look up the tables of TAB271L and TAB271H respectively to obtain the low-level and high-level pulse width count values ​​LL and LH of the lower 4-bit PWM of the byte.

[0100] According to the offset and Table 2, we can get Table 3:

[0101] Table 3 Comparison table of offset Y pulse width count values

[0102]

[0103] Next, shift X right 4 times, move the high half byte to the low half byte position, repeat the above steps a) and b) to obtain the low level and high level pulse width count values ​​HL and HH of the high 4-bit PWM of the byte.

[0104] For example, assuming X=0x3A, the offset of the lower nibble is Y=0x0A, and the table TAB271L gives LL=38, and the table TAB271H gives LH=46; the offset of the upper nibble is Y=0x03, and the table TAB271L gives HL=44, and the table TAB271H gives HH=81;

[0105] Then the PWM waveform is sent in the traditional order of sending the low bit first, the high bit second, and the stop bit last:

[0106] Define the PWM output terminal as PO and execute in the following order:

[0107] P0 is set to 1 (high level idle), 5us timer is started, counter sends LL, P0 is set to 0, counter counts down to 0, counter sends LH, P0 is set to 1, counter counts down to 0, counter sends HL, P0 is set to 0, counter counts down to 0, counter sends HH, P0 is set to 1, counter counts down to 0, counter sends STOP, P0 is set to 0, counter counts down to 0, P0 is set to 1 and ends.

[0108] 2) Single-byte offset compression table lookup method decoding and receiving method

[0109] First, according to Table 2, the following definitions are made:

[0110] Define the first offset received as Y1, define the allowable redundant error of T as ±5, and the values ​​of T in Table 2 are 125, 100, 84, and 71, corresponding to the four PWM cycles of the PWM waveform and the four PWM frequencies. In order to reduce the number of list elements and combine the allowable error redundant range, sort them from small to large, and use the method of dividing by 4 to compress the table lookup offset.

[0111] Take Y1=T / 4, perform table lookup offset compression, divide T=71, 84, 100, 125 by 4 respectively and express them as hexadecimal numbers 11, 15, 19, 1F, that is, the center offset of Y1 is hexadecimal 11, 15, 19, 1F. The list is shown in Table 4:

[0112] Table 4 Offset Y1 comparison table

[0113]

[0114] In the table, FF in TAB271R is an invalid data mark, which is used to indicate that the PWM pulse width count value deviation is too large, and communication error processing can be performed. The 0C, 08, 04, and 00 correspond to the four frequencies of PWM, respectively, thus determining the upper two bits of the half-byte data represented by the frequency PWM.

[0115] Next, the lower two bits of the half-byte data are determined by counting the low-level pulse width of the frequency PWM in the same way as above. Through the TAB271R table lookup, when 0C is found, the next table is looked up in TAB271R4, when 08 is found, the next table is looked up in TAB271R3, when 04 is found, the next table is looked up in TAB271R2, and when 00 is found, the next table is looked up in TAB271R1. The numbers obtained from these two table lookups are ORed to obtain the half-byte logic value of the PWM.

[0116] The table lookup for the PWM low level pulse width count value is as follows:

[0117] Define the second offset received as Y2, define the allowable redundancy error as ±3, and the four L values ​​corresponding to the 1.6kHz PWM in Table 2 are 81, 69, 56, and 44, corresponding to the four duty cycles of the frequency PWM. In order to reduce the number of list elements and combine the allowable error redundancy range, sort them from small to large, and use the method of dividing by 2 to compress the table lookup offset.

[0118] Take Y2=L / 2, perform table lookup offset compression, divide L=44, 56, 69, 81 by 2 and express them as hexadecimal numbers 16, 1C, 22, 28, that is, the center offset of Y2 is hexadecimal 16, 1C, 22, 28. The list is shown in Table 5:

[0119] Table 5 Offset Y2 comparison table

[0120]

[0121] The same method is used to define the four L values ​​corresponding to the 2.0kHz PWM in Table 2, taking Y3=L / 2, and dividing L=35, 45, 55, and 65 by 2 respectively and expressing them as hexadecimal numbers 11, 16, 1B, and 20, that is, the center offset of Y3 is hexadecimal 11, 16, 1B, and 20. The list is shown in Table 6:

[0122] Table 6 Offset Y3 comparison table

[0123]

[0124] The same method is used to define the four L values ​​corresponding to the 2.4kHz PWM in Table 2, taking Y4=L / 2, and dividing L=30, 38, 46, 54 by 2 and expressing them as hexadecimal numbers 0F, 13, 17, 1B, that is, the center offset of Y4 is hexadecimal 0F, 13, 17, 1B. The list is shown in Table 7:

[0125] Table 7 Offset Y4 comparison table

[0126]

[0127] The same method is used to define the four L values ​​corresponding to the 2.8kHz PWM in Table 2, taking Y5=L / 2, and dividing L=25, 32, 39, 46 by 2 and expressing them as hexadecimal numbers 0C, 10, 13, 17, that is, the center offset of Y5 is hexadecimal 0C, 10, 13, 17. The list is shown in Table 8:

[0128] Table 8 Offset Y5 comparison table

[0129]

[0130] Through the above process, the upper two bits (bit3, bit2) of the half byte obtained by looking up the table TAB271R and the lower two bits (bit1, bit0) of the half byte obtained by looking up the table TAB271R1-4 are ORed to obtain the lower half byte data in a byte; the same method is used to process the second PWM signal received to obtain the upper half byte data in a byte, and finally the data of the byte is obtained through shifting and ORing.

[0131] The complete process is as follows:

[0132] Define the PWM input terminal as Pi and execute in the following order:

[0133] For master station reception, the start bit waveform is received first, and then the 1-byte data PWM waveform is received; for slave station reception, the 1-byte data PWM waveform is received first, and then the stop bit waveform is received. Taking the master station reception as an example, the start bit is removed for the slave station reception.

[0134] The following process is carried out in sequence: Pi receives a rising edge, starts the timer, receives a falling edge and saves the count value as St, the counter is cleared and counts the PWM low level, receives the rising edge of Pi and saves the count value to LL, the counter is cleared and counts the PWM high level, receives the falling edge of Pi and saves the count value to LH, the counter is cleared and counts the PWM low level, receives the rising edge of Pi and saves the count value to HL, the counter is cleared and counts the PWM high level, receives the falling edge of Pi and saves the count value to HH, and the counting of 4 pulse widths of one byte and 2 PWM signals is completed.

[0135] The complete offset compression table lookup method PWM waveform decoding process is as follows Fig. 9 As shown:

[0136] Power PWM bus frame format

[0137] As shown in Table 9, half-duplex communication is adopted, and a frame of data consists of three time periods: idle domain, downlink domain, and uplink domain.

[0138] During the idle domain, the power PWM bus is always maintained at a high level of 24-36V by the master station to power the slave bus products.

[0139] The downlink domain sends signal data from the master station to the slave station, which consists of a group address command byte, a frame length byte, a data byte, and a check byte. The group address command byte is one byte, the upper 4 bits represent the group address, and the lower 4 bits are the command word. The command and data definitions are detailed in Table 10, the status value definitions are shown in Table A, the data definitions are shown in Table B, and the bus product type value definitions are detailed in Table C. The upper 4 bits of the group address correspond to the upper 4 bits of the slave bus product address. Each power PWM bus can carry up to 254 slave bus products.

[0140] The upstream domain is controlled by the master station to generate 16 groups of 1ms high level + 1.5ms low level on the power PWM bus. The 1ms high level is 24V-36V, which is used to supplement the power of the slave bus products; the 1.5ms low level is 8V-15V, which is used as the upstream response mark of the slave bus products. The slave can upload data during this period. Only when the high address of the bus product is equal to the downstream group address can it respond upstream, otherwise it will wait for the next frame.

[0141] The 16 low-level response tags in the upstream domain of groups 1-16 are arranged in sequence from first to last. Only when the lower 4-bit address of the slave bus product is the same as the sequence, can the upstream response data be sent during the low-level period of the sequence.

[0142] Table 9 Power PWM bus frame format

[0143]

[0144] Table 10 Command and data definition table

[0145]

[0146] Table A Status value definition table

[0147]

[0148] Table B Data definition table

[0149]

[0150] Table C Bus product type value definition table

[0151]

[0152] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A fire power two-bus power supply and communication method based on PWM, characterized in that: The following steps are involved: The master station sends a PWM voltage signal to the slave station as a downlink signal, and the slave station sends a PWM current signal to the master station as an uplink signal. Based on the combination of PWM frequency and PWM duty cycle, the signal logic is represented. The time length of the timer is defined as the unit pulse width count value according to the minimum pulse width of PWM. A comparison table containing hexadecimal numbers, binary numbers, PWM frequency, PWM duty cycle, PWM low-level pulse width count value, PWM high-level pulse width count value and PWM cycle value is prepared. A single-byte table lookup method is used to encode and send codes based on the comparison table, and a single-byte offset compression table lookup method is used to decode and receive codes based on the comparison table. The method of using a single-byte offset compression table lookup method to decode and receive codes includes: defining a received first offset, defining a redundant error of a PWM cycle value, wherein the values ​​of the PWM cycle values ​​in the comparison table correspond to four PWM cycles of a PWM waveform and four PWM frequencies, respectively, and are sorted from small to large in combination with a redundant error range, and the table lookup offset is compressed by a division by 4 method, and a table is listed and looked up to determine the upper two bits of the half-byte data represented by the frequency PWM; the lower two bits of the half-byte data are determined by counting the low-level pulse width of the frequency PWM in the same way; and the numbers obtained from the two table lookups are ORed to obtain the half-byte logic value of the PWM; The table lookup for the PWM low level pulse width count value is as follows: Define the second offset received, define the redundant error, look up the 4 low-level pulse width count values ​​corresponding to the PWM frequency in the table in turn, sort the 4 duty cycles of the PWM frequency from small to large in combination with the redundant error, compress the lookup offset by dividing by 2, list and look up the table, and repeat the table lookup process for the PWM low-level pulse width count value for all PWM frequencies; Through the above process, the upper two bits of the half-byte obtained by looking up the table and the lower two bits of the half-byte obtained by looking up the table are ORed to obtain the lower half-byte data in a byte; the same method is used to process the second PWM signal received to obtain the upper half-byte data in a byte, and finally the data of the byte is obtained through shifting and ORing.

2. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 1, characterized in that: The circuit of the master station includes: power supply from the power supply to the 24V-36V pulse switch circuit through the current protection circuit, sending data through the UART input circuit and inputting the PWM waveform encoding circuit to convert the digital signal into a PWM signal, the PWM output control circuit controls the switching state of the 0-15V pulse switch circuit and the 24V-36V pulse switch circuit according to the output of the PWM waveform encoding circuit, the current in the circuit is detected by the current sampling circuit, the detected current is input into the PWM waveform decoding circuit to convert the PWM signal into a digital signal after the differential amplifier circuit improves the signal resolution and the PWM hysteresis shaping circuit adjusts the phase of the PWM signal, and the received data is output through the UART output circuit, and power supply and signal transmission are carried out through the PWM-based fire power bus II. Before connecting to the PWM-based fire power bus II, a capacitive absorption circuit and an electromagnetic compatibility protection circuit are provided to ensure stable operation of the circuit.

3. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 1, characterized in that: The circuit of the slave station includes: power supply and signal transmission through a PWM-based fire power bus 2, before being connected from the PWM-based fire power bus 2, an electromagnetic compatibility and polarity protection circuit is provided to protect the circuit, the level of the input signal is converted by a level conversion and PWM hysteresis circuit, the PWM signal is converted into a digital signal by a PWM waveform decoding circuit, the UART receiving circuit receives the signal for the bus product function module, and the UART sending circuit sends the bus product function module signal, the PWM waveform encoding circuit converts the digital signal into a PWM signal, a 40mA constant current source circuit provides a stable current source, and a stable low-voltage power supply is provided for the slave station circuit through a low-power linear regulator.

4. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 3, characterized in that: The bus product functional modules include a smoke detection module, a manual fire alarm button module, a temperature detection module and a fire bus input and output interface module.

5. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 1, characterized in that: The PWM frequencies representing the signal logic are 1.6KHz, 2.0KHz, 2.4KHz, and 2.8KHz, and the PWM duty ratios are 35%, 45%, 55%, and 65%.

6. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 5, characterized in that: The encoding and sending of the code by using the single-byte table lookup method includes: splitting a byte of data into a high half byte and a low half byte, using the low half byte and the high half byte as the lookup table offset of the comparison table to look up the table, obtaining the count value of the PWM low-level pulse width and the high-level pulse width, and setting the single-byte hexadecimal number as X; S1: Mask the high nibble of X: X and the hexadecimal number 0x0F are ANDed, and the result is Y, Y=X && 0F, where Y is the low nibble data of X; S2: Use Y as the offset to look up the table and obtain the low-level and high-level pulse width count values ​​LL and LH of the lower 4-bit PWM of the byte; Shift X right 4 times, move the high half byte to the low half byte position, repeat the above steps S1 and S2, obtain the low and high level pulse width count values ​​HL and HH of the high 4-bit PWM of the byte, and send the PWM waveform in the order of sending the low bit first, the high bit second, and the stop bit last.

7. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 1, characterized in that: The power PWM bus frame format adopts half-duplex communication mode. One frame of data consists of three time periods: idle domain, downlink domain and uplink domain.

8. The PWM-based fire-fighting power two-bus power supply and communication method according to claim 7, characterized in that: During the idle domain, the power PWM bus is maintained at a high level of 24-36V by the master station, which is used to power the slave bus products. The downlink domain is sent by the master station to the slave station. The signal data consists of a group address command byte, a frame length byte, a data byte, and a check byte. The group address command byte is one byte, the upper 4 bits represent the group address, and the lower 4 bits are the command word. The uplink domain is controlled by the master station to generate 16 groups of 1ms high level and 1.5ms low level on the power PWM bus, of which the 1ms high level is 24V-36V, which is used to supplement the power of the slave bus products. The 1.5ms low level is 8V-15V, which is used as the uplink response mark of the slave bus product. The slave can upload data during this period.

9. A PWM-based fire-fighting power two-bus power supply and communication device, characterized in that: The communication is carried out by using the PWM-based fire power two-bus power supply and communication method as described in any one of claims 1 to 8.

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