FPGA-based Ethernet message acquisition device and implementation method
By designing an Ethernet message collection device based on FPGA, the problem of difficulty in positioning bus communication faults in industrial environments is solved, and data is quickly collected and analyzed, fault locations are efficiently located, shortening resolution time and reducing maintenance costs.
Patent Information
- Application Number
- CN202411516707.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-18
Smart Images
Figure CN119484192A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of bus control, in particular to an Ethernet message collection device based on FPGA and an implementation method thereof. Background Art
[0002] Manufacturing is the foundation of national production, and the "industrial mother machine" - machine tools have become the foundation of the foundation. The "brain" of the machine tool is the CNC system, and the servo drive, MCP, IO, etc. are its "limbs" and "sensory system". The communication between these "organs" is carried out through the field industrial bus. NCUC, as an excellent domestic field industrial bus, must be mentioned. It provides customers with many industrial communication and industrial control solutions, and has been tested in the market for decades.
[0003] However, even the most excellent bus will inevitably encounter problems in the actual industrial environment, because in the actual industrial environment, there is a lot of external interference, and many factors may affect the on-site industrial bus communication, resulting in data damage or loss during the communication process. When such a problem occurs, the message collection device becomes extremely important. Summary of the invention
[0004] The purpose of the present invention is to provide an Ethernet message collection device and implementation method based on FPGA, which is used to collect process data when multiple Ethernet or NCUC devices have communication failures, and efficiently locate the failure by analyzing the process data, thereby shortening the time to solve the problem on site. The specific technical solution is as follows:
[0005] An Ethernet message collection device based on FPGA, comprising a message collection module and a standard Ethernet interface and an NCUC interface connected to the message collection module, wherein the NCUC interface is connected to an Ethernet device through an NCUC to network port data cable or is connected to an NCUC slave station through an NCUC data cable, and the standard Ethernet interface is connected to a host computer through a network cable;
[0006] The NCUC interface is used to receive and transmit the Ethernet data frame of the Ethernet device or the NCUC data frame of the NCUC slave station;
[0007] The message collection module is used to process the received Ethernet data frame or NCUC data frame and send it to the standard Ethernet interface;
[0008] The standard Ethernet interface is used to output the Ethernet data frames or NCUC data frames collected by the message collection module to the host computer.
[0009] Furthermore, the message collection module may adopt an FPGA chip, and the FPGA chip is connected to the standard Ethernet interface and the NCUC interface respectively through a PHY chip. The collection device also includes a DCDC power chip, and the FPGA chip is connected to the power interface through the DCDC power chip.
[0010] Furthermore, the NCUC interface includes an NCUC input interface and an NCUC output interface. When the NCUC interface communicates with the NCUC slave station, both NCUC interfaces can be used as input and output. When one of the NCUC interfaces is used as the NCUC input interface, the other interface is used as the NCUC output interface.
[0011] Furthermore, the FPGA chip includes a transparent transmission module, which is connected between the NCUC input interface and the NCUC output interface, and is used to transmit data frames between the NCUC input interface and the NCUC output interface and perform reception effective signal processing on the data frames.
[0012] Furthermore, the FPGA chip also includes a FIFO module, which includes a first FIFO module and a second FIFO module. The input ends of the first FIFO module and the second FIFO module are respectively connected to the NCUC input interface and the NCUC output interface. The first FIFO module and the second FIFO module are used to cache Ethernet data frames or NCUC data frames received by the corresponding NCUC interface, and add FCS to data frames that need to add FCS.
[0013] Further, the FPGA chip also includes a CRC module and a cache register group, the CRC module includes a first CRC module and a second CRC module, the input end of the first CRC module is connected to the output ends of the first FIFO module and the second FIFO module, the output end of the first CRC module is connected to the input end of the second CRC module and the cache register group, the output end of the second CRC module is connected to the cache register group, and the output end of the cache register group is connected to the standard Ethernet interface;
[0014] The first CRC module is used to perform CRC calculation on the received Ethernet data frame or NCUC data frame, and directly send the data to the cache register if the CRC is correct, and send the data to the second CRC module if the CRC is wrong;
[0015] The second CRC module is used to perform CRC calculation on the transmitted data, append it to the end of the data, and then send it to the buffer register group;
[0016] The buffer register group includes a plurality of buffer registers, and the buffer registers are used to filter out the leading code and the frame delimiter and to supplement the data of the subsequent data frame with the number of bytes less than 64 to 64 bytes.
[0017] The present invention also provides an FPGA-based Ethernet message collection implementation method, using the above FPGA-based Ethernet message collection device, comprising the following steps:
[0018] S1, NCUC interface receives standard Ethernet data frame or NCUC data frame;
[0019] S2, the received data is written into the corresponding FIFO module;
[0020] S3, select the FIFO module to send data to send data;
[0021] S4, data is sent to the CRC module for CRC calculation;
[0022] S5. Read the data into the cache register and then transmit it to the host computer through the standard Ethernet interface.
[0023] Furthermore, the step S2 specifically includes: splicing the data received after the frame delimiter into an 8-bit data and splicing it with the received valid signal into a 9-bit data, and writing them into the FIFO module together;
[0024] When the receive valid signal is invalid, it enters the completion state and writes a 9-bit 0 to the FIFO module;
[0025] When the receive valid signal is valid and the FIFO module is full, if a frame of data is truncated at this time, it is necessary to wait for the entire frame of data of the truncated data frame to be sent out, otherwise the truncated data frame in the FIFO module and part of the next frame of data will be pieced together into one frame of data, causing data confusion.
[0026] Furthermore, the step S3 specifically includes: firstly determining whether there is data in the first FIFO module and the second FIFO module; if there is data in the first FIFO module and there is no data in the second FIFO module, then selecting the FIFO module for sending data as the first FIFO module; if there is data in the second FIFO module and there is no data in the first FIFO module, then selecting the FIFO module for sending data as the second FIFO module; if there is data in both the first FIFO module and the second FIFO module, then giving priority to sending the data in the first FIFO module.
[0027] Furthermore, the step S5 specifically includes:
[0028] When all high bits of the buffer register are 1, it means that the data has entered the valid data stage, and the data can be sent according to the buffer register pipeline. If the FIFO module is empty, it is considered that a frame of data has been sent.
[0029] When the high bit of the first buffer register is 0, the message length is determined. If the frame length is less than 64 bytes, padding is performed. At this time, the first buffer register is used as input until the message length is greater than 64 bytes, and the FCS is recalculated.
[0030] When the high bit of the second buffer register is 0 and the data length meets the requirements, check whether the FCS is correct. If it is correct, select the second buffer register as input and upload the data to the host computer directly through the standard Ethernet interface without any modification. If the FCS is incorrect, calculate the correct FCS, append it to the original frame, add the recalculated FCS, and wait for R0 to R3 to be sent.
[0031] The present invention provides an FPGA-based Ethernet message collection device and implementation method, which has the following beneficial effects:
[0032] 1. The present invention provides an FPGA-based Ethernet message collection device, which is small and light in appearance and easy to carry. It can not only collect standard Ethernet data frames and NCUC data frames, but also collect Ethernet data frames with FCS errors. At the same time, the collected messages can be viewed with the help of wireshark software, which provides great convenience in analyzing standard Ethernet or NCUC communication process data.
[0033] 2. The present invention provides an FPGA-based Ethernet message collection device and implementation method. When the device is applied to the NCUC link, the Lua plug-in is loaded using the host computer software wireshark to parse the collected NCUC data frame and analyze the process data. When multiple Ethernet devices or NCUC devices communicate and encounter communication failures, the device can be used to collect process data. By analyzing the process data, the fault can be further efficiently located, thereby shortening the time to solve on-site problems and reducing the subsequent maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 It is a schematic diagram of an Ethernet message collection device based on FPGA provided by the present invention;
[0035] Figure 2 It is a connection diagram of an Ethernet message collection device based on FPGA provided by the present invention;
[0036] Figure 3The present invention provides a schematic diagram of the working principle of an Ethernet message collection device based on FPGA. DETAILED DESCRIPTION
[0037] The following will be combined with the accompanying drawings provided by the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. According to the following description, the advantages and features of the present invention will be more clear. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0038] In the description of the present invention, unless otherwise clearly stipulated and limited, the terms "connection" and "connected" should be interpreted in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0039] In the description of the present invention, terms such as "up", "down", "left", "right", "front", "back", "center", "horizontal", "vertical", "top", "bottom", "inside" and "outside" and other orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings and are only for the convenience of description and simplification of operation, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.
[0040] Example 1
[0041] This embodiment provides an Ethernet message collection device based on FPGA, see Figure 1 As shown, the device includes a standard Ethernet interface, a message collection module and two NCUC interfaces, and the standard Ethernet interface and the NCUC interface are both connected to the message collection module. The standard Ethernet interface is connected to the host computer through a network cable, and the NCUC interface is connected to the Ethernet device through the NCUC to network port data cable or to the NCUC slave station device through the NCUC data cable to form a loop for communication. The NCUC interface is used to receive and transmit Ethernet data frames of Ethernet devices or NCUC data frames of NCUC slave stations; the message collection module is used to process the received standard Ethernet data frames or NCUC data frames and output them through the standard Ethernet interface; the standard Ethernet interface is used to output the standard Ethernet frames or NCUC data frames collected by the message collection module to the host computer.
[0042] When the NCUC interface communicates with the NCUC slave station, there is no difference between the two NCUC interfaces, and both can be used as input interfaces or output interfaces. When one of the NCUC interfaces is used as the NCUC input interface, the other interface needs to be used as the NCUC output interface. The NCUC input interface is used to forward the messages received from the NCUC slave station to the message collection module and the NCUC output interface, and the NCUC output interface is used to output the messages received by the NCUC input interface to the next-level NCUC slave station.
[0043] See also Figure 2 As shown, it is an internal circuit connection diagram of an Ethernet message collection device based on FPGA provided by this embodiment. The message collection module can be realized by FPGA chip. The FPGA chip is connected to the power interface through DC-DC power chip. The power interface inputs the required voltage and outputs the voltage value required by the FPGA chip through the DC-DC power chip. The standard Ethernet interface and two NCUC interfaces are connected to the FPGA chip through the PHY chip. The PHY chip and the FPGA chip are connected by RMII. The clock source of the PHY chip is provided by the FPGA chip. The clock source of the FPGA chip is provided by an external crystal oscillator, which is used to realize the collection of standard Ethernet data frames and NCUC data frames.
[0044] See also Figure 3 As shown, it is a specific implementation of a message collection module in an FPGA-based Ethernet message collection device provided by this embodiment. The message collection module includes a transparent transmission module, a FIFO module, a CRC (cyclic redundancy check) module and a cache register group. The FIFO module includes a first FIFO module and a second FIFO module, and the CRC module includes a first CRC module and a second CRC module. The transparent transmission module is connected between the NCUC input interface and the NCUC output interface, and the input ends of the first FIFO module and the second FIFO module are respectively connected to two NCUC interfaces. At the same time, the output ends of the first FIFO module and the second FIFO module are both connected to the first CRC module, the output end of the first CRC module is connected to the second CRC module, the output end of the second CRC module is connected to the cache register group, and the output end of the cache register group is connected to the standard Ethernet interface.
[0045] Specifically, the transparent transmission module is used to transmit data frames between the NCUC input interface and the NCUC output interface and perform reception valid signal processing on the data frames. The reception valid signal processing is processing the tail of the reception valid signal and processing the 00 before the leading code 01.
[0046] Specifically, the first FIFO module and the second FIFO module are used to cache the standard Ethernet data frames or NCUC data frames received by the corresponding NCUC interfaces to prevent data loss when the two NCUC interfaces receive data at the same time, and to facilitate the addition of FCS to the data frames that need to add FCS and then output to the host computer through the standard Ethernet interface. When the first FIFO module and the second FIFO module receive data at the same time, the first FIFO module and the second FIFO module will not output data at the same time, and will first cache the data of the second FIFO module, give priority to outputting the data in the first FIFO module, and then output the data in the second FIFO module, and the data of the two modules are output alternately.
[0047] Specifically, the first CRC module and the second CRC module are mainly used to detect or verify errors that may occur after data transmission or storage. The first CRC module is used to perform CRC calculation on the received Ethernet data frame or NCUC data frame. If the CRC is correct, the data is directly output to the cache register group. If the CRC is wrong, the data is output to the second CRC module; the second CRC module is also used to perform CRC calculation on the data, such as: data frames that require byte filling and CRC errors, and append them to the end of the data.
[0048] CRC (Cyclic Redundancy Check) is a data transmission error detection technology. The sender calculates the check code according to a certain algorithm, and attaches the check code to the end of the data frame and sends it to the receiver. The receiver verifies the received data and the check code according to the same algorithm to determine whether the received data is correct and complete. In the standard Ethernet frame format, there are 4 bytes of redundant bits at the end to store the CRC check value. This redundant bit is often called the frame check sequence FCS (frame check sequence). FCS is a type of CRC check code. FCS calculates a fixed-length check code at the end of the data frame. The receiver uses the same CRC algorithm to perform the same calculation on the received data. If the results of the two are consistent, it means that there is no error in the data transmission process. If they do not match, it means that there may be a bit error. At this time, the receiver will discard the erroneous frame and try to retransmit it.
[0049] Specifically, the cache register group includes multiple cache registers, which are used to filter out the preamble and frame delimiter, and to supplement the data to 64 bytes for subsequent data frames with less than 64 bytes; in an implementation process, the cache register group includes cache registers R0, R1, R2, and R3 in sequence, and the cache registers are all 9-bit wide registers, and there are three levels of pipeline from R0 to R3. The information received by the high bit of the cache register is a valid reception signal. When all the high bits of R3 to R0 are 1, it means that the data has entered the valid data stage, and the data can be started to be sent. The data is sent to the host computer through the standard Ethernet interface.
[0050] Finally, the host computer will compile the message collection module logic code in the TD software to generate a bit file, and convert the bit file into an FPGA solidifiable file, and then burn it into the FPGA plug-in Flash through a dedicated downloader. The Lua plug-in of the host computer is developed using the Lua language. When the device is applied to the NCUC link, the host computer software wireshark loads the Lua plug-in, and the NCUC message can be parsed during the message collection process.
[0051] Example 2
[0052] This embodiment provides an Ethernet message collection method based on FPGA. The method uses an Ethernet message collection device based on FPGA provided in Embodiment 1. The method includes the following steps:
[0053] S1, NCUC interface receives standard Ethernet data frame or NCUC data frame;
[0054] Specifically, when the device starts to receive a standard Ethernet data frame or a NCUC data frame, after detecting the end mark of the preamble code, it indicates that the valid data phase of the standard Ethernet data frame or the NCUC data frame has begun.
[0055] S2, the received data is written into the corresponding FIFO module;
[0056] Specifically, the data received after the frame delimiter is spliced into an 8-bit data and a 9-bit data with the receive valid signal, and then written into the FIFO module together. When the receive valid signal is invalid, it enters the completion state and writes a 9-bit 0 into the FIFO module at the same time. When the receive valid signal is valid and the FIFO module is full, a frame of data may be truncated. At this time, it is necessary to wait for the entire frame of data of the truncated data frame to be sent. Otherwise, the truncated data frame in the FIFO module and part of the next frame of data will be spliced into one frame of data, causing data confusion.
[0057] S3, select the FIFO module to send data to send data;
[0058] Specifically, when selecting a FIFO module to send data, first determine whether there is data in the first FIFO module and the second FIFO module. If there is data in the first FIFO module and no data in the second FIFO module, the FIFO module selected to send data is the first FIFO module; if there is data in the second FIFO module and no data in the first FIFO module, the FIFO module selected to send data is the second FIFO module; if there is data in both the first FIFO module and the second FIFO module, the data in the second FIFO module is sent first. When there are at least 8 bytes of data in the FIFO module selected to send data, the sending can begin, because the number of bytes occupied by the preamble and the frame delimiter is 8, so when there are at least 8 bytes of data in the FIFO module, it means that valid data begins to be stored in the FIFO module.
[0059] S4, data is sent to the CRC module for CRC calculation;
[0060] Specifically, the data is first sent to the first CRC module, and the first CRC module performs CRC calculation on the received Ethernet data frame or NCUC data frame. If the CRC is correct, the data is output to the cache register. If the CRC is wrong, the data is output to the second CRC module. The second CRC module is used to perform CRC calculation on the transmitted data, such as: data frames that require byte padding and CRC errors, and append them to the end of the data before transmitting them to the cache register.
[0061] S5. Read the data into the cache and memory, and then transmit it to the host computer via standard Ethernet.
[0062] Specifically, the data is read out sequentially to multiple cache registers of the cache register group, such as cache registers R0, R1, R2, and R3. Cache registers R0 to R3 are three-stage pipelines, and the information received by the high-order bits of the cache registers is a valid reception signal.
[0063] When all high bits of R3~R0 are 1, it means that the data has entered the valid data stage and data transmission can be started; first send the preamble and frame delimiter, send 31 2-bit 01s and 1 2-bit 11 respectively; then send the data in the cache register R3. The writing and reading of the FIFO module are at the same speed, so there is no waiting problem. If the FIFO module is empty, it is considered that a frame of data has been sent.
[0064] When the high bit of R0 is 0, the length of the message to be sent is determined. Since the frame length (including FCS) of the standard Ethernet frame cannot be less than 64 bytes, if the frame length (including FCS) is less than 64 bytes, padding is performed. At this time, R0 is used as input, and the content of R0 is 9'h000, until the message length is greater than 64 bytes, and the FCS is recalculated. In addition, when the frame length (including FCS) is less than 20 bytes, it does not meet the NCUC data frame standard and will be directly sent to the host computer and directly discarded by the host computer.
[0065] When the high bit of R1 is 0, it means that the data length meets the requirements. At this time, check whether the FCS is correct. If it is correct, select R1 as the input and upload the data to the host computer directly through the standard Ethernet interface without any modification. If the FCS of the captured Ethernet frame (including NCUC) is incorrect, calculate the correct FCS and append it to the original frame; add the recalculated FCS and wait for R0~R3 to be sent; wait for 960ns and start the sending process again. There is a minimum frame interval requirement for Ethernet communication. In the 10M mode, the standard Ethernet frame has a minimum interval of 9600ns between two frames; in the 100M mode, the two frames have a minimum interval of 960ns; in the 1G mode, the two frames have a minimum interval of 96ns.
[0066] Those skilled in the art should understand that the present invention can be implemented in many other specific forms without departing from the spirit and scope of the present invention. Based on the embodiments of the present invention, any changes and modifications made by ordinary technicians in the field of the present invention according to the above disclosure are within the scope of protection of the claims.
Claims
1. An Ethernet message collection device based on FPGA, characterized in that: It includes a message collection module and a standard Ethernet interface and an NCUC interface connected to the message collection module, wherein the NCUC interface is connected to an Ethernet device via an NCUC to network port data cable or is connected to an NCUC slave station via an NCUC data cable, and the standard Ethernet interface is connected to a host computer via a network cable; The NCUC interface is used to receive and transmit the Ethernet data frame of the Ethernet device or the NCUC data frame of the NCUC slave station; The message collection module is used to collect and process Ethernet data frames or NCUC data frames, and then send them to the standard Ethernet interface; The standard Ethernet interface is used to output the Ethernet data frames or NCUC data frames collected by the message collection module to the host computer.
2. The FPGA-based Ethernet message collection device according to claim 1, characterized in that: The message collection module may adopt an FPGA chip, and the FPGA chip is respectively connected to the standard Ethernet interface and the NCUC interface through a PHY chip. The collection device also includes a DCDC power chip, and the FPGA chip is connected to the power interface through the DCDC power chip.
3. The FPGA-based Ethernet message collection device according to claim 1 or 2, characterized in that: The NCUC interface includes an NCUC input interface and an NCUC output interface. When the NCUC interface communicates with the NCUC slave station, both NCUC interfaces can be used as input and output. When one of the NCUC interfaces is used as the NCUC input interface, the other interface is used as the NCUC output interface.
4. The FPGA-based Ethernet message collection device according to claim 3, characterized in that: The FPGA chip includes a transparent transmission module, which is connected between the NCUC input interface and the NCUC output interface. The transparent transmission module is used to transmit data frames between the NCUC input interface and the NCUC output interface and perform reception effective signal processing on the data frames.
5. The FPGA-based Ethernet message collection device according to claim 4, characterized in that: The FPGA chip also includes a FIFO module, which includes a first FIFO module and a second FIFO module. The input ends of the first FIFO module and the second FIFO module are respectively connected to the NCUC input interface and the NCUC output interface. The first FIFO module and the second FIFO module are used to cache Ethernet data frames or NCUC data frames received by the corresponding NCUC interface, and add FCS to data frames that need to add FCS.
6. The FPGA-based Ethernet message collection device according to claim 5, characterized in that: The FPGA chip also includes a CRC module and a cache register group, the CRC module includes a first CRC module and a second CRC module, the input end of the first CRC module is connected to the output ends of the first FIFO module and the second FIFO module, the output end of the first CRC module is connected to the input end of the second CRC module and the cache register group, the output end of the second CRC module is connected to the cache register group, and the output end of the cache register group is connected to the standard Ethernet interface; The first CRC module is used to perform CRC calculation on the collected Ethernet data frame or NCUC data frame, and directly send the data to the cache register if the CRC is correct, and send the data to the second CRC module if the CRC is wrong; The second CRC module is used to perform CRC calculation on the transmitted data, append it to the end of the data, and then send it to the buffer register group; The buffer register group includes a plurality of buffer registers, and the buffer registers are used to filter out the leading code and the frame delimiter and to supplement the data of the subsequent data frame with the number of bytes less than 64 to 64 bytes.
7. A method for implementing Ethernet message collection based on FPGA, using the Ethernet message collection device based on FPGA as described in any one of claims 1 to 6, characterized in that , including the following steps: S1, NCUC interface receives standard Ethernet data frame or NCUC data frame; S2, the received data is written into the corresponding FIFO module; S3, select the FIFO module to send data to send data; S4, data is sent to the CRC module for CRC calculation; S5. Read the data into the cache register and then transmit it to the host computer through the standard Ethernet interface.
8. The FPGA-based Ethernet message collection implementation method according to claim 7, characterized in that: The step S2 specifically includes: splicing the data received after the frame delimiter into an 8-bit data and splicing it with the received valid signal into a 9-bit data, and writing them into the FIFO module together; When the receive valid signal is invalid, it enters the completion state and writes a 9-bit 0 to the FIFO module; When the receive valid signal is valid and the FIFO module is full, if a frame of data is truncated at this time, it is necessary to wait for the entire frame of data of the truncated data frame to be sent out, otherwise the truncated data frame in the FIFO module and part of the next frame of data will be pieced together into one frame of data, causing data confusion.
9. The FPGA-based Ethernet message collection implementation method according to claim 7, characterized in that: The step S3 specifically includes: firstly determining whether there is data in the first FIFO module and the second FIFO module; if there is data in the first FIFO module and no data in the second FIFO module, selecting the FIFO module for sending data as the first FIFO module; if there is data in the second FIFO module and no data in the first FIFO module, selecting the FIFO module for sending data as the second FIFO module; and if there is data in both the first FIFO module and the second FIFO module, giving priority to sending the data in the first FIFO module.
10. The FPGA-based Ethernet message collection implementation method according to claim 7, characterized in that: The step S5 specifically includes: When all high bits of the buffer register are 1, it means that the data has entered the valid data stage, and the data can be sent according to the buffer register pipeline. If the FIFO module is empty, it is considered that a frame of data has been sent. When the high bit of the first buffer register is 0, the message length is determined. If the frame length is less than 64 bytes, padding is performed. At this time, the first buffer register is used as input until the message length is greater than 64 bytes, and the FCS is recalculated. When the high bit of the second buffer register is 0 and the data length meets the requirements, check whether the FCS is correct. If it is correct, select the second buffer register as input and upload the data to the host computer directly through the standard Ethernet interface without any modification. If the FCS is incorrect, calculate the correct FCS, append it to the original frame, add the recalculated FCS, and wait for R0 to R3 to be sent.