Packet reordering apparatus and method, chip and electronic device

Abstract

The present disclosure provides a packet reordering device and method, a chip and an electronic device. The packet reordering device comprises a burst queue (BurstFifo), a segment storage (Segment Storage) module, a segment selection (Segment Select) module and a segment check (Segment Check) module. The BurstFifo is configured to store segmented data obtained by the packet reordering device. The Segment Storage module is configured to store the segmented data. The Segment Select module is configured to obtain segment number information, obtain a lowest number based on the segment number information, and sequentially send the segmented data based on the lowest number and the segment number information. The Segment Check module is configured to determine whether the segmented data associated with the lowest number is the first transmitted segmented data. The packet reordering device can guarantee the first sending order of the packet, so that the packet can be sequentially sent.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the field of switch chip design, and relates to packet reordering, in particular to a packet reordering device and method, a chip and an electronic device. BACKGROUND

[0002] At present, the switching capacity of a single chip cannot meet the growing demand for network bandwidth. Multiple switching chips are interconnected together through stacking technology to form a large switching chip matrix, thereby providing sufficient network bandwidth for high-performance interconnection networks. Since network data transmission in chip stacking technology can cause out-of-order problems, the order of packet sending cannot be guaranteed, and therefore there is a problem that the order of packet sending cannot be guaranteed in the current chip stacking technology. SUMMARY

[0003] The present disclosure aims to provide a packet reordering device and method, a chip and an electronic device to solve the problem that the order of packet sending cannot be guaranteed in the current chip stacking technology.

[0004] In a first aspect, the present disclosure provides a packet reordering device, which comprises a burst queue (BurstFifo), a segment storage module (Segment Storage), a segment selection module (Segment Select) and a segment check module (Segment Check). The BurstFifo is configured to store segmented data received by the packet reordering device. The Segment Storage module is configured to store the segmented data, which is a segment of a packet cut during transmission. The Segment Select module is configured to obtain segment number information, and based on the segment number information, obtain the lowest number, and based on the lowest number and the segment number information, sequentially send the segmented data. The Segment Check module is configured to determine whether the segmented data associated with the lowest number is the first transmitted segmented data. If the packet reordering device subsequently receives segmented data that is sequentially after the first transmitted segmented data, the segmented data associated with the lowest number is the first transmitted segmented data, otherwise the segmented data associated with the lowest number is not the first transmitted segmented data.

[0005] In the packet reordering device, the segment number information and the segmented data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, so that the order of packet sending can be guaranteed, and the packet can be sequentially sent.

[0006] In an embodiment of the present disclosure, the packet reordering device further comprises a DataCrcChecker module; the DataCrcChecker module comprises: a segmented data receiving unit configured to receive the segmented data read from the BurstFifo; a CRC checking unit configured to perform CRC checking on the segmented data to obtain a CRC checking result, the CRC checking result being CRC checking success or CRC checking failure; and a segmented data processing unit configured to process the segmented data based on the CRC checking result; the segmented data stored in the Segment Storage module is the segmented data of CRC checking success.

[0007] In an embodiment of the present disclosure, the segmented data processing unit is further configured to: when the CRC checking result is CRC checking failure, discard the segmented data of CRC checking failure; and when the CRC checking result is CRC checking success, write the segmented data of CRC checking success into the Segment Storage module.

[0008] In an embodiment of the present disclosure, the Segment Storage module comprises: a Segment Storage unit configured to store the segmented data in a first memory and a second memory therein; and a Linked List configured to manage the storage positions of the segmented data; the first memory and the second memory each have a head pointer and a tail pointer associated with the Linked List, the head pointer being used to write the address of the segmented data, and the tail pointer being used to read the segmented data.

[0009] In an embodiment of the present disclosure, the segmented data has an associated node identifier, and the packet reordering device further comprises a source selector configured to interleave the node identifiers based on a preset period, so that the segmented data in the Segment Storage module is read into the PBC based on the interleaved node identifiers.

[0010] In an embodiment of the present disclosure, the Segment Select module comprises: a lowest number obtaining unit configured to obtain segment number information and obtain a lowest number based on the segment number information; a time checking TimerCheck unit configured to determine whether a time of waiting for a segment number exceeds a preset maximum time; and a segment data sending unit configured to read the segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the LinkedList, and sequentially send the segment data.

[0011] In an embodiment of the present disclosure, the segment data is segment data under a plurality of loops; the lowest number is a lowest number under the loops; and the first transmitted segment data is first transmitted segment data under the loops.

[0012] In a second aspect, an embodiment of the present disclosure provides a chip comprising the packet reordering device of any one of the first aspect.

[0013] In a third aspect, an embodiment of the present disclosure provides a packet reordering method, comprising: obtaining segment data and segment number information, the segment data being a plurality of segments of a packet when the packet is transmitted; obtaining a lowest number based on the segment number information; sequentially sending the segment data based on the lowest number and the segment number information; and determining whether the segment data associated with the lowest number is first transmitted segment data, if subsequent received segment data are all sequentially after the first transmitted segment data, then the segment data associated with the lowest number is the first transmitted segment data, otherwise the segment data associated with the lowest number is not the first transmitted segment data.

[0014] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, comprising: a memory; and a processor coupled to the memory and configured to execute the packet reordering method according to the third aspect.

[0015] As described above, the packet reordering device and method, the chip and the electronic device have the following beneficial effects:

[0016] In the packet reordering device, the segment number information and the segment data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, so that the packet can be sequentially transmitted. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A schematic diagram showing a stacked interface according to an embodiment of the present disclosure.

[0018] Figure 2 A schematic diagram showing a segmented continuous according to an embodiment of the present disclosure.

[0019] Figure 3 A schematic diagram showing a structure of a packet reordering apparatus according to an embodiment of the present disclosure.

[0020] Figure 4 A memory representation of a BurstFifo according to an embodiment of the present disclosure.

[0021] Figure 5 A schematic diagram showing a structure of a packet reordering apparatus according to an embodiment of the present disclosure.

[0022] Figure 6 A timing diagram showing a source selector according to an embodiment of the present disclosure.

[0023] Figure 7 An example table of lowest numbers according to an embodiment of the present disclosure.

[0024] Figure 8 A flowchart of a packet reordering method according to an embodiment of the present disclosure.

[0025] Element Numbering

[0026] 10 packet reordering apparatus

[0027] 110 BurstFifo

[0028] 120 Segment Storage module

[0029] 130 Segment Select module

[0030] 140 Segment Check module

[0031] S11-S14 steps DETAILED DESCRIPTION

[0032] The present disclosure will be described with particular reference to specific embodiments thereof, but it is to be understood that no limitation of the scope of the disclosure is intended thereby. Other advantages and benefits will also become apparent. The disclosure is also capable of other embodiments and of being practiced or being carried out in various ways. As will be understood by those familiar with the art, the disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Specific details disclosed herein are not to be interpreted as imposing limitations which are not in the scope of the present disclosure. Embodiments described herein are presented by way of example to provide an adequate understanding of the disclosure. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. Embodiments herein can be used in any number of contexts and applications. It should be noted that the use of "for example," "for instance," "like," and "like" herein are used merely for explanation. Any feature, structure, or characteristic described herein can be combined in any manner with any other feature, structure, or characteristic described herein.

[0033] It is to be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concepts of the present disclosure, and only the components related to the present disclosure are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The shapes, number and ratio of the components in actual implementation can be arbitrarily changed, and the layout of the components can be more complex.

[0034] The principles and implementation manners of the packet reordering device and the packet reordering method of the embodiments of the present disclosure will be described in detail below, so that those skilled in the art can understand the packet reordering device and the packet reordering method of the embodiments of the present disclosure without creative labor.

[0035] Please refer to Figure 1 As Figure 1 shown, the SIF (Stack Interface) is an interface connecting ingress data to the stack port and connecting the stack port to the egress path: the SIF is composed of 8 SifRacPcs (Ring Access Controller) blocks, a SifReorder (Reorder) block, a SifBcn (Back Congestion Notification) block, a SifCopyTrip (Copy / Strip) block, an ingress queue (SifIngressFifo), and a SifRingSel (Ring Selection) block. Each of the 8 SifRacPcs blocks corresponds to a logical ring. The SifBcn block is used to process Bcn messages in the stack interface, the SifCopyTrip block is used for fragment copying and stripping (deletion) in the SifRacPcs block, the SifRingSel block is used to select the logical ring, the ingress queue is used to store local segment data, and the SifReorder block is used to reorder the fragments in the SifRacPcs block. Figure 1 The IQS (Ingress Queue scheduler), the AQM (Active Queue Manager), the Receive Serdes (Receive Serdes), and the Transmit Serdes (Transmit Serdes) are also included. Each Rac has 4 Serdes (Serializer / Deserializer) running at a speed of 112 Gbps. This makes the entire stack link set have 32 Serdes, achieving a bandwidth of 3.2 TGbps.

[0036] Figure 1This invention is only intended to provide an application scenario for a message reordering device (corresponding to the SifReorder block in SIF), namely, to reorder multi-loop messages in a loop stacking network. The stacking interface is not the focus of this disclosure, and will not be described in detail in this embodiment.

[0037] Please see Figure 2 ,like Figure 2 As shown, in a stacked interface with several loops, when node #1 sends data to the stacked interface, the interface module does not know where it is going. Therefore, the local segmented data of node #1 can be inserted into the Rac (Ring Access Control) with the most available Credits. This means that the local segmented data from node #1 can (and will) be placed on the ring moving in the opposite direction. When the segmented data arrives at node #15, it must be determined whether there is any other consecutive segmented data before the segmented data can be forwarded to the PBC (Packetbuffer complex). In the stacked interface, the initial order of packets in the interface loop needs to be guaranteed so that packets can be sent sequentially.

[0038] Please see Figure 3 ,like Figure 3 As shown, this embodiment provides a message reordering device 10, which includes:

[0039] BurstFifo 110, Segment Storage 120, Segment Select 130, and Segment Check 140;

[0040] The BurstFifo110 is configured to store segmented data acquired by the message reordering device, the segmented data being fragments into which the message is cut during transmission;

[0041] The Segment Storage module 120 is configured to store the segmented data;

[0042] The Segment Select module 130 is configured to obtain segment number information, obtain the lowest number based on the segment number information, and send the segment data sequentially based on the lowest number and the segment number information.

[0043] The Segment Check module 140 is configured to determine whether the segment data with the lowest associated number is the first transmitted segment data, if the packet reordering device 10 subsequently receives segment data in order after the first transmitted segment data, then the segment data with the lowest associated number is the first transmitted segment data, otherwise the segment data with the lowest associated number is not the first transmitted segment data.

[0044] Optionally, the segment data can refer to a packet being cut into multiple segments during transmission, each segment having a length of 64 bytes, and when the last segment of the packet is less than 64 bytes, 0 is filled to make up 64 bytes. The packet can include an Ethernet packet and a switch management message.

[0045] Optionally, the packet reordering device 10 can correspond to the SifReorder block in Figure 1 , used to reorder the segment data provided by the SifRacPcs.

[0046] Optionally, the segment data obtained by the packet reordering device 10 can be the segment data received by the packet reordering device 10, for example, can be the segment data received from the SifRacPcs module in Figure 1 .

[0047] Optionally, the segment number information can include the segment number of the segment data, and the lowest number refers to the lowest segment number in the segment number information.

[0048] Optionally, the segment data is segment data of a plurality of loops, the lowest number is the lowest number under the loop, and the first transmitted segment data is the first transmitted segment data under the loop.

[0049] Optionally, sequentially sending the segment data based on the lowest number and the segment number information can include sequentially sending the segment data to the PBC based on the lowest number and the segment number information. The sequential sending can refer to sending in order from small to large according to the segment number. For example, the segment data can include segment number 1, segment number 2 and segment number 3 data, and the lowest number can be segment number 1. During the process of sending the segment data to the PBC, the segment data of segment number 1, the segment data of segment number 2 and the segment data of segment number 3 are sequentially sent to the PBC.

[0050] Optionally, in the Segment Check module 140, for example, the lowest number is 3, when the packet reordering device 10 subsequently receives segment data with segment number 2, it indicates that the subsequently received segment data is before the first transmitted segment data, when the packet reordering device 10 subsequently receives segment data with segment number 4, it indicates that the subsequently received segment data is after the first transmitted segment data. If the segment data associated with the lowest number is not the first transmitted segment data, the data transmitted after the segment data associated with the lowest number can be discarded.

[0051] In an embodiment of the present disclosure, the BurstFifo 110 can have 8-way write and 1-way read functions, and is implemented in a flip-flop, the elements of which are described in the SifRreorder BurstFifo memory table. The BurstFifo 110 can smooth the burstiness of segment data Segment Data storage resources (8 write operations cannot be performed at once), and the segment data read from the BurstFifo 110 is then sent to the DataCrcChecker module for segment data check verification.

[0052] In an embodiment of the present disclosure, Figure 4 The memory representation of the BurstFifo 110 in the embodiment of the present disclosure is shown. If the segment is the start of the packet (SOP), check if the descriptor is a 32B (32-bit) descriptor. If so, it will be expanded back to 64B (64-bit), and the data will be shifted. This is the opposite of the procedure performed in the data insertion block in the SifRac module in the SIF insertion block Figure 1 At this time, the expanded data is written to the segment data storage and restored to the form expected by the PBC. Figure 4 In the data, dataCrc, nodeId, racId, sop, eop, segmentNumber, Total, Wr sysClk, RdsysClk, FLOPS, Drop Segment or CHIEF based on configuration in the above table, data represents segment data, dataCrc represents the CRC check result, nodeId represents the node identifier, racId represents the ring access control identifier, sop represents the start of the segment, eop represents the end of the segment, segmentNumber represents the segment number, Total represents all, Wr sysClk represents the write synchronization signal, RdsysClk represents the read synchronization signal, FLOPS can refer to the number of floating-point operations that can be performed per second, Drop Segment or CHIEF based on configuration can refer to discarding the segment or configuring as the chief. Figure 4The Reorder Info in the Reorder Info field can refer to information for reordering segment numbers of the segment data. For example, the segment numbers of the segment data include 1, 5, 4, and 3, and the Reorder Info can be information including segment numbers 1, 3, 4, and 5.

[0053] Optionally, referring to Figure 5 The packet reordering device further includes a Data Crc Checker module.

[0054] The Data Crc Checker module has the following functions:

[0055] A segment data receiving unit is configured to receive the segment data read from the Burst Fifo.

[0056] A CRC (Cyclic Redundancy Check) checking unit is configured to perform CRC checking on the segment data to obtain a CRC checking result, the CRC checking result being CRC checking success or CRC checking failure.

[0057] A segment data processing unit is configured to process the segment data based on the CRC checking result.

[0058] The segment data stored in the Segment Storage module is segment data of the CRC checking success.

[0059] Optionally, the segment data processing unit is further configured to:

[0060] When the CRC checking result is CRC checking failure, discard the segment data of the CRC checking failure.

[0061] When the CRC checking result is CRC checking success, write the segment data of the CRC checking success into the Segment Storage module.

[0062] In an embodiment of the present disclosure, the data read from the Burst Fifo enters the Data Crc (Cyclic Redundancy Check) checker, i.e., the Data Crc Checker module. The Segment Data is checked to ensure that the stack link or other intermediate storage elements do not damage it. The Crc-8 polynomial used is x8+x7+x6+x4+x2+1, which can be the same as the original in Figure 1The code to generate the segment data in SifIngressFifo (ingress data queue) is the same as in the present embodiment, which will not be described again. If the CRC check fails, the segment will be discarded, or CHIEF (Chief) is set according to the SifControl.dropOnDataCrcError (stack interface control discards cyclic redundancy check error data) bit.

[0063] Optionally, as shown in Figure 5 The Segment Storage module has a Segment Storage unit configured to store the second segment data according to the first memory and the second memory therein, and a Linked List configured to manage the storage location of the segment data; the first memory and the second memory each have a head pointer and a tail pointer associated with the LinkedList, the head pointer is used to write the address of the segment data, and the tail pointer is used to read the segment data.

[0064] Optionally, the first memory and the second memory each perform reading and writing once within a preset period, for example, within any given 500MHz period, each memory must perform reading and writing once.

[0065] Optionally, when the segment data of one of the memories in the Segment Storage unit is being read and sent to the PBC, the writing and storage of the segment data will occur in the other memory. For example, the segment data of the first memory is being read, and the writing of the segment data occurs in the second memory. When the memory in the Segment Storage unit is not being read, the writing of the segment data occurs in the least full memory.

[0066] Optionally, the Segment Storage module is split into a first memory and a second memory, and the priority of reading is higher than that of writing, which can result in an overall depth (2*768) greater than the previously estimated 825 unfinished segments.

[0067] Optionally, the calculation of the storage space required for reordering can be represented as:

[0068]

[0069] wherein TotalSegments represents total segments on a given time stack link, FixedDelay represents a fixed delay, Node represents a node, Segments represents segments, Rac represents a ring access controller module, second represents a second, VariableSegments represents variable segments, Nodes represents total nodes, and Racs represents total ring access controller blocks. The stack link refers to a link of a stack in the stacking interface, and the stack link can refer to a linked list of the stack.

[0070] The differential time between the fastest path and the slowest path is represented as:

[0071] WorstCaseDifferentialDelay = TotalNodes - 1

[0072] wherein WorstCaseDifferentialDelay represents the differential time between the fastest path and the slowest path, and TotalNodes represents total nodes.

[0073] The number of segments per second per Rac is given by:

[0074]

[0075] The bandwidth of the stack is: 112 Gbps * 32 Node = 3584 Gbps.

[0076] wherein represents the number of segments per second per Rac, StackBandwidth represents the bandwidth of the stack, Byte represents a byte, and Stack represents a stack.

[0077] In an embodiment of the present disclosure, the Segment Data storage location is managed by a linked list. When segment data is written into the Segment Data Storage, i.e., the segment storage unit, a pointer is sent to the SifReorderSlice module for storage, so that the segment data can be retrieved when read out. The head pointer is the address for writing segment data. When the segment data is read out, the pointer returns to the tail of the linked list. The initial state of the linked list is that each address points to the next position.

[0078] Writing to Segment Data Store requires reading from LinkedList (to find next pointer). Reading from Segment Data Store requires writing to LinkedList (linking pointer to tail). This LinkedList memory is ECC protected as a fault in it will cause LinkedList to be artificially shortened to "1" element (itself). The Segment Data LinkedList memory table describes the LinkedList memory.

[0079] There are always 4 pointers in the SifReorder block. There is a head pointer for each of the 2 Segment Data Stores and a tail pointer for each of the 2 Segment Data Stores. At initialization, the head pointer is equal to 0 and the tail pointer is equal to 755. The Segment Data LinkedList (the LinkedList memory described above) must be initialized so that each entry point to the next (0-->1, 1-->2,... 765-->766, 766-->767). This can be done by either setting a hardware initialization bit or programming each entry by software.

[0080] Optionally, the segment data has an associated node identification, as shown in Figure 5 The packet reordering device further includes a Source Selector configured to interleave the node identification based on a preset period, so that the segment data in the Segment Storage module is read into the PBC based on the interleaved node identification. The preset period can be flexibly set according to actual conditions, and the present embodiment does not explicitly limit this.

[0081] In an embodiment of the present disclosure, the packet reordering device interleaves the NodeId (node identification) being worked on every other period. This is because the PBC cannot handle back-to-back segment data from the same NodeId. The Source Selector module is responsible for switching the machine back and forth between open sources (NodeIds). When the NodeId no longer has valid segments ready to send to the PBC, the source selector will move to the next context (NodeId). The timing diagram of the source selector is shown in Figure 6 . Figure 6 The currentNodeId in the timing diagram of the source selector can represent the current node identification, and the nodeIdDone can represent the node identification completion.

[0082] Optionally, the Segment Select module has a lowest number obtaining unit configured to obtain segment number information, and based on the segment number information, obtain the lowest number; a TimerCheck unit configured to judge whether the time of waiting for a segment number exceeds a preset maximum time; a segment data sending unit configured to read the second segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the Linked List, and sequentially send the second segment data.

[0083] Optionally, the segment number information can be the Reorder Info described above. The preset maximum time can be flexibly set according to actual conditions, and the present embodiment does not explicitly limit this.

[0084] Optionally, the segment number waited for in the TimerCheck unit can be a missing segment number in the sequentially sent segment data, for example, the lowest number is 1, and segment numbers 1, 2 and 3 need to be sequentially sent. At present, the segment data does not contain data with segment number 2, so data with segment number 2 needs to be waited for. The TimerCheck unit refers to whether the time of waiting for segment number 2 exceeds a preset time. The preset time can be flexibly set according to actual conditions, and the present embodiment does not explicitly limit this.

[0085] In an embodiment of the present disclosure, the segment selector obtains segment number information provided by RacInfoStorage Rams, and determines the lowest segment number. Once the lowest SegmentNumber is selected, all other information in the RacInfoStorage Rams is fed to the TimerCheck block. The RacInfoStorage Rams can be in the SifRacPcs module.

[0086] Even if the counter rolls over, the Segment Select module will carefully determine the lowest SegmentNumber. An example table of lowest segment number determination is provided in the lowest segment number example table. The segment number is counted from 0 to 4095 to help make these determinations easier (solve the wrapping effect). Since the stack can have approximately 850 segments at any time, a minimum counter of 0-2047 is needed. It is extended to 4096 to accommodate the future.

[0087] Figure 7The segment difference of 801 is shown as well as how it crosses the counter boundary. At any time, the difference can exceed 850, but if this happens, some segments are certainly ready to be read into the PBC. The "segment select" block relies on the fact that segments are stored one after the other in a linked list. It guarantees that the segment selection is limited to 8 options (one for each rac), after which arriving segments that are behind previously arriving segments from the same race can be guaranteed to have a segment number greater than the previously arriving segment number.

[0088] The lowest number is the lowest number under all the loops, the counter is used by each Rac in turn, so 0-4095-0-1, the minimum data is when the maximum number + minimum number in Rac0~Rac7 is less than 4096, the lowest is the current minimum number, when the maximum number + minimum number in Rac0~Rac7 is greater than 4096, it means that the count has been reversed for a round at this time. The minimum number is the minimum of the larger number. Figure 7 The Seg#Rac0-7 in the above means the segment number of Rac0~Rac7, and the lowest segment means the lowest number.

[0089] In an embodiment of the present disclosure, once the lowest segment number is selected, the "first transmission" is determined. It is only because it looks like "the first transmission", although it may not actually be. The segment check block determines whether this segment is actually "the first transmission", or whether we need to wait longer. By storing segment number information for each race, it can be guaranteed that even if 50 segments are copied from the stack link, only 8 segment numbers will be checked at a time. All subsequent segments copied from the stack link by a given Rac are "behind" this segment in order.

[0090] The BurstFifo described above corresponds to Figure 5 The DataCrcChecker module corresponds to Figure 5 The dataCrcCheck in the above, the Segment Storage unit corresponds to Figure 5 The Segment Data Store in the above, the Linked List corresponds to Figure 5 The LinkedList in the above, the pointer can correspond to Figure 5 The SegementDataLink in the above, the source selector corresponds to Figure 5 The Source Select in the above, the Segment Select module corresponds to Figure 5 The SegmentSelect in the above, the Segment Check module corresponds to Figure 5Segment Check.

[0091] In an embodiment of the present disclosure, the embodiment provides a chip, which comprises the packet reordering device.

[0092] Figure 8 is a flow chart showing a packet reordering method according to an embodiment of the present disclosure. As shown in Figure 8 the embodiment provides a packet reordering method, which comprises:

[0093] S11, obtaining segment data and segment number information, the segment data being segments into which a packet is cut when being transmitted.

[0094] S12, obtaining a lowest number based on the segment number information.

[0095] S13, sequentially transmitting the segment data based on the lowest number and the segment number information.

[0096] S14, determining whether the segment data associated with the lowest number is first-transmitted segment data, if subsequently received segment data is sequentially after the first-transmitted segment data, the segment data associated with the lowest number is the first-transmitted segment data, otherwise the segment data associated with the lowest number is not the first-transmitted segment data.

[0097] Optionally, the sequential order can refer to an order from small to large of segment numbers, and the subsequently received segment data sequentially after the first-transmitted segment data can refer to that segment numbers of the subsequently received segment data are sequentially after a segment number of the first-transmitted segment data from small to large, for example, the lowest number is 2, the first-transmitted segment data refers to segment data with a segment number of 2, if subsequently received segment data has segment numbers of 3, 4, 5, etc., the segment data associated with the lowest number is the first-transmitted segment data, if subsequently received segment data has a segment number of 1, the segment data associated with the lowest number is not the first-transmitted segment data.

[0098] The protection scope of the packet reordering method according to the embodiment of the present disclosure is not limited to the execution order of the steps listed in the embodiment, and any scheme realized by adding, reducing or replacing steps of the prior art according to the principle of the present disclosure is included in the protection scope of the present disclosure.

[0099] In summary, in the packet reordering device, the segment number information and the segment data are processed by the BurstFifo, the Segement Storage module, the Segment Select module and the Segment Check module, so that the packet sending order can be guaranteed, and the packet can be sent in sequence.

[0100] In several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus or method can be implemented in other manners. For example, the described apparatus embodiments are merely schematic. For example, the division of the modules / units is merely a logical function division. There can be another division manner for the actual implementation, for example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, apparatuses, modules or units, and can be electrical, mechanical or in other forms.

[0101] The modules / units described as separated components can or can not be physically separated, and the components displayed as modules / units can or can not be physical modules, i.e., can be located in one place, or can be distributed on multiple network units. Some or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present disclosure. For example, the functional modules / units in the various embodiments of the present disclosure can be integrated into one processing module, or each module / unit can be physically separated, or two or more modules / units can be integrated into one module / unit.

[0102] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A skilled person can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present disclosure.

[0103] The present embodiment provides an electronic device, which includes a memory, a processor coupled with the memory and configured to execute Figure 8 the packet reordering method shown.

[0104] The embodiments of the present disclosure further provide a computer readable storage medium. A person of ordinary skill in the art can understand that all or part of the steps of the methods described in the above embodiments can be instructed by a program to complete by a processor, and the program can be stored in a computer readable storage medium. The storage medium is a non-transitory medium, for example, a random access memory, a read only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, and the like, which includes one or more available medium sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), and the like.

[0105] The embodiments of the present disclosure can further provide a computer program product including one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in the embodiments of the present disclosure are generated. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions can be transmitted from one website, computer or data center to another website, computer or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner.

[0106] When the computer program product is executed by a computer, the computer executes the method described in the foregoing method embodiments. The computer program product can be a software installation package, and when the foregoing method needs to be used, the computer program product can be downloaded and executed on the computer.

[0107] The description of the processes or structures corresponding to the above respective figures has its own emphasis, and the parts not described in detail in a certain process or structure can be referred to the related description of other processes or structures.

[0108] The above embodiments are only illustrative of the principles and effects of the present disclosure, and are not used to limit the present disclosure. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present disclosure should be covered by the claims of the present disclosure.

Claims

1. A packet reordering apparatus, characterized by comprising: The packet reordering device comprises a burst queue (BurstFifo), a segment storage module (Segment Storage), a segment selection module (Segment Select) and a segment check module (Segment Check). The BurstFifo is configured to store segment data obtained by the packet reordering device, wherein the segment data is a segment obtained by cutting a packet during transmission. The Segment Storage module is configured to store the segment data. The Segment Select module is configured to obtain segment number information, obtain a lowest number based on the segment number information, and sequentially send the segment data based on the lowest number and the segment number information. The Segment Check module is configured to determine whether the segment data associated with the lowest number is first transmission segment data, wherein if all the segment data subsequently received by the packet reordering device is sequentially after the first transmission segment data, the segment data associated with the lowest number is the first transmission segment data, otherwise, the segment data associated with the lowest number is not the first transmission segment data. The Segment Storage module comprises: a Segment Storage unit configured to store the segment data according to a first memory and a second memory therein; a linked list (Linked List) configured to manage the storage position of the segment data; the first memory and the second memory each have a head pointer and a tail pointer associated with the Linked List, wherein the head pointer is used to write the address of the segment data, and the tail pointer is used to read the segment data. The Segment Select module comprises: a lowest number obtaining unit configured to obtain segment number information and obtain a lowest number based on the segment number information; a time check (TimerCheck) unit configured to determine whether the time of waiting for a segment number exceeds a preset maximum time; a segment data sending unit configured to read the segment data from the Segment Storage unit based on the lowest number, the segment number information, the TimerCheck unit and the pointer associated with the Linked List, and sequentially send the segment data.

2. The packet reordering device of claim 1, wherein The packet reordering device further comprises a data cyclic redundancy check (DataCrcChecker) module. The DataCrcChecker module comprises: a segment data receiving unit configured to receive the segment data read from the BurstFifo; a CRC check unit configured to perform CRC check on the segment data to obtain a CRC check result, wherein the CRC check result is CRC check success or CRC check failure; a segment data processing unit configured to process the segment data based on the CRC check result. The segment data stored by the Segment Storage module is segment data for which the CRC check is successful.

3. The packet reordering apparatus of claim 2, wherein The segment data processing unit is further configured to: discard segment data for which the CRC check is unsuccessful when the CRC check result is CRC check unsuccessful; write segment data for which the CRC check is successful into the Segment Storage module when the CRC check result is CRC check successful.

4. The packet reordering device of claim 1, wherein The segment data has an associated node identifier, and the packet reordering device further comprises a source selector configured to interleave the node identifiers based on a preset period, so that the segment data in the Segment Storage module is read into the PBC based on the interleaved node identifiers.

5. The packet reordering device of claim 4, wherein: the segment data is segment data under a plurality of loops; the lowest number is the lowest number under the loop; the first transmitted segment data is the first transmitted segment data under the loop.

6. A chip, characterized by A packet reordering device as claimed in any one of claims 1 to 5.

7. A method for reordering packets, the method comprising: A method for reordering packets, comprising: obtaining segment data and segment number information, the segment data being fragments into which a packet is cut when being transmitted; based on the segment number information, obtaining a lowest number; based on the lowest number and the segment number information, sequentially transmitting the segment data; determining whether the segment data associated with the lowest number is first transmitted segment data, if subsequent received segment data are all sequentially after the first transmitted segment data, then the segment data associated with the lowest number is the first transmitted segment data, otherwise the segment data associated with the lowest number is not the first transmitted segment data; storing the segment data according to a first memory and a second memory; managing the storage location of the segment data through a linked list, the first memory and the second memory each having a head pointer and a tail pointer associated with the linked list, the head pointer being used to write the address of the segment data, and the tail pointer being used to read the segment data; an implementation method for sequentially transmitting the segment data based on the lowest number and the segment number information, comprising: based on the lowest number, the segment number information, a result of judging whether the time of waiting for a segment number exceeds a preset maximum time, and a pointer associated with the linked list, sequentially transmitting the segment data.

8. An electronic device, comprising: A device, comprising: a memory; a processor coupled to the memory and configured to execute the packet reordering method of claim 7.

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