Optical signal processing circuit and device, optical signal processing method, and storage medium

Abstract

The application relates to an optical signal processing circuit and device, an optical signal processing method and a storage medium. The optical signal processing circuit comprises a signal input node for receiving an initial voltage signal converted from an optical signal; a first transistor and a second transistor connected in series, the first transistor being turned on when the initial voltage signal is greater than a first threshold voltage and being turned off when the initial voltage signal is not greater than the first threshold voltage, the second transistor being turned on when the initial voltage signal is less than a second threshold voltage and being turned off when the initial voltage signal is greater than the second threshold voltage; a third transistor and a fourth transistor connected in series, the third transistor being turned on when the initial voltage signal is greater than the second threshold voltage and being turned off when the initial voltage signal is less than the second threshold voltage, the fourth transistor being turned on when the initial voltage signal is less than a third threshold voltage and being turned off when the initial voltage signal is greater than the third threshold voltage; a first operational amplifier for amplifying the initial voltage signal output by the second transistor by a preset multiple and supplying the amplified initial voltage signal to an analog-to-digital converter; and a second operational amplifier for amplifying the initial voltage signal output by the fourth transistor by a preset multiple and supplying the amplified initial voltage signal to the analog-to-digital converter.

Description

Technical Field

[0001] The present application relates to an optical signal processing circuit and device, an optical signal processing method and a storage medium. Background Art

[0002] Photoelectric sensors are devices that convert light signals into electrical signals. They can be used for FLICK testing and brightness testing of display screens.

[0003] In display screen testing applications, photoelectric sensors mostly use photodiodes to collect light signals emitted by the display screen under test, convert the collected light signals into amplified analog voltage signals, and then transmit them to the analog-to-digital converter (ADC). The ADC then converts the amplified analog voltage signals into digital voltage signals. The optical display performance of the display screen is judged based on the analysis of the digital voltage signals.

[0004] In related technologies, the amplification factor used to convert light signals into amplified analog voltage signals is fixed. Therefore, as light intensity changes, the converted analog voltage signal also changes proportionally. If the light intensity is too high, the converted analog voltage signal may exceed the readable range or optimal reading range of the analog-to-digital converter (ADC), resulting in inaccurate readings, large errors, or even unreadable readings. Summary of the Invention

[0005] In view of this, the present application proposes an optical signal processing circuit and device, an optical signal processing method and a storage medium.

[0006] In a first aspect, the present application provides an optical signal processing circuit, comprising:

[0007] a signal input node, configured to receive an initial voltage signal converted from the optical signal, wherein the initial voltage signal is an analog signal;

[0008] a first transistor connected to the signal input node and a second transistor connected in series with the first transistor, wherein the first transistor is configured to be turned on when the initial voltage signal is greater than a first threshold voltage and turned off when the initial voltage signal is not greater than the first threshold voltage; and the second transistor is configured to be turned on when the initial voltage signal is less than a second threshold voltage and turned off when the initial voltage signal is greater than the second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage;

[0009] a third transistor connected to the signal input node and a fourth transistor connected in series with the third transistor, wherein the third transistor is configured to be turned on when the initial voltage signal is greater than the second threshold voltage and to be turned off when the initial voltage signal is less than the second threshold voltage; the fourth transistor is configured to be turned on when the initial voltage signal is less than a third threshold voltage and to be turned off when the initial voltage signal is greater than the third threshold voltage, the third threshold voltage being greater than the second threshold voltage;

[0010] an analog-to-digital converter configured to convert an analog signal supplied thereto into a digital signal;

[0011] a first operational amplifier configured to amplify the initial voltage signal output by the second transistor by a first preset multiple and then supply the amplified voltage signal to the analog-to-digital converter;

[0012] The second operational amplifier is configured to amplify the initial voltage signal output by the fourth transistor by a second preset multiple and then supply the amplified signal to the analog-to-digital converter, wherein the second preset multiple is smaller than the first preset multiple.

[0013] In some possible implementations, the following further comprises:

[0014] a fifth transistor connected to the signal input node and a sixth transistor connected in series with the fifth transistor, wherein the fifth transistor is configured to be turned on when the initial voltage signal is greater than the third threshold voltage and to be turned off when the initial voltage signal is less than the third threshold voltage; the sixth transistor is configured to be turned on when the initial voltage signal is less than a fourth threshold voltage and to be turned off when the initial voltage signal is greater than the fourth threshold voltage, wherein the fourth threshold voltage is greater than the third threshold voltage;

[0015] a seventh transistor connected to the signal input node, the seventh transistor being configured to be turned on when the initial voltage signal is greater than a fourth threshold voltage and turned off when the initial voltage signal is less than the fourth threshold voltage, wherein the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage increase in sequence;

[0016] a third operational amplifier, configured to amplify the initial voltage signal output by the sixth transistor by a third preset multiple and then supply the amplified voltage signal to the analog-to-digital converter;

[0017] a fourth operational amplifier, configured to amplify the initial voltage signal output by the seventh transistor by a fourth preset multiple and then supply the amplified voltage signal to the analog-to-digital converter;

[0018] The first preset multiple, the second preset multiple, the third preset multiple and the fourth preset multiple decrease in sequence.

[0019] In some possible implementations, the first transistor, the third transistor, the fifth transistor, and the seventh transistor are N-type transistors, and the circuit further includes:

[0020] A first comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a first reference voltage node providing the first threshold voltage; and an output terminal connected to the gate of the first transistor;

[0021] a second comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a second reference voltage node providing the second threshold voltage; and an output terminal connected to the gate of the third transistor;

[0022] a third comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a third reference voltage node providing the third threshold voltage; and an output terminal connected to the gate of the fifth transistor;

[0023] The fourth comparator has: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a fourth reference voltage node providing the fourth threshold voltage; and an output terminal connected to the gate of the seventh transistor.

[0024] In some possible embodiments, the second transistor, the fourth transistor and the sixth transistor are P-type transistors, the gate of the second transistor is connected to the first circuit node between the third transistor and the fourth transistor, the gate of the fourth transistor is connected to the second circuit node between the fifth transistor and the sixth transistor, and the gate of the sixth transistor is connected to the output terminal of the seventh transistor.

[0025] In some possible implementations, the first threshold voltage is zero volt.

[0026] In a second aspect, an optical signal processing device is proposed, comprising:

[0027] The circuit according to the first aspect;

[0028] The optical signal conversion unit includes a photosensor, and is configured to convert the optical signal into the initial voltage signal using the photosensor, and supply the initial voltage signal to the signal input node.

[0029] In some possible implementations, the following further comprises:

[0030] The image processor is connected to the output terminal of the analog-to-digital converter and is configured to generate a corresponding digital image signal based on the size of the digital signal output by the analog-to-digital converter.

[0031] In a third aspect, a method for processing an optical signal is provided, comprising:

[0032] obtaining an initial voltage signal, wherein the initial voltage signal is an analog signal converted from the optical signal;

[0033] if the initial voltage signal is greater than a first threshold voltage and less than a second threshold voltage, amplifying the initial voltage signal by a first preset multiple to obtain a first analog voltage signal, and inputting the first analog voltage signal into an analog-to-digital converter;

[0034] if the initial voltage signal is greater than the second threshold voltage and less than a third threshold voltage, amplifying the initial voltage signal by a second preset multiple to obtain a second analog voltage signal, and inputting the second analog voltage signal into the analog-to-digital converter, wherein the second preset multiple is less than the first preset multiple;

[0035] if the initial voltage signal is greater than the third threshold voltage and less than a fourth threshold voltage, amplifying the initial voltage signal by a third preset multiple to obtain a third analog voltage signal, and inputting the third analog voltage signal into the analog-to-digital converter, wherein the third preset multiple is less than the second preset multiple;

[0036] if the initial voltage signal is greater than the fourth threshold voltage, amplifying the initial voltage signal by a fourth preset multiple to obtain a fourth analog voltage signal, and inputting the fourth analog voltage signal into the analog-to-digital converter, wherein the fourth preset multiple is less than the third preset multiple;

[0037] outputting, by the analog-to-digital converter, a digital output signal representing the intensity of the optical signal.

[0038] In some possible implementations, the method is performed by the circuit according to the first aspect or the device according to the second aspect.

[0039] In a fourth aspect, a computer-readable storage medium storing program instructions is provided, when the program instructions are executed by a computer, the method according to the third aspect is implemented.

[0040] According to the optical signal processing circuit provided in the present application, the initial voltage signal converted from the optical signal is amplified by a corresponding multiple according to the size of the initial voltage signal, and then is transmitted to the analog-to-digital converter, so that the size of the analog signal received by the analog-to-digital converter is always within a proper range, thereby helping to improve the measurement accuracy of the optical signal. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not limitations to the present application.

[0042] Figure 1 This is a circuit block diagram of the optical signal processing device provided in an embodiment of the present application.

[0043] Figure 2 This is a flowchart of an optical signal processing method provided in an embodiment of the present application.

[0044] Description of reference numerals:

[0045] 1000-optical signal processing equipment;

[0046] 100-optical signal conversion unit;

[0047] 200-optical signal processing circuit;

[0048] 300-Image processor;

[0049] 400-Storage;

[0050] 10-Signal input node;

[0051] 20-Signal output node;

[0052] T1, T2, T3, T4, T5, T6, T7 - ​​transistors;

[0053] 11, 12, 13, 14 - comparators;

[0054] 21, 22, 23, 24 - operational amplifiers;

[0055] n1, n2 - circuit nodes;

[0056] ADC - analog-to-digital converter;

[0057] Vin-initial voltage signal;

[0058] Vout-digital output signal;

[0059] Vref1 is a first threshold voltage, Vref2 is a second threshold voltage, Vref3 is a third threshold voltage, and Vref4 is a fourth threshold voltage. DETAILED DESCRIPTION

[0060] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to make a clear and complete description of the technical solutions of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the described embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without any creative effort belong to the scope of protection of the present application. It can be understood that some technical means of the various embodiments described herein can be replaced or combined with each other without conflict.

[0061] In the description and claims of the present application, if there are terms "first", "second" and the like, they are only used to distinguish the described objects, and do not have any sequential or technical meaning. Therefore, the objects defined with "first", "second" and the like can explicitly or implicitly include one or more of the objects. And "one" or "an" and the like similar words do not represent a quantity limitation, but represent the existence of at least one.

[0062] Figure 1 The circuit block diagram of the optical signal processing device 1000 (hereinafter, sometimes referred to as the device 1000) provided by the embodiments of the present application is shown, which includes an optical signal conversion unit 100 and an optical signal processing circuit 200, wherein the optical signal conversion unit 100 is used to convert an optical signal into an initial voltage signal Vin which is an analog signal, and the optical signal processing circuit 200 can amplify the initial voltage signal Vin by a corresponding gear (multiplication factor) according to the size of the initial voltage signal Vin, and then convert the amplified analog signal into a digital signal and output it from a signal output node 20 thereof.

[0063] The optical signal conversion unit 100 can include a photosensitive device for receiving light irradiation and a coupling circuit electrically coupled with the photosensitive device. When light of different intensities irradiates the photosensitive device, the photosensitive device exhibits different electrical properties (for example, different resistance values), and the coupling circuit generates an initial voltage signal Vin related to the current light intensity by measuring the electrical property parameter of the photosensitive device in the current state, which is an analog voltage signal and positively related to the light intensity, that is, the greater the light intensity, the greater the initial voltage signal Vin, and the smaller the light intensity, the smaller the initial voltage signal Vin. However, the value of the initial voltage signal Vin is usually very small, so if it is directly input into an analog-to-digital converter ADC for analog-to-digital conversion, it is difficult to obtain ideal measurement accuracy of the optical signal.

[0064] The optical signal processing circuit 200 includes a signal input node 10 , transistors T1 , T2 , T3 , T4 , T5 , T6 , T7 , comparators 11 , 12 , 13 , 14 , operational amplifiers 21 , 22 , 23 , 24 , an analog-to-digital converter ADC, and a signal output node 20 .

[0065] The signal input node 10 is connected to the output end of the optical signal conversion unit 100 and is used to receive the initial voltage signal Vin converted from the optical signal.

[0066] Transistors T1, T3, T5, and T7 are N-type transistors, while transistors T2, T4, and T6 are P-type transistors. Transistors T1, T3, T5, and T7 are each connected to a signal input node 10 to receive an initial voltage signal Vin from the signal input node 10. Transistor T2 is connected in series with transistor T1, transistor T4 is connected in series with transistor T3, and transistor T6 is connected in series with transistor T5.

[0067] The comparator 11 has a non-inverting input connected to the signal input node 10, an inverting input connected to a first reference voltage node providing a threshold voltage Vref1, and an output connected to the gate of the transistor T1. In this embodiment, the first reference voltage node is a ground voltage node, and the threshold voltage Vref1 provided by the comparator 11 is a ground potential, i.e., zero volts. Therefore, for the comparator 11, when the voltage at the non-inverting input is greater than the voltage at the inverting input, that is, when the initial voltage signal Vin is greater than the threshold voltage Vref1, the output of the comparator 11 generates a high-level signal that is supplied to the gate of the transistor T1, turning on the transistor T1 and transmitting the initial voltage signal Vin to the transistor T2 via the transistor T1. When the voltage at the non-inverting input is not greater than the voltage at the inverting input, that is, when the initial voltage signal Vin is not greater than the threshold voltage Vref1, the output generates a low-level signal that is supplied to the gate of the transistor T1, turning off the transistor T1 and preventing the initial voltage signal Vin from being transmitted to the transistor T2 and the operational amplifier 21.

[0068] The non-inverting input of the comparator 12 is connected to the signal input node 10, the inverting input is connected to a second reference voltage node providing a threshold voltage Vref2, and the output is connected to the gate of the transistor T3. The threshold voltage Vref2 is greater than the threshold voltage Vrefl. Thus, for the comparator 12, when the voltage at the non-inverting input is greater than the voltage at the inverting input, i.e. the initial voltage signal Vin is greater than the threshold voltage Vref2, the output generates a high level signal supplied to the gate of the transistor T3, the transistor T3 is turned on, and the initial voltage signal Vin is transmitted to the transistor T4 via the transistor T3; and when the voltage at the non-inverting input is less than the voltage at the inverting input, i.e. the initial voltage signal Vin is less than the threshold voltage Vref2, for example, the initial voltage is Vrefl, the output generates a low level signal supplied to the gate of the transistor T3, the transistor T3 is turned off, and the initial voltage signal Vin cannot be transmitted to the transistor T4 and the operational amplifier 22.

[0069] The non-inverting input of the comparator 13 is connected to the signal input node 10, the inverting input is connected to a third reference voltage node providing a threshold voltage Vref3, and the output is connected to the gate of the transistor T5. The threshold voltage Vref3 is greater than the threshold voltage Vref2. Thus, for the comparator 13, when the voltage at the non-inverting input is greater than the voltage at the inverting input, i.e. the initial voltage signal Vin is greater than the threshold voltage Vref3, the output generates a high level signal supplied to the gate of the transistor T5, the transistor T5 is turned on, and the initial voltage signal Vin is transmitted to the transistor T6 via the transistor T5; and when the voltage at the non-inverting input is less than the voltage at the inverting input, i.e. the initial voltage signal Vin is less than the threshold voltage Vref3, for example, the initial voltage is Vrefl or Vref2, the output generates a low level signal supplied to the gate of the transistor T5, the transistor T5 is turned off, and the initial voltage signal Vin cannot be transmitted to the transistor T6 and the operational amplifier 23.

[0070] Comparator 14 has a non-inverting input connected to signal input node 10, an inverting input connected to a fourth reference voltage node providing a threshold voltage Vref4, and an output connected to the gate of transistor T7. Threshold voltage Vref4 is greater than threshold voltage Vref3. Therefore, for comparator 14, when the voltage at the non-inverting input is greater than the voltage at the inverting input, that is, when the initial voltage signal Vin is greater than threshold voltage Vref4, the output of comparator 14 generates a high-level signal that is supplied to the gate of transistor T7, turning on transistor T7 and transmitting the signal to the input of operational amplifier 24. When the voltage at the non-inverting input is less than the voltage at the inverting input, that is, when the initial voltage signal Vin is less than threshold voltage Vref4, for example, when the initial voltage is Vref1 or Vref2, the output generates a low-level signal that is supplied to the gate of transistor T7, turning off transistor T7 and preventing the initial voltage signal Vin from being transmitted to transistor T6 and operational amplifier 24.

[0071] The analog-to-digital converter ADC is configured to convert an analog signal supplied to an input terminal of the analog-to-digital converter ADC into a digital signal.

[0072] One input terminal of the operational amplifier 21 is connected to the transistor T2 , and the operational amplifier 21 is configured to amplify the initial voltage signal Vin output by the transistor T2 by a first preset multiple and then supply the amplified signal to the input terminal of the analog-to-digital converter ADC.

[0073] One input terminal of the operational amplifier 22 is connected to the transistor T4 , and the operational amplifier 22 is configured to amplify the initial voltage signal Vin output by the transistor T4 by a second preset multiple and then supply the amplified signal to the input terminal of the analog-to-digital converter ADC.

[0074] One input terminal of the operational amplifier 23 is connected to the transistor T6 , and the operational amplifier 23 is configured to amplify the initial voltage signal Vin output by the transistor T6 by a third preset multiple and then supply the amplified signal to the input terminal of the analog-to-digital converter ADC.

[0075] One input terminal of the operational amplifier 24 is connected to the transistor T7 and is configured to amplify the initial voltage signal Vin output by the transistor T7 by a fourth predetermined multiple and then supply the amplified signal to the input terminal of the analog-to-digital converter ADC. The first predetermined multiple, the second predetermined multiple, the third predetermined multiple, and the fourth predetermined multiple decrease in sequence.

[0076] As described above, when the initial voltage signal Vin is greater than the threshold voltage Vref4, transistors T1, T3, T5, and T7 are all in the on state, and therefore transistors T2, T4, and T6 all receive the initial voltage signal Vin. If transistors T2, T4, and T6 are all in the on state in this situation, operational amplifiers 21, 22, 23, and 24 will amplify the initial voltage signal Vin at different rates, making it difficult to determine the input voltage of the analog-to-digital converter (ADC), thereby affecting the accurate measurement of the current optical signal.

[0077] In view of this, please refer to Figure 1The embodiment also designs the optical signal circuit as follows: the gate of the transistor T2 is connected to the circuit node n1 between the transistor T3 and the transistor T4, the gate of the transistor T4 is connected to the circuit node n2 between the transistor T5 and the transistor T6, and the gate of the transistor T6 is connected to the output of the transistor T7, i.e. the drain of the transistor T7. Through the design, when the initial voltage signal Vin is greater than the threshold voltage Vref2 but less than the threshold voltage Vref3, the initial voltage signal Vin is also applied to the gate of the P-type transistor T2, so that the transistor T2 works in the off state. Thus, the initial voltage signal Vin cannot be transmitted to the input of the operational amplifier 21 via the transistor T2, but only transmitted to the input of the operational amplifier 22 via the conducting transistor T4. The initial voltage signal Vin is amplified by a second preset multiple via the operational amplifier 22, supplied to the input of the analog-to-digital converter ADC, converted into a digital output signal Vout of a corresponding size by the analog-to-digital converter ADC, and output via the signal output node 20, which can be the output terminal of the analog-to-digital converter ADC. Correspondingly, when the initial voltage signal Vin is greater than the threshold voltage Vref3 but less than the threshold voltage Vref4, the initial voltage signal Vin is applied to the gates of the P-type transistors T2 and T4, so that the transistors T2 and T4 both work in the off state. Thus, the initial voltage signal Vin cannot be transmitted to the input of the operational amplifier 21 via the transistor T2, nor to the input of the operational amplifier 22 via the transistor T4, but only transmitted to the input of the operational amplifier 23 via the conducting transistor T6. The initial voltage signal Vin is amplified by a third preset multiple via the operational amplifier 23, supplied to the input of the analog-to-digital converter ADC, converted into a digital output signal Vout of a corresponding size by the analog-to-digital converter ADC, and output via the signal output node 20. In addition, when the initial voltage signal Vin is greater than the threshold voltage Vref4, the initial voltage signal Vin is applied to the gates of the P-type transistors T2, T4 and T6, so that the transistors T2, T4 and T6 all work in the off state. Thus, the initial voltage signal Vin cannot be transmitted to the input of the operational amplifier 21 via the transistor T2, nor to the input of the operational amplifier 22 via the transistor T4, nor to the input of the operational amplifier 23 via the transistor T6, but only transmitted to the input of the operational amplifier 24 via the conducting transistor T7. The initial voltage signal Vin is amplified by a fourth preset multiple via the operational amplifier 24, supplied to the input of the analog-to-digital converter ADC, converted into a digital output signal Vout of a corresponding size by the analog-to-digital converter ADC, and output via the signal output node 20.

[0078] It can be understood that by setting the first preset multiple, the second preset multiple, the third preset multiple and the fourth preset multiple to decrease in sequence, when the initial voltage signal Vin is in different voltage intervals defined by the aforementioned four threshold voltages Vref1, Vref2, Vref3 and Vref4, the size of the analog voltage signal received by the analog-to-digital converter ADC can be within an appropriate range, and the digital output signal Vout output by the analog-to-digital converter ADC can be maintained within an appropriate range, thereby avoiding the voltage exceeding the range of the analog-to-digital converter ADC.

[0079] Please review Figure 1 The device 1000 further includes an image processor 300 connected to the signal output node 20, i.e., connected to the output terminal of the analog-to-digital converter ADC, and a memory 400 connected to the image processor 300. The image processor 300 is configured to generate a corresponding digital image signal based on the magnitude of the digital output signal Vout output by the analog-to-digital converter ADC. The memory 400 is used to store the aforementioned digital image signal. The digital image signal is a digital signal in an image format that can be read and displayed by a display device, such as a liquid crystal display.

[0080] Based on the above description, the embodiment of the present application further provides an optical signal processing method, which can be Figure 1 The optical signal processing device 1000 shown in the figure is particularly implemented by the optical signal processing circuit 200 in the device. Figure 2 , the method comprising:

[0081] S201 , obtaining an initial voltage signal Vin, where the initial voltage signal Vin is an analog signal converted from an optical signal.

[0082] As described above, the optical signal conversion unit 100 can be used to convert the optical signal into the initial voltage signal Vin.

[0083] S202 , if the initial voltage signal Vin is greater than the threshold voltage Vref1 and less than the second threshold voltage Vref2 , amplify the initial voltage signal Vin by a first preset multiple to obtain a first analog voltage signal, and input the first analog voltage signal into an analog-to-digital converter ADC;

[0084] S203, if the initial voltage signal Vin is greater than the threshold voltage Vref2 and less than the threshold voltage Vref3, amplifying the initial voltage signal Vin by a second preset multiple to obtain a second analog voltage signal, and inputting the second analog voltage signal into an analog-to-digital converter ADC, wherein the second preset multiple is less than the first preset multiple;

[0085] S204, if the initial voltage signal Vin is greater than the threshold voltage Vref3 and less than the threshold voltage Vref4, amplifying the initial voltage signal Vin by a third preset multiple to obtain a third analog voltage signal, and inputting the third analog voltage signal into an analog-to-digital converter ADC, wherein the third preset multiple is less than the second preset multiple;

[0086] S205, if the initial voltage signal Vin is greater than the threshold voltage Vref4, the initial voltage signal Vin is amplified by a fourth preset multiple to obtain a fourth analog voltage signal, and the fourth analog voltage signal is input into the analog-to-digital converter ADC, wherein the fourth preset multiple is smaller than the third preset multiple.

[0087] S206 , using the analog-to-digital converter ADC to output a digital output signal Vout representing the intensity of the optical signal.

[0088] In some embodiments, the threshold voltage Vref1, the threshold voltage Vref2, the threshold voltage Vref3 and the threshold voltage Vref4 are 0V, 1V, 1.8V and 3.3V respectively, and the first preset multiple, the first preset multiple, the first preset multiple and the first preset multiple are 100 times, 75 times, 50 times and 25 times respectively.

[0089] In addition, an embodiment of the present application further provides a computer-readable storage medium having program instructions stored therein. When the program instructions are executed by a computer, the above-mentioned optical signal processing method can be implemented.

[0090] In addition, an embodiment of the present application further provides a display screen testing device for testing the optical display performance of a display screen, such as a liquid crystal display screen, and includes the aforementioned optical signal conversion unit 100 and optical signal processing circuit 200. The optical signal conversion unit 100 of the display screen testing device may be an optical probe that detects light emitted by the display screen under a given driving voltage, thereby generating an initial voltage signal Vin supplied to a signal input node 10 of the optical signal processing circuit 200. Based on the magnitude of the initial voltage signal Vin, the optical signal processing circuit 200 selects one of the operational amplifiers 21, 22, 23, and 24, amplifies the signal at a corresponding magnification, and then transmits the signal to an analog-to-digital converter ADC. The analog-to-digital converter ADC then converts the signal into a digital output signal Vout of a corresponding magnitude, which is then transmitted to an analysis module of the display screen testing device. The analysis module then analyzes the optical display performance of the display screen under test based on the value of the digital output signal Vout.

Claims

1. An optical signal processing circuit, characterized in that: include: a signal input node, configured to receive an initial voltage signal converted from the optical signal, wherein the initial voltage signal is an analog signal; a first transistor connected to the signal input node and a second transistor connected in series with the first transistor, wherein the first transistor is configured to be turned on when the initial voltage signal is greater than a first threshold voltage and turned off when the initial voltage signal is not greater than the first threshold voltage; and the second transistor is configured to be turned on when the initial voltage signal is less than a second threshold voltage and turned off when the initial voltage signal is greater than the second threshold voltage, wherein the second threshold voltage is greater than the first threshold voltage; a third transistor connected to the signal input node and a fourth transistor connected in series with the third transistor, wherein the third transistor is configured to be turned on when the initial voltage signal is greater than the second threshold voltage and to be turned off when the initial voltage signal is less than the second threshold voltage; the fourth transistor is configured to be turned on when the initial voltage signal is less than a third threshold voltage and to be turned off when the initial voltage signal is greater than the third threshold voltage, the third threshold voltage being greater than the second threshold voltage; an analog-to-digital converter configured to convert an analog signal supplied thereto into a digital signal; a first operational amplifier, configured to amplify the initial voltage signal output by the second transistor by a first preset multiple and then supply the amplified voltage signal to the analog-to-digital converter; The second operational amplifier is configured to amplify the initial voltage signal output by the fourth transistor by a second preset multiple and then supply the amplified signal to the analog-to-digital converter, wherein the second preset multiple is smaller than the first preset multiple.

2. The circuit according to claim 1, wherein: Also includes: a fifth transistor connected to the signal input node and a sixth transistor connected in series with the fifth transistor, wherein the fifth transistor is configured to be turned on when the initial voltage signal is greater than the third threshold voltage and to be turned off when the initial voltage signal is less than the third threshold voltage; the sixth transistor is configured to be turned on when the initial voltage signal is less than a fourth threshold voltage and to be turned off when the initial voltage signal is greater than the fourth threshold voltage, wherein the fourth threshold voltage is greater than the third threshold voltage; a seventh transistor connected to the signal input node, the seventh transistor being configured to be turned on when the initial voltage signal is greater than a fourth threshold voltage and turned off when the initial voltage signal is less than the fourth threshold voltage, wherein the first threshold voltage, the second threshold voltage, the third threshold voltage, and the fourth threshold voltage increase in sequence; a third operational amplifier, configured to amplify the initial voltage signal output by the sixth transistor by a third preset multiple and then supply the amplified voltage signal to the analog-to-digital converter; a fourth operational amplifier, configured to amplify the initial voltage signal output by the seventh transistor by a fourth preset multiple and then supply the amplified voltage signal to the analog-to-digital converter; The first preset multiple, the second preset multiple, the third preset multiple and the fourth preset multiple decrease in sequence.

3. The circuit according to claim 2, characterized in that The first transistor, the third transistor, the fifth transistor, and the seventh transistor are N-type transistors, and the circuit further includes: A first comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a first reference voltage node providing the first threshold voltage; and an output terminal connected to the gate of the first transistor; a second comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a second reference voltage node providing the second threshold voltage; and an output terminal connected to the gate of the third transistor; a third comparator having: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a third reference voltage node providing the third threshold voltage; and an output terminal connected to the gate of the fifth transistor; The fourth comparator has: a non-inverting input terminal connected to the signal input node; an inverting input terminal connected to a fourth reference voltage node providing the fourth threshold voltage; and an output terminal connected to the gate of the seventh transistor.

4. The circuit according to claim 3, characterized in that The second transistor, the fourth transistor and the sixth transistor are P-type transistors, the gate of the second transistor is connected to the first circuit node between the third transistor and the fourth transistor, the gate of the fourth transistor is connected to the second circuit node between the fifth transistor and the sixth transistor, and the gate of the sixth transistor is connected to the output end of the seventh transistor.

5. The circuit according to claim 4, characterized in that The first threshold voltage is zero volts.

6. An optical signal processing device, characterized in that: include: The circuit according to any one of claims 1 to 5; The optical signal conversion unit includes a photosensor, and is configured to convert the optical signal into the initial voltage signal using the photosensor, and supply the initial voltage signal to the signal input node.

7. The device according to claim 6, characterized in that Also includes: The image processor is connected to the output terminal of the analog-to-digital converter and is configured to generate a corresponding digital image signal based on the size of the digital signal output by the analog-to-digital converter.

8. A method for processing an optical signal, characterized in that: include: Acquiring an initial voltage signal, wherein the initial voltage signal is an analog signal converted from an optical signal; If the initial voltage signal is greater than the first threshold voltage and less than the second threshold voltage, amplifying the initial voltage signal by a first preset multiple to obtain a first analog voltage signal, and inputting the first analog voltage signal into an analog-to-digital converter; If the initial voltage signal is greater than the second threshold voltage and less than the third threshold voltage, amplifying the initial voltage signal by a second preset multiple to obtain a second analog voltage signal, and inputting the second analog voltage signal into the analog-to-digital converter, wherein the second preset multiple is less than the first preset multiple; If the initial voltage signal is greater than the third threshold voltage and less than the fourth threshold voltage, amplifying the initial voltage signal by a third preset multiple to obtain a third analog voltage signal, and inputting the third analog voltage signal into the analog-to-digital converter, wherein the third preset multiple is less than the second preset multiple; If the initial voltage signal is greater than the fourth threshold voltage, amplifying the initial voltage signal by a fourth preset multiple to obtain a fourth analog voltage signal, and inputting the fourth analog voltage signal into the analog-to-digital converter, wherein the fourth preset multiple is less than the third preset multiple; The analog-to-digital converter is used to output a digital output signal representing the intensity of the optical signal.

9. The method according to claim 8, characterized in that The method is performed by the circuit according to any one of claims 1 to 5 or the device according to any one of claims 6 to 7.

10. A computer-readable storage medium storing program instructions, characterized in that: When the program instructions are executed by a computer, the method according to any one of claims 8 to 9 is implemented.

Images