High power factor and flicker-free LED linear constant current driver chip and circuit

Abstract

This invention relates to the field of LED constant current drive technology, and discloses a high power factor and flicker-free LED linear constant current drive chip and circuit. The circuit includes a voltage attenuation unit, a zero-crossing detection unit, a pulse voltage generation unit, an adder, a comparator, a pulse delay unit, an RS latch, a first current control unit, a second current control unit, switches S1, S2, S3, and S4, a rectifier unit, an energy storage capacitor CAP, and a start-up resistor RST. In practical use, since the charging current of the energy storage capacitor CAP in the start-up state is only about 10% of that in the steady state, even though the MOSFET Q1 bears the entire bus voltage VBUS during startup, the peak power consumption of the MOSFET Q1 is greatly attenuated due to the small current operation, improving the reliability of the control circuit. Once startup is complete and the circuit enters the steady state, the current returns to normal, so there is no impact in the steady state.

Description

Technical Field

[0001] This invention relates to the field of LED constant current drive technology, and more specifically to LED linear constant current drive chips and circuits with high power factor and no flicker. Background Technology

[0002] The 5th edition of the standard from the IEC Technical Subcommittee specifically stipulates that LED lighting products with a rated power of 5W≤P≤25W need to be tested for input harmonic current. The input current waveform requirements are as follows: before the conduction angle is 60°, the current must reach at least 5% of the current peak value; before 65°, the current must reach the maximum value; and at 90°, the current value must not be less than 5%.

[0003] To meet the above standards, the existing high-power frequencyless lightning circuit topology is as follows: Figure 1 As shown, it includes a rectifier bridge, a storage capacitor (CAP), a load (LED), and a control circuit unit. The control circuit unit includes a high-voltage power supply unit, a reference unit, a current control unit 1, a current control unit 2, a zero-crossing detection unit, a pulse voltage unit, and an adder.

[0004] for Figure 1 In the structure shown, the node voltage where the negative terminal of CAP is connected to the current control unit 1 is denoted as VCAP-, and the negative terminal of the LED is connected to the current control unit 2.

[0005] When the bus voltage (VBUS) is higher than the energy storage capacitor voltage, the input power supply charges the energy storage capacitor through the rectifier bridge. At the same time, because the bus voltage is also higher than the LED operating voltage (LED voltage drop), the bus voltage also supplies power to the LED.

[0006] When the bus voltage drops below the LED voltage drop, the positive terminal of CAP supplies current to the LED. This current returns to the negative terminal of CAP through the body diode of Q1 inside the current control unit 1. By setting a reasonable charging current, it can be ensured that CAP always supplies power to the LED until VBUS is higher than the voltage of CAP again, at which point the LED remains operational. Simultaneously, the negative terminal of the LED can also power the entire system, generating the necessary reference source.

[0007] Additionally, the current control unit 1 includes a MOSFET (Q1), an operational amplifier (EA1), and a sampling resistor (R). CS1 The current control unit 2 includes a MOSFET (Q2), an operational amplifier (EA2), and a sampling resistor (R). CS2 ).

[0008] The inverting input of EA1 is connected to the source of Q1 and R. CS1 One end, R CS1The other end is grounded. The output of EA1 is connected to the gate of Q1.

[0009] In the current control unit 1, the positive input terminal of EA1 is connected to the output terminal of the adder. EA1 controls the gate of Q1 to adjust the equivalent resistance of Q1, so that the voltage on the source of Q1 is always the voltage V at the positive input terminal of EA1. EA1+ R CS1 Under constant conditions, the charging current of CAP is controlled at V. EA1+ / R CS1 .

[0010] To ensure the current reaches its maximum value before the 65° phase angle, the control circuit unit samples VCAP- using a zero-crossing detection unit. When VCAP- is detected to have exceeded zero, the zero-crossing detection unit outputs a high-level signal, and the pulse voltage unit outputs a high-level pulse V. PULSE V PULSE And another benchmark V REF1 The values ​​are respectively passed to the two input terminals of the adder, and the output V of the adder is... REF1 +V PULSE The current is transmitted to the positive input terminal of EA1. Current control unit 1 controls the current flowing through CAP to (V... REF1 +V PULSE ) / R CS1 .

[0011] Due to V PULSE Since it is a pulse voltage, it presents a pulse current during CAP charging. This current is superimposed with the LED current (ILED for short) to become the input current, so the input current will exhibit a pulsed state to meet the phase requirements.

[0012] The positive input terminal of EA2 in current control unit 2 is connected to a fixed reference V. REF2 The output of EA controls the gate of Q2 to adjust the equivalent resistance of Q2. This ensures that, given a sufficient DRN voltage on Q1, the voltage at the source of the MOS transistor is always the reference at the positive input of EA. Thus, the current flowing through EA is V. REF2 / R CS2 Since the current flowing through the LED is the same as that of the MOSFET, the current flowing through the LED can be controlled. Figure 1 The waveforms of the relevant nodes during the use of the structure shown are as follows: Figure 2 As shown.

[0013] However, during startup, the capacitance of CAP cannot change abruptly and must rise from zero. Therefore, during startup, VBUS is fully loaded onto Q1 in the current control unit 1, causing the instantaneous power consumption of MOSFET Q1 to exceed the limit and Q1 to fail. Summary of the Invention

[0014] In view of the shortcomings of the prior art, the present invention provides a high power factor and flicker-free LED linear constant current drive chip and circuit. The problem to be solved is that in the existing high power factor and flicker-free LED linear constant current drive circuit, the transistor of the current control unit will fail due to high instantaneous power consumption during the startup process.

[0015] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a high power factor and flicker-free LED linear constant current drive chip, comprising a voltage attenuation unit, a zero-crossing detection unit, a pulse voltage generation unit, an adder, a comparator, a pulse delay unit, an RS latch, a first current control unit, a second current control unit, a switch S1, a switch S2, a switch S3, and a switch S4.

[0016] The input terminal of the first current control unit is electrically connected to the input terminal of the voltage attenuation unit and the detection terminal of the zero-crossing detection unit, respectively.

[0017] The output of the voltage attenuation unit is electrically connected to the negative input of the comparator CMP. The positive input of the comparator CMP is used to input the reference voltage VREF1. The output of the comparator CMP is electrically connected to the input of the pulse delay unit. The output of the pulse delay unit is electrically connected to the R input of the RS latch. The QN output of the RS latch is electrically connected to the control terminals of switch S1 and switch S3, respectively. The outputs of switches S1 and S2 are electrically connected to the control terminals of the first current control unit, respectively. The QP output of the RS latch is electrically connected to the control terminals of switch S2 and switch S4, respectively. The outputs of switches S3 and S4 are electrically connected to the control terminals of the second current control unit, respectively.

[0018] The output terminal of the zero-crossing detection unit is electrically connected to the input terminal of the pulse voltage generation unit. The output terminal of the pulse voltage generation unit is electrically connected to one input terminal of the adder. The other input terminal of the adder is used to input the reference voltage VREF2. The output terminal of the adder is electrically connected to the input terminal of switch S1. The input terminal of switch S2 is used to input the reference voltage VREF3. The input terminal of switch S3 is used to input the reference voltage VREF4. The input terminal of switch S4 is used to input the reference voltage VREF5.

[0019] In one embodiment of the first aspect, the present invention further includes a high-voltage power supply unit and a reference unit, wherein the input terminal of the high-voltage power supply unit is electrically connected to the input terminal of the second current control unit, and the reference unit is electrically connected to the output terminal of the high-voltage power supply unit, and reference voltages VREF1, VREF2, VREF3, VREF4 and VREF5 are generated based on the output voltage of the high-voltage power supply unit.

[0020] In one embodiment of the first aspect, the attenuation coefficient α of the voltage attenuation unit is less than 1.

[0021] In one embodiment of the first aspect, the delay time of the pulse delay unit is 30ms.

[0022] In one embodiment of the first aspect, the first current control unit includes an operational amplifier EA1, a MOSFET Q1, and a resistor RCS1. The positive terminal of the operational amplifier EA1 is the control terminal of the first current control unit, the negative terminal of the operational amplifier EA1 is electrically connected to the source of the MOSFET Q1 and grounded through the resistor RCS1, the output terminal of the operational amplifier EA1 is electrically connected to the gate of the MOSFET Q1, and the drain of the MOSFET Q1 is the input terminal of the first current control unit.

[0023] In one embodiment of the first aspect, the second current control unit includes an operational amplifier EA2, a MOSFET Q2, and a resistor RCS2. The positive terminal of the operational amplifier EA2 is the control terminal of the second current control unit, the negative terminal of the operational amplifier EA2 is electrically connected to the source of the MOSFET Q2 and grounded through the resistor RCS2, the output terminal of the operational amplifier EA2 is electrically connected to the gate of the MOSFET Q2, and the drain of the MOSFET Q2 is the input terminal of the second current control unit.

[0024] In one embodiment of the first aspect, both MOS transistors Q1 and Q2 are NMOS transistors.

[0025] In one embodiment of the first aspect, the switches S1, S2, S3 and S4 are all NMOS transistors.

[0026] In one embodiment of the first aspect, the output terminal of the high-voltage power supply unit is also grounded through an output capacitor.

[0027] Secondly, the present invention provides a high power factor and flicker-free LED linear constant current driving circuit, including the aforementioned high power factor and flicker-free LED linear constant current driving chip, and further including a rectifier unit, an energy storage capacitor CAP, and a starting resistor RST; the rectifier unit is used to convert the input AC power into DC power, the DC output terminal of the rectifier unit is electrically connected to the positive terminal of the energy storage capacitor CAP and one end of the starting resistor RST, the negative terminal of the energy storage capacitor CAP is electrically connected to the input terminal of the first current control unit, and the other end of the starting resistor RST is electrically connected to the input terminal of the second current control unit.

[0028] In actual use, when the bus voltage VBUS output by the rectifier unit after rectifying the input AC power exceeds the LED voltage drop, the voltage at the input terminal of the second current control unit rises to the working voltage. After the circuit starts, the output terminal of the reference unit outputs the reference voltage. The reference voltage VREF3 is 10% of the reference voltage VREF2, and the reference voltage VREF5 is 5% of the reference voltage VREF4.

[0029] Meanwhile, the QP and QN outputs of the RS latch are set to high and low levels by default, respectively; at this time, switches S2 and S4 are closed, and switches S1 and S3 are open. Reference voltages VREF3 and VREF5 are connected to the positive inputs of operational amplifiers EA1 and EA2, respectively. The first and second current control units control the charging current of the energy storage capacitor CAP and the current flowing through the LED to be relatively small, and the circuit is in the startup state at this time.

[0030] Meanwhile, since the initial voltage of the energy storage capacitor CAP is zero, the input terminal of the first current control unit bears all the bus voltage, i.e., Vcap-≈VBUS. The peak value of Vcap- is connected to the negative terminal of the comparator CMP after passing through the voltage attenuation unit. At this time, the input of the comparator CMP is low, and the pulse delay unit does not start.

[0031] During the decreasing phase of the bus voltage VBUS cycle, when the output of the voltage attenuation unit is less than the reference voltage VREF1, the comparator CMP output goes high, and the pulse delay unit starts timing. After the bus voltage VBUS becomes less than the LED voltage drop, the LED is in an off state, so the energy storage capacitor CAP is powered through the start-up resistor RST circuit. Because the LED current is much smaller during this phase than under normal operating conditions, the energy storage capacitor CAP will not drop rapidly due to powering the LED, preventing a rapid decrease in its voltage.

[0032] Since the pulse delay unit in the circuit is set to delay the output pulse by 30ms after activation, and the pulsating voltage period of the rectifier unit is between 8ms and 10.7ms, the pulsating voltage of the rectifier unit will definitely rise again during the delay phase. During this rise, the energy storage capacitor CAP will be charged again, and the voltage of the energy storage capacitor CAP will continue to increase within the second pulsating cycle of the peak value. If VCAP- is still greater than the reference voltage VREF1 after passing through the voltage attenuation unit within the second pulsating cycle, the comparator CMP output will return to a normal level, and the pulse delay unit will be reset. The charging current of the energy storage capacitor CAP remains small, the output current of the load also remains small, and the control circuit continues to operate in the startup state.

[0033] Until the voltage of the energy storage capacitor CAP increases to a level that keeps the output of the voltage attenuation unit below the reference voltage VREF1 during a certain pulse cycle, the comparator CMP will no longer output a high level and the RS latch will no longer be reset. After the pulse delay unit completes its delay, the output pulse is input to the R terminal of the RS latch as a high-level pulse. According to the RS latch principle, the output values ​​of QP and QN are inverted, switches S1 and S3 are closed, and switches S2 and S4 are opened. The positive input terminal of operational amplifier EA1 is connected to the output terminal of the adder, and the positive input terminal of operational amplifier EA2 is connected to the reference voltage VREF4. The operation then reverts to the existing control circuit mode, and the control circuit unit enters a stable state.

[0034] The beneficial effects of this invention compared to existing technologies are as follows: As can be seen from the operating state of the circuit described above, since the charging current of the energy storage capacitor CAP in the startup state is only about 10% of that in the steady state, even though the MOSFET Q1 bears the entire bus voltage VBUS during startup, the peak power consumption of the MOSFET Q1 is greatly attenuated due to the small current operation, thus improving the reliability of the control circuit. Once startup is complete and the circuit enters a steady state, the current returns to normal, so there is no impact in the steady state. Attached Figure Description

[0035] Figure 1 A schematic diagram of an existing high power factor and flicker-free LED linear constant current drive circuit;

[0036] Figure 2 Waveforms of relevant signals when the existing high power factor and flicker-free LED linear constant current drive circuit is working;

[0037] Figure 3 This is a schematic diagram of the structure of the high power factor and flicker-free LED linear constant current driver chip in the embodiment;

[0038] Figure 4 This is a schematic diagram of the high power factor and flicker-free LED linear constant current drive circuit and LED load in the embodiment.

[0039] Figure 5 for Figure 4 Waveforms of relevant nodes when the circuit is working. Detailed Implementation

[0040] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0041] Example 1

[0042] like Figure 3As shown, this embodiment provides a high power factor and flicker-free LED linear constant current driver chip, including a voltage attenuation unit 5, a zero-crossing detection unit 6, a pulse voltage generation unit 7, an adder 8, a comparator CMP, a pulse delay unit 9, an RS latch 10, a first current control unit 3, a second current control unit 4, a switch S1, a switch S2, a switch S3, and a switch S4.

[0043] The input terminal of the first current control unit 3 is electrically connected to the input terminal of the voltage attenuation unit 5 and the detection terminal of the zero-crossing detection unit 6, respectively.

[0044] The output of voltage attenuation unit 5 is electrically connected to the negative input of comparator CMP. The positive input of comparator CMP is used to input the reference voltage VREF1. The output of comparator CMP is electrically connected to the input of pulse delay unit 9. The output of pulse delay unit 9 is electrically connected to the R input of RS latch 10. The QN output of RS latch 10 is electrically connected to the control terminals of switch S1 and switch S3 respectively. The outputs of switch S1 and switch S2 are electrically connected to the control terminals of the first current control unit 3 respectively. The QP output of RS latch is electrically connected to the control terminals of switch S2 and switch S4 respectively. The outputs of switch S3 and switch S4 are electrically connected to the control terminals of the second current control unit 4 respectively.

[0045] The output terminal of the zero-crossing detection unit 6 is electrically connected to the input terminal of the pulse voltage generation unit 7. The output terminal of the pulse voltage generation unit 7 is electrically connected to one input terminal of the adder. The other input terminal of the adder is used to input the reference voltage VREF2. The output terminal of the adder 8 is electrically connected to the input terminal of switch S1. The input terminal of switch S2 is used to input the reference voltage VREF3. The input terminal of switch S3 is used to input the reference voltage VREF4. The input terminal of switch S4 is used to input the reference voltage VREF5.

[0046] In this embodiment, when the sampling voltage collected by the zero-crossing detection unit 5 exceeds zero, the zero-crossing detection unit 5 outputs a high level, and the pulse voltage generation unit 7 outputs a high-level pulse.

[0047] In this embodiment, as Figure 2As shown, the present invention also includes a high-voltage power supply unit 1 and a reference unit 2. The input terminal of the high-voltage power supply unit 1 is electrically connected to the input terminal of the second current control unit 4, and the reference unit 2 is electrically connected to the output terminal of the high-voltage power supply unit 1. Reference voltages VREF1, VREF2, VREF3, VREF4, and VREF5 are generated based on the output voltage of the high-voltage power supply unit 1. Furthermore, the output terminal of the high-voltage power supply unit 1 is grounded through an output capacitor. Reference voltage VREF3 is 10% of reference voltage VREF2, and reference voltage VREF5 is 5% of reference voltage VREF4.

[0048] It should be noted that either the high-voltage power supply unit 1 or the reference unit 2 in this embodiment is an existing circuit, and will not be described further here.

[0049] In this embodiment, the attenuation coefficient α of the voltage attenuation unit 5 is less than 1, meaning that the output voltage of the voltage attenuation unit 5 is less than its input voltage. For example, the attenuation coefficient α can be 0.8, 0.75, or 0.5. Furthermore, the specific structure of the voltage attenuation unit 5 will not be described further. Those skilled in the art can configure it based on a simple resistor divider circuit, or simply make sure that the input voltage is attenuated by a ratio less than 1 before being output.

[0050] In this embodiment, the delay time of the pulse delay unit 9 is 30ms.

[0051] exist Figure 2 In the first current control unit 3, there are operational amplifier EA1, MOSFET Q1 and resistor RCS1. The positive terminal of operational amplifier EA1 is the control terminal of the first current control unit 3. The negative terminal of operational amplifier EA1 is electrically connected to the source of MOSFET Q1 and grounded through resistor RCS1. The output terminal of operational amplifier EA1 is electrically connected to the gate of MOSFET Q1. The drain of MOSFET Q1 is the input terminal of the first current control unit 3.

[0052] exist Figure 2 In the second current control unit 4, there are operational amplifier EA2, MOSFET Q2 and resistor RCS2. The positive terminal of operational amplifier EA2 is the control terminal of the second current control unit 4. The negative terminal of operational amplifier EA2 is electrically connected to the source of MOSFET Q2 and grounded through resistor RCS2. The output terminal of operational amplifier EA2 is electrically connected to the gate of MOSFET Q2. The drain of MOSFET Q2 is the input terminal of the second current control unit 4.

[0053] In addition, in this embodiment, MOSFETs Q1 and Q2 are both NMOS transistors. Switches S1, S2, S3 and the on-state transistor S4 can also be NMOS transistors.

[0054] The principle and implementation effect of the chip in this example are explained in the circuit of Example 2, and will not be described in detail here.

[0055] Example 2

[0056] like Figure 4 As shown, this embodiment provides a high power factor and flicker-free LED linear constant current drive circuit, including the high power factor and flicker-free LED linear constant current drive chip in Embodiment 1, and also includes a rectifier unit 11, an energy storage capacitor CAP, and a starting resistor RST. The rectifier unit 11 is used to convert the input AC power into DC power. The DC output terminal of the rectifier unit 11 is electrically connected to the positive terminal of the energy storage capacitor CAP and one end of the starting resistor RST, respectively. The negative terminal of the energy storage capacitor CAP is electrically connected to the input terminal of the first current control unit 3, and the other end of the starting resistor RST is electrically connected to the input terminal of the second current control unit 4. An LED load branch 12 (hereinafter referred to as LED) is connected in parallel across the starting resistor RST.

[0057] In actual use, when the bus voltage VBUS output by the rectifier unit 11 after rectifying the input AC power exceeds the LED voltage drop, the voltage at the input terminal of the second current control unit 4 rises to the working voltage, that is, the voltage at node DRN rises to the working voltage. After the circuit starts, the output terminal of the reference unit 2 outputs the reference voltage VREF1-reference voltage VREF5.

[0058] Meanwhile, the QP and QN outputs of RS latch 10 are set to high and low levels by default, respectively; at this time, switches S2 and S4 are closed, and switches S1 and S3 are open. Reference voltages VREF3 and VREF5 are connected to the positive inputs of operational amplifiers EA1 and EA2, respectively. The first current control unit 3 and the second current control unit 4 control the charging current of the energy storage capacitor CAP and the current flowing through the LED to be relatively small. At this time, the circuit is in the startup state.

[0059] Meanwhile, since the initial voltage of the energy storage capacitor CAP is zero, the input terminal of the first current control unit 3 bears all the bus voltage, i.e., Vcap-≈VBUS. The peak value of Vcap- is connected to the negative terminal of the comparator CMP after passing through the voltage attenuation unit 5. At this time, the input of the comparator CMP is low, and the pulse delay unit 9 is not started.

[0060] During the decreasing phase of the bus voltage VBUS cycle, when the output of voltage attenuation unit 5 is less than the reference voltage VREF1, the comparator CMP output goes high, and the pulse delay unit 9 starts timing. After the bus voltage VBUS is less than the LED voltage drop, since the LED is in an off state, the energy storage capacitor CAP is powered through the start-up resistor RST circuit. Because the LED current is much smaller during this phase than under normal operating conditions, the energy storage capacitor CAP will not experience a rapid decrease in voltage due to powering the LED.

[0061] Since the pulse delay unit 9 in the circuit is set to delay the output pulse by 30ms after being activated, and the pulsating voltage period of the rectifier unit 11 is between 8ms and 10.7ms, the pulsating voltage of the rectifier unit 11 will definitely rise again during the delay phase, and the energy storage capacitor CAP will be charged again during the rising phase. The voltage of the energy storage capacitor CAP continues to increase within the second pulsating cycle of the peak. If VCAP- is still greater than the reference voltage VREF1 after passing through the voltage attenuation unit 5 within the second pulsating cycle, the comparator CMP output will return to the normal level, and the pulse delay unit will be reset. The charging current of the energy storage capacitor CAP is still a small current, the output current of the load is also a small current, and the control circuit still operates in the startup state.

[0062] Until the voltage of the energy storage capacitor CAP increases to a level that keeps the output of voltage attenuation unit 5 below the reference voltage VREF1 during a certain pulse cycle, comparator CMP will no longer output a high level and the RS latch will no longer be reset. After the pulse delay unit 9 completes its delay, the output pulse is input to the R terminal of the RS latch as a high-level pulse. According to the principle of the RS latch, the output values ​​of QP and QN at its output terminal are reversed, switches S1 and S3 are closed, and switches S2 and S4 are opened. The positive input terminal of operational amplifier EA1 is connected to the output terminal of adder 8, and the positive input terminal of operational amplifier EA2 is connected to the reference voltage VREF4. The operation mode then returns to the existing control circuit mode, and the control circuit unit enters a stable state.

[0063] From the operating states of the circuit described above, we can see that since the charging current of the energy storage capacitor CAP in the startup state is only about 10% of that in the steady state, even though the MOSFET Q1 bears the entire bus voltage VBUS during startup, the peak power consumption of the MOSFET Q1 is greatly attenuated due to the small current operation, thus improving the reliability of the control circuit. Once startup is complete and the circuit enters the steady state, the current returns to normal, so there is no impact in the steady state.

[0064] The circuit of this invention was simulated, and the signal waveforms of the relevant nodes are shown below. Figure 5 As shown, for Figure 2 and Figure 5The comparison is as follows:

[0065] first Figure 5 The input voltage and input current are the instantaneous voltage and instantaneous current of the input AC power, the LED current is the current flowing through the LED load branch 12, and the CAP current is the current flowing through the energy storage capacitor CAP. CAP- The voltage across the negative terminal of the energy storage capacitor CAP is the instantaneous power consumption of MOSFET Q1.

[0066] exist Figure 2 In the instantaneous power dissipation curve of MOSFET Q1, each unit on the vertical axis represents 5W. When the input AC voltage is applied, the power loss of MOSFET Q1 in existing circuits is significant. The maximum power dissipation after startup is approximately 35W (about 7 units), and after stabilization, it drops to about 1.6W (about 1 / 3 unit). Comparing the instantaneous power dissipation during startup and stabilization, the former is about 21 times the latter. In practical applications, existing product control circuits must add external protection devices for MOSFET Q1; otherwise, it is extremely easy for the MOSFET to break down once it is turned on.

[0067] exist Figure 5 In the instantaneous power consumption curve of MOSFET Q1, each unit on the vertical axis represents 0.5W. In the startup to steady-state phase, the maximum power consumption after startup is approximately 4.5W (9 units), and after stabilization, it is approximately 1.6W (3.3 units). The maximum instantaneous power consumption of MOSFET Q1 during startup is only 2.7 times that of steady-state instantaneous power consumption, which greatly reduces the instantaneous power consumption during startup and ensures the reliability of the circuit.

[0068] Furthermore, after entering the steady-state phase, the input current and load current of the control circuit of this invention are no different from those of existing products, meeting the input current waveform requirements, and the output current in the steady-state state has no ripple current, also meeting the flicker-free requirement. In other words, the added control circuit portion in this invention has no impact on the steady-state state.

[0069] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A high power factor and flicker-free LED linear constant current driver chip, characterized in that, It includes a voltage attenuation unit, a zero-crossing detection unit, a pulse voltage generation unit, an adder, a comparator, a pulse delay unit, an RS latch, a first current control unit, a second current control unit, and switches S1, S2, S3, and S4. The input terminal of the first current control unit is electrically connected to the input terminal of the voltage attenuation unit and the detection terminal of the zero-crossing detection unit, respectively. The output terminal of the voltage attenuation unit is electrically connected to the negative input terminal of the comparator CMP. The positive input terminal of the comparator CMP is used to input the reference voltage VREF1. The output terminal of the comparator CMP is electrically connected to the input terminal of the pulse delay unit. The output terminal of the pulse delay unit is electrically connected to the R input terminal of the RS latch. The QN output terminal of the RS latch is electrically connected to the control terminals of switch S1 and switch S3, respectively. The QP output terminal of the RS latch is electrically connected to the control terminals of switch S2 and switch S4, respectively. The output terminals of switches S1 and S2 are electrically connected to the control terminals of the first current control unit, respectively. The output terminals of switches S3 and S4 are electrically connected to the control terminals of the second current control unit, respectively. The output terminal of the zero-crossing detection unit is electrically connected to the input terminal of the pulse voltage generation unit. The output terminal of the pulse voltage generation unit is electrically connected to one input terminal of the adder. The other input terminal of the adder is used to input the reference voltage VREF2. The output terminal of the adder is electrically connected to the input terminal of switch S1. The input terminal of switch S2 is used to input the reference voltage VREF3. The input terminal of switch S3 is used to input the reference voltage VREF4. The input terminal of switch S4 is used to input the reference voltage VREF5.

2. The high power factor and flicker-free LED linear constant current driver chip according to claim 1, characterized in that, It also includes a high-voltage power supply unit and a reference unit. The input terminal of the high-voltage power supply unit is electrically connected to the input terminal of the second current control unit, and the reference unit is electrically connected to the output terminal of the high-voltage power supply unit. Reference voltages VREF1, VREF2, VREF3, VREF4, and VREF5 are generated based on the output voltage of the high-voltage power supply unit.

3. The high power factor and flicker-free LED linear constant current driver chip according to claim 1, characterized in that, The attenuation coefficient α of the voltage attenuation unit is less than 1.

4. The high power factor and flicker-free LED linear constant current driver chip according to claim 1, characterized in that, The delay time of the pulse delay unit is 30ms.

5. The high power factor and flicker-free LED linear constant current driver chip according to claim 1, characterized in that, The first current control unit includes an operational amplifier EA1, a MOSFET Q1, and a resistor RCS1. The positive terminal of the operational amplifier EA1 is the control terminal of the first current control unit. The negative terminal of the operational amplifier EA1 is electrically connected to the source of the MOSFET Q1 and grounded through the resistor RCS1. The output terminal of the operational amplifier EA1 is electrically connected to the gate of the MOSFET Q1, and the drain of the MOSFET Q1 is the input terminal of the first current control unit.

6. The high power factor and flicker-free LED linear constant current driver chip according to claim 5, characterized in that, The second current control unit includes an operational amplifier EA2, a MOSFET Q2, and a resistor RCS2. The positive terminal of the operational amplifier EA2 is the control terminal of the second current control unit. The negative terminal of the operational amplifier EA2 is electrically connected to the source of the MOSFET Q2 and grounded through the resistor RCS2. The output terminal of the operational amplifier EA2 is electrically connected to the gate of the MOSFET Q2, and the drain of the MOSFET Q2 is the input terminal of the second current control unit.

7. The high power factor and flicker-free LED linear constant current driver chip according to claim 6, characterized in that, Both MOS transistors Q1 and Q2 are NMOS transistors.

8. The high power factor and flicker-free LED linear constant current driver chip according to claim 1, characterized in that, The switches S1, S2, S3 and S4 are all NMOS transistors.

9. The high power factor and flicker-free LED linear constant current driver chip according to claim 2, characterized in that, The output terminal of the high-voltage power supply unit is also grounded through an output capacitor.

10. A high power factor and flicker-free LED linear constant current drive circuit, characterized in that, The LED linear constant current driver chip with high power factor and no flicker as described in any one of claims 1-9 further includes a rectifier unit, an energy storage capacitor CAP, and a start-up resistor RST; the rectifier unit is used to convert the input AC power into DC power, the DC output terminal of the rectifier unit is electrically connected to the positive terminal of the energy storage capacitor CAP and one end of the start-up resistor RST, the negative terminal of the energy storage capacitor CAP is electrically connected to the input terminal of the first current control unit, and the other end of the start-up resistor RST is electrically connected to the input terminal of the second current control unit.

Images