A capacitor assembly, power assembly and converter

Abstract

The application provides a capacitor assembly, a power assembly and a converter. In the capacitor assembly, the first ends of a plurality of capacitors of a positive capacitor array and a positive terminal are connected to a positive conduction path, the second ends of the plurality of capacitors of the positive capacitor array and a negative terminal are connected to a negative conduction path, the second ends of the plurality of capacitors of the positive capacitor array, the first ends of the plurality of capacitors of a negative capacitor array and a transfer terminal are connected to a second conduction path, and the neutral terminal and the transfer terminal are connected to a third conduction path, so that for the positive capacitor array, the commutation paths of the positive terminal after passing through each capacitor to the neutral terminal are equal in length, and for the negative capacitor array, the commutation paths of the negative terminal after passing through each capacitor to the neutral terminal are equal in length. The second conduction path and the third conduction path are respectively located in different wiring layers, so that current sharing between the capacitors of the positive capacitor array and current sharing between the capacitors of the negative capacitor array are realized, and wiring is facilitated.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese patent application filed on March 28, 2024, with application number 202410363349.5 and entitled "A capacitor assembly, power assembly and converter with multiple capacitors in parallel", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of integrated circuit technology, and in particular to a capacitor assembly, a power assembly, and a converter. Background Technology

[0004] In the power supply field, capacitors are commonly used to improve circuit stability and reduce noise, especially in inverters and uninterruptible power supplies (UPS). Using capacitors as bus capacitors not only filters out high-frequency noise but also provides a stable power supply voltage, making them widely applicable. To meet the demand for large capacitance values, multiple capacitors are often connected in parallel. When multiple capacitors are connected in parallel, improving the current sharing among them is a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a capacitor assembly, a power assembly, and a converter.

[0006] In a first aspect, embodiments of this application provide a capacitor assembly, the capacitor assembly including a capacitor pool disposed on a printed circuit board and terminal groups and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal groups include a positive terminal, a neutral terminal and a negative terminal, the capacitor pool includes at least one positive capacitor array and at least one negative capacitor array, the positive capacitor array and the negative capacitor array include multiple capacitors connected in parallel;

[0007] The first terminals of the multiple capacitors in the positive capacitor array and the positive terminal are all connected to a positive conduction path, and the second terminals of the multiple capacitors in the negative capacitor array and the negative terminal are all connected to a negative conduction path. The first conduction path includes the positive conduction path and / or the negative conduction path. The second terminals of the multiple capacitors in the positive capacitor array, the first terminals of the multiple capacitors in the negative capacitor array, and the transfer terminal are all connected to a second conduction path. The neutral terminal and the transfer terminal are all connected to a third conduction path, so that for the positive capacitor array, the commutation path from the positive terminal to the neutral terminal after passing through each capacitor is of equal length, and for the negative capacitor array, the commutation path from the negative terminal to the neutral terminal after passing through each capacitor is of equal length.

[0008] The printed circuit board comprises a plurality of wiring layers, and the second conduction path and the third conduction path are located in different wiring layers.

[0009] In some embodiments, the positive conduction path, the second conduction path and the third conduction path are located in different wiring layers, and the positive conduction path and the negative conduction path are located in the same wiring layer.

[0010] The plurality of wiring layers comprises a first wiring layer, a second wiring layer and a third wiring layer, the first wiring layer comprises a first wiring area and a second wiring area, the second wiring layer comprises a third wiring area, and the third wiring layer comprises a fourth wiring area; the positive terminal is electrically connected with the first wiring area, the negative terminal is electrically connected with the second wiring area, the transit terminal is electrically connected with the third wiring area, and the transit terminal and the neutral terminal are electrically connected with the fourth wiring area.

[0011] In some embodiments, the minimum area among the area of the first wiring area, the area of the second wiring area, the area of the third wiring area and the area of the fourth wiring area corresponds to the minimum current carrying value of the capacitor assembly.

[0012] In some embodiments, the plurality of wiring layers further comprises a fourth wiring layer and a fifth wiring layer.

[0013] The third conduction path is located in the fourth wiring layer, and the second conduction path is located in the fifth wiring layer; the positive conduction path comprises a first sub-path located in the fourth wiring layer and a second sub-path located in the fifth wiring layer, and the first sub-path and the second sub-path are connected in parallel; the negative conduction path comprises a third sub-path located in the fourth wiring layer and a fourth sub-path located in the fifth wiring layer, and the third sub-path and the fourth sub-path are connected in parallel.

[0014] In some embodiments, the fourth wiring layer comprises a fifth wiring area, a sixth wiring area and a seventh wiring area, and the fifth wiring layer comprises an eighth wiring area, a ninth wiring area and a tenth wiring area.

[0015] The positive terminal is electrically connected with the fifth wiring area and the eighth wiring area, the negative terminal is electrically connected with the seventh wiring area and the tenth wiring area, the transit terminal is electrically connected with the ninth wiring area, and the transit terminal and the neutral terminal are electrically connected with the sixth wiring area.

[0016] In some embodiments, in the fourth wiring layer, the fifth wiring area, the sixth wiring area and the seventh wiring area all extend along a first direction, and the fifth wiring area, the sixth wiring area and the seventh wiring area are arranged in sequence along a second direction; in the fifth wiring layer, the eighth wiring area, the ninth wiring area and the tenth wiring area all extend along the first direction, and the eighth wiring area, the ninth wiring area and the tenth wiring area are arranged in sequence along the second direction.

[0017] The projection of the fifth wiring area and the eighth wiring area along a third direction overlaps, the projection of the sixth wiring area and the ninth wiring area along the third direction overlaps, and the projection of the seventh wiring area and the tenth wiring area along the third direction overlaps.

[0018] The first direction and the second direction are in a plane in which the printed circuit board is located, and the third direction is perpendicular to the plane in which the printed circuit board is located.

[0019] In some embodiments, the minimum area among the sum of the areas of the fifth wiring area and the eighth wiring area, the sum of the areas of the seventh wiring area and the tenth wiring area, the area of the sixth wiring area and the area of the ninth wiring area corresponds to the minimum current carrying value of the capacitor assembly.

[0020] In some embodiments, the positive terminal is a first terminal of a first capacitor in the positive capacitor array; the negative terminal is a second terminal of a first capacitor in the negative capacitor array; the relay terminal is a second terminal of a last capacitor in the positive capacitor array, and / or the relay terminal is a first terminal of a last capacitor in the negative capacitor array.

[0021] The first capacitor and the last capacitor are the two capacitors farthest apart in the positive capacitor array and / or in the negative capacitor array.

[0022] In a second aspect, the embodiments of the present application provide a power assembly, which comprises a power conversion circuit and the capacitor assembly according to any one of the first aspect, and the power conversion circuit is connected to the capacitor assembly through the terminal group.

[0023] In a third aspect, the embodiments of the present application provide a converter, which comprises the capacitor assembly according to any one of the first aspect, or the power assembly according to the second aspect.

[0024] The embodiment of the present application provides a capacitor assembly, a power assembly and a converter, the capacitor assembly comprises a capacitor bank arranged on a printed circuit board and a terminal group and a transfer terminal respectively located on opposite sides of the capacitor bank; the terminal group comprises a positive terminal, a neutral terminal and a negative terminal, the capacitor bank comprises at least one positive capacitor array and at least one negative capacitor array, the positive capacitor array and the negative capacitor array comprise a plurality of capacitors connected in parallel; the first ends of the plurality of capacitors of the positive capacitor array and the positive terminal are connected to a positive conduction path, the second ends of the plurality of capacitors of the negative capacitor array and the negative terminal are connected to a negative conduction path, the first conduction path comprises the positive conduction path and / or the negative conduction path, the second ends of the plurality of capacitors of the positive capacitor array, the first ends of the plurality of capacitors of the negative capacitor array and the transfer terminal are connected to a second conduction path, and the neutral terminal and the transfer terminal are connected to a third conduction path, so that for the positive capacitor array, the commutation paths of the positive terminal after passing through each capacitor to the neutral terminal are equal in length, and for the negative capacitor array, the commutation paths of the negative terminal after passing through each capacitor to the neutral terminal are equal in length; wherein the printed circuit board comprises a plurality of wiring layers, and the second conduction path and the third conduction path are located on different wiring layers. In this way, by arranging the transfer terminal on the opposite side of the terminal group, and by the positive capacitor array and the negative capacitor array sharing the three connecting terminals in the terminal group and sharing the second conduction path and the third conduction path, for the positive capacitor array and / or the negative capacitor array, the commutation paths after passing through each capacitor are equal in length, so that the equivalent impedance on the conduction path is equal, the current sharing between the capacitors in the positive capacitor array and the current sharing between the capacitors in the negative capacitor array are realized, meanwhile, the connection paths between the capacitors are reduced, and the wiring difficulty is reduced; in addition, by distributing the second conduction path and the third conduction path on different wiring layers, the wiring can be realized in a three-dimensional staggered layer in the direction perpendicular to the board surface of the printed circuit board, so that the current sharing is realized under the condition that the board surface area is constrained, and the wiring is facilitated. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A connection equivalent diagram of a capacitor assembly provided by the embodiment of the present application Figure 1

[0026] Figure 2 A connection equivalent diagram of a capacitor assembly provided by the embodiment of the present application Figure 2

[0027] Figure 3 A structure diagram of a printed circuit board of a capacitor assembly provided by the embodiment of the present application Figure 1

[0028] Figure 4 A structure diagram of a printed circuit board of a capacitor assembly provided by the embodiment of the present application Figure 2

[0029] Figure 5 ​​​​A power component schematic diagram provided for an embodiment of the present application;

[0030] Figure 6 A power component schematic diagram provided for an embodiment of the present application with multiple conversion bridge arms Figure 1 ;

[0031] Figure 7 A power component schematic diagram provided for an embodiment of the present application with multiple conversion bridge arms Figure 2 ;

[0032] Figure 8 A T-type three-level bridge arm schematic diagram provided for an embodiment of the present application;

[0033] Figure 9 An I-type three-level bridge arm schematic diagram provided for an embodiment of the present application;

[0034] Figure 10 A T-type three-level bridge arm rectangular layout schematic diagram provided for an embodiment of the present application;

[0035] Figure 11 A T-type three-level bridge arm rhombus layout schematic diagram provided for an embodiment of the present application;

[0036] Figure 12 An I-type three-level bridge arm layout schematic diagram provided for an embodiment of the present application Figure 1 ;

[0037] Figure 13 An I-type three-level bridge arm layout schematic diagram provided for an embodiment of the present application Figure 2 ;

[0038] Figure 14 An I-type three-level bridge arm layout schematic diagram provided for an embodiment of the present application Figure 3 ;

[0039] Figure 15 An I-type three-level bridge arm layout schematic diagram provided for an embodiment of the present application Figure 4 ;

[0040] Figure 16 A conversion component structure schematic diagram provided for an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. It can be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, it should be noted that, for the convenience of description, only the parts related to the application are shown in the drawings. Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as those commonly understood by the person skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application. In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subset of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first", "second", "third" involved in the embodiments of the present application are only used to distinguish similar objects, and do not represent a specific order of the objects. It can be understood that "first", "second", "third" can be interchanged in a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described.

[0042] IGBT (Insulated Gate Bipolar Transistor): Insulated Gate Bipolar Transistor

[0043] MOS (Metal-Oxide-Semiconductor Field-Effect Transistor): Metal-Oxide-Semiconductor Field-Effect Transistor

[0044] BJT (Bipolar Junction Transistor): Bipolar Junction Transistor

[0045] HBT (Hetero Junction Bipolar Transistor): Hetero Junction Bipolar Transistor

[0046] The embodiments of the present application will be described in detail below with reference to the drawings.

[0047] In an embodiment of the present application, a capacitor assembly is provided, which includes a capacitor bank arranged on a printed circuit board, and a terminal group and a transfer terminal respectively arranged on opposite sides of the capacitor bank. The terminal group includes a first terminal and a second terminal. The capacitor bank includes at least one capacitor array. Each capacitor array includes a plurality of capacitors connected in parallel. The first ends of the plurality of capacitors are connected to a first conduction path, and the second ends of the plurality of capacitors are connected to a second conduction path. The second terminal and the transfer terminal are connected to a third conduction path, so that the commutation path of the first terminal through each capacitor of the capacitor to the second terminal is equal in length.

[0048] In this embodiment, the connection relationship of the capacitor components is equivalent to: Figure 1 As shown, the first terminal 11 and the second terminal 12 are used to connect the capacitor assembly to other external components. Multiple capacitors C1 are connected in parallel to form a capacitor array. The first end of each capacitor C1 is connected to the first terminal 11 via a first conductive path 21, and the second end of each capacitor C1 is connected to a relay terminal 13 via a second conductive path 22. The relay terminal 13 is connected to the second terminal 12 via a third conductive path 23. Figure 1 As can be seen in the diagram, the path length of each capacitor C1 through the first conduction path 21 is the same as the sum of the lengths through the second conduction path 22 and the third conduction path 23. That is, the commutation path from the first terminal 11 through each capacitor C1 to the second terminal 12 is of equal length. As a result, the equivalent impedance on the conduction path of different capacitors is equal, thereby ensuring that the current flowing through each capacitor C1 is equal.

[0049] Furthermore, by connecting multiple small capacitors in parallel to form a large capacitor of a preset capacitance value, the stray inductance of a capacitor is proportional to the pin spacing. Since the small package size of the small capacitors results in low stray inductance for each individual capacitor, experimental data shows that the stray inductance of the large capacitor is greater than that of the equivalent large capacitor formed by connecting multiple small capacitors in parallel. This demonstrates that connecting multiple small capacitors in parallel can further reduce stray inductance and reduce device reverse peaks. Additionally, the placement of each small capacitor can be flexibly chosen, providing greater freedom in PCB layout.

[0050] In another embodiment of this application, the capacitor assembly includes a capacitor pool disposed on a printed circuit board and terminal groups and a transfer terminal respectively located on opposite sides of the capacitor pool; the terminal groups include a positive terminal, a neutral terminal and a negative terminal, and the capacitor pool includes at least one positive capacitor array and at least one negative capacitor array, the positive capacitor array and the negative capacitor array including multiple capacitors connected in parallel;

[0051] The first terminals and positive terminals of multiple capacitors in the positive capacitor array are connected to the positive conduction path, and the second terminals and negative terminals of multiple capacitors in the negative capacitor array are connected to the negative conduction path. The first conduction path includes a positive conduction path and / or a negative conduction path. The second terminals of multiple capacitors in the positive capacitor array, the first terminals of multiple capacitors in the negative capacitor array, and the intermediate terminals are all connected to the second conduction path. The neutral terminal and the intermediate terminals are all connected to the third conduction path, so that for the positive capacitor array, the commutation path from the positive terminal to the neutral terminal after passing through each capacitor is of equal length, and for the negative capacitor array, the commutation path from the negative terminal to the neutral terminal after passing through each capacitor is of equal length.

[0052] The printed circuit board includes multiple wiring layers, with the second and third conductive paths located on different wiring layers.

[0053] In the embodiment, the connection relationship of the capacitor assembly is equivalent to as shown in Figure 2 , which comprises at least one positive capacitor array (comprising a plurality of capacitors C1, hereinafter denoted as C1) and at least one negative capacitor array (comprising a plurality of capacitors C2, hereinafter denoted as C2). For the positive capacitor array C1, the positive terminal BUS+ and the neutral terminal N are equivalent to the first terminal 11 and the second terminal 12 of the capacitor assembly in the last embodiment Figure 1 , the positive conduction path 21 is equivalent to the first conduction path 21 of the last embodiment, the second conduction path 22 is equivalent to the second conduction path 22 of the last embodiment, the third conduction path 23 is equivalent to the third conduction path 23 of the last embodiment, and the transit end (i.e., the N line bus point in the figure) is equivalent to the transit end 13 of the last embodiment. For the negative capacitor array C2, the negative terminal BUS- and the neutral terminal N in the embodiment are equivalent to the first terminal 11 and the second terminal 12 in the last embodiment, the negative conduction path 24 is equivalent to the first conduction path 21 in the last embodiment, the second conduction path 22 is equivalent to the second conduction path 22 in the last embodiment, the third conduction path 23 is equivalent to the third conduction path 23 in the last embodiment, and the transit end (i.e., the N line bus point in the figure) is equivalent to the transit end 13 in the last embodiment. It can be seen that in the embodiment, two capacitor arrays in the last embodiment are connected in series, and the connection relationship and Figure 2 It can also be seen that in the embodiment, the positive capacitor array C1 and the negative capacitor array C2 are connected in series, and the positive capacitor array and the negative capacitor array share three connection terminals (the positive terminal BUS+, the neutral terminal N, and the negative terminal BUS-), and also share the second conduction path 22 and the third conduction path 23 on the conduction path, thereby achieving current sharing among the capacitors of the positive capacitor array C1 and the capacitors of the negative capacitor array C2, and reducing the connection paths among the capacitors and the wiring difficulty.

[0054] It should be noted that the second conduction path 22 and the third conduction path 23 are distributed in different wiring layers, which can facilitate wiring. Specifically, since current sharing needs to be achieved, the transit end is added during actual wiring, and thus the corresponding lines need to occupy more board surface area of the printed circuit board compared to the case where current sharing is not achieved. However, by arranging the second conduction path 22 and the third conduction path 23 in different wiring layers, the lines can be arranged in a three-dimensional staggered manner in a direction perpendicular to the board surface of the printed circuit board, thereby achieving current sharing under the condition that the board surface area is constrained. Further, according to actual conditions, the positive conduction path and / or the negative conduction path can be distributed in the corresponding wiring layer, thereby saving the board surface area of the printed circuit board.

[0055] In some embodiments, the positive conduction path 21, the second conduction path 22, and the third conduction path 23 are located in different wiring layers, while the positive conduction path 21 and the negative conduction path 24 are located in the same wiring layer.

[0056] The multi-layer cabling system includes a first cabling layer, a second cabling layer, and a third cabling layer. The first cabling layer includes a first cabling area and a second cabling area. The second cabling layer includes a third cabling area. The third cabling layer includes a fourth cabling area. The positive terminal is electrically connected to the first cabling area, the negative terminal is electrically connected to the second cabling area, the intermediate terminal is electrically connected to the third cabling area, and the intermediate terminal and the neutral terminal are electrically connected to the fourth cabling area.

[0057] The PCB layout in this embodiment is as follows: Figure 3 As shown. Figure 3 The diagram illustrates a capacitor pool composed of multiple capacitors 1, and terminal groups (including positive terminal 11, negative terminal 14, and neutral terminal 12) and a transfer terminal 13 located on both sides of the capacitor pool. Figure 3 As can be seen, the terminal group is located on the left side of the capacitor pool along the first direction, while the intermediate terminal 13 is located on the right side of the capacitor pool along the first direction. That is, the terminal group and the intermediate terminal are located on opposite sides of the capacitor pool. The multiple capacitors 1 constituting the capacitor pool are divided into a positive capacitor array and a negative capacitor array. Figure 3 Images (a), (b), and (c) show the wiring diagrams for different wiring layers of the PCB board. Positive conduction path 21 and negative conduction path 24 are located on the same wiring layer. Figure 3 As shown in (a), the second conduction path 22 and the third conduction path 23 are located in two other wiring layers, as shown in Figure 23. Figure 3 (b) Figure 3 As shown in (c) in the figure.

[0058] Specifically, by Figure 3 As can be seen in (a), the positive terminal 11 (i.e., the corresponding...) Figure 2 The BUS+) and the first terminal of each capacitor 1 in the positive capacitor array are connected to the positive conduction path 21 (the two pins of capacitor 1). The small white dot inside the conduction path indicates a connection to the corresponding conduction path, and the black ring dot indicates a non-connection to the conduction path. Figure 3 As shown in (a), the 15 capacitors 1 on the upper side of the PCB board are a positive capacitor array, and the negative terminal 14 (i.e., corresponding to...) Figure 2 The first terminal of each capacitor 1 in the BUS- array and the negative capacitor array is connected to the negative conduction path 24 (from...). Figure 3 As shown in (a), the 15 capacitors distributed on the lower side of the PCB board are a negative capacitor array; Figure 3 As can be seen in (b), the second terminal of each capacitor 1 in the positive capacitor array, the first terminal of each capacitor 1 in the negative capacitor array, and the relay terminal 13 are all connected to the second conduction path 22;Figure 3 As can be seen in (c), the neutral terminal 12 and the transfer terminal 13 are connected through the third conductive path 23.

[0059] It should be noted that, Figure 3 (a) in the diagram represents the first wiring layer. Figure 3 (b) in the diagram represents the second wiring layer. Figure 3 In the diagram, (c) represents the third routing layer. Furthermore, the first, second, and third routing layers can be any three of a plurality of routing layers. The positional relationship between the first, second, and third routing layers is not limited. For example, the third routing layer is located above the second routing layer, and the second routing layer is located above the first routing layer.

[0060] It should also be noted that, such as Figure 3 As shown, region a1 represents the first wiring area, region a2 represents the second wiring area, region a3 represents the third wiring area, and region a4 represents the fourth wiring area. Positive conduction path 21 passes through the first wiring area (a1), negative conduction path 24 passes through the second wiring area (a2), second conduction path 22 passes through the third wiring area (a3), and third conduction path 23 passes through the fourth wiring area (a4). Furthermore, each wiring area can be composed of copper foil from the PCB board.

[0061] In some embodiments, the minimum area among the areas of the first wiring area (a1), the second wiring area (a2), the third wiring area (a3), and the fourth wiring area (a4) corresponds to the minimum current carrying value of the capacitor component.

[0062] like Figure 3 As shown, the areas of the first wiring area (a1) and the second wiring area (a2) are smaller than the areas of the third wiring area (a3) ​​and the fourth wiring area (a4). For example, the areas of the first wiring area (a1) and the second wiring area (a2) are equal, and the areas of the third wiring area (a3) ​​and the fourth wiring area (a4) are equal. The current-carrying values ​​corresponding to the areas of the first wiring area (a1) and / or the second wiring area (a2) are sufficient to meet the minimum current-carrying value of the capacitor assembly. The larger areas of the third wiring area (a3) ​​and / or the fourth wiring area (a4) are due to redundant areas, resulting in a lower PCB board utilization rate in this embodiment.

[0063] According to the above Figure 3It can be seen that the positive conduction path 21, the second conduction path 22 and the third conduction path 23 are respectively located in different wiring layers of the printed circuit board, and the negative conduction path 24 is located in the same wiring layer as the positive conduction path 21. Distributing different conduction paths in different wiring layers facilitates wiring. In addition, since the distribution of the positive capacitor array and the negative capacitor array on the printed circuit board cannot overlap, as long as the positive capacitor array and the negative capacitor array are partitioned and arranged, the positive conduction path 21 corresponding to the positive capacitor array and the negative conduction path 24 corresponding to the negative capacitor array can be respectively arranged in the same wiring layer, the wiring layer can be fully utilized, and for many circuits, the working current and working voltage of the positive half cycle and the negative half cycle are symmetrical, the positive half cycle and the negative half cycle can also be relatively symmetrical from the wiring perspective, which is beneficial to error checking.

[0064] In some embodiments, the positive terminal is a first terminal of a first capacitor in the positive capacitor array; the negative terminal is a second terminal of a first capacitor in the negative capacitor array; the transfer terminal is a second terminal of a last capacitor in the positive capacitor array, and / or the transfer terminal is a first terminal of a last capacitor in the negative capacitor array.

[0065] In some embodiments, the first capacitor and the last capacitor are the two capacitors farthest away from each other in the positive capacitor array and / or in the negative capacitor array.

[0066] It can be seen from Figure 4 It can be seen from

[0067] In the present embodiment, one pin of the first capacitor or the last capacitor in the capacitor array is used as the first terminal (positive terminal 11 and / or negative terminal 14) or transfer terminal 13 of the terminal group, thereby reducing the number of connection terminals and increasing the layout freedom of the printed circuit board.

[0068] When the capacitor assembly is used as a bus capacitor, the terminal group can further include a third terminal 15 and a fourth terminal 16, wherein the third terminal 15 is connected with the first terminal 11 to connect other devices, and the fourth terminal 16 is connected with the second terminal 12 to connect other devices. The other devices can be inductors, absorption circuits, etc., which are not specifically limited. Thus, the capacitor cell and the other devices form a complete capacitor assembly, and the external connection terminals of the capacitor assembly include the third terminal 15, the neutral terminal 12, and the fourth terminal 16, which increase the integration of the PCB and reduce the assembly difficulty of the assembly personnel.

[0069] In the related art, how to improve the current sharing degree among the capacitors with smaller board area under the condition of limited board area of the PCB is also an urgent problem to be solved. In addition, how to improve the current sharing degree among the capacitors with fewer boards under the condition of the same board area is also a direction to solve the problem.

[0070] In some embodiments, referring to Figure 2 , a structure diagram of a printed circuit board of a capacitor assembly is shown. Figure 4 As shown in Figure 4 , the multi-layer wiring layer further includes a fourth wiring layer and a fifth wiring layer;

[0071] The third conduction path 23 is located on the fourth wiring layer, and the second conduction path 22 is located on the fifth wiring layer; the positive conduction path 21 includes a first sub-path 211 located on the fourth wiring layer and a second sub-path 212 located on the fifth wiring layer, and the first sub-path 211 and the second sub-path 212 are connected in parallel; the negative conduction path 24 includes a third sub-path 241 located on the fourth wiring layer and a fourth sub-path 242 located on the fifth wiring layer, and the third sub-path 241 and the fourth sub-path 242 are connected in parallel.

[0072] Figure 4 As shown in Figure 4 , a plurality of capacitors 1 form a capacitor cell, and a terminal group (including a positive terminal 11, a negative terminal 14, and a neutral terminal 12) and a transfer terminal 13 located on both sides of the capacitor cell are shown. As shown in Figure 4 , the terminal group is located on the left side of the capacitor cell along the first direction, and the transfer terminal 13 is located on the right side of the capacitor cell along the first direction, that is, the terminal group and the transfer terminal are located on opposite sides of the capacitor cell, respectively. The plurality of capacitors 1 constituting the capacitor cell are divided into a positive capacitor array (6 capacitors 1 distributed on the upper side in the PCB) and a negative capacitor array (6 capacitors 1 distributed on the lower side in the PCB). Figure 4(a) and (b) in the diagram represent the wiring diagrams of different wiring layers of the PCB board. The positive conduction path 21 and the negative conduction path 24 each include two sub-paths located in the two wiring layers respectively. The second conduction path 22 and the third conduction path 23 are located in the two wiring layers respectively.

[0073] Specifically, by Figure 4 As shown in (a), the positive terminal 11 and the first end of each capacitor 1 in the positive capacitor array are connected to the positive conduction path 21 (in the two pins of capacitor 1, the small white dot inside the conduction path indicates a connection to the corresponding conduction path, and the black ring indicates a non-connection to the conduction path), the negative terminal 14 and the first end of each capacitor 1 in the negative capacitor array are connected to the negative conduction path 24; and the neutral terminal 12 and the relay terminal 13 are connected through the third conduction path 23. Figure 4 As can be seen in (b), the second end of each capacitor 1 in the positive capacitor array, the first end of each capacitor 1 in the negative capacitor array, and the relay end 13 are all connected to the second conduction path 22.

[0074] It should be noted that, Figure 4 (a) in the diagram represents the fourth wiring layer. Figure 4 In the diagram, (b) represents the fifth routing layer. Furthermore, the fourth and fifth routing layers can be any two of multiple routing layers, and there are no restrictions on their positional relationship. For example, the fifth routing layer is located above the fourth routing layer.

[0075] It should also be noted that, as the current busbar to the terminal group, the pins of capacitor 1 connected to the electrical connection network cannot be connected to the fourth wiring layer; the fifth wiring layer, as the current busbar for all capacitors 1, cannot have its copper foil connected to the neutral terminal 12. The current connection point between the fourth and fifth wiring layers is at the capacitor furthest from the terminal group (i.e., the last capacitor), and is connected via vias. The same applies when more wiring layers are required for connection. This embodiment only illustrates that the fourth and fifth wiring layers each include one wiring layer; however, the fourth and / or fifth wiring layers can also include multiple sub-wiring layers connected in parallel, and this is not specifically limited.

[0076] It should be further noted that, in the fourth wiring layer, the first ends of the plurality of capacitors of the positive capacitor array and the positive terminal 11 are connected to the first sub-path 211; in the fifth wiring layer, the first ends of the plurality of capacitors of the positive capacitor array and the positive terminal 11 are connected to the second sub-path 212. Similarly, in the fourth wiring layer, the second ends of the plurality of capacitors of the negative capacitor array and the negative terminal 14 are connected to the third sub-path 241; in the fifth wiring layer, the second ends of the plurality of capacitors of the negative capacitor array and the negative terminal 14 are connected to the fourth sub-path 242. That is, for the positive conduction path 21 and the negative conduction path 24, the current passes through the two sub-paths located in the two wiring layers at the same time.

[0077] In some embodiments, as shown in FIG. 4, the fourth wiring layer includes a fifth wiring area, a sixth wiring area and a seventh wiring area, and the fifth wiring layer includes an eighth wiring area, a ninth wiring area and a tenth wiring area. Figure 4

[0078] The positive terminal 11 is electrically connected to the fifth wiring area and the eighth wiring area, the negative terminal 14 is electrically connected to the seventh wiring area and the tenth wiring area, the transit terminal 13 is electrically connected to the ninth wiring area, and the transit terminal 13 and the neutral terminal 23 are electrically connected to the sixth wiring area.

[0079] Specifically, as shown in FIG. 5, the area a5 represents the fifth wiring area, the area a6 represents the sixth wiring area, the area a7 represents the seventh wiring area, the area a8 represents the eighth wiring area, the area a9 represents the ninth wiring area, and the area a10 represents the tenth wiring area. The first sub-path 211 passes through the fifth wiring area (a5), the third conduction path 23 passes through the sixth wiring area (a6), the third sub-path 241 passes through the seventh wiring area (a7), the second sub-path 212 passes through the eighth wiring area (a8), the second conduction path 22 passes through the ninth wiring area (a9), and the fourth sub-path 242 passes through the tenth wiring area (a10). In addition, each wiring area can be composed of a copper foil in the PCB board. Figure 4 In some embodiments, as shown in FIG. 6, in the fourth wiring layer, the fifth wiring area (a5), the sixth wiring area (a6) and the seventh wiring area (a7) all extend along the first direction, and the fifth wiring area (a5), the sixth wiring area (a6) and the seventh wiring area (a7) are arranged in the second direction in sequence; in the fifth wiring layer, the eighth wiring area (a8), the ninth wiring area (a9) and the tenth wiring area (a10) all extend along the first direction, and the eighth wiring area (a8), the ninth wiring area (a9) and the tenth wiring area (a10) are arranged in the second direction in sequence.

[0080] Figure 5

[0081] ​​​The projection of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction overlaps, the projection of the sixth wiring area (a6) and the ninth wiring area (a9) along the third direction overlaps, and the projection of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction overlaps;

[0082] The first direction and the second direction are in the plane in which the printed circuit board is located, and the third direction is perpendicular to the plane in which the printed circuit board is located.

[0083] That is, along the third direction, the fifth wiring area (a5) and the eighth wiring area (a8) correspond, the sixth wiring area (a6) and the ninth wiring area (a9) correspond, and the seventh wiring area (a7) and the tenth wiring area (a10) correspond.

[0084] It should be noted that the third direction is perpendicular to the plane in which the printed circuit board is located. On the surface of the printed circuit board, two directions intersecting (for example, perpendicular) each other, that is, the first direction and the second direction, are defined.

[0085] It should also be noted that the projection of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction can completely overlap or partially overlap, and when they completely overlap, the shapes of the fifth wiring area (a5) and the eighth wiring area (a8) are the same and the areas are equal. The projection of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction can completely overlap or partially overlap, and when they completely overlap, the shapes of the seventh wiring area (a7) and the tenth wiring area (a10) are the same and the areas are equal. Because the copper foil of the fifth wiring layer is not connected with the neutral terminal 12, the projection of the sixth wiring area (a6) and the ninth wiring area (a9) along the third direction partially overlaps. Exemplarily, the specific implementation of the embodiments of the present application is described in detail taking the example that the projection of the fifth wiring area (a5) and the eighth wiring area (a8) along the third direction and the projection of the seventh wiring area (a7) and the tenth wiring area (a10) along the third direction both completely overlap.

[0086] In some embodiments, the minimum area among the sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8), the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10), the area of the sixth wiring area (a6), and the area of the ninth wiring area (a9) corresponds to the minimum current carrying value of the capacitor assembly.

[0087] Exemplarily, the sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8) is equal to the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10), and the area value is less than or equal to the area of the sixth wiring area (a6) and the area of the ninth wiring area (a9). Wherein, the sum of the areas of the fifth wiring area (a5) and the eighth wiring area (a8), and / or the sum of the areas of the seventh wiring area (a7) and the tenth wiring area (a10) corresponds to the current carrying value that can already meet the minimum current carrying value of the capacitor assembly; if the minimum current carrying value of the capacitor assembly is 10A (ampere, A), the current carrying values corresponding to the areas of the fifth wiring area (a5), the eighth wiring area (a8), the seventh wiring area (a7) and the tenth wiring area (a10) are 5A respectively.

[0088] In the embodiment, the second conducting path 22 and the third conducting path 23 are distributed in different layers, and the positive conducting path 21 and the negative conducting path 24 are divided into two sub-paths in different layers, so that not only the current sharing between the capacitors in the positive capacitor array and the current sharing between the capacitors in the negative capacitor array can be realized, the connection paths between the capacitors are reduced, and the wiring difficulty is reduced, but also the area of the board surface of the printed circuit board is less occupied, and the board layer of the printed circuit board is also less occupied.

[0089] In another embodiment of the present application, a power assembly is provided, such as Figure 5 As shown, the power assembly 300 includes the aforementioned capacitor assembly 100 and the power conversion circuit 3. For the power assembly 300, since it includes the aforementioned capacitor assembly 100, at least the same advantages as the capacitor assembly are possessed.

[0090] In Figure 6 In the embodiment, the capacitor assembly 100 and the power conversion circuit 3 are arranged on the same PCB board, and in other embodiments, the capacitor assembly 100 and the power conversion circuit 3 constituting the power assembly 300 can be arranged on different PCB boards or distributed into multiple PCB boards, which can be set by engineers as needed, and no specific limitation is made.

[0091] In the embodiment, the power conversion circuit 3 can include multiple conversion bridge arms 31, and the capacitor bank further includes at least one first positive capacitor array 41 and at least one first negative capacitor array 42, the first positive capacitor array 41 and the first negative capacitor array 42 are arranged alternately, and each conversion bridge arm 31 is arranged between the first positive capacitor array 41 and the first negative capacitor array 42.

[0092] In the embodiment, the first positive capacitor array 41 and the first negative capacitor array 42 are arranged alternately, and the power conversion bridge arm (i.e., the conversion bridge arm 31) is arranged between the positive capacitor array and the negative capacitor array, so that each power conversion bridge arm is relatively equal in distance to the paths of the capacitor banks, and the capacitor arrays are arranged on both sides of the power conversion bridge arm, so that each power conversion bridge arm has a positive capacitor array and a negative capacitor array nearby, which is beneficial to shorten the commutation path, reduce the commutation inductance, and reduce the inverse peak.

[0093] For example, referring to Figure 6 , the number of conversion bridge arms 31 is three, and the three conversion bridge arms 31 can constitute three parallel conversion bridge arms, or can correspond to three phases of a three-phase circuit respectively, and no specific limitation is made in this regard. As can be seen from Figure 6 , the three conversion bridge arms 31 are arranged in sequence along the first direction, and the first positive capacitor array 41 and the first negative capacitor array 42 are arranged on both sides of each conversion bridge arm 31. In the embodiment, the first positive capacitor array 41 and the first negative capacitor array 42 are collectively referred to as the first capacitor array, and the number of first capacitors included in each first capacitor array is different. In other embodiments, the number of capacitors included in each bus capacitor array can be the same.

[0094] As shown in the power assembly 300, Figure 6 in the embodiment, the capacitor bank includes electrolytic capacitors (schematically shown as small circles in Figure 6 ) and film capacitors (schematically shown as small squares in Figure 7 ), wherein the electrolytic capacitors constitute the aforementioned positive capacitor array and negative capacitor array, and the film capacitors constitute the aforementioned first positive capacitor array and first negative capacitor array. In other embodiments, the electrolytic capacitors and the film capacitors can both constitute the aforementioned capacitor array, positive capacitor array, negative capacitor array, first positive capacitor array, and first negative capacitor array, and no specific limitation is made in this regard.

[0095] In the embodiment, the conversion bridge arm 31 is a multi-level bridge arm, and the two multi-level bridge arms distributed on both sides of the first capacitor array are mirror-symmetric in layout. The first capacitor array includes the first positive capacitor array 41 and the first negative capacitor array 42. More specifically, the multi-level bridge arm can be a T-type three-level bridge arm or an I-type three-level bridge arm.

[0096] As shown in detail in Figure 7 (not shown in Figure 8 , which does not mean that there is no electrolytic capacitor), the region where the plurality of switching devices constituting the conversion bridge arm 31 is located is defined as the core device region, and the plurality of switching devices and the decoupling capacitor are located within the core device region. The capacitor bank is located outside the core device region and on both sides of the first capacitor array (the first positive capacitor array 41 or the first negative capacitor array 42), and the conversion bridge arms 31 on both sides of the first capacitor array are mirror-symmetric.

[0097] In the embodiment, the first positive capacitor array 41 and the first negative capacitor array 42 are arranged on both sides of the conversion bridge arm 31, so that a large number of small capacitors are connected in parallel in the positive half cycle or the negative half cycle commutation loop of each conversion bridge arm 31, so that the path is short, the stray inductance is small, and the anti-peak is small.

[0098] In the embodiment, the multi-level bridge arm further comprises a decoupling capacitor, the decoupling capacitor is arranged in a core device region, and the two ends of the decoupling capacitor are connected in parallel with the positive capacitor array or the negative capacitor array, respectively, wherein the core device region is a device region formed by wrapping a plurality of switching devices constituting the multi-level bridge arm.

[0099] The conversion bridge arm 31 is further described below by taking the T-type three-level bridge arm and the I-type three-level bridge arm as examples.

[0100] The connection relationship of the T-type three-level bridge arm is shown in Figure 9 The plurality of switching devices constituting the T-type three-level bridge arm include a first switching device 311, a second switching device 312, a third switching device 313, and a fourth switching device 314, and the bus capacitor includes a first bus capacitor 315 and a second bus capacitor 316; the first switching device 311 and the fourth switching device 314 are connected in series to constitute a vertical pipe bridge arm, the second switching device 312 and the third switching device 313 are connected in series to constitute a horizontal pipe bridge arm, and the first bus capacitor 315 and the second bus capacitor 316 are connected in series to constitute a capacitor bridge arm, wherein the common point of the first switching device 311 and the fourth switching device 314 is used as an output point (i.e., an alternating current end), the common point of the first bus capacitor 315 and the second bus capacitor 316 is used as a midpoint O, the two free ends of the vertical pipe bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, the first end of the horizontal pipe bridge arm is connected to the midpoint, and the second end is connected to the output point, and the two free ends of the capacitor bridge arm are further connected to the positive and negative ends of the power supply, respectively, and the decoupling capacitor is connected across the free end of the vertical pipe bridge arm and the first end of the horizontal pipe bridge arm.

[0101] The connection relationship of the I-type three-level bridge arm is shown in Figure 9As shown, the multiple switching devices constituting the Type I three-level bridge arm include a first switching device 311, a second switching device 312, a third switching device 313, a fourth switching device 314, a first diode 321, and a second diode 322. The bus capacitors include a first bus capacitor 315 and a second bus capacitor 316. The first switching device 311, the second switching device 312, the third switching device 313, and the fourth switching device 314 are connected in series to form the Type I bridge arm. The first bus capacitor 315 and the second bus capacitor 316 are connected in series to form the capacitor bridge arm. The first diode 321 and the second diode 322 are connected in series to form the diode bridge arm. The common point of the first switching device 311 and the second switching device 312 is used as the first connection point. The common point of the second switching device 312 and the third switching device 313 is used as the output point. The common point of the third switching device 313 and the fourth switching device 314 is used as the second connection point. The common point of the first bus capacitor 315 and the second bus capacitor 316 is used as the midpoint O. The two free ends of the type I bridge arm are connected in parallel with the two free ends of the capacitor bridge arm, respectively. The two free ends of the diode bridge arm are connected to the first connection point and the second connection point, respectively. The common point of the diode bridge arm is connected to the midpoint O. The decoupling capacitor is connected between the free end of the type I bridge arm and the common point of the diode bridge arm.

[0102] exist Figure 9 In (a) of the diagram, the decoupling capacitors include a first decoupling capacitor 317 and a second decoupling capacitor 318. In one specific embodiment, please refer to [reference needed]. Figure 9 In (a), the first decoupling capacitor 317 is connected between the free end of the first switching device 311 and the anode of the first diode 321, and the second decoupling capacitor 318 is connected between the free end of the fourth switching device 314 and the cathode of the first diode 322; Figure 9 In (b), the first decoupling capacitor 317 is connected between the free end of the first switching device 311 and the cathode of the second diode 322, and the second decoupling capacitor 318 is connected between the free end of the fourth switching device 314 and the anode of the first diode 321. Compared to Figure 9 The connection scheme of the decoupling capacitor in (a) is as follows. Figure 8 The converter path in (b) is shorter.

[0103] From the above Figure 9 and Figure 8 As can be seen, the two ends of the decoupling capacitor are connected in parallel with either the first bus capacitor (i.e., the positive capacitor array) or the second bus capacitor (i.e., the negative capacitor array). It should be noted that conventional T-type and I-type three-level bridge arms do not include decoupling capacitors. In this invention, decoupling capacitors are added to shorten the commutation loop, effectively reducing the inductance of the commutation path and lowering reverse peaks.

[0104] It should be noted that, Figure 9 andFigure 8 The first switch device 311 to the fourth switch device 314 are all IGBT devices in the embodiment, and in other embodiments, the first switch device 311 to the fourth switch device 314 can also be formed by other types of switch devices / switch device combinations, such as MOS, BJT, HBT, diode, etc. Meanwhile, each switch device can include a single transistor or multiple transistors.

[0105] In the above description, the capacitance of the decoupling capacitor satisfies: the decoupling capacitor current division for the anti-peak current ripple > the decoupling capacitor current division for the power frequency ripple current, and the decoupling capacitor current division for the anti-peak current ripple > the decoupling capacitor current division for the switching frequency ripple.

[0106] It should be noted that there are mainly three types of ripple currents in the conversion bridge arm 31: (1) power frequency ripple current; (2) switching frequency ripple current; (3) anti-peak ripple current (also known as commutation current). The frequencies of the three types of ripple currents are different, the frequency of the power frequency ripple < the frequency of the switching frequency ripple < the frequency of the anti-peak ripple (generally, the frequency of the power frequency ripple is 50Hz or 60Hz and its multiple, the frequency of the switching frequency ripple is 10kHz-100kHz, and the frequency of the anti-peak ripple is 1MHz-10MHz). It is found through experiments that different types and different capacitances of capacitors have different through amounts for the three types of different frequency ripples, and capacitors with small capacitances have a large through amount for high switching frequency. The capacitance of the decoupling capacitor needs to be able to well allow the anti-peak ripple current to pass through, and at the same time, the through amounts of the power frequency ripple current and the switching frequency ripple current are small, so the capacitance of the decoupling capacitor cannot be too large, otherwise, too much switching frequency current will be divided, which will cause the capacitor to overheat.

[0107] In a specific scenario, the decoupling capacitor for shortening the commutation path of the switching process from one current loop to another current loop has a capacitance of 0.47 microfarad, and the bus capacitor for absorbing the power frequency ripple current has a capacitance of 470 microfarad, and an electrolytic capacitor is selected, which is large in size and is arranged in a more peripheral area, and can be composed of multiple capacitors in parallel. The bus capacitor for absorbing the switching frequency ripple current has a capacitance of 12 microfarad, and a film capacitor is generally selected, which is also arranged in a more peripheral area, and can be composed of multiple capacitors in parallel. Through experimental verification, the 0.47 microfarad decoupling capacitor has almost no current division for the power frequency ripple current, about 1% for the switching frequency ripple current, and about 99% for the anti-peak ripple current. The 12 microfarad bus capacitor has about 95% current division for the switching frequency ripple current, and about 1% for the anti-peak ripple current. The 0.47 microfarad decoupling capacitor has almost no current division for the anti-peak ripple current, and about 99% for the power frequency ripple current. As can be seen, the anti-peak ripple current (i.e. commutation current) mainly passes through the decoupling capacitor. The above capacitance values and test data are only a set of values obtained by the inventors during the test, and cannot limit the unique range of capacitance values of the present application, nor can they limit the current division of different capacitors for different ripple currents, which should be understood based on the inventive concept of the present application.

[0108] In the present embodiment, by arranging the decoupling capacitor and arranging the decoupling capacitor and the plurality of switching devices constituting the multi-level bridge arm in the core device area, and arranging the positive and negative capacitor arrays outside the core device area, the commutation path through the decoupling capacitor is greatly shortened relative to the commutation path through the positive and negative capacitor arrays, the path stray inductance in the commutation process is reduced, and the anti-peak is reduced, thereby prolonging the service life of the device. That is, the present embodiment can reduce the length of the commutation path in the switching process from the middle freewheeling loop to the reverse freewheeling loop by introducing the decoupling capacitor, thereby reducing the anti-peak and prolonging the service life of the device.

[0109] In still another embodiment of the present application, a converter is provided, which includes the aforementioned capacitor assembly 100, or the aforementioned power assembly 300.

[0110] The following provides several specific layouts taking the T-type three-level bridge arm (i.e. Figure 7 The structure shown) as an example for reference.

[0111] In some embodiments, the layout of the T-type three-level bridge arm can be as Figure 7As shown, under this layout, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 present a T-shaped layout; the first switch device 311 and the fourth switch device 314 constitute the short side of the T-shaped layout; the second switch device 312 and the third switch device 313 constitute the long side of the T-shaped layout; the third switch device 313 is close to the short side of the T-shaped layout, and the second switch device 312 is far away from the long side of the T-shaped layout.

[0112] It should be noted that under the T-shaped layout, even the commutation path via the bus capacitor is relatively short, and the reverse peak is low. When the PCB multi-layer board is wired, the two conduction paths of different wiring layers between the switch devices have an overlapping area in the projection direction, and the angle between the current directions of the overlapping area is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths are superimposed and offset, so that the stray inductance generated by the two conduction paths is also offset, the induced voltage AV is reduced, the reverse peak is reduced, permanent damage to the switch device is avoided, and the circuit life is improved.

[0113] In addition, for the T-shaped layout, the first decoupling capacitor 317 and the second decoupling capacitor 318 are located between the first switch device 311, the fourth switch device 314, and the third switch device 313; one of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the first switch device 311 away from the fourth switch device 314, and the other of the first bus capacitor 315 and the second bus capacitor 316 is located on the side of the fourth switch device 314 away from the first switch device 311.

[0114] In this way, the first decoupling capacitor 317 is arranged between the first switch device 311 and the third switch device 313, and the second decoupling capacitor 318 is arranged between the fourth switch device 314 and the third switch device 313, so that the commutation path via the first decoupling capacitor 317 and the commutation path via the second decoupling capacitor 318 are further shortened, thereby reducing the reverse peak.

[0115] As described above, each switch device can include a single transistor or include multiple transistors. In the case where each switch device includes multiple transistors, please refer to Figure 10The second switch device 312 includes four second transistors, and the four second transistors are arranged in a trapezoidal shape; the third switch device 313 includes four third transistors, and the four third transistors are arranged in a 2*2 array; the first switch device 311 includes three first transistors, and the three first transistors are arranged in a triangular shape; the fourth switch device 314 includes three fourth transistors, and the three fourth transistors are arranged in a triangular shape (the specific shape of the triangular shape is not limited, for example, a right triangle or an isosceles triangle); the first decoupling capacitor 317 and the second decoupling capacitor 318 are arranged in a region surrounded by the first transistor at the top of the triangular shape, the fourth transistor at the top of the triangular shape, and the four third transistors.

[0116] In this way, the decoupling capacitors do not occupy additional area, and at the same time, the inverse peak is better reduced.

[0117] Please refer to Figure 11 , a second layout of a T-shaped three-level bridge arm is provided, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 are arranged in a rectangular shape; the first switch device 311 and the fourth switch device 314 are arranged along a first direction, and the second switch device 312 and the third switch device 313 are arranged along the first direction; the first switch device 311 and the third switch device 313 are arranged along a second direction, and the second switch device 312 and the fourth switch device 314 are arranged along the second direction.

[0118] The first decoupling capacitor 317 and the second decoupling capacitor 318 are arranged between the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314.

[0119] It should be noted that the commutation path of the rectangular layout is shorter than that of the T-shaped layout, and at the same time, the first decoupling capacitor 317 and the second decoupling capacitor 318 are also increased, so the inverse peak is smaller.

[0120] Please refer to Figure 10 , a third layout of a T-shaped three-level bridge arm is provided, the first switch device 311, the second switch device 312, the third switch device 313, and the fourth switch device 314 are arranged in a diamond shape; the first switch device 311, the third switch device 313, and the fourth switch device 314 are arranged along a first direction, and the first switch device 311, the second switch device 312, and the fourth switch device 314 are arranged along the first direction; the third switch device 313 and the second switch device 312 are arranged along a second direction; the first decoupling capacitor 317 is arranged between the second switch device 312 and the third switch device 313, and close to the first switch device 311; the second decoupling capacitor 318 is arranged between the second switch device 312 and the third switch device 313, and close to the fourth switch device 314.

[0121] As can be seen from the second and third layouts described above, the core device area can be divided into a first core device area and a second core device area arranged adjacent to each other. Correspondingly, the multiple switching devices constituting the multi-level circuit are divided into positive half-cycle devices (corresponding to...). Figure 11 and Figure 10 The first switching device 311 and the second switching device 312) and the negative half-cycle device (corresponding to) Figure 11 and Figure 9 The fourth switching device 314 and the third switching device 313 in the first core device area are arranged with the positive half-cycle device and the first decoupling capacitor in the first core device area, and the negative half-cycle device and the second decoupling capacitor in the second core device area. This makes the closely related switching devices and decoupling capacitors more compact in layout, thereby shortening the connection path between the switching devices and the decoupling capacitors, which can further shorten the commutation path, reduce noise inductance, and reduce reverse peaks.

[0122] Similarly, using a type I three-level bridge arm (i.e. Figure 12 The following are some specific layouts for reference and understanding, using the structure shown as an example.

[0123] Please refer to Figure 13 The core device area is divided into a first core device area and a second core device area. In the first core device area, the first switching device 311, the second switching device 312, and the first diode 321 form a triangular layout. The first decoupling capacitor 317 is disposed inside the triangular layout (first core device area). In the second core device area, the fourth switching device 314, the third switching device 313, and the second diode 322 form a triangular layout. The second decoupling capacitor 318 is disposed inside the triangular layout (second core device area). The first core device area and the second core device area are mirror symmetrical. The fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0124] Furthermore, the first pin of the first decoupling capacitor 317 (i.e., the pin connected to the first diode 321) faces the first diode 321, and the second pin of the first decoupling capacitor 317 (i.e., the pin connected to the first switching device 311) faces the first switching device 311. Similarly, the second decoupling capacitor 318 is to be mirror-symmetrical to the first decoupling capacitor 317. Therefore, the first pin of the second decoupling capacitor 318 (i.e., the pin connected to the second diode 322) faces the second diode 322, and the second pin of the second decoupling capacitor 318 (i.e., the pin connected to the fourth switching device 314) faces the fourth switching device 314.

[0125] Thus, the first decoupling capacitor 317 is arranged between the first switch device 311 and the first diode 321, and the second decoupling capacitor 318 is arranged between the fourth switch device 314 and the second diode 322, so that the commutation path via the first decoupling capacitor 317 and the commutation path via the second decoupling capacitor 318 are further shortened, thereby reducing the anti-peak. Moreover, this layout is beneficial to reduce electromagnetic interference and improve electromagnetic compatibility performance.

[0126] In addition to the core device region, the first bus capacitor 315 and the second bus capacitor 316 are arranged. The bus capacitor can be composed of a plurality of small capacitors in parallel, and the distribution position can be flexibly selected. As shown in Figure 14 In this embodiment, the first bus capacitor 315 and the second bus capacitor 316 can each include a plurality of electrolytic bus capacitors (small circles in the figure) and a plurality of thin-film bus capacitors (small squares in the figure). The electrolytic bus capacitors and the thin-film bus capacitors together constitute a capacitor assembly and are arranged on one side of the core device region.

[0127] In a second specific layout embodiment, please refer to Figure 15 , similarly, the core device region is divided into a first core device region and a second core device region. The first switch device 311, the second switch device 312, and the second diode 322 form a triangular layout in the first core device region, the first decoupling capacitor 317 is arranged inside the triangular layout (the first core device region), the fourth switch device 314, the third switch device 313, and the first diode 321 form a triangular layout in the second core device region, the second decoupling capacitor 318 is arranged inside the triangular layout (the second core device region), and the first core device region and the second core device region are mirror-symmetric, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0128] More specifically, the first pin (i.e., the pin connected to the second diode 322) of the first decoupling capacitor 317 is directed towards the second diode 322, and the second pin (i.e., the pin connected to the first switch device 311) of the first decoupling capacitor 317 is directed towards the first switch device 311. Similarly, the second decoupling capacitor 318 is mirror-symmetric to the first decoupling capacitor 317, so that the first pin (i.e., the pin connected to the first diode 321) of the second decoupling capacitor 318 is directed towards the first diode 321, and the second pin (i.e., the pin connected to the fourth switch device 314) of the second decoupling capacitor 318 is directed towards the fourth switch device 314.

[0129] In this layout, the stress of the commutation loop is small while inheriting the advantages of the capacitor assembly, and the two conduction paths of different wiring layers between the switching devices have overlapping areas in the projection direction, and the angle between the current directions of the overlapping areas is greater than 90 degrees, that is, the magnetic fields generated by the currents of the two conduction paths are superimposed and offset, so the mutual inductance generated by the two conduction paths is also offset, the induced voltage ΔV is reduced, the anti-peak is reduced, permanent damage to the switching device is avoided, and the circuit life is improved.

[0130] In a third specific layout embodiment, please refer to Figure 13 to 15 , the first switching device 311, the second switching device 312 and the second diode 322 form an L-shaped layout in the first core device area, and the second switching device 312 is located at the corner of the L-shaped layout, the first decoupling capacitor 317 is arranged on the inner side of the L-shaped layout (the first core device area), the fourth switching device 314, the third switching device 313 and the first diode 321 form an L-shaped layout in the second core device area, the second decoupling capacitor 318 is arranged on the inner side of the L-shaped layout (the second core device area), and the first core device area and the second core device area are mirror-symmetric, wherein the fourth switching device 314 corresponds to the first switching device 311, the third switching device 313 corresponds to the second switching device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0131] More specifically, the first pin (i.e. the pin connected to the second diode 322) of the first decoupling capacitor 317 faces the second diode 322, and the second pin (i.e. the pin connected to the first switching device 311) of the first decoupling capacitor 317 faces the first switching device 311. Similarly, the second decoupling capacitor 318 is mirror-symmetric with the first decoupling capacitor 317, so the first pin (i.e. the pin connected to the first diode 321) of the second decoupling capacitor 318 faces the first diode 321, and the second pin (i.e. the pin connected to the fourth switching device 314) of the second decoupling capacitor 318 faces the fourth switching device 314.

[0132] In this layout, the stress of the commutation loop is small.

[0133] In a fourth specific layout embodiment, please refer to Figure 12, the core device region is divided into a first core device region and a second core device region, wherein the first switch device 311, the second switch device 312 and the first diode 321 form an "I" type layout in the first core device region, and the first diode 321 is placed adjacent to the first switch device 311, the first decoupling capacitor 317 is arranged between the first diode 321 and the first switch device 311, the fourth switch device 314, the third switch device 313 and the second diode 322 form an "I" type layout in the second core device region, and the second diode 322 is placed adjacent to the fourth switch device 314, the second decoupling capacitor 318 is arranged between the second diode 322 and the fourth switch device 314, and the first core device region and the second core device region are mirror-symmetric, wherein the fourth switch device 314 corresponds to the first switch device 311, the third switch device 313 corresponds to the second switch device 312, the second diode 322 corresponds to the first diode 321, and the first decoupling capacitor 317 corresponds to the second decoupling capacitor 318.

[0134] The first pin (i.e., the pin connected to the first diode 321) of the first decoupling capacitor 317 faces the first diode 321, and the second pin (i.e., the pin connected to the first switch device 311) of the first decoupling capacitor 317 faces the first switch device 311. Similarly, the second decoupling capacitor 318 and the first decoupling capacitor 317 are mirror-symmetric, so that the first pin (i.e., the pin connected to the second diode 322) of the second decoupling capacitor 318 faces the second diode 322, and the second pin (i.e., the pin connected to the fourth switch device 314) of the second decoupling capacitor 318 faces the fourth switch device 314.

[0135] In this layout embodiment, the advantages of shortening the commutation path and reducing the reverse peak are also met.

[0136] It should be noted that the above Figure 6 only shows the layout of the core device region (i.e., the conversion bridge arm 31), and the layout of the capacitor assembly can be as shown in Figure 12 or Figure 6 , Figure 16 and Figure 16 only takes three core device regions as an example, and more or less can be provided in other embodiments, which are not specifically limited.

[0137] In some embodiments, referring to Figure 16 , a schematic structural diagram of a converter provided in an embodiment of the present application is shown. As shown in Figure 16 , the converter 400 includes the aforementioned capacitor assembly 100 or the power assembly 300.

[0138] Specifically, as shown in ​As shown in (a) of FIG. 4, the converter 400 includes the aforementioned capacitor assembly 100; as shown in (b) of FIG. 4, the converter 400 includes the aforementioned power assembly 300. ​ As shown in (a) of FIG. 4, the converter 400 includes the aforementioned capacitor assembly 100; as shown in (b) of FIG. 4, the converter 400 includes the aforementioned power assembly 300.

[0139] For the converter 400, since it includes the aforementioned capacitor assembly 100 or power assembly 300, it at least has the same advantages as the capacitor assembly 100 or power assembly 300.

[0140] The above merely provides preferred embodiments of the present application, but not for limiting the protection scope of the present application. It is to be explained that, in the present application, the terms “comprising”, “containing” or any other variants thereof are intended to cover the non-exclusive containing, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes the elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement “including a…” does not exclude the presence of another identical element in the process, method, article or device including the element. The above sequence number of the embodiments of the present application is only for description, but not for representing the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method embodiments. The features disclosed in several product embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present application can be combined arbitrarily without conflict, to obtain new method or device embodiments. The above is merely the specific implementation method of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application.

Claims

1. A capacitor assembly, characterized by, The capacitor assembly comprises a capacitor bank arranged on a printed circuit board, and a terminal group and a transfer terminal respectively arranged on opposite sides of the capacitor bank; the terminal group comprises a positive terminal, a neutral terminal and a negative terminal, the capacitor bank comprises at least one positive capacitor array and at least one negative capacitor array, and the positive capacitor array and the negative capacitor array comprise a plurality of capacitors connected in parallel; The first ends of the plurality of capacitors of the positive capacitor array and the positive terminal are connected to a positive conduction path, the second ends of the plurality of capacitors of the negative capacitor array and the negative terminal are connected to a negative conduction path, a first conduction path comprises the positive conduction path and / or the negative conduction path, the second ends of the plurality of capacitors of the positive capacitor array, the first ends of the plurality of capacitors of the negative capacitor array and the transfer terminal are connected to a second conduction path, and the neutral terminal and the transfer terminal are connected to a third conduction path, so that for the positive capacitor array, the commutation paths of the positive terminal to the neutral terminal after passing through each capacitor are equal in length, and for the negative capacitor array, the commutation paths of the negative terminal to the neutral terminal after passing through each capacitor are equal in length; The printed circuit board comprises a plurality of wiring layers, and the second conduction path and the third conduction path are arranged on different wiring layers.

2. The capacitor assembly of claim 1, wherein, The positive conduction path, the second conduction path and the third conduction path are arranged on different wiring layers, and the positive conduction path and the negative conduction path are arranged on the same wiring layer. The plurality of wiring layers comprise a first wiring layer, a second wiring layer and a third wiring layer, the first wiring layer comprises a first wiring area and a second wiring area, the second wiring layer comprises a third wiring area, and the third wiring layer comprises a fourth wiring area; the positive terminal is electrically connected to the first wiring area, the negative terminal is electrically connected to the second wiring area, the transfer terminal is electrically connected to the third wiring area, and the transfer terminal and the neutral terminal are electrically connected to the fourth wiring area.

3. The capacitor assembly of claim 2, wherein, The minimum current-carrying value of the capacitor assembly corresponds to the minimum area among the area of the first wiring area, the area of the second wiring area, the area of the third wiring area and the area of the fourth wiring area.

4. The capacitor assembly of claim 1, wherein, The plurality of wiring layers further comprise a fourth wiring layer and a fifth wiring layer; The third conduction path is arranged on the fourth wiring layer, and the second conduction path is arranged on the fifth wiring layer; the positive conduction path comprises a first sub-path arranged on the fourth wiring layer and a second sub-path arranged on the fifth wiring layer, and the first sub-path and the second sub-path are connected in parallel; the negative conduction path comprises a third sub-path arranged on the fourth wiring layer and a fourth sub-path arranged on the fifth wiring layer, and the third sub-path and the fourth sub-path are connected in parallel.

5. The capacitor assembly of claim 4, wherein, The fourth wiring layer comprises a fifth wiring area, a sixth wiring area and a seventh wiring area, and the fifth wiring layer comprises an eighth wiring area, a ninth wiring area and a tenth wiring area. The positive terminal is electrically connected with the fifth wiring area and the eighth wiring area, the negative terminal is electrically connected with the seventh wiring area and the tenth wiring area, the transfer terminal is electrically connected with the ninth wiring area, and the transfer terminal and the neutral terminal are electrically connected with the sixth wiring area.

6. The capacitor assembly of claim 5, wherein, The fifth wiring area, the sixth wiring area and the seventh wiring area all extend along a first direction on the fourth wiring layer, and the fifth wiring area, the sixth wiring area and the seventh wiring area are arranged in sequence along a second direction; the eighth wiring area, the ninth wiring area and the tenth wiring area all extend along the first direction on the fifth wiring layer, and the eighth wiring area, the ninth wiring area and the tenth wiring area are arranged in sequence along the second direction; The fifth wiring area and the eighth wiring area overlap along a third direction, the sixth wiring area and the ninth wiring area overlap along the third direction, and the seventh wiring area and the tenth wiring area overlap along the third direction; The first direction and the second direction are in a plane in which the printed circuit board is located, and the third direction is perpendicular to the plane in which the printed circuit board is located.

7. The capacitor assembly of claim 6, wherein, The minimum area among the sum of the areas of the fifth wiring area and the eighth wiring area, the sum of the areas of the seventh wiring area and the tenth wiring area, the area of the sixth wiring area and the area of the ninth wiring area corresponds to the minimum current carrying value of the capacitor assembly.

8. The capacitor assembly according to any one of claims 1 to 7, characterized in that, The positive terminal is a first terminal of a first capacitor in the positive capacitor array, the negative terminal is a second terminal of a first capacitor in the negative capacitor array, the transfer terminal is a second terminal of a last capacitor in the positive capacitor array, and / or the transfer terminal is a first terminal of a last capacitor in the negative capacitor array. The first capacitor and the last capacitor are the two capacitors farthest apart in the positive capacitor array and / or in the negative capacitor array.

9. A power assembly, characterized by The power assembly comprises a power conversion circuit and the capacitor assembly according to any one of claims 1 to 8, and the power conversion circuit is connected with the capacitor assembly through the terminal group.

10. A converter, characterized by The converter comprises the capacitor assembly according to any one of claims 1 to 8, or comprises the power assembly according to claim 9.

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