Semiconductor device and method of manufacturing the same, storage system

Abstract

The application provides a semiconductor device and a manufacturing method thereof, and a storage system, comprising: a plurality of channel structures arranged in a first direction and a second direction and extending in a third direction, the first direction intersecting the second direction, and the third direction intersecting the first direction and the second direction; a plurality of conductive shielding structures arranged in the second direction, the conductive shielding structures being located between adjacent channel structures in the second direction; a gate line extending in the first direction and the third direction, and the gate line being located between adjacent channel structures; and a shielding structure lead-out wire, at least part of the shielding structure lead-out wire extending in the second direction and being connected with at least two conductive shielding structures.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method, and a memory system. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an important type of memory. A DRAM storage cell mainly consists of a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor stores data, and the transistor controls the storage of data within the capacitor.

[0003] Currently, the manufacturing process of dynamic random access memory (DRAM) is quite difficult, and how to reduce the manufacturing difficulty of DRAM is a technical problem that needs to be solved. Summary of the Invention

[0004] The purpose of this application is to provide a semiconductor device and its manufacturing method, as well as a storage system, to reduce the manufacturing difficulty of semiconductor devices.

[0005] In a first aspect, this application provides a semiconductor device, comprising:

[0006] Multiple channel structures are arranged in an array along a first direction and a second direction, and extend along a third direction, wherein the first direction intersects the second direction, and the third direction intersects both the first direction and the second direction;

[0007] Multiple conductive shielding structures are arranged along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction;

[0008] Gate lines extending along the first direction and the third direction, wherein the gate lines are located between adjacent channel structures; and

[0009] A shielding structure leads out a wire, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

[0010] In some embodiments of the semiconductor device, the semiconductor device further includes: a plurality of bit lines extending along the second direction and arranged along the first direction, and respectively connected to one end of the plurality of channel structures in the third direction;

[0011] Multiple bit line lead-out contacts are respectively connected to the multiple bit lines; and

[0012] The shielding structure leads out a contact, which is connected to the shielding structure leads out a wire. In the third direction, it is located on the same side of the channel structure as the bit line leads out a contact, and in the second direction, it is located on at least one side of the bit line.

[0013] In some embodiments of the semiconductor device, in the third direction, a plurality of the bit lines and the shielding structure lead wires are located on the same side of the channel structure, and in the first direction, the shielding structure lead wires are located on at least one side of the bit lines.

[0014] In some embodiments of the semiconductor device, the semiconductor device further includes: a redundant channel structure extending along the third direction and disconnected from the plurality of bit lines; the shielding structure lead wire is disposed adjacent to the redundant channel structure.

[0015] In some embodiments of the semiconductor device, in the first direction, the lead wires of the shielding structure are spaced apart from the redundant channel structure.

[0016] In some embodiments of the semiconductor device, the lead wires of the shielding structure are in contact with the redundant channel structure.

[0017] In some embodiments of the semiconductor device, the semiconductor device further includes: a plurality of gate line lead-out contacts located on both sides of the bit line in the first direction and respectively connected to the plurality of gate lines;

[0018] In the second direction, the plurality of bit line lead-out contacts and the shielding structure lead-out contacts are respectively located on both sides of the gate line.

[0019] In some embodiments of the semiconductor device, the semiconductor device further includes: a capacitor connected to the other end of the channel structure in the third direction;

[0020] In the third direction, the capacitor and the lead wire of the shielding structure are located on both sides of the channel structure.

[0021] In some embodiments of the semiconductor device, the shielding structure leads extend along the second direction; or,

[0022] The shielding structure leads include a first conductor segment extending along the second direction and a second conductor segment extending along the first direction. The first conductor segment is connected to the second conductor segment and is in contact with a plurality of conductive shielding structures.

[0023] Secondly, this application provides a method for manufacturing a semiconductor device, comprising:

[0024] A groove is formed in the semiconductor layer, the groove being recessed from a first surface to a second surface of the semiconductor layer, and the remaining semiconductor layer includes a plurality of channel structures arranged in an array along a first direction and a second direction and extending along a third direction, the first surface and the second surface being disposed opposite each other in the third direction, the first direction intersecting the second direction, and the third direction intersecting the first direction and the second direction;

[0025] A plurality of conductive shielding structures are formed in the semiconductor layer along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction;

[0026] Gate lines extending along the first direction and the third direction are formed in the semiconductor layer, and the gate lines are located between adjacent channel structures; and

[0027] A shielded structure leads out, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielded structures.

[0028] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: forming a plurality of bit lines extending along a second direction and arranged along a first direction, wherein the plurality of bit lines are respectively connected to one end of a plurality of channel structures in the third direction;

[0029] Forming multiple bit line lead-out contacts that are respectively connected to the multiple bit lines; and

[0030] A shielding structure lead-out contact is formed to connect with the lead-out wire of the shielding structure. The shielding structure lead-out contact and the bit line lead-out contact are located on the same side of the plurality of channel structures in the third direction. The shielding structure lead-out contact is located on at least one side of the bit line in the second direction.

[0031] In some embodiments of a semiconductor device manufacturing method, forming a plurality of bit lines extending along the second direction and arranged along the first direction includes: in the third direction, positioning the plurality of bit lines and the shielding structure lead wires on the same side of a plurality of channel structures, and in the first direction, positioning the shielding structure lead wires on at least one side of the bit lines.

[0032] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: further comprising a redundant channel structure extending along the third direction of the remaining semiconductor layer;

[0033] The formation of multiple bit lines extending along the second direction and arranged along the first direction includes: forming multiple bit lines that are disconnected from the redundant channel structure;

[0034] The formation of the shielded structure lead wire includes: forming the shielded structure lead wire disposed adjacent to the redundant channel structure.

[0035] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: filling the groove with a dielectric layer;

[0036] The second surface of the semiconductor layer is thinned to expose the dielectric layer, and a thinned third surface is formed; and

[0037] The dielectric layer and / or the semiconductor layer adjacent to the redundant channel structure are removed to form a lead wire receiving groove, the lead wire receiving groove exposing a plurality of the conductive shielding structures, and at least a portion of the lead wire receiving groove extends along the third direction, the lead wire receiving groove being recessed from the third surface toward the first surface.

[0038] The formation of the shielded structure lead wire includes: forming a shielded structure lead wire in the lead wire receiving groove that contacts the plurality of conductive shielding structures.

[0039] In some embodiments of a method for manufacturing a semiconductor device, forming a groove in the semiconductor layer includes:

[0040] A first groove extending along the second direction and the third direction is formed in the semiconductor layer, and the remaining semiconductor layer includes semiconductor lines;

[0041] A plurality of second grooves and a plurality of third grooves are formed in the semiconductor layer, extending along the third direction and the first direction and arranged along the second direction. The second grooves and the third grooves intersect the semiconductor line. The size of the second groove along the first direction is smaller than the size of the third groove along the first direction.

[0042] The formation of a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer includes: filling a plurality of second grooves and a plurality of third grooves with a conductive layer; and

[0043] The conductive layer in the plurality of third grooves is removed, and at least a portion of the remaining conductive layer in the plurality of second grooves forms the plurality of conductive shielding structures.

[0044] In some embodiments of a semiconductor device manufacturing method, the method further includes: enlarging the dimensions of the third groove along the third direction and the second direction to form a plurality of fourth grooves;

[0045] The formation of gate lines extending in the first direction in the semiconductor layer includes: forming multiple gate lines extending in the first direction and arranged in the second direction in the multiple fourth grooves respectively;

[0046] The method further includes: forming a plurality of gate line lead-out contacts, wherein the plurality of gate line lead-out contacts are located on both sides of the bit line in the first direction and are respectively connected to the plurality of gate lines.

[0047] In some embodiments of a method for manufacturing a semiconductor device, the method further includes: forming a capacitor connected to the other end of the plurality of channel structures in the third direction;

[0048] The formation of the shielded structure lead wire includes: forming the shielded structure lead wire on the side of the channel structure away from the capacitor in the third direction.

[0049] In some embodiments of a semiconductor device manufacturing method, forming the shielding structure lead wire includes: forming the shielding structure lead wire extending along the second direction and in contact with a plurality of the conductive shielding structures; or,

[0050] The formation of the shielding structure lead wire includes: making the shielding structure lead wire include a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and is in contact with the plurality of conductive shielding structures.

[0051] Thirdly, this application also provides a storage system, the storage system comprising:

[0052] Memory, including semiconductor devices as described in any of the above embodiments; and

[0053] A controller, connected to the memory, is used to control the memory.

[0054] The beneficial effects of some embodiments of this application include: the gate line extends along a first direction, and at least a portion of the shielding structure lead wire extends along a second direction, with the first and second directions intersecting. Therefore, the extension direction of at least a portion of the shielding structure lead wire intersects the extension direction of the gate line. When shielding structure lead wires are led out using shielding structure lead contacts, the process window of the shielding structure lead contacts is not limited by the spacing between adjacent gate lines in the second direction, reducing the manufacturing difficulty of the semiconductor device. Furthermore, multiple conductive shielding structures are arranged at intervals along the second direction, and one shielding structure lead wire is connected to at least two conductive shielding structures. With this design, the number of shielding structure lead wires in the semiconductor device is reduced, further reducing the manufacturing difficulty of the semiconductor device. Attached Figure Description

[0055] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application;

[0056] Figure 2A This is a planar schematic diagram of the semiconductor layer, the first insulating layer, and the mask layer in some embodiments of this application;

[0057] Figure 2B For along Figure 2A A schematic diagram of the cross-sectional structure intercepted by the A-A' tangent;

[0058] Figure 2C This is a schematic diagram of a planar structure in which semiconductor lines and a first dielectric layer are formed in a semiconductor layer, according to some embodiments of this application;

[0059] Figure 2D For along Figure 2C A schematic diagram of the cross-sectional structure intercepted by the B-B' tangent;

[0060] Figure 2E This is a schematic diagram of a planar structure in which a second and a third groove are formed in a semiconductor layer in some embodiments of this application;

[0061] Figure 2F For along Figure 2E A schematic diagram of the cross-sectional structure intercepted by the C-C' tangent;

[0062] Figure 2G This is a schematic diagram of a planar structure in which a conductive layer is formed in the second and third grooves in some embodiments of this application;

[0063] Figure 2H For along Figure 2G A schematic diagram of the cross-sectional structure intercepted by the D-D' tangent;

[0064] Figure 2I This is a plan view of a conductive shielding structure and a protective layer and a first insulating filling portion formed in a second groove in some embodiments of this application;

[0065] Figure 2J For along Figure 2I A schematic diagram of the cross-sectional structure intercepted by the E-E' tangent;

[0066] Figure 2K This is a schematic diagram of a planar structure in some embodiments of this application, showing the expansion of a third groove to form a fourth groove;

[0067] Figure 2L For along Figure 2K A schematic diagram of the cross-sectional structure intercepted by the F1-F1' tangent;

[0068] Figure 2MFor along Figure 2K A schematic diagram of the cross-sectional structure intercepted by the F2-F2' tangent;

[0069] Figure 3A This is a schematic diagram of the planar structure forming the initial gate layer in some embodiments of this application;

[0070] Figure 3B For along Figure 3A A schematic diagram of the cross-sectional structure intercepted by the G-G' tangent;

[0071] Figure 3C This is a schematic diagram of the planar structure forming the gate line and the second insulating fill portion in some embodiments of this application;

[0072] Figure 3D For along Figure 3C A schematic diagram of the cross-sectional structure intercepted by the H-H' tangent;

[0073] Figure 3E A schematic diagram of a planar structure in some embodiments of this application, showing the thinning of the second surface to form the third surface;

[0074] Figure 3F For along Figure 3E A schematic diagram of the cross-sectional structure intercepted by the I-I' tangent line;

[0075] Figure 4A This is a planar schematic diagram of a second mask pattern formed on a third surface in some embodiments of this application;

[0076] Figure 4B For along Figure 4A A schematic diagram of the cross-sectional structure intercepted by the tangent line J1-J1' in the diagram;

[0077] Figure 4C For along Figure 4A A schematic diagram of the cross-sectional structure intercepted by the tangent line J2-J2' in the diagram;

[0078] Figure 5A This is a schematic diagram of the planar structure of the lead wire receiving groove in some embodiments of this application;

[0079] Figure 5B For along Figure 5A A schematic diagram of the cross-sectional structure intercepted by the K1-K1' tangent;

[0080] Figure 5C For along Figure 5A A schematic diagram of the cross-sectional structure intercepted by the K2-K2' tangent;

[0081] Figure 5D This is a schematic diagram of the planar structure of the lead wire in some embodiments of this application, in which a shielding structure is formed in the lead wire receiving groove;

[0082] Figure 5E For along Figure 5D A schematic diagram of the cross-sectional structure intercepted by the M-M' tangent;

[0083] Figure 6A This is a schematic diagram of the planar structure forming the bit line in some embodiments of this application;

[0084] Figure 6B For along Figure 6A A schematic diagram of the cross-sectional structure intercepted by the N-N' tangent;

[0085] Figure 7A This is a schematic diagram of the planar structure forming bit line lead-out contacts, shielding structure lead-out contacts, and gate line lead-out contacts in some embodiments of this application;

[0086] Figure 7B This is a schematic diagram of the planar structure of the gate line, conductive shielding structure, channel structure, and redundant channel structure in some embodiments of this application;

[0087] Figure 7C For along Figure 7A A schematic diagram of the cross-sectional structure intercepted by the O1-O1' tangent;

[0088] Figure 7D For along Figure 7A A schematic diagram of the cross-sectional structure taken by the O2-O2' tangent;

[0089] Figure 8A This is a planar schematic diagram of a second mask pattern formed on a third surface in some other embodiments of this application;

[0090] Figure 8B For along Figure 8A A schematic diagram of the cross-sectional structure intercepted by the tangent line P1-P1' in the diagram;

[0091] Figure 8C For along Figure 8A A schematic diagram of the cross-sectional structure intercepted by the tangent line P2-P2' in the diagram;

[0092] Figure 8D This is a schematic diagram of the planar structure of the shielded structure lead wires, bit line lead contacts, shielded structure lead contacts, and gate line lead contacts in some other embodiments of this application.

[0093] Figure 8E For along Figure 8D A schematic diagram of the cross-sectional structure intercepted by the Q-Q' tangent;

[0094] Figure 9 This is a block diagram of a storage system according to some embodiments of this application;

[0095] Figure 10This is a block diagram of a storage system according to other embodiments of this application;

[0096] Figure 11 This is a block diagram of an electronic device according to some embodiments of this application.

[0097] Figure label:

[0098] x, first direction; y, second direction; z, third direction;

[0099] 11, Semiconductor layer; 11a, First surface; 11b, Second surface; 111, Semiconductor line; 11c1, Storage region; 11c2, Peripheral region; 11d, First groove; 11e, Second groove; 11f, Third groove; 11g, Fourth groove; 11h, Third surface; 112, Columnar semiconductor structure; 113, Channel structure; 114, Redundant channel structure; 1151, First electrode; 1152, Second electrode;

[0100] 121, First insulating layer; 122, First dielectric layer; 1231, First isolation layer; 1232, Second isolation layer; 1233, Protective layer; 1234, First insulating fill portion; 1235, Insulating pad portion; 1235a, Insulating pad top surface; 1235b, Insulating pad bottom surface; 1236, Gate insulating layer; 1237, Second insulating fill portion; 1238, Third isolation layer; 1239, Fourth isolation layer;

[0101] 131, First mask layer; 131a, First mask pattern; 132a, Second mask opening; 132b, Second mask pattern; 133a, Third mask opening; 133b, Third mask pattern;

[0102] 141, Conductive layer; 142, Conductive shielding structure; 142a, Conductive shielding bottom surface; 142b, Conductive shielding top surface;

[0103] 151, Initial gate layer; 1511, First initial conductive layer; 1512, Second initial conductive layer; 152, Gate line; 152a, Top surface of gate line; 152b, Bottom surface of gate line;

[0104] 161, Connecting contact point; 162, Capacitor; 163, First electrode; 164, Second electrode;

[0105] 171, Lead wire receiving slot; 1711, First lead wire receiving slot; 1712, Second lead wire receiving slot; 172, Shielded structure lead wire; 1721, First wire segment; 1722, Second wire segment;

[0106] 181, bit line; 182, bit line receiving slot;

[0107] 191, Bit line lead-out contact; 192, Shielding structure lead-out contact; 193, Gate line lead-out contact;

[0108] 100, Semiconductor device; 200, Memory; 300, Controller; 400, Storage system; 500, Electronic device; Host; 600. Detailed Implementation

[0109] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0110] Please refer to Figure 1 The diagram shown is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this application. The method for manufacturing a semiconductor device includes the following steps:

[0111] Step S101: A groove is formed in the semiconductor layer. The groove is recessed from the first surface of the semiconductor layer to the second surface. The remaining semiconductor layer includes a plurality of channel structures arranged in an array along the first direction and the second direction and extending along the third direction. The first surface and the second surface are disposed opposite each other in the third direction. The first direction intersects the second direction, and the third direction intersects the first direction and the second direction.

[0112] Step S102: A plurality of conductive shielding structures are formed in the semiconductor layer along the second direction, wherein the conductive shielding structures in the second direction are located between adjacent channel structures.

[0113] Step S103: Form a gate line extending along a first direction in the semiconductor layer, wherein the gate line is located between adjacent channel structures;

[0114] Step S104: Form a shielded structure lead wire, at least a portion of which extends along a second direction and is connected to at least two conductive shielded structures.

[0115] In some embodiments of this application, gate lines extending along a first direction are formed in the semiconductor layer, and shielding structure lead-out wires are also formed. At least a portion of the shielding structure lead-out wires extends along a second direction, and the first and second directions intersect. Therefore, the extension direction of at least a portion of the shielding structure lead-out wires intersects the extension direction of the gate lines. When shielding structure lead-out wires are led out using shielding structure lead-out contacts, the process window of the shielding structure lead-out contacts is not limited by the spacing between adjacent gate lines in the second direction, which reduces the manufacturing difficulty of the semiconductor device. Moreover, multiple conductive shielding structures are arranged at intervals along the second direction, and one shielding structure lead-out wire is connected to at least two conductive shielding structures. With this design, the number of shielding structure lead-out wires in the semiconductor device is reduced, further reducing the manufacturing difficulty of the semiconductor device.

[0116] The manufacturing process of the aforementioned semiconductor devices is described in detail below.

[0117] First, perform step S101 as described above, referring to... Figures 2A to 2M As shown, a groove is formed in the semiconductor layer 11. The groove is recessed from the first surface 11a to the second surface 11b of the semiconductor layer 11. The remaining semiconductor layer 11 includes a plurality of channel structures 113 arranged in an array along the first direction x and the second direction y and extending along the third direction z. The first surface 11a and the second surface 11b are disposed opposite to each other in the third direction z. The first direction x intersects the second direction y, and the third direction z intersects the first direction x and the second direction y.

[0118] In some embodiments, refer to Figure 2A and Figure 2B As shown, before forming a groove in the semiconductor layer 11, a method for manufacturing a semiconductor device includes: providing a semiconductor layer 11, the semiconductor layer 11 including a first surface 11a and a second surface 11b opposite to each other in a third direction z; and forming a first insulating layer 121 on the first surface 11a of the semiconductor layer 11.

[0119] Semiconductor layer 11 has adjacent memory region 11c1 and peripheral region 11c2, with peripheral region 11c2 located on at least one side of memory region 11c1 in a first direction x. Memory region 11c1 is used to form memory elements. The material of semiconductor layer 11 includes, but is not limited to, single-element semiconductor materials such as monocrystalline silicon. Specifically, semiconductor layer 11 includes a silicon wafer.

[0120] During the processing of semiconductor layer 11, the first insulating layer 121 protects semiconductor layer 11. The material of the first insulating layer 121 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the first insulating layer 121 includes silicon oxide to ensure that it can better adhere to semiconductor layer 11.

[0121] Any two of the first direction x, the second direction y, and the third direction z are perpendicular to each other, but not limited to these.

[0122] In some embodiments, please continue to refer to Figures 2A to 2D As shown, before forming a groove in the semiconductor layer 11, the method for manufacturing a semiconductor device includes: forming a first mask layer 131 on the surface of the first insulating layer 121 away from the semiconductor layer 11; and patterning the first mask layer 131 to form a first mask pattern 131a.

[0123] After patterning the first mask layer 131, a first mask pattern 131a is formed. Using the first mask pattern 131a as a mask, the semiconductor layer 11 can be patterned. The material of the first mask layer 131 may include at least one of inorganic insulating materials and organic insulating materials. Inorganic insulating materials include, but are not limited to, silicon nitride. Organic insulating materials include, but are not limited to, photoresist. Specifically, the material of the first mask layer 131 includes silicon nitride.

[0124] In some embodiments, please refer to Figure 2C and Figure 2D As shown, forming a groove in the semiconductor layer 11 includes forming a plurality of first grooves 11d in the semiconductor layer 11, and the remaining semiconductor layer 11 includes a plurality of semiconductor lines 111.

[0125] Specifically, a portion of the semiconductor layer 11 is removed by an etching process, and the remaining semiconductor layer 11 includes multiple semiconductor lines 111.

[0126] A plurality of first grooves 11d are provided at intervals along a first direction x. The plurality of first grooves 11d are recessed from a first surface 11a toward a second surface 11b and extend along a second direction y.

[0127] Multiple semiconductor lines 111 are arranged at intervals along a first direction x, and a first groove 11d is provided between two adjacent semiconductor lines 111. The multiple semiconductor lines 111 are disposed in a storage region 11c1 and a peripheral region 11c2. Each semiconductor line 111 extends along a second direction y and a third direction z. Each semiconductor line 111 includes a first end face and a second end face opposite each other in the second direction y. The first end faces of two adjacent semiconductor lines 111 are staggered. The second end faces of two adjacent semiconductor lines 111 are staggered.

[0128] In some embodiments, please continue to refer to Figure 2C and Figure 2D As shown, after forming multiple semiconductor lines 111, the method for manufacturing a semiconductor device further includes forming a first dielectric layer 122 in a first groove 11d.

[0129] In some embodiments of this application, adjacent semiconductor lines 111 are isolated by a first dielectric layer 122. The material of the first dielectric layer 122 includes at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0130] In some embodiments, before forming the first dielectric layer 122 in the first groove 11d, the method of manufacturing the semiconductor device further includes forming a second insulating layer (not shown) on the sidewalls of a plurality of semiconductor lines 111.

[0131] In some embodiments of this application, the second insulating layer serves to repair the sidewalls of the semiconductor line 111. Exemplarily, the sidewalls of the semiconductor line 111 are oxidized at high temperature to form the second insulating layer, but this is not a limitation.

[0132] In some embodiments, refer to Figure 2E and Figure 2F As shown, forming a groove in the semiconductor layer 11 further includes forming a plurality of second grooves 11e and a plurality of third grooves 11f extending along a third direction z and a first direction x and arranged along a second direction y in the semiconductor layer 11. The second grooves 11e and the third grooves 11f intersect with the semiconductor line 111 to form a columnar semiconductor structure 112. The size of the second groove 11e along the first direction x is smaller than the size of the third groove 11f along the first direction x.

[0133] In the second direction y, multiple second grooves 11e and multiple third grooves 11f are alternately arranged in a one-to-one manner. In the second direction y, the dimensions of the second grooves 11e and the third grooves 11f are the same. In the third direction z, the dimensions of the second grooves 11e and the third grooves 11f are also the same. In the first direction x, the dimensions of the second grooves 11e are smaller than the dimensions of the third grooves 11f.

[0134] In some embodiments, refer to Figure 2G and 2H As shown, after forming a plurality of second grooves 11e and a plurality of third grooves 11f, the method of manufacturing a semiconductor device further includes: forming a first isolation layer 1231 in the plurality of second grooves 11e and forming a second isolation layer 1232 in the plurality of third grooves 11f, wherein the first isolation layer 1231 and the second isolation layer 1232 are located on the sidewall of the columnar semiconductor structure 112.

[0135] In some embodiments, a first isolation layer 1231 and a second isolation layer 1232 may be formed in a plurality of second grooves 11e and a plurality of third grooves 11f respectively by a thin film deposition process. In other embodiments, the sidewalls of the columnar semiconductor structure 112 may be oxidized under heating conditions to form the first isolation layer 1231 and the second isolation layer 1232. The materials of the first isolation layer 1231 and the second isolation layer 1232 include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0136] Next, please refer to Figures 2G to 2J As shown, by performing step 102 above, a plurality of conductive shielding structures 142 arranged along the second direction y are formed in the semiconductor layer 11.

[0137] In some embodiments, forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11 includes: filling a plurality of second grooves 11e and a plurality of third grooves 11f with conductive layers 141; and removing the conductive layers 141 in the plurality of third grooves 11f, wherein at least a portion of the remaining conductive layers 141 in the plurality of second grooves 11e form a plurality of conductive shielding structures 142.

[0138] It should be noted that in some related technologies, a sacrificial layer needs to be formed in the third groove and a conductive layer needs to be formed in the second groove. The sacrificial layer and the conductive layer are formed using different materials and different steps. However, in some embodiments of this application, a conductive layer 141 is filled in both the third groove 11f and the second groove 11e. At least a portion of the remaining conductive layer 141 in the second groove 11e forms a conductive shielding structure 142, and the conductive layer 141 in the third groove 11f serves as a sacrificial layer, which helps to simplify the manufacturing process of semiconductor devices.

[0139] In some embodiments, the material of the conductive layer 141 includes at least one of a metallic material and a non-metallic conductive material. Metallic materials include, but are not limited to, copper, tungsten, and aluminum. Non-metallic conductive materials include, but are not limited to, titanium nitride.

[0140] In some embodiments, after filling the plurality of second grooves 11e and the plurality of third grooves 11f with conductive layer 141, and before removing the conductive layer 141 in the plurality of third grooves 11f, the method of manufacturing a semiconductor device further includes forming a protective layer 1233, the protective layer 1233 covering the conductive layer 141 in the plurality of third grooves 11f.

[0141] In some embodiments of this application, during the removal of a portion of the conductive layer 141 in the second groove 11e, the protective layer 1233 protects the conductive layer 141 in the third groove 11f. The material of the protective layer 1233 includes, but is not limited to, silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the protective layer 1233 includes silicon nitride.

[0142] In some embodiments, please refer to Figure 2I and Figure 2J As shown, after forming the protective layer 1233, forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11 further includes: removing a portion of the conductive layer 141 in the plurality of second grooves 11e, with the remaining conductive layer 141 in the plurality of second grooves 11e constituting the conductive shielding structure 142. The conductive shielding structure 142 includes a conductive shielding top surface 142b and a conductive shielding bottom surface 142a facing each other in the third direction z, with the conductive shielding bottom surface 142a contacting the bottom of the second grooves 11e.

[0143] In some embodiments of this application, a portion of the conductive layer 141 in the plurality of second grooves 11e is removed, making the conductive shielding top surfaces 142b of the plurality of conductive shielding structures 142 flush or substantially flush. Using this method, the dimensions of the conductive shielding structure 142 in the third direction z are controllable, thus providing a better shielding effect.

[0144] In some embodiments, the conductive shielding bottom surface 142a includes a curved surface, and the conductive shielding top surface 142b includes a flat surface.

[0145] In some embodiments, please continue to refer to Figure 2I and Figure 2J As shown, after forming a plurality of conductive shielding structures 142 arranged along the second direction y in the semiconductor layer 11, the method for manufacturing the semiconductor device further includes forming a first insulating fill portion 1234 filling the second groove 11e on the conductive shielding structures 142 in the second groove 11e. The material of the first insulating fill portion 1234 includes, but is not limited to, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0146] In some embodiments, please refer to Figure 2K , Figure 2L as well as Figure 2M As shown, the method for manufacturing a semiconductor device further includes removing the protective layer 1233 after forming the first insulating filling portion 1234.

[0147] In some embodiments, please continue to refer to Figure 2K , Figure 2L as well as Figure 2MAs shown, after removing the protective layer 1233, the method for manufacturing the semiconductor device further includes: removing the conductive layer 141 in the plurality of third grooves 11f; expanding the dimensions of the third grooves 11f along the third direction z and the second direction y to form a plurality of fourth grooves 11g, and the remaining columnar semiconductor structure 112 in the storage region 11c1 includes a plurality of channel structures 113.

[0148] In some embodiments of this application, the third groove 11f is widened to form a fourth groove 11g. The fourth groove 11g provides a forming accommodating space for forming the gate line 152 described below.

[0149] It should be noted that, while forming the fourth groove 11g, the remaining columnar semiconductor structure 112 includes multiple channel structures 113, which need to be connected to the bit line 181 described below. The multiple channel structures 113 are arranged in an array along the first direction x and the second direction y, and extend along the third direction z. The multiple channel structures 113 are located in the memory region 11c1.

[0150] In some embodiments, the method of manufacturing the semiconductor device further includes: the remaining columnar semiconductor structure 112 further includes a plurality of redundant channel structures 114 located in the peripheral region 11c2. The plurality of redundant channel structures 114 are used to improve the process yield of the plurality of channel structures 113, and the plurality of redundant channel structures 114 are not connected to the bit line 181. The plurality of redundant channel structures 114 are located in the peripheral region 11c2.

[0151] In some embodiments, in the first direction x, a plurality of redundant channel structures 114 are located on at least one side of a plurality of channel structures 113. Specifically, in the first direction x, a plurality of redundant channel structures 114 are located on one side of a plurality of channel structures 113.

[0152] In other embodiments, in the first direction x, the plurality of redundant channel structures 114 may also be located on both sides of the plurality of channel structures 113.

[0153] Next, refer to Figures 3A to 3D As shown, the above step S103 is performed: a gate line 152 extending along the first direction x is formed in the semiconductor layer 11, and the gate line 152 is located between adjacent channel structures 113.

[0154] In some embodiments, refer to Figure 3A and Figure 3BAs shown, before forming the gate line 152 extending along the first direction x in the semiconductor layer 11, the method for manufacturing the semiconductor device further includes forming an insulating pad portion 1235 at the bottom of the fourth groove 11g. The insulating pad portion 1235 includes an insulating pad top surface 1235a and an insulating pad bottom surface 1235b opposite to each other in the third direction z, with the insulating pad bottom surface 1235b contacting the groove wall of the fourth groove 11g.

[0155] In some embodiments of this application, the insulating pad 1235 serves to isolate the gate line 152 and the semiconductor layer 11. Adjusting the dimensions of the insulating pad 1235 in the third z-direction allows for adjustment of the dimensions of the gate line 152 in that direction. The top surface 1235a of the insulating pad is planar, facilitating adjustment of the dimensions of the gate line 152 in the third z-direction. The bottom surface 1235b of the insulating pad is curved. The material of the insulating pad 1235 includes at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0156] In some embodiments, on the third direction z, the conductive shielding bottom surface 142a is located between the insulating pad top surface 1235a and the insulating pad bottom surface 1235b, such that the insulating pad top surface 1235a is located above the conductive shielding bottom surface 142a. This facilitates the area of ​​action of the gate voltage transmitted by the gate line 152 on the channel structure 113 to be covered by the conductive shielding structure 142, ensuring that the conductive shielding structure 142 can better play its shielding role.

[0157] In some embodiments, please continue to refer to Figure 3A and Figure 3B As shown, after forming the insulating pad 1235, the semiconductor device manufacturing method further includes forming a gate insulating layer 1236 on the trench wall of the fourth trench 11g. The gate insulating layer 1236 serves to isolate the gate line 152 from the channel structure 113 and the redundant channel structure 114. The material of the gate insulating layer 1236 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0158] In some embodiments, refer to Figure 3C and Figure 3D As shown, forming a gate line 152 extending along the first direction x in the semiconductor layer 11 includes forming a plurality of gate lines 152 extending along the first direction x and arranged along the second direction y in a plurality of fourth grooves 11g.

[0159] Specifically, refer to Figures 3A to 3DAs shown, forming a gate line 152 extending along the first direction x in the semiconductor layer 11 includes: forming an initial gate layer 151 in the fourth groove 11g that covers the gate insulating layer 1236 and the insulating pad portion 1235; and removing a portion of the initial gate layer 151, with the remaining initial gate layer 151 constituting a plurality of gate lines 152.

[0160] In some embodiments, refer to Figure 3A and Figure 3B As shown, the initial gate layer 151 includes a first initial conductive layer 1511 and a second initial conductive layer 1512. A portion of the first initial conductive layer 1511 is located on the trench wall of the fourth trench 11g, and the second initial conductive layer 1512 covers the first initial conductive layer 1511. The fourth trench 11g forming the initial gate layer 151 still has gaps, meaning the initial gate layer 151 does not fill the fourth trench 11g. The materials of the first initial conductive layer 1511 and the second initial conductive layer 1512 include at least one of metallic and non-metallic materials. Metallic materials include, but are not limited to, copper, tungsten, and aluminum. Non-metallic conductive materials include, but are not limited to, titanium nitride.

[0161] In some embodiments, removing a portion of the initial gate layer 151 includes: removing the initial gate layer 151 outside the fourth recess 11g, and removing a portion of the initial gate layer 151 in the fourth recess 11g, forming two disconnected gate lines 152 in each fourth recess 11g.

[0162] Reference Figure 3D As shown, gate line 152 includes a gate line top surface 152a and a gate line bottom surface 152b opposite each other in the third direction z. The gate line bottom surface 152b contacts the insulating pad top surface 1235a. Both the gate line top surface 152a and the gate line bottom surface 152b include planes, which makes the dimensions of gate line 152 more controllable in the third direction z, and makes it easier to control the uniformity of the dimensions of multiple gate lines 152.

[0163] In some embodiments, the top surface 152a of the gate line is flush with or substantially flush with the top surface 142b of the conductive shield, or, in the third direction z, the top surface 152a of the gate line is located between the top surface 142b and the bottom surface 142a of the conductive shield. With this design, the area of ​​effect of the gate voltage transmitted by the gate line 152 on the channel structure 113 is covered by the conductive shield structure 142, ensuring that the conductive shield structure 142 can better perform its shielding function.

[0164] In some embodiments, please continue to refer to Figure 3C and Figure 3DAs shown, after forming multiple gate lines 152, the semiconductor device manufacturing method further includes forming a second insulating filler portion 1237 covering the multiple gate lines 152 and filling a fourth groove 11g. The material of the second insulating filler portion 1237 is the same as the material of the first insulating filler portion 1234. The material of the second insulating filler portion 1237 includes, but is not limited to, at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0165] In some embodiments, please refer to Figure 3E and Figure 3F As shown, the method for manufacturing a semiconductor device further includes: doping one end of a plurality of channel structures 113 away from the second surface 11b to form a plurality of first electrodes 163; forming a plurality of connection contacts 161 respectively connected to the plurality of first electrodes 163; forming a plurality of capacitors 162 connected to the plurality of connection contacts 161; and forming a third isolation layer 1238 between the plurality of capacitors 162.

[0166] In some embodiments, please continue to refer to Figure 3E and Figure 3F As shown, the method for manufacturing a semiconductor device further includes: flipping the semiconductor layer 11 so that the second surface 11b of the semiconductor layer 11 faces upward and the first surface 11a faces downward; thinning the second surface 11b of the semiconductor layer 11 to expose the first dielectric layer 122; and forming a thinned third surface 11h.

[0167] In some embodiments, please refer to Figures 4A to 4C As shown, before forming the shielding structure lead wire 172, the semiconductor device manufacturing method further includes: forming a second mask layer covering the third surface 11h; forming a second mask opening 132a on the second mask layer, and forming a second mask pattern 132b on the remaining second mask layer, with the second mask opening 132a exposing the first dielectric layer 122 and the semiconductor layer 11 adjacent to the redundant channel structure 114.

[0168] Finally, please refer to Figures 5A to 5E As shown, by performing the above step S104, a shielded structure lead wire 172 is formed. At least a portion of the shielded structure lead wire 172 extends along the second direction y and is connected to at least two conductive shielded structures 142.

[0169] In some embodiments, please refer to Figures 5A to 5CAs shown, the shielded structure lead wire 172 includes: removing a portion of a first dielectric layer 122 adjacent to the redundant channel structure 114, forming a lead wire receiving groove 171 overlapping the first dielectric layer 122, the lead wire receiving groove 171 being recessed from the third surface 11h to the first surface 11a, the lead wire receiving groove 171 exposing a plurality of conductive shielding structures 142, and at least a portion of the lead wire receiving groove 171 extending along the second direction y.

[0170] It should be noted that in order to expose multiple conductive shielding structures 142, in addition to removing the first dielectric layer 122 adjacent to the redundant channel structure 114, it is also necessary to remove the first isolation layer 1231 covering the conductive shielding bottom surface 142a of the conductive shielding structure 142.

[0171] In some embodiments, at least a portion of the lead wire receiving groove 171 further extends along a second direction y, which facilitates the exposure of a plurality of conductive shielding structures 142 by one lead wire receiving groove 171. In addition to extending along the second direction y, a portion of the lead wire receiving groove 171 may also extend along a first direction x.

[0172] Specifically, the lead wire receiving slot 171 includes two first lead wire receiving slots 1711 extending along a second direction y and a second lead wire receiving slot 1712 extending along a first direction x. The second lead wire receiving slot 1712 is located on one side of the two first lead wire receiving slots 1711 and communicates with the two first lead wire receiving slots 1711. The lead wire receiving slots 171 are arranged around a plurality of redundant channel structures 114.

[0173] In some embodiments, please refer to Figure 5D and Figure 5E As shown, the shielded structure lead wire 172 further includes: a shielded structure lead wire 172 formed in the lead wire receiving groove 171 that contacts the plurality of conductive shielding structures 142, and the shielded structure lead wire 172 is adjacent to and spaced apart from the redundant channel structure 114 in the first direction x.

[0174] In some embodiments, at least a portion of the shielding structure lead wire 172 extends along the second direction y, such that one shielding structure lead wire 172 is connected to a plurality of conductive shielding structures 142, thereby reducing the number of shielding structure lead wires 172.

[0175] Specifically, the shielding structure lead wire 172 includes two first conductor segments 1721 extending along the second direction y and a second conductor segment 1722 extending along the first direction x, to reduce the impedance of the shielding structure lead wire 172. The first conductor segments 1721 and 1722 are connected and in contact with a plurality of conductive shielding structures 142. The first conductor segments 1721 are located within the first lead wire receiving groove 1711. The second conductor segment 1722 is located within the second lead wire receiving groove 1712.

[0176] In some embodiments, the shielded structure lead wire 172 includes a first shielded structure lead layer (not shown) and a second shielded structure lead layer (not shown). The first shielded structure lead layer contacts the wall of the lead wire receiving groove 171, and the second shielded structure lead layer covers the first shielded structure lead layer and fills the lead wire receiving groove 171. The material of the shielded structure lead wire 172 includes at least one of a metallic material and a non-metallic conductive material. The metallic material includes, but is not limited to, copper, tungsten, and aluminum. The non-metallic conductive material includes, but is not limited to, titanium nitride.

[0177] In some embodiments, refer to Figure 6A and Figure 6B As shown, after forming the shielding structure lead wire 172, the semiconductor device manufacturing method further includes removing the second mask pattern 132b; forming a third mask layer covering the third surface 11h and the shielding structure lead wire 172; forming a third mask opening on the third mask layer, the remaining third mask layer forming a third mask pattern 133b, and the third mask opening exposing the first dielectric layer 122 and the semiconductor layer 11 adjacent to the channel structure 113.

[0178] In some embodiments, please continue to refer to Figure 6A and Figure 6B As shown, the method for manufacturing a semiconductor device further includes: doping one end of a plurality of channel pillars away from the first electrode 163 to form a second electrode 164; forming a plurality of bit lines 181 extending along the second direction y and arranged along the first direction x, wherein the plurality of bit lines 181 are respectively connected to one end of a plurality of channel structures 113 in the third direction z.

[0179] In some embodiments, forming a plurality of bit lines 181 extending along a second direction y and arranged along a first direction x includes: forming a bit line receiving groove 182, the bit line receiving groove 182 being recessed from a third surface 11h toward a first surface 11a, the bit line receiving groove 182 extending along the second direction y and overlapping with a plurality of channel structures 113; and forming a plurality of bit lines 181 in the bit line receiving groove 182, the plurality of bit lines 181 being connected to one end of a plurality of channel structures 113 and disconnected from a plurality of redundant channel structures 114.

[0180] In some embodiments, forming the bit line receiving groove 182 includes removing the semiconductor layer 11 on the third surface 11h that overlaps with the channel structure 113.

[0181] In some embodiments, refer to Figure 7A and Figure 7C As shown, the method for manufacturing a semiconductor device further includes: forming a plurality of bit line lead-out contacts 191, wherein the plurality of bit line lead-out contacts 191 are respectively connected to a plurality of bit lines 181.

[0182] In some embodiments, refer to Figure 7A As shown, the method for manufacturing a semiconductor device further includes: forming a shielding structure lead-out contact 192 connected to a shielding structure lead-out wire 172, wherein the shielding structure lead-out contact 192 and the bit line lead-out contact 191 are located on the same side of a plurality of channel structures 113 in a third direction z, and the shielding structure lead-out contact 192 is located on at least one side of a bit line 181 in a second direction y.

[0183] In some embodiments, refer to Figure 7A and Figure 7B As shown, multiple gate line lead-out contacts 193 are formed. The multiple gate line lead-out contacts 193 are located on both sides of the bit line 181 in the first direction x and are respectively connected to multiple gate lines 152.

[0184] In some embodiments, gate line lead-out contacts 193, bit line lead-out contacts 191, and shielding structure lead-out contacts 192 are formed simultaneously to simplify the manufacturing process of semiconductor devices.

[0185] In other embodiments, please refer to Figure 8A , Figure 8B as well as Figure 8C As shown, forming a shielded structure lead wire 172 includes: removing a portion of the semiconductor layer 11 adjacent to the redundant channel structure 114, forming a lead wire receiving groove 171 overlapping with the redundant channel structure 114, the lead wire receiving groove 171 being recessed from the third surface 11h to the first surface 11a, the lead wire receiving groove 171 exposing a plurality of conductive shielding structures 142, and at least a portion of the lead wire receiving groove 171 extending along the second direction y.

[0186] It should be noted that, as mentioned above, in order to expose multiple conductive shielding structures 142, in addition to removing the first dielectric layer 122 adjacent to the redundant channel structure 114, it is also necessary to remove the first isolation layer 1231 covering the conductive shielding bottom surface 142a of the conductive shielding structure 142.

[0187] Specifically, the lead wire receiving groove 171 contacts a row of redundant channel structures 114 arranged along the second direction y.

[0188] In other embodiments, please refer to Figure 8D and Figure 8E As shown, the shielded structure lead wire 172 further includes: forming a shielded structure lead wire 172 in the lead wire receiving groove 171 that contacts the plurality of conductive shielding structures 142, and the shielded structure lead wire 172 contacts the redundant channel structure 114.

[0189] In some other embodiments, the portion of the first dielectric layer 122 adjacent to the redundant channel structure 114 and the portion of the semiconductor layer 11 adjacent to it may be removed to form a lead wire receiving groove 171 that overlaps with the redundant channel structure 114 and the first dielectric layer 122. The lead wire receiving groove 171 is recessed from the third surface 11h to the first surface 11a. The lead wire receiving groove 171 exposes a plurality of conductive shielding structures 142, and at least a portion of the lead wire receiving groove 171 extends along the second direction y.

[0190] This application also provides a semiconductor device obtained by the above-described semiconductor device manufacturing method. The following is in conjunction with... Figures 7A to 7D as well as Figure 8D and Figure 8E The semiconductor devices of some embodiments of this application are described in detail.

[0191] Reference Figures 7A to 7D as well as Figure 8D and Figure 8E As shown, the semiconductor device 100 includes multiple channel structures 113, multiple conductive shielding structures 142, multiple gate lines 152, shielding structure lead wires 172, multiple bit lines 181, capacitors 162, multiple bit line lead contacts 191, shielding structure lead contacts 192, redundant channel structures 114, and multiple gate line lead contacts 193.

[0192] Reference Figure 7B As shown, multiple channel structures 113 are arranged in an array along a first direction x and a second direction y, and extend along a third direction z. The first direction x intersects the second direction y, and the third direction z intersects both the first direction x and the second direction y. Specifically, any two of the first direction x, the second direction y, and the third direction z are perpendicular to each other, but are not limited thereto.

[0193] Reference Figure 7C As shown, the channel structure 113 is in contact with a first electrode 163 and a second electrode 164 at its two opposite ends in the third direction z. One of the first electrode 163 and the second electrode 164 is the source, and the other is the drain. One end of the channel structure 113 is connected to the bit line 181 through the second electrode 164. The first electrode 163 is connected to the capacitor 162 through the connection contact point 161, so that the other end of the channel structure 113 in the third direction z is connected to the capacitor 162 through the first electrode 163.

[0194] Reference Figure 7B As shown, in some embodiments, in the first direction x, a plurality of redundant channel structures 114 are located on at least one side of a plurality of channel structures 113. The redundant channel structures 114 extend along a third direction z and are disconnected from a plurality of bit lines 181. Specifically, in the first direction x, the plurality of redundant channel structures 114 are located on both sides of the plurality of channel structures 113. In other embodiments, in the first direction x, the plurality of channel structures 113 may also be located on both sides of the plurality of redundant channel structures 114.

[0195] Reference Figure 7B and Figure 7C As shown, multiple conductive shielding structures 142 extend along a first direction x and a third direction z, and are arranged at intervals along a second direction y. In the second direction y, the conductive shielding structures 142 are located between adjacent rows of channel structures 113 to shield against the coupling effect between adjacent channel structures 113 in the second direction y. Parts of the multiple conductive shielding structures 142 are also located between adjacent redundant channel structures 114 in the second direction y. A first isolation layer 1231 is provided between the conductive shielding structures 142 and the sidewalls of the redundant channel structures 114. A first isolation layer 1231 is also provided between the conductive shielding structures 142 and the sidewalls of the channel structures 113.

[0196] The conductive shielding structure 142 includes a conductive shielding top surface 142b and a conductive shielding bottom surface 142a opposite each other in the z-direction. The conductive shielding top surface 142b is disposed near the first electrode 163, and the conductive shielding bottom surface 142a is disposed near the second electrode 164. The conductive shielding bottom surface 142a includes a curved surface, and the conductive shielding top surface 142b includes a flat surface. The conductive shielding top surface 142b is in contact with the first insulating filler portion 1234. The first insulating filler portion 1234 provides protection for the conductive shielding structure 142.

[0197] Reference Figure 7B As shown, multiple gate lines 152 extend along a first direction x and a third direction z, and are arranged along a second direction y. In the second direction y, each gate line 152 is located between two adjacent rows of channel structures 113. A portion of each gate line 152 is also located between two adjacent redundant channel structures 114 in the second direction y. In the second direction y, two disconnected gate lines 152 are disposed between two adjacent conductive shielding structures 142.

[0198] Reference Figure 7CAs shown, the gate line 152 includes a top surface 152a and a bottom surface 152b opposite each other in the third direction z. The top surface 152a is disposed near the first electrode 163, and the bottom surface 152b is disposed near the second electrode 164. Both the top surface 152a and the bottom surface 152b are planar, which makes the size of the gate line 152 in the third direction z more controllable, and makes it easier to control the uniformity of the size of multiple gate lines 152.

[0199] The bottom surface 152b of the gate line contacts the insulating pad portion 1235, and the top surface 152a of the gate line 152 contacts the second insulating fill portion 1237. The insulating pad portion 1235 includes an insulating pad top surface 1235a and an insulating pad bottom surface 1235b opposite each other in the third direction z, and the insulating pad top surface 1235a contacts the bottom surface 152b of the gate line.

[0200] In some embodiments, on the third direction z, the conductive shielding bottom surface 142a is located between the insulating pad top surface 1235a and the insulating pad bottom surface 1235b, such that the insulating pad top surface 1235a is located above the insulating pad top surface 1235a. This facilitates the area of ​​action of the gate voltage transmitted by the gate line 152 on the channel structure 113 being covered by the conductive shielding structure 142, ensuring that the conductive shielding structure 142 can better perform its shielding function.

[0201] In some embodiments, the top surface 152a of the gate line is flush with or substantially flush with the top surface 142b of the conductive shield, or, in the third direction z, the top surface 152a of the gate line is located between the top surface 142b and the bottom surface 142a of the conductive shield. With this design, the area of ​​effect of the gate voltage transmitted by the gate line 152 on the channel structure 113 is covered by the conductive shield structure 142, ensuring that the conductive shield structure 142 can better perform its shielding function.

[0202] Reference Figure 7A and Figure 8D As shown, at least a portion of the shielding structure lead wire 172 extends along the second direction y and connects to at least two conductive shielding structures 142. With this design, the extension direction of at least a portion of the shielding structure lead wire 172 intersects the extension direction of the gate line 152. When the shielding structure lead wire 172 is led out using the shielding structure lead contact 192, the process window of the shielding structure lead contact 192 is not limited by the spacing between adjacent gate lines 152 in the second direction y, reducing the manufacturing difficulty of the semiconductor device. Furthermore, multiple conductive shielding structures 142 are arranged at intervals along the second direction y, and one shielding structure lead wire 172 connects to at least two conductive shielding structures 142. With this design, the number of shielding structure lead wires 172 in the semiconductor device is reduced, further reducing the manufacturing difficulty of the semiconductor device.

[0203] In some embodiments, in the third direction z, the shielding structure lead wire 172 and the plurality of bit lines 181 are located on the same side of the channel structure 113, and in the first direction x, the shielding structure lead wire 172 is located on at least one side of the bit lines 181. Meanwhile, in the third direction z, the capacitor 162 and the shielding structure lead wire 172 are located on opposite sides of the channel structure 113.

[0204] In other embodiments, the shielding structure lead wire 172 may also be located on the same side of the channel structure 113 as the capacitor 162. Meanwhile, in the third direction z, the bit line 181 and the shielding structure lead wire 172 are located on opposite sides of the channel structure 113.

[0205] In some embodiments, the shielded structure lead wire 172 is disposed adjacent to the redundant channel structure 114, so that the shielded structure lead wire 172 is disposed in the area where the redundant channel structure 114 is disposed, thereby improving the problem that the area where the bit line 181 is located is disposed of by the shielded structure lead wire 172, which in turn leads to a reduction in the area where the bit line 181 is disposed.

[0206] In other embodiments, reference is made to Figure 7A As shown, in the first direction x, the shielding structure lead wire 172 is spaced apart from the redundant channel structure 114. Therefore, the shielding structure lead wire 172 is located in a region adjacent to and spaced apart from the redundant channel structure 114.

[0207] In other embodiments, reference is made to Figure 8D and Figure 8E As shown, the shielding structure lead wire 172 contacts the redundant channel structure 114. Therefore, in the third direction z, the shielding structure lead wire 172 is located in the region overlapping with the redundant channel structure 114.

[0208] In some embodiments, refer to Figure 7A and Figure 7D As shown, the shielding structure lead wire 172 includes a first wire segment 1721 extending along the second direction y and a second wire segment 1722 extending along the first direction x. The first wire segment 1721 is connected to the second wire segment 1722 and is in contact with a plurality of conductive shielding structures 142.

[0209] Specifically, the shielding structure lead wire 172 includes two first wire segments 1721 extending along the second direction y and a second wire segment 1722 extending along the first direction x. The first wire segments 1721 are connected to the second wire segments 1722 and are in contact with the plurality of conductive shielding structures 142.

[0210] In other embodiments, reference is made to Figure 8DAs shown, the shielding structure lead wire 172 is straight and extends along the second direction y.

[0211] Reference Figure 7A and Figure 7C As shown, multiple bit lines 181 extend along the second direction y and are arranged along the first direction x, and are respectively connected to multiple channel structures 113 at one end in the third direction z. In the first direction x, a shielded structure lead-out conductor 172 is located on at least one side of the multiple bit lines 181. Specifically, in the first direction x, a shielded structure lead-out conductor 172 is located on one side of the multiple bit lines 181.

[0212] Reference Figure 7A As shown, multiple bit line lead-out contacts 191 are connected to multiple bit lines 181 respectively. Shielding structure lead-out contacts 192 are connected to shielding structure lead-out wires 172. In the third direction z, the shielding structure lead-out contacts 192 and the bit line lead-out contacts 191 are located on the same side of the channel structure 113, and in the second direction y, they are located on at least one side of the bit line 181. In the second direction y, the multiple bit line lead-out contacts 191 and the shielding structure lead-out contacts 192 are located on both sides of the gate line 152 respectively.

[0213] It should be noted that the shielding structure leads to contact 192 and loads a ground potential or a fixed voltage, transmitting the ground potential and fixed voltage to the conductive shielding structure 142, which can improve the coupling effect of the gate voltage transmitted by the gate line on the adjacent channel structure.

[0214] Reference Figure 7A and Figure 7B As shown, multiple gate line lead-out contacts 193 are located on both sides of bit line 181 in the first direction x, and are respectively connected to multiple gate lines 152.

[0215] In some embodiments, multiple bit line lead-out contacts 191, multiple gate line lead-out contacts 193, and shielding structure lead-out contacts 192 all penetrate the fourth isolation layer 1239, which covers multiple bit lines 181 and shielding structure lead-out wires 172. This design facilitates the simultaneous formation of multiple bit line lead-out contacts 191, multiple gate line lead-out contacts 193, and shielding structure lead-out contacts 192, reducing the photomasks required for manufacturing semiconductor devices and simplifying the semiconductor device manufacturing process.

[0216] In addition, see Figure 9 and Figure 10 As shown, based on the same inventive concept, this application also provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the embodiments described above.

[0217] The storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein.

[0218] In some embodiments, refer to Figure 9 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 can be integrated into a 3D memory card.

[0219] Among them, 3D memory cards include any one of the following: PC card (PCMCIA, the International Association for Personal Computer 3D Memory Cards), Compact Flash (CF) card, Smart Media (SM) card, 3D memory, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0220] In other embodiments, reference is made to Figure 10 As shown, the storage system 400 includes multiple memory units 200 and a controller 300. The storage system 400 is integrated into a solid-state drive (SSD).

[0221] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0222] In other embodiments, in storage system 400, controller 300 is configured to operate in high duty cycle environments in SSDs or eMMCs used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0223] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and to communicate with external devices (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions relating to data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes relating to data read from or written to the memory 200.

[0224] Of course, controller 300 can also perform any other suitable functions, such as formatting memory 200; for example, controller 300 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0225] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0226] Please refer to Figure 11 Some embodiments of this application also provide an electronic device 500. The electronic device 500 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0227] Electronic device 500 may include the aforementioned storage system 400 and host 600, wherein host 600 includes at least one of a central processing unit (CPU) and a cache.

[0228] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Multiple channel structures are arranged in an array along a first direction and a second direction, and extend along a third direction, wherein the first direction intersects the second direction, and the third direction intersects both the first direction and the second direction; Multiple conductive shielding structures are arranged along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction; Gate lines extending along the first direction and the third direction, and the gate lines being located between adjacent channel structures; as well as A shielding structure leads out a wire, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielding structures.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: a plurality of bit lines extending along the second direction and arranged along the first direction, and respectively connected to one end of the plurality of channel structures in the third direction; Multiple bit line lead-out contacts are respectively connected to the multiple bit lines; and The shielding structure leads out a contact, which is connected to the shielding structure leads out a wire. In the third direction, it is located on the same side of the channel structure as the bit line leads out a contact, and in the second direction, it is located on at least one side of the bit line.

3. The semiconductor device according to claim 2, characterized in that, In the third direction, multiple bit lines and the lead wires of the shielding structure are located on the same side of the channel structure, and in the first direction, the lead wires of the shielding structure are located on at least one side of the bit lines.

4. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: a redundant channel structure extending along the third direction, disconnected from the plurality of bit lines; and a shielding structure lead wire disposed adjacent to the redundant channel structure.

5. The semiconductor device according to claim 4, characterized in that, In the first direction, the lead wires of the shielding structure are spaced apart from the redundant channel structure.

6. The semiconductor device according to claim 4 or 5, characterized in that, The lead wire of the shielding structure is in contact with the redundant channel structure.

7. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: a plurality of gate line lead-out contacts, located on both sides of the bit line in the first direction, and respectively connected to the plurality of gate lines; In the second direction, the plurality of bit line lead-out contacts and the shielding structure lead-out contacts are respectively located on both sides of the gate line.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a capacitor connected to the other end of the channel structure in the third direction. In the third direction, the capacitor and the lead wire of the shielding structure are located on both sides of the channel structure.

9. The semiconductor device according to claim 1, characterized in that, The shielding structure leads out along the second direction; or... The shielding structure leads include a first conductor segment extending along the second direction and a second conductor segment extending along the first direction. The first conductor segment is connected to the second conductor segment and is in contact with a plurality of conductive shielding structures.

10. A method for manufacturing a semiconductor device, characterized in that, include: A groove is formed in the semiconductor layer, the groove being recessed from a first surface to a second surface of the semiconductor layer, and the remaining semiconductor layer includes a plurality of channel structures arranged in an array along a first direction and a second direction and extending along a third direction, the first surface and the second surface being disposed opposite each other in the third direction, the first direction intersecting the second direction, and the third direction intersecting the first direction and the second direction; A plurality of conductive shielding structures are formed in the semiconductor layer along the second direction, wherein the conductive shielding structures are located between adjacent channel structures in the second direction; Gate lines extending along the first direction and the third direction are formed in the semiconductor layer, and the gate lines are located between adjacent channel structures; as well as A shielded structure leads out, at least a portion of which extends along the second direction and is connected to at least two of the conductive shielded structures.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The method further includes: forming a plurality of bit lines extending along the second direction and arranged along the first direction, wherein the plurality of bit lines are respectively connected to one end of a plurality of channel structures in the third direction; Forming multiple bit line lead-out contacts that are respectively connected to the multiple bit lines; and A shielding structure lead-out contact is formed to connect with the lead-out wire of the shielding structure. The shielding structure lead-out contact and the bit line lead-out contact are located on the same side of the plurality of channel structures in the third direction. The shielding structure lead-out contact is located on at least one side of the bit line in the second direction.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The formation of multiple bit lines extending along the second direction and arranged along the first direction includes: in the third direction, arranging the multiple bit lines and the shielding structure lead wires on the same side of the multiple channel structures, and in the first direction, arranging the shielding structure lead wires on at least one side of the bit lines.

13. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The method further includes: making the remaining semiconductor layer further include a redundant channel structure extending along the third direction; The formation of multiple bit lines extending along the second direction and arranged along the first direction includes: forming multiple bit lines that are disconnected from the redundant channel structure; The formation of the shielded structure lead wire includes: forming the shielded structure lead wire disposed adjacent to the redundant channel structure.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The method further includes: filling the groove with a dielectric layer; The second surface of the semiconductor layer is thinned to expose the dielectric layer, and a thinned third surface is formed; and The dielectric layer and / or the semiconductor layer adjacent to the redundant channel structure are removed to form a lead wire receiving groove, the lead wire receiving groove exposing a plurality of the conductive shielding structures, and at least a portion of the lead wire receiving groove extends along the third direction, the lead wire receiving groove being recessed from the third surface toward the first surface. The formation of the shielded structure lead wire includes: forming a shielded structure lead wire in the lead wire receiving groove that contacts the plurality of conductive shielding structures.

15. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The process of forming a groove in the semiconductor layer includes: A first groove extending along the second direction and the third direction is formed in the semiconductor layer, and the remaining semiconductor layer includes semiconductor lines; A plurality of second grooves and a plurality of third grooves are formed in the semiconductor layer, extending along the third direction and the first direction and arranged along the second direction. The second grooves and the third grooves intersect the semiconductor line. The size of the second groove along the first direction is smaller than the size of the third groove along the first direction. The formation of a plurality of conductive shielding structures arranged along the second direction in the semiconductor layer includes: filling a conductive layer into a plurality of second grooves and a plurality of third grooves; and The conductive layer in the plurality of third grooves is removed, and at least a portion of the remaining conductive layer in the plurality of second grooves forms a plurality of conductive shielding structures.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, The method further includes: increasing the size of the third groove along the third direction and the second direction to form a plurality of fourth grooves; The formation of gate lines extending in the first direction in the semiconductor layer includes: forming multiple gate lines extending in the first direction and arranged in the second direction in the multiple fourth grooves respectively; The method further includes: forming a plurality of gate line lead-out contacts, wherein the plurality of gate line lead-out contacts are located on both sides of the bit line in the first direction and are respectively connected to the plurality of gate lines.

17. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The method further includes: forming a capacitor connected to the other end of the plurality of said channel structures in the third direction; The formation of the shielded structure lead wire includes: forming the shielded structure lead wire on the side of the channel structure away from the capacitor in the third direction.

18. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The formation of the shielding structure lead wire includes: forming the shielding structure lead wire extending along the second direction and in contact with the plurality of conductive shielding structures; or... The formation of the shielding structure lead wire includes: making the shielding structure lead wire include a first wire segment extending along the second direction and a second wire segment extending along the first direction, wherein the first wire segment is connected to the second wire segment and is in contact with the plurality of conductive shielding structures.

19. A storage system, characterized in that, The storage system includes: Memory, including the semiconductor device as described in any one of claims 1-9; and A controller, connected to the memory, is used to control the memory.

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