Insulated gate bipolar transistor

Abstract

The invention relates to an insulated gate bipolar transistor. The insulated gate bipolar transistor comprises a substrate, a collector, a gate, an insulating layer and a plurality of emitters, the substrate includes a trench, a drift region, a first surface and a second surface. The drift region is disposed corresponding to the first surface and has a first conductivity type. The trench is formed by recessing the first surface toward the drift region. The trench includes an inner wall. The collector is formed on the second surface of the substrate and has the second conductive type. The gate is formed in the trench. The insulating layer is formed between the gate and the inner wall of the trench and includes a side edge. The plurality of emitters are respectively formed from the first surface of the substrate towards the drift region, are adjacent to the side edge of the insulating layer, and have the first conductive type. The plurality of emitters are arranged at intervals along the side edge.

Description

Technical Field

[0001] This case relates to a semiconductor device, particularly an insulated gate bipolar transistor. Background Art

[0002] Generally speaking, insulated gate bipolar transistors (IGBTs) are often used in the output control of AC motors in electric vehicles, and have the advantages of small drive current and low on-resistance. However, when a short circuit occurs, the IGBT will burn out in a short time under the condition of large short-circuit current. On the contrary, in order to reduce the short-circuit current, the saturation current must be suppressed, which will cause the saturation voltage drop (Collector-Emitter saturation voltage) of the power supply on the IGBT to increase and cause energy loss. Therefore, the short-circuit current needs to be controlled within an appropriate range to avoid device damage or energy loss.

[0003] Figure 1 Schematic diagram of the cross-sectional structure of an existing insulated gate bipolar transistor. The existing insulated gate bipolar transistor 900 includes multiple gates 901, a hot carrier injection region 902, multiple emitters 903 and a well region 904. The well region 904 is formed in the upper layer of the hot carrier injection region 902 and is located between two adjacent gates 901. Multiple emitters 903 are respectively formed on both sides of the multiple gates 901. The short-circuit current is related to the density of the emitters 903, wherein the density of the emitters 903 is related to the distance D between two adjacent gates 901. Therefore, the existing IGBT usually adjusts the short-circuit current to an appropriate range by adjusting the distance D. However, in response to different wafer designs, the above method requires the preparation of a large number of different wafers and masks for development and testing, and the setting positions of multiple components such as the gate, the insulating layer and the emitter must be adjusted to adjust the short-circuit current to an appropriate range, resulting in high costs.

[0004] In view of this, it is necessary to develop an insulated gate bipolar transistor to solve the problems faced by the prior art. Summary of the invention

[0005] The purpose of this case is to provide an insulated gate bipolar transistor, which can achieve the effects of reducing costs, avoiding device damage and reducing energy loss.

[0006] To achieve the above-mentioned purpose, a general implementation of the present invention is to provide an insulated gate bipolar transistor, including a substrate, a collector, at least one gate, at least one insulating layer and a plurality of emitters. The substrate includes at least one trench, a drift region, a first surface and a second surface. The first surface and the second surface are two opposite surfaces of the substrate. The drift region is arranged corresponding to the first surface and has a first conductivity type. At least one trench is formed by being recessed from the first surface toward the drift region. At least one trench includes an inner wall. The collector is formed on the second surface of the substrate and has a second conductivity type relative to the first conductivity type. At least one gate is formed in the at least one trench. At least one insulating layer is formed between at least one gate and the inner wall of at least one trench and includes at least one side. A plurality of emitters are respectively formed from the first surface of the substrate toward the drift region, adjacent to at least one side of the at least one insulating layer, and have the first conductivity type. A plurality of emitters are respectively arranged in an interval along at least one side. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic cross-sectional structure diagram of a conventional insulated gate bipolar transistor.

[0008] Figure 2 FIG. 4 is a schematic cross-sectional structure diagram of an insulated gate bipolar transistor according to an embodiment of the present invention.

[0009] Figure 3 for Figure 2 The insulated gate bipolar transistor is shown in a top view with partial enlargement.

[0010] Figure 4 FIG. 4 is a schematic cross-sectional structure diagram of an insulated gate bipolar transistor according to another embodiment of the present invention.

[0011] The reference numerals are described as follows:

[0012] 900: Insulated Gate Bipolar Transistor

[0013] 901: Gate

[0014] 902: Hot carrier injection region

[0015] 100, 101: Insulated Gate Bipolar Transistor

[0016] 1: Substrate

[0017] 11: Ditch

[0018] 12: Drift Zone

[0019] 13: First surface

[0020] 14: Second Surface

[0021] 15: Well Area

[0022] 15a: Valid area

[0023] 15b: Virtual Unit

[0024] 2: Collector

[0025] 3: Gate

[0026] 4: Insulation layer

[0027] 41: First side

[0028] 42: Second side

[0029] 5: Emitter

[0030] 51: First emitter

[0031] 51a: First end

[0032] 51b: Second end

[0033] 52: Second emitter

[0034] 52a: The third end

[0035] 52b: The fourth end

[0036] A: First distance

[0037] B: Second distance

[0038] D: Distance

[0039] X: Width direction

[0040] Y: Depth direction

[0041] Z: length direction DETAILED DESCRIPTION

[0042] Some typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different aspects without departing from the scope of the present invention, and the descriptions and illustrations therein are essentially for illustrative purposes rather than for limiting the present invention.

[0043] Figure 1Schematic diagram of the cross-sectional structure of an insulated gate bipolar transistor of an embodiment of the present case. In this embodiment, the insulated gate bipolar transistor 100 includes a substrate 1, a collector 2, at least one gate 3, at least one insulating layer 4 and a plurality of emitters 5. The substrate 1 includes at least one trench 11, a drift region 12, a first surface 13 and a second surface 14. The first surface 13 and the second surface 14 are two opposite surfaces of the substrate 1. The drift region 12 is arranged corresponding to the first surface 13 and has a first conductivity type. In this embodiment, the first conductivity type is an N-type semiconductor, but not limited thereto. At least one trench 11 is formed by being recessed from the first surface 13 toward the drift region 12. At least one trench 11 includes an inner wall (not shown). The collector 2 is formed on the second surface 14 of the substrate 1. The collector 2 has a second conductivity type relative to the first conductivity type. In this embodiment, the second conductivity type is a P-type semiconductor, but not limited thereto. At least one gate 3 is formed in at least one trench 11. At least one insulating layer 4 is formed between at least one gate 3 and the inner wall of at least one trench 11. At least one insulating layer 4 includes at least one side. This embodiment is described by taking multiple gates 3, multiple insulating layers 4 and multiple trenches 11 as examples, but is not limited thereto. Each gate 3 is respectively disposed in the corresponding trench 11, and each insulating layer 4 is formed between the corresponding gate 3 and the inner wall of the trench 11. In this embodiment, at least one side of each insulating layer 4 includes a first side 41 and a second side 42, and the first side 41 and the second side 42 are two opposite sides of the insulating layer 4, but is not limited thereto. Multiple emitters 5 are respectively formed from the first surface 13 of the substrate 1 toward the drift region 12, and are adjacent to the first side 41 or the second side 42 of the insulating layer 4. Multiple emitters 5 have a first conductivity type respectively. By arranging multiple emitters 5 at intervals along the extension direction of the first side 41 or the second side 42, the short-circuit current of the insulated gate bipolar transistor 100 is adjusted to an appropriate range.

[0044] like Figure 2 As shown, the trench 11 of this embodiment has a width direction X, a depth direction Y and a length direction Z. The depth direction Y, the width direction X and the length direction Z are, for example but not limited to, perpendicular to each other. A plurality of trenches 11 are arranged at intervals along the width direction X, but not limited to this. Each trench 11 is formed by a first surface 13 being recessed toward the depth direction Y. A plurality of emitters 5 are arranged at intervals along the length direction Z, but not limited to this. In this embodiment, the emitter 5 adjacent to the first side 41 and the emitter 5 adjacent to the second side 42 are symmetrically arranged on both sides of the trench 11.

[0045] Figure 3 for Figure 2FIG. 1 is a partial enlarged schematic diagram of a top view of an insulated gate bipolar transistor. In the present embodiment, the plurality of emitters 5 include a first emitter 51 and a second emitter 52. The first emitter 51 includes two opposite first ends 51a and a second end 51b. The first end 51a and the second end 51b have a first distance A. The second emitter 52 includes two opposite third ends 52a and a fourth end 52b. The third end 52a of the second emitter 52 is disposed adjacent to the second end 51b of the first emitter 51. The second end 51b of the first emitter 51 and the fourth end 52b of the second emitter 52 have a second distance B. The short-circuit current of the insulated gate bipolar transistor 100 is related to the ratio (B / A) of the second distance B to the first distance A. In the present embodiment, the range of the above ratio (second distance B / first distance A) is preferably between 10% and 70%, but is not limited thereto. By adjusting the distance and length of the first emitter 51 and the second emitter 52, the first distance A and the second distance B are changed, thereby adjusting the short-circuit current of the insulated gate bipolar transistor 100 to an appropriate range. The above method only needs to adjust the position and length of the first emitter 51 and the second emitter 52, and other components of the insulated gate bipolar transistor 100 do not need to be changed, which is low in cost and easy to develop.

[0046] In this embodiment, the substrate 1 further includes a plurality of well regions 15. Each well region 15 is formed on the drift region 12 and is located between two adjacent trenches 11. The plurality of emitters 5 are respectively formed in the plurality of well regions 15. The plurality of well regions 15 respectively have the second conductivity type, but the present invention is not limited thereto.

[0047] Figure 4 FIG. 1 is a cross-sectional view of an insulated gate bipolar transistor according to another embodiment of the present invention. Figure 2The insulated gate bipolar transistor 100 shown has a similar structure, and the same element symbols represent the same elements and functions, so they are not repeated here. The multiple well regions 15 of the substrate 1 of the insulated gate bipolar transistor 101 of this embodiment include at least one effective area 15a and at least one dummy cell 15b (Dummy cell). This embodiment is described by taking multiple effective areas 15a and multiple dummy cells 15b as examples, but is not limited to this. Multiple effective areas 15a and multiple dummy cells 15b are respectively formed on the drift region 12 and are respectively located between two adjacent trenches 11. Each effective area 15a of this embodiment is located between two dummy cells 15b, or each dummy cell 15b is located between two effective areas 15a, but is not limited to this. Multiple emitters 5 are respectively formed in multiple effective areas 15a. The dummy cell 15b is structured to adjust the pattern density or isolate the gate 3. Through the setting of the dummy cell 15b, it can achieve the function equivalent to adjusting the spacing of the gate 3, and the short-circuit current of the insulated gate bipolar transistor 101 can be adjusted to an appropriate range. In addition, the above method only needs to adjust the position and length of the first emitter 51, the second emitter 52 or the dummy unit 16, and other components of the insulated gate bipolar transistor 100 do not need to be changed, which is low in cost and easy to develop. In some embodiments, the effective areas 15a and the dummy units 15b of the plurality of well regions 15 can be arbitrarily arranged between two adjacent gates 3 as required, and are not limited to the above-mentioned implementation of the present case.

[0048] In summary, the present invention provides an insulated gate bipolar transistor, which includes at least one trench, and at least one side of each trench includes multiple emitters. By adjusting the distance and respective lengths of two adjacent emitters among the multiple emitters, the first distance and the second distance are changed, thereby adjusting the short-circuit current of the insulated gate bipolar transistor to an appropriate range, which is low in cost and easy to develop. By setting a virtual unit, it can achieve the function equivalent to adjusting the gate spacing, and the short-circuit current of the insulated gate bipolar transistor can be adjusted to an appropriate range, which is low in cost and easy to develop.

[0049] This case may be modified in various ways by those familiar with this technology, but all of them will not deviate from the protection sought by the attached claims.

Claims

1. An insulated gate bipolar transistor, comprising: A substrate, comprising at least one trench, a drift region, a first surface and a second surface, wherein the first surface and the second surface are two opposite surfaces of the substrate, the drift region is arranged corresponding to the first surface and has a first conductivity type, wherein the at least one trench is formed by the first surface being recessed toward the drift region, wherein the at least one trench comprises an inner wall; a collector formed on the second surface of the substrate and having a second conductivity type relative to the first conductivity type; at least one gate formed in the at least one trench; At least one insulating layer is formed between the at least one gate and the inner wall of the at least one trench and includes at least one side; as well as A plurality of emitters are respectively formed from the first surface of the substrate toward the drift region, are adjacent to the at least one side of the at least one insulating layer, and have the first conductivity type, wherein the plurality of emitters are respectively arranged at intervals along the at least one side.

2. The insulated gate bipolar transistor as claimed in claim 1, wherein the plurality of emitters include a first emitter and a second emitter, the first emitter includes two opposite first ends and a second end, the first end and the second end have a first distance, wherein the second emitter includes two opposite third ends and a fourth end, the third end of the second emitter is arranged adjacent to the second end of the first emitter, wherein the second end of the first emitter and the fourth end of the second emitter have a second distance, wherein a short-circuit current of the insulated gate bipolar transistor is related to the ratio of the second distance to the first distance.

3. The insulated gate bipolar transistor as described in claim 1, wherein the at least one side of the at least one insulating layer includes a first side and a second side, wherein the first side and the second side are respectively located on two opposite sides of the at least one insulating layer, wherein the multiple emitters are respectively adjacent to the first side or the second side, and are respectively arranged at intervals along the first side or the second side. 4 . The insulated gate bipolar transistor of claim 1 , wherein the at least one trench comprises a plurality of trenches, wherein the at least one gate comprises a plurality of gates, wherein each of the gates is formed in a corresponding trench of the plurality of trenches. 5 . The insulated gate bipolar transistor as claimed in claim 4 , wherein the substrate comprises a plurality of well regions, each of the well regions is formed on the drift region and is located between two adjacent trenches, wherein the plurality of well regions have the second conductivity type.

6. An insulated gate bipolar transistor as described in claim 5, wherein the multiple well regions include at least one effective area and at least one virtual unit, the at least one effective area and the at least one virtual unit are respectively formed on the drift region and are respectively located between two adjacent trenches, wherein the at least one effective area has the second conductivity type.

7. The insulated gate bipolar transistor as described in claim 6, wherein the at least one effective region includes a plurality of effective regions, and the at least one virtual unit includes a plurality of virtual units, wherein any of the virtual units is located between two of the effective regions, or any of the effective regions is located between two of the virtual units. 8 . The insulated gate bipolar transistor as claimed in claim 1 , wherein the first conductivity type is an N-type semiconductor, and the second conductivity type is a P-type semiconductor.

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