Shielded gate trench power device with improved termination structure

Abstract

A shielded gate trench MOSFET is disclosed, in which a first type body region is formed in an active region, and a first type electric field lowering region is formed in an adjacent region of a cross region between a first terminal trench and a trench end of a gate trench. The first type electric field lowering region is formed between the first type body region and the first terminal trench, and the first type electric field lowering region is free of the first type body region to enhance a breakdown voltage. At least one second type body region having a floating voltage and having a second conductivity type is formed in the first type electric field lowering region, and the second type body region is separated from the first type body region and the first terminal trench to further enhance the breakdown voltage.

Description

TECHNICAL FIELD

[0001] The present invention relates to a shielded gate trench (SGT) MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a field reduction region to increase the avalanche breakdown voltage and to reduce the drain-to-source leakage current. BACKGROUND

[0002] Figure 1A A top view of a conventional SGT semiconductor power device is shown, in which a first type P body region is formed in the area surrounded by a first termination trench. There are a plurality of intersection regions between the first termination trench along the X axis and the trench ends of a plurality of gate trenches along the Y axis. For medium voltage shielded gate trench MOSFETs with a breakdown voltage of 60-300V, early avalanche breakdown can be observed in the above-mentioned plurality of intersection regions. In Figure 1A The plurality of hot spots marked as "H" in the above-mentioned plurality of intersection regions have a very high drain-to-source leakage current Ids due to the occurrence of early avalanche breakdown. The ruggedness of the device is reduced due to the excessively high leakage current Ids. Figure 1B and 1C are respectively Figure 1A The cross-sectional view of the device along the A1-A1' section along the X axis and the B1-B1' section along the Y axis is shown. Figure 1B The first type P body region 110' in the above-mentioned active region between two adjacent gate trenches and in the active region adjacent to the termination region and in the termination region adjacent to the active region maintains uniform avalanche breakdown due to oxide charge balance. However, Figure 1C The cross-sectional view along the Y axis shown in the above-mentioned has a hot spot (breakdown point, as shown in the figure) near the first termination trench. Figure 1A The first type P body region 110" is connected to the source metal and extends from the active region to the termination region, connecting to the trench sidewall of the first termination trench. Figure 1C The cross-sectional view shown in the above-mentioned is very different from Figure 1B which results in early avalanche breakdown at the P / N junction near the first termination trench.

[0003] Therefore, there is still a need to provide a new device structure to solve the above-mentioned problems and limitations. SUMMARY

[0004] A novel SGT MOSFET is disclosed having an improved device region proximate to the intersection between a first termination trench and the trench end of a plurality of gate trenches. A first type electric field reduction region is formed in an adjacent region of the intersection between a first type termination trench along the X-axis and the trench end of a plurality of gate trenches along the Y-axis, and the first type electric field reduction region is free of a first type P-body region to avoid early avalanche breakdown at the P / N junction proximate to the first termination trench.

[0005] One aspect of the present invention is to disclose a SGT device comprising: an active region, a termination region, a gate metal pad region, a central gate metal wire and at least one shield gate trench contact row region; the active region comprising: a plurality of gate trenches along the X-axis formed in an epitaxial layer having a first conductivity type, the epitaxial layer being on a substrate having a first conductivity type, the gate trenches comprising a first type active trench having a first trench length and a second type active trench proximate to the gate metal pad region having a second trench length, wherein the first type active trench has a length greater than the second type active trench; the termination region comprising at least one first type termination trench surrounding the outer periphery of the plurality of gate trenches along the X-axis and the Y-axis, the at least one first type termination trench being spaced apart from the plurality of gate trenches and not surrounding the gate metal pad region; the SGT device further comprising: the plurality of gate trenches of the active region being surrounded by a first type source region having the first conductivity type, the first type source region being in a first type body region having a second conductivity type and proximate to an upper surface of the epitaxial layer having the first conductivity type, wherein each gate trench comprises a gate and a shield gate; the shield gate being insulated from the epitaxial layer by a first insulating layer, the gate being insulated from the epitaxial layer by a gate oxide layer, the shield gate being insulated from the gate by an interpoly oxide (IPO) layer, the gate oxide layer surrounding the gate and having a thickness less than the first insulating layer; the gate in each gate trench being connected to the gate metal pad through a central gate metal wire having a plurality of gate trench contact regions below; and the shield gate in each gate trench being connected to a source metal through at least one shield gate trench contact region on the gate trench.

[0006] According to another aspect of the present invention, in some preferred embodiments, at least one second type P-body region having a floating voltage is formed between the first type P-body region and the at least one termination trench to enhance the breakdown voltage. The at least one second type P-body region is spaced apart from the first type P-body region and the at least one first type termination trench.

[0007] According to another aspect of the present application, in some preferred embodiments, the epitaxial layer is a single epitaxial layer with a uniform doping concentration. In other preferred embodiments, the epitaxial layer is a multiple step epitaxial (MSE) layer with different doping concentrations, which doping concentrations decrease stepwise from the bottom of the gate trench to the body region of the first type along the sidewall of the gate trench.

[0008] According to another aspect of the present application, in some preferred embodiments, the SGT device further comprises a second type field reduction region of the second conductivity type surrounding the bottom of each gate trench and having a lower doping concentration than the bottom first epitaxial layer of the multiple step epitaxial layer to enhance the breakdown voltage. The purpose of providing the second type field reduction region in the SGT device is to solve the problem of breakdown voltage reduction due to the field oxide thickness at the bottom of each gate trench being smaller than the sidewall field oxide.

[0009] According to another aspect of the present application, in some preferred embodiments, the SGT device further comprises a third type field reduction region of the second conductivity type surrounding the bottom of at least one first type termination trench located in the termination region.

[0010] The above and other objects and advantages of the present application will no doubt become apparent to those ordinarily skilled in the art from the following detailed description of the preferred embodiments, when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0011] The advantages of these and other embodiments of the present application will become apparent to those skilled in the art from the following detailed description of the preferred embodiments, when read in conjunction with the accompanying drawings.

[0012] Figure 1A is a top view of a conventional SGT MOSFET.

[0013] Figure 1B is Figure 1A is a conventional cross-sectional view of the SGT MOSFET shown in FIG. 1 along the A1-A1' section.

[0014] Figure 1C is Figure 1A is a conventional cross-sectional view of the SGT MOSFET shown in FIG. 1 along the B1-B1' section.

[0015] Figure 2 is a top view of a preferred SGT MOSFET with a single termination trench according to the present application.

[0016] Figure 3A is a top view of a preferred SGT MOSFET.

[0017] Figure 3B is a top view of another preferred SGT MOSFET according to the present application.

[0018] Figure 3C is a cross-sectional view of the SGT MOSFET along the A2-A2' cross-section and labeled breakdown points. Figure 3A Figure 3B

[0019] Figure 3D is a top view of another preferred SGT MOSFET according to the present application. Figure 3B

[0020] Figure 4A is a top view of another preferred SGT MOSFET according to the present application.

[0021] Figure 4B is a cross-sectional view of the SGT MOSFET along the B3-B3' cross-section and labeled breakdown points. Figure 4A

[0022] Figure 5A is a top view of another preferred SGT MOSFET according to the present application.

[0023] Figure 5B is a cross-sectional view of the SGT MOSFET along the B4-B4' cross-section and labeled breakdown points. Figure 5A

[0024] Figure 6A is a cross-sectional view of the SGT MOSFET along the A2-A2' cross-section and labeled breakdown points. Figure 3B

[0025] Figure 6B is a cross-sectional view of the SGT MOSFET along the B2-B2' cross-section and labeled breakdown points. Figure 3B

[0026] Figure 7A is a cross-sectional view of the SGT MOSFET along the A2-A2' cross-section and labeled breakdown points. Figure 3B

[0027] Figure 7B is a cross-sectional view of the SGT MOSFET along the B2-B2' cross-section and labeled breakdown points. Figure 3B

[0028] Figure 8A is a cross-sectional view of the SGT MOSFET along the A2-A2' cross-section and labeled breakdown points. Figure 3B ​​​​​​​​​Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the A2-A2' plane, and illustrating the variation of the epitaxial layer doping concentration along the vertical direction.

[0029] Figure 8B is according to the present application Figure 3B Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B2-B2' plane.

[0030] Figure 9A is according to the present application Figure 3B Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the A2-A2' plane, and illustrating the variation of the epitaxial layer doping concentration along the vertical direction.

[0031] Figure 9B is according to the present application Figure 3B Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B2-B2' plane.

[0032] Figure 10 is according to the present application Figure 5A Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B4-B4' plane.

[0033] Figure 11 is according to the present application Figure 5A Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B4-B4' plane.

[0034] Figure 12A is according to the present application Figure 3B Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the A2-A2' plane, and illustrating the variation of the epitaxial layer doping concentration along the vertical direction.

[0035] Figure 12B is according to the present application Figure 3B Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B2-B2' plane.

[0036] Figure 12C is according to the present application Figure 5A Another preferred cross-sectional view of the SGT MOSFET of FIG. 1, taken along the B4-B4' plane DETAILED DESCRIPTION

[0037] The present application is described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the application are shown. The application may, however, be embodied in different forms, but should not be construed as limited to the embodiments set forth herein. For instance, the description herein refers more to N-channel semiconductor integrated circuits, but it will be apparent that other devices are possible. The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiments of the application, and is not intended to represent the only embodiments in which the present application can be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the inventive concepts. However, it will be apparent to those skilled in the art that the present application can be practiced without these specific details. In some instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concept of the application. It is to be understood that the various alternatives presented for one feature are also applicable to other features unless specifically stated otherwise. The direction terms as used in this patent document, such as top, bottom, front, back, up, down, right, left, and the like, are made only by way of reference to the orientation of the various embodiments as drawn to facilitate description of the relative location and / or movement of the various parts. Since the components of the embodiments can be positioned in a number of different orientations, the directional terms used herein are made only for purposes of description and not as limitations on the application. It is to be understood that various substitutions and modifications can be made to the embodiments without departing from the spirit and scope of the present application. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the present application is defined only by the appended claims. It is understood that the features of the various illustrated embodiments described herein can be combined with each other, unless specifically stated otherwise.

[0038] Figure 2 FIG. 1 is a top view of a preferred SGT semiconductor power device according to the present application, which includes an active region, a termination region, a gate metal pad region 237, and a central gate metal line 227 having a plurality of gate trench contact regions 207 located below and near the middle of the source metal 212. In the active region, a plurality of first type active trenches 214 and second type active trenches 204 are formed in the N-type epitaxial layer over the N+ substrate along a first axis (Y-axis direction), wherein the trench length of the first type active trenches 214 is greater than that of the second type active trenches 204, and the second type active trenches 204 are located above the gate metal pad region 237. In each of the first type active trenches 214, a top shield gate trench contact region 205, a bottom shield gate trench contact region 206, and a gate trench contact region 207 located near the middle of the source metal 212 are formed. In each of the second type active trenches 204, a top shield gate trench contact region 205, a bottom shield gate trench contact region 208, and a gate trench contact region 207 are formed. In the termination region, a single termination trench 220 is formed around the outer periphery of the first type active gate trenches 214 and the second type active gate trenches 204 along the first axis (Y-axis direction) and a second axis (X-axis direction), wherein the first axis is perpendicular to the second axis, the single termination trench 220 is separated from the gate trenches 214 and 204, and does not surround the gate metal pad region 237. In addition, a channel stop metal 218 is formed within the termination region.

[0039] Figure 3Ais a top view of a preferred SGT MOSFET, wherein the SGT semiconductor power device includes an active region 332 (indicated by the dashed box 332), a termination region 334 (outside the dashed box 332) surrounding the active region 332, a gate metal pad region 337, a gate metal trace 327, and a channel stopper metal 318. The semiconductor power device is similar to that shown in Figure 2 The present invention has similar structures, except in the present invention, a plurality of termination trenches are formed in the termination region, including a first termination trench 320 and a second termination trench 322 having a termination contact region 319, surrounding the outer periphery of the first type active gate trench and the second type active gate trench along a first axial direction (Y-axis direction) and a second axial direction (X-axis direction), wherein the first axis is perpendicular to the second axis. In addition, the first type P-body region 310 (inside the dashed box 310) is connected to the source metal 312 and is separated from the first termination trench 320. The first type electric field reduction regions 336, 338, and 339 are formed between the first type P-body region 310 and the first termination trench 320 along the second axial direction (X-axis direction), and there is no first type P-body region within the first type electric field reduction regions 336, 338, and 339. Thus, early avalanche breakdown at the P / N junction near the first termination trench is avoided, as well as hot spots near the intersection region between the first termination trench and the trench end of the gate trench.

[0040] Figure 3B is a top view of another preferred SGT semiconductor power device according to the present invention, which is Figure 3A is a magnified portion of

[0041] Figure 3C is Figure 3A and Figure 3B is a cross-sectional view of a preferred A2-A2' cross-section of the SGT MOSFET shown in Figure 1B is a conventional cross-sectional view along the A1-A1' cross-section of the SGT MOSFET shown in Figure 3CThe breakdown point is marked, and uniform avalanche breakdown is maintained due to oxide charge balancing. This embodiment includes an active region and a termination region, and has a single N-type epitaxial layer 302" with a uniform doping concentration. The device includes an N-channel SGT MOSFET formed on the N-type epitaxial layer 302" overlying an N+ substrate 300" with a Ti / Ni / Ag back metal layer 301" on the backside of the N+ substrate 300" serving as the drain metal. Each gate trench 304" in the active region includes a shield gate (SG, as shown) 305" in the lower portion of the trench, and a single gate (G, as shown) 307" overlying the shield gate 305" in the upper portion of the trench. The shield gate 305" is insulated from the adjacent epitaxial layer by a first insulating layer 306", and the gate 307" is insulated from the adjacent epitaxial layer by a gate oxide layer 309" having a thickness less than the first insulating layer 306", and the first insulating layer 306" has a uniform thickness along the sidewalls of the trench. Meanwhile, the shield gate 305" is insulated from the gate 307" by an interpoly oxide layer (IPO) 308". Between every two adjacent gate trenches 304", a P-body region 310" with an n+ source region 311" is formed extending from near the top surface of the N-type epitaxial layer 302". The P-body region 310", the n+ source region 311", and the shield gate 305" are connected to the source metal 312" by a plurality of trench contacts 313" filled with a metal plug and a barrier layer extending through an insulating layer 317" into the P-body region 310", and the bottom of each trench contact 313" is surrounded by a p+ body contact region 320" underlying the n+ source region 311". In the termination region outside the active region edge in the N-type epitaxial layer 302", a p+ body contact doped region 320" is formed surrounding at least the bottom of the trench source-body contact 313", and there is no n+ source region 311" above the p+ body contact region 320". Between two adjacent edge trenches 314" in the termination region, there is no source region 311" and P-body region 310" in the active region. Each edge trench 314" in the termination region includes a trench field plate 315" insulated from the adjacent epitaxial layer by a second insulating layer 316", and the edge trench 314" has a trench width Tw2 and a trench depth Td2 both of which are greater than or equal to the trench width Twl and the trench depth Tdl of the gate trench 304" in the active region (Tw2≥Tw2 and Td2≥Td1). The mesa width Mwl between two adjacent gate trenches 304" is greater than or equal to the mesa width Mw2 between two adjacent edge trenches 314" (Mwl≥Mw2).In addition, the termination region also includes a channel termination metal 318" which is connected to the n+ source region 311", the N-type epitaxial layer 302" and the p+ body contact doped region 320" through the trench channel termination contact region 319".

[0042] Figure 3D is a top view of another preferred SGT semiconductor power device according to the present invention, wherein the SGT semiconductor power device includes a first termination trench 420, a second termination trench 422, first type field reduction regions 436 and 438, a first type P body region 410 (within the dashed box), and second type P body regions 440 and 442 (within the dashed boxes, denoted by 440 and 442, respectively) with floating voltage, wherein the second type P body region 442 is spaced apart from the first termination trench 420 by a distance L2t and spaced apart from the first type P body region 410 by a distance L12. Figure 3B is a cross-sectional view of a preferred B2-B2' cross-section of the SGT MOSFET shown in FIG. 4. The semiconductor power device has a first type field reduction region 338"' and a first type P body region 310"'. The first type P body region 310"' is absent in the first type field reduction region 338"', thereby avoiding early avalanche breakdown at the P / N junction near the first termination trench.

[0043] Figure 4A is a top view of another preferred SGT semiconductor power device according to the present invention, wherein the SGT semiconductor power device includes a first termination trench 420, a second termination trench 422, first type field reduction regions 436 and 438, a first type P body region 410 (within the dashed box), and second type P body regions 440 and 442 (within the dashed boxes, denoted by 440 and 442, respectively) with floating voltage, wherein the second type P body region 442 is spaced apart from the first termination trench 420 by a distance L2t and spaced apart from the first type P body region 410 by a distance L12.

[0044] Figure 4B is a cross-sectional view of a preferred B2-B2' cross-section of the SGT MOSFET shown in FIG. 4. The semiconductor power device has a first type field reduction region 338"' and a first type P body region 310"'. The first type P body region 310"' is absent in the first type field reduction region 338"', thereby avoiding early avalanche breakdown at the P / N junction near the first termination trench. Figure 4A is a cross-sectional view of a preferred B3-B3' cross-section of the SGT MOSFET shown in FIG. 4. The semiconductor power device has a first type field reduction region 438"' and a first type P body region 410"'. The first type P body region 410"' is absent in the first type field reduction region 438"', thereby avoiding early avalanche breakdown at the P / N junction near the first termination trench. Figure 3D The present invention has similar structure as the SGT MOSFET shown in FIG. 4, except that in the present invention, a second type P body region 442' with floating voltage is formed between the first type P body region 410' and the termination trench 420' to enhance the breakdown voltage. In addition, the second type P body region 442' is spaced apart from the first type P body region by a distance L12 and spaced apart from the termination trench 420' by a distance L2t.

[0045] Figure 5AThis is a top view of another preferred SGT semiconductor power device according to the present invention, wherein the SGT semiconductor power device includes: a first termination trench 520, a second termination trench 522, first type electric field reduction regions 536 and 538, a first type P-body region 510 (located within the dashed box), and second type P-body regions 540 and 542 (located within the dashed box, denoted by 540 and 542 respectively) having a floating voltage, wherein each of the second type P-body regions 540 and 542 includes two P-body regions, and the distance between the P-body region in the second type P-body region 542 closest to the first termination trench 520 and the first termination trench 520 is L2t, the distance between the other P-body region in the second type P-body region 542 and the first type P-body region 510 is L12, and the distance between the two P-body regions in the second type P-body region 542 is L22.

[0046] Figure 5B It is based on the present invention Figure 5A The diagram shows a preferred cross-sectional view of the SGT MOSFET along its B4-B4' section. The semiconductor power device described herein... Figure 4B The invention described has a similar structure, except that in this invention, two second-type P-body regions 542' with floating voltages are formed between the first-type P-body region 510' and the terminal trench 520' to enhance the breakdown voltage. Furthermore, the distance between one of the second-type P-body regions 542' close to the first terminal trench 520' and the first terminal trench 520' is L2t, the distance between the other P-body region 542' and the first-type P-body region 510' is L12, and the distance between the two P-body regions in the second-type P-body region 542' is L22.

[0047] Figure 6A It is based on the present invention Figure 3B The diagram shows a cross-sectional view of another preferred A2-A2' section of the SGT MOSFET. This embodiment includes an active region and a termination region, and has two stepped epitaxial layer structures, revealing the variation of epitaxial layer doping concentration along the vertical direction. The described N-channel trench semiconductor power device and... Figure 3C The inventions described have similar structures, except for different epitaxial layer structures. In this invention, the trench semiconductor power device includes an N-channel SGT MOSFET formed on an N-type epitaxial layer located above an N+ substrate 600. A Ti / Ni / Ag backing layer 601 is applied to the back of the substrate 600 and used as a drain metal. An OCB region T... OCB A buffer zone T is formed between two adjacent gate trenches 604, below the body region 610, and above the bottom of the shielding gate 605 (between the BB line and the DD line). B, formed between the bottom of the N+ substrate 600 and the bottom of the shielding gate 605 (between line D-D and line E-E). The N-type epitaxial layer includes a first bottom epitaxial layer (N1, as shown, between line C-C and line E-E) 602 with a doping concentration of D1 and a second top epitaxial layer (N2, as shown, between line A-A and line C-C) 603 located above the first bottom epitaxial layer 602 with a doping concentration of D2. Here, the relationship between D1 and D2 is D2 < D1 to increase the breakdown voltage and reduce the specific on-resistance. The first bottom epitaxial layer 602 is located above the N+ substrate 600 and extends to buffer zone T B above. The doping concentration of the buffer epitaxial layer is the same as the doping concentration D1 of the first bottom epitaxial layer 602. In the N-type epitaxial layer, multiple gate trenches 604 located in the active region and edge trenches 614 located in the termination region vertically extend from the upper surface of the second top epitaxial layer 603 to the first bottom epitaxial layer 602. The bottoms of the gate trenches 604 and the edge trenches 614 are both located above the common interface of the N+ substrate 600 and the first bottom epitaxial layer 602. Each gate trench 604 located in the active region includes a shielding gate (SG, as shown) 605 in the lower part of the trench and a single gate (G, as shown) 607 above the shielding gate 605 in the higher part of the trench. Insulation between the shielding gate 605 and the adjacent epitaxial layer is achieved through the first insulating layer 606, and insulation between the gate 607 and the adjacent epitaxial layer is achieved through the gate oxide layer 609. The thickness of the gate oxide layer 609 is less than that of the first insulating layer 606, and the first insulating layer 606 has a uniform thickness along the sidewall of the trench. At the same time, insulation between the shielding gate 605 and the gate 607 is achieved through the polysilicon inter-oxide layer (IPO) 608. Between every two adjacent trench gates 604, a P-body region 610 with an n+ source region 611 extends from near the upper surface of the second top epitaxial layer 603, forming a source-body region T between line A-A and line B-B SBThe P-body region 610, n+ source region 611 and shield gate 605 are connected to the source metal 612 through a plurality of trench contact regions 613. The plurality of trench contact regions 613 are each filled with a metal plug and barrier layer that extends through the insulating layer 617 into the body region, and the bottom of each trench contact region 613 is surrounded by a p+ body contact region 620 that is located below the n+ source region 611. In the top second epitaxial layer 603, a p+ body contact doped region 620 is formed in the termination region outside the active region edge, which at least surrounds the bottom of the trench source-body contact region 613, and there is no n+ source region above the p+ body contact region 620. Between two adjacent edge trenches 614 in the termination region, there is no source region 611 and P-body region 610 in the active region. Each edge trench 614 in the termination region includes a trench field plate 615, which is insulated from the adjacent epitaxial layer by a second insulating layer 616, wherein the width Tw2 and the depth Td2 of the edge trench 614 are greater than or equal to the width Tw1 and the depth Td1 of the gate trench 604 in the active region (Tw2≥Tw2 and Td2≥Td1). In addition, the mesa width Mw1 between two adjacent gate trenches 604 is greater than or equal to the mesa width Mw2 between two adjacent edge trenches 614 (Mw1≥Mw2).

[0048] Figure 6B is another preferred B2-B2' cross-sectional view of the SGT MOSFET according to the present application Figure 3B has a similar structure to the Figure 3D application except for the different epitaxial layer structure. In the present application, the N-type epitaxial layer includes a bottom first epitaxial layer (N1, as shown) 602' with a doping concentration D1 and a top second epitaxial layer (N2, as shown) 603' located above the bottom first epitaxial layer 602' with a doping concentration D2, wherein the relationship between D1 and D2 is D2<D1 to improve the breakdown voltage and reduce the specific on-resistance.

[0049] Figure 7A is another preferred A2-A2' cross-sectional view of the SGT MOSFET according to the present application Figure 3B this embodiment includes an active region and a termination region, has two stepped epitaxial layers (N1, as shown) 702 and (N2, as shown) 703, and discloses the variation of the epitaxial layer doping concentration in the vertical direction. The N-channel trench semiconductor power device has a similar structure to the Figure 6AThe application has similar structure, except that in the application, further comprising a N-type field reduction region (N*, as shown) 739 with a doping concentration of D* as the second type of field reduction region, which surrounds the bottom of each gate trench 704 in the active region and each edge trench 714 in the termination region, wherein the doping concentration D* of the N-type field reduction region 739 is lower than the doping concentration D1 of the bottom first epitaxial layer 702. The purpose of setting the second type of field reduction region 739 in the SGT device is to solve the problem of breakdown voltage reduction caused by the field oxide layer thickness of the bottom of each gate trench being less than the sidewall field oxide layer.

[0050] Figure 7B is according to the application Figure 3B Another preferred cross-sectional view of the B2-B2' section of the SGT MOSFET shown. The semiconductor power device described has a similar structure to Figure 6B The application has similar structure, except that in the application, further comprising a N-type field reduction region (N*, as shown) 739' with a doping concentration of D* as the second type of field reduction region, which surrounds the bottom of each edge trench 720' in the termination region, wherein the doping concentration D* of the N-type field reduction region 739' is lower than the doping concentration D1 of the bottom first epitaxial layer (N1, as shown) 702'.

[0051] Figure 8A is according to the application Figure 3B Another preferred cross-sectional view of the A2-A2' section of the SGT MOSFET shown, which embodiment comprises an active region and a termination region, and has a three-step epitaxial layer structure, and discloses the change of epitaxial layer doping concentration in the vertical direction. The N-channel conductor power device described has a similar structure to Figure 6A The application has similar structure, except that in the application, the N-type epitaxial layer comprises three step epitaxial layers with different doping concentrations: a bottom first epitaxial layer (N1, as shown) 802 with a doping concentration of D1, a middle second epitaxial layer (N2, as shown) 803 with a doping concentration of D2, and a top third epitaxial layer (N3, as shown) 823 with a doping concentration of D3, wherein the relationship between D1, D2 and D3 is D3 < D2 < D1, to further reduce the specific on-resistance. Among them, D2 can be the average of D1 and D3.

[0052] Figure 8B is according to the application Figure 3B Another preferred cross-sectional view of the B2-B2' section of the SGT MOSFET shown. The semiconductor power device described has a similar structure to Figure 6BThe application has similar structure except for different epitaxial layer structure. In the application, the N-type epitaxial layer comprises a bottom first epitaxial layer (N1, as shown in the figure) 802' with a doping concentration of D1, a middle second epitaxial layer (N2, as shown in the figure) 803' with a doping concentration of D2, and a top third epitaxial layer (N3, as shown in the figure) 823' with a doping concentration of D3, wherein the relationship between D1, D2 and D3 is D3 < D2 < D1, so as to further reduce the specific on-resistance. D2 can be the average of D1 and D3.

[0053] Figure 9A is according to the application Figure 3B Another preferred cross-sectional view of the A2-A2' section of the SGT MOSFET is shown, which embodiment comprises an active region and a termination region, and has three stepped epitaxial layer structures, and reveals the variation of the epitaxial layer doping concentration in the vertical direction. The N-channel conductor power device is similar to Figure 8A The application has similar structure except that in the structure of the application, it further comprises an N-type field reduction region (N*, as shown in the figure) 939 with a doping concentration of D* as the second type field reduction region, which surrounds the bottom of each gate trench 904 in the active region and each edge trench 914 in the termination region, wherein the doping concentration D* of the N-type field reduction region 939 is lower than the doping concentration D1 of the bottom first epitaxial layer (N1, as shown in the figure). The purpose of arranging the second type field reduction region 939 in the SGT device is to solve the problem of breakdown voltage reduction caused by the fact that the field oxide layer thickness at the bottom of each gate trench is less than the sidewall field oxide layer.

[0054] Figure 9B is according to the application Figure 3B Another preferred cross-sectional view of the B2-B2' section of the SGT MOSFET is shown. The semiconductor power device is similar to Figure 8B The application has similar structure except that in the application, it further comprises an N-type field reduction region (N*, as shown in the figure) 939' with a doping concentration of D* as the second type field reduction region, which surrounds the bottom of each edge trench 920' in the termination region, wherein the doping concentration D* of the N-type field reduction region 939' is lower than the doping concentration D1 of the bottom first epitaxial layer (N1, as shown in the figure) 902'.

[0055] Figure 10 is according to the application Figure 5A Another preferred cross-sectional view of the B4-B4' section of the SGT MOSFET is shown. The semiconductor power device is similar to Figure 8BThe application has similar structure, except that in the present application, two second type P body regions 1042 with floating voltage are formed between the first type P body region 1010 and the first termination trench 1020 to increase the breakdown voltage.

[0056] Figure 11 is according to the present application Figure 5A is another preferred B4-B4' cross-sectional view of the SGT MOSFET, which embodiment includes an active region and a termination region, and has three step-epi layer structures, and reveals the variation of epi layer doping concentration along the vertical direction. The N-channel trench-conductor power semiconductor device is according to the present application Figure 10 The application has similar structure, except that in the present application, further includes a N-type field reducing region (N*, as shown in the figure) 1139 with doping concentration D* as the second type field reducing region, which surrounds the bottom of each edge trench 1120 in the termination region, wherein the doping concentration D* of the N-type field reducing region 1139 is lower than the doping concentration D1 of the bottom first epi layer (N1, as shown in the figure).

[0057] Figure 12A is according to the present application Figure 3B is another preferred A2-A2' cross-sectional view of the SGT MOSFET, which embodiment includes an active region and a termination region, and has three step-epi layer structures, and reveals the variation of epi layer doping concentration along the vertical direction. The N-channel trench-conductor power semiconductor device is according to the present application Figure 9A The application has similar structure, except that in the present application, further has different epi layer structure, different shield gate structure in the gate trench 1204 of the active region, and different third type field reducing region 1241. In the present application, an OCB region T OCB is formed between two adjacent gate trenches 1204, below the body region 1210 and above the bottom of the shield gate 1205 (between the B-B line and the D-D line), a buffer region T B is formed between the N+ substrate 1200 and the bottom of the shield gate 1205. The OCB region T OCB has two step-epi layer structures: a bottom first epi layer (N B , as shown in the figure, between the D-D line and the E-E line) 1202 with doping concentration D1, and a top second epi layer (N S1 , as shown in the figure, between the C-C line and the D-D line) 1203 with doping concentration D2, wherein the relationship between D1 and D2 is D2 S2 , as shown in the figure, between the A-A line and the C-C line) 1223, wherein the doping concentration of the epi layer in the source body region T SB is the same as that in the OCB region T OCBThe doping concentration of the top second epitaxial layer 1223 inside is the same as the doping concentration D2 of the buffer epitaxial layer 1202. The doping concentration of the buffer epitaxial layer 1202 is lower than the doping concentration D1 of the first epitaxial layer 1201. B Lower than the OCB region T OCB The doping concentration of the top second epitaxial layer 1223 inside is the same as the doping concentration D2 of the buffer epitaxial layer 1202. The doping concentration of the buffer epitaxial layer 1202 is lower than the doping concentration D1 of the first epitaxial layer 1201.

[0058] Figure 12B is according to the present invention Figure 3B is another preferred cross-sectional view of the B2-B2' section of the SGT MOSFET shown. The semiconductor power device described has the same epitaxial layer structure as Figure 12A the invention described has a similar structure, except in the present invention, in the termination region, a P-type electric field relaxation region 1241' is formed as the third type of electric field relaxation region, which surrounds the bottom of each termination trench 1220' located in the termination region, to further reduce the electric field strength. Figure 8B

[0059] Figure 12C is according to the present invention Figure 5A is another preferred cross-sectional view of the B4-B4' section of the SGT MOSFET shown. The semiconductor power device described has the same epitaxial layer structure as Figure 12B the invention described has a similar structure, except in the present invention, between the first type P-body region 1210" and the first termination trench 1220", two second type P-body regions 1242" with floating voltage are formed to improve the breakdown voltage.

[0060] While the present invention has been described in terms of preferred embodiments, it is to be understood that the disclosure is not to be interpreted as limiting. The embodiments described above are typically N-channel devices, and by reversing the polarity of the conductivity type, the embodiments can also be applied to P-channel devices. Numerous modifications and alterations of this application can become apparent to those skilled in the art without departing from the true scope and spirit of this application. It is intended that all such modifications and alterations be considered part of this disclosure. Accordingly, the appended claims are intended to cover all such modifications and alterations.​

Claims

1. A shielded gate trench (SGT) device, comprising: an active region, comprising: a plurality of gate trenches along a first axis formed in an epitaxial layer having a first conductivity type, the epitaxial layer being on a substrate having the first conductivity type and surrounded by a first type source region having the first conductivity type, the first type source region being in a first type body region having a second conductivity type and proximate to an upper surface of the epitaxial layer having the first conductivity type, wherein each of the gate trenches includes a gate and a shield gate along the first axis; the shield gate is insulated from the epitaxial layer by a first insulating layer, the gate is insulated from the epitaxial layer by a gate oxide layer, the shield gate is insulated from the gate by an interpoly oxide (IPO) layer, the gate oxide layer surrounds the gate, and the gate oxide layer has a thickness less than the first insulating layer; a termination region, comprising: at least one termination trench surrounding an outer periphery of the plurality of gate trenches along a first axis and a second axis, wherein the first axis is perpendicular to the second axis, the at least one termination trench is separated from the plurality of gate trenches; a termination trench field plate in the at least one termination trench, the termination trench field plate is insulated from the epitaxial layer by a second insulating layer and is connected to the first type source region and the first type body region by a source metal; a first type field relaxation region formed between the first type body region in the active region and the at least one termination trench along the second axis and comprising at least one second type body region having a floating voltage and having the second conductivity type, and the at least one second type body region is separated from the first type body region and the at least one termination trench along the second axis; an oxide charge balance (OCB) region formed between two adjacent gate trenches, below the first type body region and above a bottom of the shield gate; a buffer region formed between the substrate and the OCB region along the first axis; the epitaxial layer in the OCB region has a multi-step epitaxial layer structure with a doping concentration that decreases in a stepwise manner from the bottom of the shield gate to the body region along a sidewall of the gate trench in the first axis, wherein each of the multi-step epitaxial layers has a uniform doping concentration; the epitaxial layer in the buffer region has a doping concentration lower than each of the multi-step epitaxial layers in the OCB region; a second type field relaxation region having the first conductivity type surrounding a bottom of each of the gate trenches in the active region, and the second type field relaxation region has a doping concentration lower than a bottom first epitaxial layer of the multi-step epitaxial layer on the substrate; and a third type field relaxation region having the second conductivity type surrounding a bottom of the at least one termination trench in the termination region. ​ ​ ​ ​ ​ ​ ​ ​ ​

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