A semiconductor device terminal structure and its manufacturing process

Abstract

The present invention discloses a semiconductor device terminal structure and its manufacturing process. The semiconductor device terminal structure is disposed in an N-P-N-type doped wide-bandgap semiconductor epitaxial wafer. This structure uses ion implantation or epitaxy plus ion implantation to provide an N-type doped electric field cutoff region and an N-type doped charge compensation region in a P-type doped buried layer. The deepest portion of the N-type doped electric field cutoff region exceeds the P-type doped buried layer and extends into the N-type doped drift region. This structure can achieve a gradual decrease in the equivalent acceptor impurity atomic weight of the P-type doped buried layer from the main junction region to the terminal region and from the cutting path region to the terminal region by adjusting the spacing and volume of at least one N-type doped charge compensation region and doping. This ultimately reduces the curvature effect of the main junction region, alleviates the problem of electric field concentration near the main junction, and avoids premature breakdown of the main junction of the power device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device terminal structure and a manufacturing process thereof. Background Art

[0002] Traditional silicon devices are limited by their own material properties, and further performance improvements are hoped to rely on higher-performance semiconductor materials.

[0003] The third and fourth generation of wide bandgap semiconductor materials represented by SiC and Ga2O3 came into being. Wide bandgap semiconductor materials have more advantages than Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity.

[0004] In power switching applications, power devices made of SiC and Ga2O3, such as diodes, transistors, and power integrated circuits, have smaller footprints and superior electrical properties. In today's power electronics applications, which demand higher power density and lower power consumption, SiC and Ga2O3 materials have greater research significance and broader market application prospects.

[0005] In the blocking state, the device mainly bears voltage through the depletion region formed by the PN junction under reverse bias. According to Poisson's equation, the peak value of the electric field strength in the depletion region is located near the PN junction. When the peak value of the electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will be broken down.

[0006] In the actual preparation process, cylindrical junctions and spherical junctions are formed at the edges and corners of the PN junction. Under the effect of curvature, the electric field near the cylindrical junction and spherical junction is more concentrated, and the electric field intensity is much greater than the electric field intensity of the parallel plane junction in the middle area. The edges and corners will break down before the parallel plane junction, resulting in the breakdown voltage of the device being much lower than the ideal case. Figure 1 shown.

[0007] In order to alleviate the problem of premature breakdown of the edges and corners of the PN junction (main junction of the device) due to the curvature effect, resulting in reduced device blocking capability, the industry often adds a junction termination structure around the PN junction (main junction). The introduced junction termination structure can disperse the electric field originally concentrated at the edge of the main junction, thereby reducing the electric field strength at the edge of the main junction and making the device breakdown voltage closer to the ideal value of a parallel plane junction.

[0008] Commonly used junction terminal structures include field plates, tables, junction terminal extensions and field limiting rings, such as Figure 2 shown.

[0009] The principle of the field plate (FP) structure is to apply a voltage to the field plate to expand the depletion layer at the junction terminal surface, thereby alleviating the electric field concentration phenomenon at the PN junction edge. The principle of the mesa (MESA) structure is to widen the depletion region at the PN junction by etching a slope, thereby reducing the electric field concentration phenomenon.

[0010] The Junction Termination Extension (JTE) structure expands the depletion region of the P+ main junction through self-depletion, thereby reducing electric field concentration at the main junction. The Field Limiting Ring (FLR) structure is equivalent to adding a voltage divider to the edge of the main junction in planar power devices. By optimizing the amount, width, doping concentration, and spacing of the FLR, the main junction depletion region can be effectively widened, reducing electric field concentration between the main junction and the ring, thereby increasing the breakdown voltage.

[0011] However, existing junction termination technology still has some problems. Taking SiC materials as an example, the main technical defects are as follows:

[0012] Technical Flaw 1: Although junction termination technology is relatively mature for Si materials, due to the extremely low diffusion coefficient of impurities in SiC materials, doping of SiC materials is often done through high-temperature ion implantation, forming a shallow PN junction. This results in a smaller radius of curvature of the PN junction in SiC power devices, making the electric field more easily concentrated, further reducing the device's blocking capability and the protection capabilities of the junction termination. In addition, with the development of device structure design capabilities, NPN epitaxial layers have emerged. However, due to limitations in implantation capabilities, existing terminations cannot effectively protect the main junction of devices based on NPN epitaxial layers.

[0013] Technical Defect 2: In high-voltage, high-temperature, and high-humidity environments, charge accumulation, moisture corrosion, and ion migration can occur at the terminals, potentially short-circuiting the front electrode and the cut path. In this situation, both the cut path and the back electrode, as well as the main junction and the back electrode, must withstand the device's blocking voltage. Traditional terminal structures only protect the main junction, neglecting the cut path area. This can lead to increased leakage current in the cut path area or premature breakdown in the cut path area, resulting in a lower-than-ideal breakdown voltage.

[0014] Technical Defect 3: Outside the junction terminal, at the very edge of the device, in the device's scribe area, when the device is in the blocking state, the potential in the scribe area is equal to the bus voltage, while the potential of the electrode in the middle of the device's front side is 0V. This means that there is a huge potential difference between the electrode and the scribe, and air breakdown may occur between the front electrode and the scribe, causing device burnout.

[0015] Technical Defect 4: The semiconductor surface and the outside of the device may carry an unknown amount of charge due to crystal defects or operating environment factors. This charge can affect the electric field distribution at the device terminals, causing the actual electric field distribution to differ from the designed value, leading to premature device breakdown. Summary of the Invention

[0016] In view of the fact that the existing junction terminal structure is limited by the thermal diffusion coefficient of the material, the ion implantation depth and other reasons and cannot well protect the main junction of the power device, especially the problem that air breakdown occurs between the surface electrode and the cutting path of the NPN power device and the existing terminal structure cannot protect the cutting path area, which ultimately leads to a serious reduction in the breakdown voltage of the device, the present invention provides a new junction terminal structure and its manufacturing process.

[0017] The technical solution of the present invention to solve the above technical problems is as follows:

[0018] The present invention provides a new junction terminal structure, wherein the semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer;

[0019] This structure sets an N-type doped electric field stop region and an N-type doped charge compensation region in a P-type doped buried layer by ion implantation, or epitaxy plus ion implantation. The deepest part of the N-type doped electric field stop region needs to extend beyond the P-type doped buried layer into the N-type doped drift region, that is, the N-type doped electric field stop region needs to penetrate the P-type doped buried layer; at least one of the N-type doped charge compensation regions and the N-type doped electric field stop region can be formed by gradually reducing the distance between the charge compensation regions in the direction from the main junction region to the terminal region, or in the direction from the cutting path region to the terminal region, or gradually increasing the charge compensation region doping concentration, or by other means so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer in the direction from the main junction region to the terminal region, or in the direction from the cutting path region to the terminal region is gradually reduced.

[0020] This structure can achieve a gradual decrease in the equivalent acceptor impurity atomic mass of the P-type doped buried layer from the main junction region to the terminal region and from the cutting path region to the terminal region by adjusting the spacing, volume, and doping concentration of at least one N-type doped charge compensation region. This ultimately reduces the curvature of the main junction region, alleviates the problem of electric field concentration near the main junction, and avoids premature breakdown of the main junction of the power device. Adjusting the volume of the N-type doped charge compensation region includes adjusting the width, and / or depth, and / or thickness.

[0021] More specifically,

[0022] A semiconductor device terminal structure is provided in an NPN-doped wide-bandgap semiconductor epitaxial wafer, wherein the wide-bandgap semiconductor epitaxial wafer comprises a main junction region, a terminal region, and a cutting path, which are sequentially connected and include a P-type doped buried layer;

[0023] In this structure, an N-type doped electric field stop region and an N-type doped charge compensation region are provided in a P-type doped buried layer by ion implantation or epitaxy plus ion implantation. The deepest portion of the N-type doped electric field stop region exceeds the P-type doped buried layer and extends into the N-type doped drift region. By varying the spacing, volume, and / or doping concentration of the N-type doped charge compensation region, the P-type doped buried layer has a lower equivalent acceptor impurity atomic weight as it approaches the N-type doped electric field stop region in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region.

[0024] Changing the volume includes changing the depth, and / or width, and / or thickness.

[0025] Furthermore, in the above-mentioned semiconductor device terminal structure, the wide bandgap semiconductor epitaxial wafer includes an N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, an N-type doped current diffusion layer, and a P-type doped main junction region connected in sequence from bottom to top, the side of the N-type doped substrate away from the P-type doped buried layer is connected to a cathode, the side of the P-type doped main junction region away from the P-type doped buried layer is connected to an anode, the end close to the anode forms the main junction region, the end away from the anode forms a cutting path, and the middle portion forms a terminal region;

[0026] A first insulating dielectric layer for isolating metal ions, a second insulating dielectric layer for isolating water vapor, and a third insulating dielectric layer for isolating external electric fields are sequentially connected above the P-type doped main junction region, and one end of the three insulating dielectric layers close to the anode is connected to the anode;

[0027] The N-type doped electric field stop region is connected to the middle of the terminal region, and the N-type doped charge compensation region is connected to the terminal region and distributed on the left and right sides of the N-type doped electric field stop region. The number of the N-type doped charge compensation regions on each side is not less than one.

[0028] Furthermore, in the above-mentioned semiconductor device terminal structure, the N-type doped electric field stop region, at least one N-type doped charge compensation region on the left side, and at least one N-type doped charge compensation region on the right side are connected, so that both sides of the N-type doped electric field stop region form a step-shaped structure inclined toward it.

[0029] Furthermore, in the above-mentioned semiconductor device terminal structure, the closer it is to the N-type doped electric field cut-off region, the smaller the spacing between the N-type doped charge compensation regions, and / or the larger the volume, and / or the higher the doping concentration, and the larger the volume includes the deeper depth, and / or the wider width, and / or the thicker thickness.

[0030] Furthermore, in the above-mentioned semiconductor device terminal structure, the N-type doped charge compensation regions have the same area, but the closer they are to the N-type doped electric field stop region, the smaller the interval between adjacent N-type doped charge compensation regions; or

[0031] The N-type doped charge compensation regions have the same spacing and width, but the closer they are to the N-type doped electric field cut-off region, the deeper the N-type doped charge compensation regions are; or

[0032] The N-type doped charge compensation regions have the same spacing and depth, but the closer they are to the N-type doped electric field cutoff region, the wider the N-type doped charge compensation regions are; or

[0033] The N-type doped charge compensation regions have the same spacing, depth, and interval, but the closer they are to the N-type doped electric field cut-off region, the higher the doping concentration of the N-type doped charge compensation region; or

[0034] Increase the depth of the P-type doped main junction region so that the P-type doped main junction region and the P-type doped buried layer are connected and the N-type doped current diffusion layer is completely swallowed up; or

[0035] The terminal structures on the left and right sides of the terminal area are different.

[0036] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the first insulating dielectric layer is silicon oxide; and / or

[0037] The material of the second insulating dielectric layer is silicon nitride; and / or

[0038] The third insulating dielectric layer is made of silicon oxide.

[0039] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

[0040] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the N-type doped substrate is SiC, GaN, Ga2O3, C or AlN.

[0041] Furthermore, the terminal structure of the semiconductor device mentioned above is subjected to opposite type of doping, that is, N-type doping is changed to P-type doping, and P-type doping is changed to N-type doping.

[0042] The process for manufacturing a semiconductor device terminal structure as described in any one of the above items comprises the following steps:

[0043] Growing an N-type doped drift region on a wide bandgap semiconductor material substrate;

[0044] forming a P-type doped buried layer by ion implantation, epitaxy or growth of a P-type oxide;

[0045] forming an N-type doped current diffusion layer by epitaxy;

[0046] An N-type doped electric field stop region and an N-type doped charge compensation region are formed by ion implantation or epitaxy + ion implantation;

[0047] forming a P-type doped main junction region by ion implantation or the like;

[0048] The first insulating dielectric layer, the second insulating dielectric layer and the third insulating dielectric layer are deposited and etched, and metal is deposited and etched on the front and back sides to form anode and cathode electrodes.

[0049] In the above-mentioned process for manufacturing the terminal structure of a semiconductor device, after forming the P-type doped buried layer, the N-type doped electric field stop region and the N-type doped charge compensation region are first formed, and then the N-type doped current diffusion layer is formed.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] The structure has at least one N-type doped charge compensation region and an N-type doped electric field cutoff region on the left side near the anode (i.e., the main junction region), and a P-type doped buried layer whose equivalent acceptor impurity atomic weight gradually decreases in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0052] The P-type doped buried layer formed by at least one N-type doped charge compensation region and an N-type doped electric field cut-off region near the cutting path area on the right side of this structure, in which the equivalent acceptor impurity atomic weight gradually decreases in the direction away from the cutting path area, can reduce the curvature effect of the cutting path area, alleviate the problem of electric field concentration near the cutting path, prevent the cutting path area from breaking down prematurely after the cutting path surface is short-circuited with the anode metal (front electrode of the device), and solve technical defect 2.

[0053] In the blocking state of the device, the P-type doped buried layer can block the cathode (the electrode on the back of the device) potential and leakage current, thereby solving technical defects 2 and 3.

[0054] Because the electric field and potential from the cathode are shielded by the P-type doped buried layer, the P-type doped main junction region located on the device surface can ignore the electric field concentration effect, and a highly doped P-type doped main junction region can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 A schematic diagram of a structure in which the curvature effect of a PN junction edge leads to electric field concentration in the background technology of the present invention;

[0056] Figure 2Schematic diagram of a common terminal structure in the background technology of the present invention, (a) field plate; (b) mesa; (c) junction terminal extension; (d) field limiting ring;

[0057] Figure 3 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 1 of the present invention;

[0058] Figure 4 Schematic diagram of doping concentration distribution structure of a simulated structure of the terminal structure near the main junction region on the left side of the embodiment 1 of the present invention;

[0059] Figure 5 is a breakdown characteristic curve diagram of the terminal structure of Example 1 of the present invention;

[0060] Figure 6 for Figure 4 Potential distribution diagram on the AA' tangent line;

[0061] Figure 7 for Figure 4 The electric field intensity distribution on the AA' tangent line;

[0062] Figure 8 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 2 of the present invention;

[0063] Figure 9 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 3 of the present invention;

[0064] Figure 10 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 4 of the present invention;

[0065] Figure 11 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 5 of the present invention;

[0066] Figure 12 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 6 of the present invention;

[0067] Figure 13 This is a schematic structural diagram of a semiconductor device terminal structure according to embodiment 7 of the present invention;

[0068] Figure 14 The method comprises growing an N-type doped drift region on a wide bandgap semiconductor material substrate in the terminal structure manufacturing process of embodiment 12 of the present invention;

[0069] Figure 15 The P-type doped buried layer is formed by ion implantation, epitaxy, growth of P-type oxide, etc. in the manufacturing process of the terminal structure of embodiment 12 of the present invention;

[0070] Figure 16The N-type doped current diffusion layer is formed by epitaxy in the terminal structure manufacturing process of embodiment 12 of the present invention;

[0071] Figure 17 The N-type doped electric field stop region and the N-type doped charge compensation region are formed by ion implantation or the like in the terminal structure manufacturing process of embodiment 12 of the present invention;

[0072] Figure 18 The P-type doped main junction region is formed by ion implantation or the like in the manufacturing process of the terminal structure according to embodiment 12 of the present invention;

[0073] Figure 19 Forming an N-type doped charge compensation region and an N-type doped electric field stop region in the terminal structure manufacturing process of embodiment 13 of the present invention;

[0074] Figure 20 This is the process for forming an N-type doped current diffusion layer in the terminal structure manufacturing process of embodiment 13 of the present invention.

[0075] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0076] 1. Main junction region; 2. Terminal region; 3. Cutting road; 4. Cathode; 5. N-type doped substrate; 6. N-type doped drift region; 7. P-type doped buried layer; 8. N-type doped current diffusion layer; 9. P-type doped main junction region; 10. Anode; 11. N-type doped electric field stop region; 12. N-type doped charge compensation region; 13. First insulating dielectric layer; 14. Second insulating dielectric layer; 15. Third insulating dielectric layer. DETAILED DESCRIPTION

[0077] For ease of understanding of the present application, the present application will be described more fully below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0079] It will be understood that spatial relational terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be understood that in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0080] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc., if the connected circuits, modules, units, etc. can transmit electrical signals or data to each other.

[0081] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0082] The present invention addresses the problem that existing junction termination structures are unable to effectively protect the main junction of power devices, especially the main junction of NPN epitaxial wafer structures, due to limitations such as the thermal diffusion coefficient of semiconductor materials and the depth of ion implantation (Technical Defect 1); the problem that short circuits may occur between the surface electrodes of power devices and the cutting street 3, and the existing termination structure cannot protect the cutting street 3 area, ultimately resulting in a significant reduction in the device's breakdown voltage (Technical Defect 2); the problem that air breakdown is prone to occur in the cutting street 3 area (Technical Defect 3); and the problem that charges of unknown magnitude may exist on the semiconductor surface and the outside of the device due to crystal defects and working environment factors. This partial charge affects the electric field distribution at the device terminal, causing the actual electric field distribution to differ from the designed value and leading to premature device breakdown (Technical Defect 4). The present invention provides a new junction termination structure and a manufacturing process thereof.

[0083] Taking SiC as an example of the semiconductor material used in this solution, the semiconductor material in this solution can be replaced with other semiconductor materials, such as Si, GaN, Ga2O3, AlN, diamond (C), etc.; and the semiconductor material in this solution can be doped with opposite types, such as changing N-type doping to P-type doping, and vice versa, and is also applicable and within the scope of protection of the present invention.

[0084] The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, wherein the wide bandgap refers to a semiconductor with a bandgap width greater than 2.2 eV;

[0085] In this structure, an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 are provided in the P-type doped buried layer 7 by ion implantation, or epitaxy plus ion implantation. The deepest portion of the N-type doped electric field stop region 11 needs to extend beyond the P-type doped buried layer 7 into the N-type doped drift region 6, that is, the N-type doped electric field stop region 11 needs to penetrate the P-type doped buried layer 7. At least one of the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 can be provided by gradually reducing the distance between the charge compensation regions in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 region to the terminal region 2, and / or gradually increasing the volume of the charge compensation regions and / or gradually increasing the doping concentration of the charge compensation regions, and / or other methods to gradually reduce the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 region to the terminal region 2. The gradual increase in the volume of the charge compensation region includes a gradual increase in the thickness of the charge compensation region, and / or a gradual increase in the depth of the charge compensation region, and / or a gradual increase in the width of the charge compensation region. The gradual decrease in volume may be formed by the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11, or may be formed by adjacent N-type doped charge compensation regions.

[0086] This structure can achieve a gradual decrease in the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2 by adjusting the spacing, volume, and doping concentration of at least one N-type doped charge compensation region 12. This ultimately reduces the curvature of the main junction region 1, alleviates the problem of electric field concentration near the main junction, and avoids premature breakdown of the main junction of the power device. Adjusting the volume includes adjusting the thickness, and / or width, and / or depth.

[0087] In this structure, at least one N-type doped charge compensation region 12 is formed on the left side near the anode 10 (i.e., the main junction region 1), and a P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1 can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0088] The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting street 3 area, formed by at least one N-type doped charge compensation region 12 on the right side of the structure near the cutting street 3 area, can reduce the curvature effect of the cutting street 3 area, alleviate the problem of electric field concentration near the cutting street 3, and prevent the cutting street 3 area from breaking down prematurely after the surface of the cutting street 3 is short-circuited with the anode 10 metal (the front electrode of the device), thereby solving technical defect 2.

[0089] In the blocking state of the device, the P-type doped buried layer 7 can block the cathode 4 (device back electrode) potential and leakage current, solving technical defects 2 and 3.

[0090] Thanks to the fact that the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4.

[0091] Regarding technical defect 1: This structure provides an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 in the P-type doped buried layer 7 by ion implantation, or epitaxy plus ion implantation. The deepest part of the N-type doped electric field stop region 11 needs to extend beyond the P-type doped buried layer 7 and into the P-type doped buried layer 7, that is, the N-type doped electric field stop region 11 needs to penetrate the P-type doped buried layer 7; at least one of the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 can be formed by gradually reducing the distance between the charge compensation regions in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 region to the terminal region 2, and / or gradually increasing the charge compensation region volume and / or gradually increasing the charge compensation region doping concentration, and / or other means to gradually reduce the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 region to the terminal region 2. The gradual increase in the volume of the charge compensation region includes a gradual increase in the width of the charge compensation region and / or a gradual increase in the thickness of the charge compensation region and / or a gradual increase in the depth of the charge compensation region.

[0092] In this structure, the P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1, formed by at least one N-type doped charge compensation region 12 and an N-type doped electric field cut-off region 11 on the left side near the anode 10 (main junction region 1), can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0093] Regarding technical defect 2: The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting street 3 area, formed by at least one N-type doped charge compensation region 12 near the cutting street 3 area on the right side of the structure, can reduce the curvature effect of the cutting street 3 area, alleviate the problem of electric field concentration near the cutting street 3, and prevent the cutting street 3 area from breaking down prematurely after the surface of the cutting street 3 is short-circuited with the anode 10 metal (the front electrode of the device).

[0094] Regarding technical defect 3: in the blocking state of the device, the P-type doped buried layer 7 can play a role in isolating the cathode 4 (the back electrode of the device) potential and leakage current.

[0095] Regarding technical defect 4: the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, so the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device.

[0096] Example 1

[0097] A semiconductor device terminal structure is provided in an NPN-type doped wide bandgap semiconductor epitaxial wafer, such as Figure 3 shown.

[0098] The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer;

[0099] The wide bandgap semiconductor epitaxial wafer includes an N-type doped substrate 5, an N-type doped drift region 6, a P-type doped buried layer 7, an N-type doped current diffusion layer 8, and a P-type doped main junction region 91, which are sequentially connected from bottom to top. The side of the N-type doped substrate 5 away from the P-type doped buried layer 7 is connected to a cathode 4. The side of the P-type doped main junction region 91 away from the P-type doped buried layer 7 is connected to an anode 10. The end close to the anode 10 forms a main junction region 1, and the end away from the anode 10 forms a cutting street 3, with a terminal region 2 in the middle.

[0100] This structure uses ion implantation or epitaxy plus ion implantation to provide an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 in the P-type doped buried layer 7. The N-type doped electric field stop region 11 extends beyond the P-type doped buried layer 7 and into the N-type doped drift region 6 at its deepest point. By varying the spacing, volume, and / or doping concentration of the N-type doped charge compensation region 12, the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 decreases as it approaches the N-type doped electric field stop region 11, both in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 to the terminal region 2. Varying the volume of the N-type doped charge compensation region 12 includes varying its width, depth, and / or thickness.

[0101] The P-type doped main junction region 91 is sequentially connected to a first insulating dielectric layer 13 for isolating metal ions, a second insulating dielectric layer 14 for isolating water vapor, and a third insulating dielectric layer 15 for isolating external electric fields, and one end close to the anode 10 is connected to the anode 10;

[0102] The N-type doped electric field stop region 11 is connected to the middle of the terminal region 2, and the N-type doped charge compensation region 12 is connected to the terminal region 2 and distributed on the left and right sides of the N-type doped electric field stop region 11. The number of the N-type doped charge compensation regions 12 on each side is not less than one.

[0103] The first insulating dielectric layer 13 is made of silicon oxide; the second insulating dielectric layer 14 is made of silicon nitride; and the third insulating dielectric layer 15 is made of silicon oxide.

[0104] The doping element of the N-type doped drift region 6 is nitrogen; the doping element of the P-type doped buried layer 7 is aluminum or boron; the doping element of the N-type doped current diffusion layer 8 is nitrogen; and the doping element of the P-type doped main junction region 9 is aluminum or boron.

[0105] In order to more intuitively demonstrate the effect of this structure, the protection effect of the terminal left side structure on the main junction is demonstrated by simulation software, as shown in the figure. Figures 4 to 7 shown.

[0106] From the breakdown characteristic curve, it can be seen that the terminal structure of the present invention achieves a withstand voltage of more than 1600V on an 11μm SiC epitaxial layer, and at least one N-type doped charge compensation region plays a role in dispersing the potential and electric field strength distribution, avoiding the problem of premature breakdown caused by excessive concentration of the electric field at the edge of the main junction.

[0107] Example 2

[0108] Example 2 is substantially the same as Example 1, except that Figure 8As shown, in addition to using the solution of implanting at least one N-type doped charge compensation region 12 as in Example 1, a single multi-level N-type doped charge compensation region 12 can also be formed to achieve the effect of gradually reducing the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2. This ultimately reduces the curvature effect of the main junction region 1, alleviates the problem of electric field concentration near the main junction, and avoids the problem of premature breakdown of the main junction of the power device. That is, unlike Example 1, where the N-type doped electric field stop region 11, at least one N-type doped charge compensation region 12 on the left, and at least one N-type doped charge compensation region 12 on the right are independent of each other, in this embodiment, the N-type doped electric field stop region 11, at least one N-type doped charge compensation region 12 on the left, and at least one N-type doped charge compensation region 12 on the right are connected, thereby forming a stepped structure on both sides of the N-type doped electric field stop region 11 that is inclined toward it.

[0109] Example 3

[0110] Example 3 is substantially the same as Example 1, except that Figure 9 As shown, unlike Example 1, the area of ​​the N-type doped charge compensation region 12 becomes larger the closer it is to the N-type doped electric field stop region 11. The area of ​​the N-type doped charge compensation region 12 in this embodiment is the same, but the closer it is to the N-type doped electric field stop region 11, the smaller the interval between adjacent N-type doped charge compensation regions 12, so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 gradually decreases in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2.

[0111] Example 4

[0112] Example 4 is substantially the same as Example 1, except that Figure 10 As shown, the N-type doped charge compensation regions 12 of this embodiment have the same spacing and width, but the closer to the N-type doped electric field cut-off region 11, the deeper the N-type doped charge compensation region 12 is, so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 gradually decreases in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2.

[0113] Example 5

[0114] Example 5 is substantially the same as Example 1, except that Figure 11 As shown, the N-type doped charge compensation regions 12 of this embodiment have the same spacing and depth, but the closer to the N-type doped electric field cut-off region 11, the wider the N-type doped charge compensation region 12 is, so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 gradually decreases in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2.

[0115] Example 6

[0116] Example 6 is substantially the same as Example 1, except that Figure 12 As shown, the N-type doped charge compensation regions 12 of this embodiment have the same pitch, depth, and spacing, but the closer to the N-type doped electric field cut-off region 11, the higher the doping concentration of the N-type doped charge compensation region 12, so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 gradually decreases in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting street 3 region to the terminal region 2.

[0117] Example 7

[0118] Example 7 is substantially the same as Example 1, except that Figure 13 As shown, the depth of the P-type doped main junction region 9 is increased so that the P-type doped main junction region 9 and the P-type doped buried layer 7 are connected, that is, the P-type doped main junction region 9 swallows up the N-type doped current diffusion layer 8.

[0119] Example 8

[0120] Example 8 is basically the same as Example 1, except that the terminal structures on the left and right sides of the terminal area 2 may be different, that is, the terminal protection structure for the main junction and the terminal protection structure for the cutting path 3 may be freely combined. For example, the terminal structure on the left side is achieved by changing the spacing of the N-type doped charge compensation area 12, and the terminal structure on the right side is achieved by changing the doping concentration of the N-type doped charge compensation area 12.

[0121] Example 9

[0122] The semiconductor material used in the above embodiment is SiC. In this embodiment, the semiconductor material in the present invention can be replaced by other semiconductor materials, such as Si, GaN, Ga2O3, AlN, diamond (C), etc.

[0123] Example 10

[0124] Example 10 is basically the same as Example 1, except that the situation of applying opposite type of doping to the semiconductor material in this scheme, such as changing N-type doping to P-type doping and P-type doping to N-type doping, is also applicable and is within the scope of protection of the present invention.

[0125] Example 11

[0126] The difference between Example 11 and Example 1 is that the width of the charge compensation region is gradually increased, the thickness of the charge compensation region is gradually increased, and the depth of the charge compensation region is gradually increased, so as to achieve the effect of gradually increasing the volume of the charge compensation region, and the distance between the charge compensation regions is gradually reduced, and the doping concentration of the charge compensation region is gradually increased, so that the volume of the P-type doped buried layer 7 compensated in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 shows an increasing trend, that is, in this direction, the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 gradually decreases.

[0127] Example 12

[0128] The specific manufacturing process of a semiconductor device terminal structure according to embodiment 1 of the present invention is as follows:

[0129] 1) Grow an N-type doped drift region 6 on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate, such as Figure 14 As shown;

[0130] 2) Form a P-type doped buried layer 7 by ion implantation, epitaxy, growth of P-type oxide, etc. Figure 15 As shown;

[0131] 3) Forming an N-type doped current diffusion layer 8 by epitaxy, such as Figure 16 As shown;

[0132] 4) Forming an N-type doped electric field cutoff region 11 and an N-type doped charge compensation region 12 by ion implantation or the like, such as Figure 17 As shown;

[0133] 5) Form a P-type doped main junction region 9 by ion implantation or other methods, such as Figure 18 As shown;

[0134] 6) Deposit and etch the first insulating dielectric layer 13, the second insulating dielectric layer 14 and the third insulating dielectric layer 15, deposit and etch metal on the front and back sides to form the anode 10 and the cathode 4 electrodes, forming Figure 3 A terminal structure of a semiconductor device is shown.

[0135] Example 13

[0136] Example 13 is basically the same as Example 12, except that some process steps are changed to realize the present structure. For example, the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 can be formed before the N-type doped current diffusion layer 8 is formed by epitaxial growth. Figure 19 shown.

[0137] In detail, after forming the P-type doped buried layer 7, the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 are first formed by ion implantation or the like, as shown in FIG. Figure 19 As shown, an N-type doped current diffusion layer 8 is formed by epitaxy, as shown in FIG. Figure 20 shown.

[0138] In this structure, at least one N-type doped charge compensation region 12 is formed on the left side near the anode 10 (main junction region 1), and the P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1 can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0139] The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting street 3 area, formed by at least one N-type doped charge compensation region 12 on the right side of the structure near the cutting street 3 area, can reduce the curvature effect of the cutting street 3 area, alleviate the problem of electric field concentration near the cutting street 3, and prevent the cutting street 3 area from breaking down prematurely after the surface of the cutting street 3 is short-circuited with the anode 10 metal (the front electrode of the device), thereby solving technical defect 2.

[0140] In the blocking state of the device, the P-type doped buried layer 7 can block the cathode 4 (device back electrode) potential and leakage current, solving technical defects 2 and 3.

[0141] Thanks to the fact that the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor device terminal structure, characterized in that: The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, wherein the wide bandgap semiconductor epitaxial wafer comprises a main junction region, a terminal region and a cutting path which are sequentially connected and include a P-type doped buried layer; In this structure, an N-type doped electric field stop region and an N-type doped charge compensation region are provided in a P-type doped buried layer by ion implantation or epitaxy plus ion implantation. The deepest portion of the N-type doped electric field stop region exceeds the P-type doped buried layer and extends into the N-type doped drift region. By changing the spacing, volume, and / or doping concentration of the N-type doped charge compensation region, the equivalent acceptor impurity atomic weight of the P-type doped buried layer decreases as the P-type doped buried layer approaches the N-type doped electric field stop region in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region. The wide bandgap semiconductor epitaxial wafer includes an N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, an N-type doped current diffusion layer, and a P-type doped main junction region, which are sequentially connected from bottom to top. The side of the N-type doped substrate away from the P-type doped buried layer is connected to a cathode, and one end of the P-type doped main junction region away from the P-type doped buried layer is connected to an anode. The end close to the anode forms a main junction region, and the end away from the anode forms a cutting path, with a terminal region in the middle. The N-type doped electric field stop region is connected to the middle of the terminal region, and the N-type doped charge compensation region is connected to the terminal region and distributed on the left and right sides of the N-type doped electric field stop region. The number of the N-type doped charge compensation region on each side is not less than one. The N-type doped charge compensation regions have the same area, but the closer they are to the N-type doped electric field cut-off region, the smaller the interval between adjacent N-type doped charge compensation regions; or The N-type doped charge compensation regions have the same spacing and width, but the closer they are to the N-type doped electric field cut-off region, the deeper the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing and depth, but the closer they are to the N-type doped electric field cutoff region, the wider the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing, depth and interval, but the closer they are to the N-type doped electric field cutoff region, the higher the doping concentration of the N-type doped charge compensation region.

2. A semiconductor device terminal structure according to claim 1, characterized in that: The P-type doped main junction region is sequentially connected with a first insulating dielectric layer for isolating metal ions, a second insulating dielectric layer for isolating water vapor, and a third insulating dielectric layer for isolating external electric fields, and the three insulating dielectric layers are connected to the anode at one end close to the anode.

3. A semiconductor device terminal structure according to claim 1, characterized in that: The N-type doped electric field stop region, at least one N-type doped charge compensation region on the left, and at least one N-type doped charge compensation region on the right are connected, so that both sides of the N-type doped electric field stop region form a step-shaped structure inclined toward it.

4. A semiconductor device terminal structure according to claim 1, characterized in that: The terminal structures on the left and right sides of the terminal area are different.

5. A semiconductor device terminal structure according to claim 2, characterized in that: The material of the first insulating dielectric layer is silicon oxide; and / or The material of the second insulating dielectric layer is silicon nitride; and / or The third insulating dielectric layer is made of silicon oxide.

6. A semiconductor device terminal structure according to claim 2, characterized in that: The doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; the doping element of the P-type doped main junction region is aluminum or boron; the material of the N-type doped substrate is SiC, GaN, Ga2O3, diamond or AlN.

7. A semiconductor device terminal structure according to claim 1, characterized in that: Apply the opposite type of doping, changing N-type doping to P-type doping and P-type doping to N-type doping.

8. The process for manufacturing a semiconductor device terminal structure according to any one of claims 2 to 6, wherein: The following steps are involved: Growing an N-type doped drift region on a wide bandgap semiconductor material substrate; forming a P-type doped buried layer by ion implantation, epitaxy or growth of a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; An N-type doped electric field stop region and an N-type doped charge compensation region are formed by ion implantation or epitaxy plus ion implantation; Forming a P-type doped main junction region by ion implantation; The first insulating dielectric layer, the second insulating dielectric layer and the third insulating dielectric layer are deposited and etched, and metal is deposited and etched on the front and back sides to form anode and cathode electrodes.

9. The process for manufacturing a semiconductor device terminal structure according to claim 8, wherein: After forming the P-type doped buried layer, an N-type doped electric field stop region and an N-type doped charge compensation region are formed first, and then an N-type doped current diffusion layer is formed.

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